paolo della vedova / FastIO

Replacement for regular GPIO (DigitalIn, DigitalOut, DigitalInOut) classes which has superior speed. (modified for use opendrain in stm32)

Dependents:   hctl2032_encoder

Fork of FastIO by Erik -

Devices/FastIO_NUCLEO_F401.h@9:6e0f24f71081, 2014-09-05 (annotated)

Committer:
c128
Date:
Fri Sep 05 04:48:50 2014 +0000
Revision:
9:6e0f24f71081
Parent:
7:1e784ae11fba 
changes to make opendrain working in stm32

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 4:6ebbf25b9167 1 #ifdef TARGET_NUCLEO_F401RE
Sissors 4:6ebbf25b9167 2
Sissors 4:6ebbf25b9167 3 #include "mbed.h"
Sissors 4:6ebbf25b9167 4 #include "pinmap.h"
Sissors 4:6ebbf25b9167 5
Sissors 4:6ebbf25b9167 6 typedef struct {
Sissors 4:6ebbf25b9167 7 uint32_t mask;
Sissors 4:6ebbf25b9167 8 } fastio_vars;
Sissors 4:6ebbf25b9167 9
Sissors 4:6ebbf25b9167 10 #define PINMASK (1 << STM_PIN(pin))
Sissors 4:6ebbf25b9167 11 #define PORT ((GPIO_TypeDef *)(GPIOA_BASE + 0x0400 * STM_PORT(pin)))
Sissors 4:6ebbf25b9167 12
Sissors 5:3dd1ab9bbc59 13 #define INIT_PIN RCC->AHB1ENR |= (1 << STM_PORT(pin)); (PORT->MODER &= ~(GPIO_MODER_MODER0_1 << (STM_PIN(pin) * 2))); container.mask = PINMASK
Sissors 4:6ebbf25b9167 14 #define DESTROY_PIN
Sissors 4:6ebbf25b9167 15
Sissors 7:1e784ae11fba 16 #define SET_DIR_INPUT (PORT->MODER &= ~(GPIO_MODER_MODER0_0 << (STM_PIN(pin) * 2)))
Sissors 4:6ebbf25b9167 17 #define SET_DIR_OUTPUT (PORT->MODER |= (GPIO_MODER_MODER0_0 << (STM_PIN(pin) * 2)))
Sissors 4:6ebbf25b9167 18 #define SET_MODE(pull) pin_mode(pin, pull);
c128 9:6e0f24f71081 19 #define SET_FUNCTION pin_function(pin, STM_PIN_DATA(2, GPIO_NOPULL, GPIO_AF10_OTG_FS));
c128 9:6e0f24f71081 20
c128 9:6e0f24f71081 21 //pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP));
c128 9:6e0f24f71081 22 //void pin_function(PinName pin, int data) {
c128 9:6e0f24f71081 23 // MBED_ASSERT(pin != (PinName)NC);
c128 9:6e0f24f71081 24 // // Get the pin informations
c128 9:6e0f24f71081 25 // uint32_t mode = STM_PIN_MODE(data);
c128 9:6e0f24f71081 26 // uint32_t pupd = STM_PIN_PUPD(data);
c128 9:6e0f24f71081 27 // uint32_t afnum = STM_PIN_AFNUM(data);
c128 9:6e0f24f71081 28
c128 9:6e0f24f71081 29 // uint32_t port_index = STM_PORT(pin);
c128 9:6e0f24f71081 30 // uint32_t pin_index = STM_PIN(pin);
c128 9:6e0f24f71081 31
c128 9:6e0f24f71081 32 // Enable GPIO clock
c128 9:6e0f24f71081 33 // uint32_t gpio_add = Set_GPIO_Clock(port_index);
c128 9:6e0f24f71081 34 // GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
c128 9:6e0f24f71081 35
c128 9:6e0f24f71081 36 // Configure GPIO
c128 9:6e0f24f71081 37 // GPIO_InitTypeDef GPIO_InitStructure;
c128 9:6e0f24f71081 38 // GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index);
c128 9:6e0f24f71081 39 // GPIO_InitStructure.Mode = gpio_mode[mode];
c128 9:6e0f24f71081 40 // GPIO_InitStructure.Pull = pupd;
c128 9:6e0f24f71081 41 // GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
c128 9:6e0f24f71081 42 // GPIO_InitStructure.Alternate = afnum;
c128 9:6e0f24f71081 43 // HAL_GPIO_Init(gpio, &GPIO_InitStructure);
c128 9:6e0f24f71081 44
Sissors 4:6ebbf25b9167 45
Sissors 4:6ebbf25b9167 46 #define WRITE_PIN_SET (PORT->BSRRL = PINMASK)
Sissors 4:6ebbf25b9167 47 #define WRITE_PIN_CLR (PORT->BSRRH = PINMASK)
Sissors 4:6ebbf25b9167 48
Sissors 4:6ebbf25b9167 49 #define READ_PIN ((PORT->IDR & container.mask) ? 1 : 0)
Sissors 4:6ebbf25b9167 50
Sissors 4:6ebbf25b9167 51 #endif
c128 9:6e0f24f71081 52