paolo della vedova / FastIO

Replacement for regular GPIO (DigitalIn, DigitalOut, DigitalInOut) classes which has superior speed. (modified for use opendrain in stm32)

Dependents:   hctl2032_encoder

Fork of FastIO by Erik -

Devices/FastIO_LPC81X.h@9:6e0f24f71081, 2014-09-05 (annotated)

Committer:
c128
Date:
Fri Sep 05 04:48:50 2014 +0000
Revision:
9:6e0f24f71081
Parent:
4:6ebbf25b9167 
changes to make opendrain working in stm32

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 1:85a4a54f15e3 1 #ifdef TARGET_LPC81X
Sissors 1:85a4a54f15e3 2
Sissors 1:85a4a54f15e3 3 #include "mbed.h"
Sissors 1:85a4a54f15e3 4 #include "pinmap.h"
Sissors 1:85a4a54f15e3 5
Sissors 1:85a4a54f15e3 6 typedef struct {
Sissors 1:85a4a54f15e3 7 __I uint32_t *reg_in;
Sissors 1:85a4a54f15e3 8 uint32_t mask;
Sissors 1:85a4a54f15e3 9 } fastio_vars;
Sissors 1:85a4a54f15e3 10
Sissors 1:85a4a54f15e3 11 #define PINMASK (1 << ((int)pin & 0x1F))
Sissors 1:85a4a54f15e3 12 static void gpio_enable(void);
Sissors 1:85a4a54f15e3 13
Sissors 1:85a4a54f15e3 14 #define INIT_PIN container.mask = PINMASK; container.reg_in = &LPC_GPIO_PORT->PIN0; gpio_enable(); pin_function(pin, 0)
Sissors 2:1a6ed4b84590 15 #define DESTROY_PIN
Sissors 1:85a4a54f15e3 16
Sissors 1:85a4a54f15e3 17 #define SET_DIR_INPUT (LPC_GPIO_PORT->DIR0 &= ~PINMASK)
Sissors 1:85a4a54f15e3 18 #define SET_DIR_OUTPUT (LPC_GPIO_PORT->DIR0 |= PINMASK)
Sissors 1:85a4a54f15e3 19 #define SET_MODE(pull) (pin_mode(pin, pull))
Sissors 1:85a4a54f15e3 20
Sissors 1:85a4a54f15e3 21 #define WRITE_PIN_SET (LPC_GPIO_PORT->SET0 = PINMASK)
Sissors 1:85a4a54f15e3 22 #define WRITE_PIN_CLR (LPC_GPIO_PORT->CLR0 = PINMASK)
Sissors 1:85a4a54f15e3 23
Sissors 1:85a4a54f15e3 24 #define READ_PIN ((*container.reg_in & container.mask) ? 1 : 0)
Sissors 1:85a4a54f15e3 25
Sissors 1:85a4a54f15e3 26 static int gpio_enabled = 0;
Sissors 1:85a4a54f15e3 27 static void gpio_enable(void)
Sissors 1:85a4a54f15e3 28 {
Sissors 1:85a4a54f15e3 29 if (!gpio_enabled) {
Sissors 1:85a4a54f15e3 30 gpio_enabled = 1;
Sissors 1:85a4a54f15e3 31
Sissors 1:85a4a54f15e3 32 /* Enable AHB clock to the GPIO domain. */
Sissors 1:85a4a54f15e3 33 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
Sissors 1:85a4a54f15e3 34
Sissors 1:85a4a54f15e3 35 /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */
Sissors 1:85a4a54f15e3 36 LPC_SYSCON->PRESETCTRL &= ~(0x1<<10);
Sissors 1:85a4a54f15e3 37 LPC_SYSCON->PRESETCTRL |= (0x1<<10);
Sissors 1:85a4a54f15e3 38 }
Sissors 1:85a4a54f15e3 39 }
Sissors 1:85a4a54f15e3 40
Sissors 1:85a4a54f15e3 41 #endif