Diff: i2c_mbed_fpga.cpp

Revision:

6:019ab407ac3c

Parent:

5:daab0e0e67e2

Child:

7:5fb0ad55b339

--- a/i2c_mbed_fpga.cpp	Fri Jan 22 14:06:54 2021 +0000
+++ b/i2c_mbed_fpga.cpp	Mon Jan 25 13:21:57 2021 +0000
@@ -1,37 +1,60 @@
 #include "mbed.h"
 #include "i2c_mbed_fpga.h"
+DigitalOut led3(LED3);
 
+/** i2c read from slave DUT
+*  retun 0 on success, otherwise fails
+*
+*  @param i2c_master specifies the i2c interface
+*  @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
+*/
+int i2c_mbed_fpga::i2c_word_read(char *word){
+    int ack = 0;
+    ack = i2c_master.write(I2C_SLAVE_ADDR, word, 2, true);  //restart
+    ack += i2c_master.read(I2C_SLAVE_ADDR, word+2, 2, false); //stop bit
+    wait_us(100); 
+    return (ack == 0) ? 0 : 1; 
+}
 
 /** i2c write to slave DUT
+*   ==> one time write, not read back check
 *
 *  @param i2c_master specifies the i2c interface
 *  @param word is considered as 4byte char data
 */
 int i2c_mbed_fpga::i2c_word_write(char *word){
-    int ack;
-    ack = i2c_master.write(i2c_slave_addr, word, 4, 0);
-    wait_us(100); 
+    int ack = 0;
+    ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
     return ack; 
 }
 
 
-/** i2c read from slave DUT
+/** i2c write to slave DUT
+*   ==> Safe write with 3 times read back check
 *
 *  @param i2c_master specifies the i2c interface
-*  @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
+*  @param word is considered as 4byte char data
 */
-int i2c_mbed_fpga::i2c_word_read(char *word){
-    int ack;
-    ack = i2c_master.write(i2c_slave_addr, word, 2, 1);
-    ack += i2c_master.read(i2c_slave_addr, word+2, 2, 0);
-    wait_us(100); 
-    return (ack == 0) ? 0 : 1; 
+int i2c_mbed_fpga::i2c_word_safe_write(char *word){
+    int ack = 0;
+    char readBuff[4];
+    std::copy(word, word+4, readBuff);
+    int i = 0;
+    do{
+        ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
+        wait_us(100);
+        ack +=i2c_word_read(readBuff);
+        wait_us(100);
+        if( *(readBuff+2) == *(word+2) && *(readBuff+3) == *(word+3) ){
+            ack++;
+            }
+        i++;
+    }while ( ack!=0 && i<3 );
+    return ack; 
 }
 
 
 /** i2c enter key to open I2C window
-*
-*  @param specifc key needed to enter i2c mode of DUT
 */
 int i2c_mbed_fpga::i2c_window_open(){
     char i2cKey[4] = {0x13, 0xA4, 0xD0, 0xD0};
@@ -39,10 +62,182 @@
 }
 
 /** i2c enter key to Start the motor
-*
-*  @param specifc key needed to enter i2c mode of DUT
 */
 int i2c_mbed_fpga::i2c_motor_start(){
     char i2cKey[4] = {0x13, 0xA4, 0xCA, 0xFE};
     return i2c_word_write(i2cKey);
 }
+
+/** i2c to set the Postion Pulse width
+*/
+int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
+    nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
+    nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_POSITION >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_POSITION >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_positin_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_positin_val >> 0)& 0xff;          
+    return i2c_word_safe_write(i2cMessage);
+}
+
+/** i2c to set the Postion Pulse duty cycle
+*/
+int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
+    nv_positin_val &= ~NV_POSITION_DUTY_MASK;
+    nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_POSITION >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_POSITION >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_positin_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_positin_val >> 0)& 0xff;          
+    return i2c_word_safe_write(i2cMessage);
+}
+
+/** i2c to enable the Postion Pulse majority volting
+*/
+int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
+    nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
+    nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_POSITION >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_POSITION >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_positin_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_positin_val >> 0)& 0xff;          
+    return i2c_word_safe_write(i2cMessage);
+}
+
+/** i2c to set the anti-cogging rotation direction
+*/
+int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
+    nv_positin_val &= ~NV_ANTI_COG_MASK;
+    nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_POSITION >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_POSITION >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_positin_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_positin_val >> 0)& 0xff;          
+    return i2c_word_safe_write(i2cMessage);
+}
+
+
+/** i2c to set the Start Up Pulse width (pulse train)
+*/
+int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
+    nv_start_up_val &= ~NV_START_UP_TIME_MASK;
+    nv_start_up_val |= ((exponent_3b << 2) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_START_UP >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_START_UP >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_start_up_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_start_up_val >> 0)& 0xff;          
+    return i2c_word_safe_write(i2cMessage);
+}
+
+/** i2c to set the Start up Pulse duty cycle (pulse train)
+*/
+int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
+    nv_start_up_val &= ~NV_START_DUTY_MASK;
+    nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_START_UP >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_START_UP >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_start_up_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_start_up_val >> 0)& 0xff;          
+    return i2c_word_safe_write(i2cMessage);
+}
+
+/** i2c to set the Start up commutation number of EHPs (pulse train)
+*/
+int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
+    nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
+    nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_START_UP >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_START_UP >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_start_up_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_start_up_val >> 0)& 0xff;          
+    return i2c_word_safe_write(i2cMessage);
+}
+
+/** i2c to set the Soft Start Up (pulse train)
+*/
+int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
+    int ack = 0;
+    nv_start_up_val &= ~NV_SOFT_START_MASK;
+    nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
+    nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
+    nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
+    nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
+    nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
+    nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
+    nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_POSITION >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_POSITION >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_positin_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_positin_val >> 0)& 0xff;  
+    ack += i2c_word_safe_write(i2cMessage);
+    
+    *(i2cMessage+0) = (NV_START_UP >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_START_UP >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_start_up_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_start_up_val >> 0)& 0xff;          
+    ack += i2c_word_safe_write(i2cMessage);
+    
+    *(i2cMessage+0) = (NV_WIND_BRAKE >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_WIND_BRAKE >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_wind_brake_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_wind_brake_val >> 0)& 0xff;          
+    ack += i2c_word_safe_write(i2cMessage);
+    
+    return ack; 
+}
+
+/** i2c to set the High Torque Start Up (pulse train)
+*/
+int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
+    int ack = 0;
+    nv_start_up_val &= ~NV_LONG_START_MASK;
+    nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
+    nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
+    nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_POSITION >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_POSITION >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_positin_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_positin_val >> 0)& 0xff;  
+    ack += i2c_word_safe_write(i2cMessage);
+    
+    *(i2cMessage+0) = (NV_START_UP >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_START_UP >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_start_up_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_start_up_val >> 0)& 0xff;          
+    ack += i2c_word_safe_write(i2cMessage);
+        
+    return ack; 
+}
+
+/** i2c to set the Single Pulse Start Up (pulse train)
+*/
+int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
+    int ack = 0;
+    nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
+    nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
+    nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
+    nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
+    char i2cMessage[4];
+    *(i2cMessage+0) = (NV_POSITION >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_POSITION >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_positin_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_positin_val >> 0)& 0xff;  
+    ack += i2c_word_safe_write(i2cMessage);
+    
+    *(i2cMessage+0) = (NV_START_UP >> 8)& 0xff;
+    *(i2cMessage+1) = (NV_START_UP >> 0)& 0xff;
+    *(i2cMessage+2) = (nv_start_up_val >> 8)& 0xff;
+    *(i2cMessage+3) = (nv_start_up_val >> 0)& 0xff;          
+    ack += i2c_word_safe_write(i2cMessage);
+        
+    return ack; 
+}
\ No newline at end of file