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Dependencies:   FastPWM3 mbed

PreferenceWriter/stm32f4xx_flash.c@178:4e721c904fd7, 2018-02-08 (annotated)

Committer:
bwang
Date:
Thu Feb 08 02:16:04 2018 +0000
Revision:
178:4e721c904fd7
02/07/2018 21:15 - moved PreferenceWriter and prefs.h back from test project, code still compiles

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bwang 178:4e721c904fd7 1 /**
bwang 178:4e721c904fd7 2 ******************************************************************************
bwang 178:4e721c904fd7 3 * @file stm32f4xx_flash.c
bwang 178:4e721c904fd7 4 * @author MCD Application Team
bwang 178:4e721c904fd7 5 * @version V1.7.1
bwang 178:4e721c904fd7 6 * @date 20-May-2016
bwang 178:4e721c904fd7 7 * @brief This file provides firmware functions to manage the following
bwang 178:4e721c904fd7 8 * functionalities of the FLASH peripheral:
bwang 178:4e721c904fd7 9 * + FLASH Interface configuration
bwang 178:4e721c904fd7 10 * + FLASH Memory Programming
bwang 178:4e721c904fd7 11 * + Option Bytes Programming
bwang 178:4e721c904fd7 12 * + Interrupts and flags management
bwang 178:4e721c904fd7 13 *
bwang 178:4e721c904fd7 14 @verbatim
bwang 178:4e721c904fd7 15 ===============================================================================
bwang 178:4e721c904fd7 16 ##### How to use this driver #####
bwang 178:4e721c904fd7 17 ===============================================================================
bwang 178:4e721c904fd7 18 [..]
bwang 178:4e721c904fd7 19 This driver provides functions to configure and program the FLASH memory
bwang 178:4e721c904fd7 20 of all STM32F4xx devices. These functions are split in 4 groups:
bwang 178:4e721c904fd7 21
bwang 178:4e721c904fd7 22 (#) FLASH Interface configuration functions: this group includes the
bwang 178:4e721c904fd7 23 management of the following features:
bwang 178:4e721c904fd7 24 (++) Set the latency
bwang 178:4e721c904fd7 25 (++) Enable/Disable the prefetch buffer
bwang 178:4e721c904fd7 26 (++) Enable/Disable the Instruction cache and the Data cache
bwang 178:4e721c904fd7 27 (++) Reset the Instruction cache and the Data cache
bwang 178:4e721c904fd7 28
bwang 178:4e721c904fd7 29 (#) FLASH Memory Programming functions: this group includes all needed
bwang 178:4e721c904fd7 30 functions to erase and program the main memory:
bwang 178:4e721c904fd7 31 (++) Lock and Unlock the FLASH interface
bwang 178:4e721c904fd7 32 (++) Erase function: Erase sector, erase all sectors
bwang 178:4e721c904fd7 33 (++) Program functions: byte, half word, word and double word
bwang 178:4e721c904fd7 34
bwang 178:4e721c904fd7 35 (#) Option Bytes Programming functions: this group includes all needed
bwang 178:4e721c904fd7 36 functions to manage the Option Bytes:
bwang 178:4e721c904fd7 37 (++) Set/Reset the write protection
bwang 178:4e721c904fd7 38 (++) Set the Read protection Level
bwang 178:4e721c904fd7 39 (++) Set the BOR level
bwang 178:4e721c904fd7 40 (++) Program the user Option Bytes
bwang 178:4e721c904fd7 41 (++) Launch the Option Bytes loader
bwang 178:4e721c904fd7 42
bwang 178:4e721c904fd7 43 (#) Interrupts and flags management functions: this group
bwang 178:4e721c904fd7 44 includes all needed functions to:
bwang 178:4e721c904fd7 45 (++) Enable/Disable the FLASH interrupt sources
bwang 178:4e721c904fd7 46 (++) Get flags status
bwang 178:4e721c904fd7 47 (++) Clear flags
bwang 178:4e721c904fd7 48 (++) Get FLASH operation status
bwang 178:4e721c904fd7 49 (++) Wait for last FLASH operation
bwang 178:4e721c904fd7 50 @endverbatim
bwang 178:4e721c904fd7 51 ******************************************************************************
bwang 178:4e721c904fd7 52 * @attention
bwang 178:4e721c904fd7 53 *
bwang 178:4e721c904fd7 54 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
bwang 178:4e721c904fd7 55 *
bwang 178:4e721c904fd7 56 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
bwang 178:4e721c904fd7 57 * You may not use this file except in compliance with the License.
bwang 178:4e721c904fd7 58 * You may obtain a copy of the License at:
bwang 178:4e721c904fd7 59 *
bwang 178:4e721c904fd7 60 * http://www.st.com/software_license_agreement_liberty_v2
bwang 178:4e721c904fd7 61 *
bwang 178:4e721c904fd7 62 * Unless required by applicable law or agreed to in writing, software
bwang 178:4e721c904fd7 63 * distributed under the License is distributed on an "AS IS" BASIS,
bwang 178:4e721c904fd7 64 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bwang 178:4e721c904fd7 65 * See the License for the specific language governing permissions and
bwang 178:4e721c904fd7 66 * limitations under the License.
bwang 178:4e721c904fd7 67 *
bwang 178:4e721c904fd7 68 ******************************************************************************
bwang 178:4e721c904fd7 69 */
bwang 178:4e721c904fd7 70
bwang 178:4e721c904fd7 71 /* Includes ------------------------------------------------------------------*/
bwang 178:4e721c904fd7 72 #include "stm32f4xx_flash.h"
bwang 178:4e721c904fd7 73
bwang 178:4e721c904fd7 74 /** @addtogroup STM32F4xx_StdPeriph_Driver
bwang 178:4e721c904fd7 75 * @{
bwang 178:4e721c904fd7 76 */
bwang 178:4e721c904fd7 77
bwang 178:4e721c904fd7 78 /** @defgroup FLASH
bwang 178:4e721c904fd7 79 * @brief FLASH driver modules
bwang 178:4e721c904fd7 80 * @{
bwang 178:4e721c904fd7 81 */
bwang 178:4e721c904fd7 82
bwang 178:4e721c904fd7 83 /* Private typedef -----------------------------------------------------------*/
bwang 178:4e721c904fd7 84 /* Private define ------------------------------------------------------------*/
bwang 178:4e721c904fd7 85 #define SECTOR_MASK ((uint32_t)0xFFFFFF07)
bwang 178:4e721c904fd7 86
bwang 178:4e721c904fd7 87 /* Private macro -------------------------------------------------------------*/
bwang 178:4e721c904fd7 88 /* Private variables ---------------------------------------------------------*/
bwang 178:4e721c904fd7 89 /* Private function prototypes -----------------------------------------------*/
bwang 178:4e721c904fd7 90 /* Private functions ---------------------------------------------------------*/
bwang 178:4e721c904fd7 91
bwang 178:4e721c904fd7 92 /** @defgroup FLASH_Private_Functions
bwang 178:4e721c904fd7 93 * @{
bwang 178:4e721c904fd7 94 */
bwang 178:4e721c904fd7 95
bwang 178:4e721c904fd7 96 /** @defgroup FLASH_Group1 FLASH Interface configuration functions
bwang 178:4e721c904fd7 97 * @brief FLASH Interface configuration functions
bwang 178:4e721c904fd7 98 *
bwang 178:4e721c904fd7 99
bwang 178:4e721c904fd7 100 @verbatim
bwang 178:4e721c904fd7 101 ===============================================================================
bwang 178:4e721c904fd7 102 ##### FLASH Interface configuration functions #####
bwang 178:4e721c904fd7 103 ===============================================================================
bwang 178:4e721c904fd7 104 [..]
bwang 178:4e721c904fd7 105 This group includes the following functions:
bwang 178:4e721c904fd7 106 (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
bwang 178:4e721c904fd7 107 To correctly read data from FLASH memory, the number of wait states (LATENCY)
bwang 178:4e721c904fd7 108 must be correctly programmed according to the frequency of the CPU clock
bwang 178:4e721c904fd7 109 (HCLK) and the supply voltage of the device.
bwang 178:4e721c904fd7 110 [..]
bwang 178:4e721c904fd7 111 For STM32F405xx/07xx and STM32F415xx/17xx devices
bwang 178:4e721c904fd7 112 +-------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 113 | Latency | HCLK clock frequency (MHz) |
bwang 178:4e721c904fd7 114 | |---------------------------------------------------------------------|
bwang 178:4e721c904fd7 115 | | voltage range | voltage range | voltage range | voltage range |
bwang 178:4e721c904fd7 116 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 178:4e721c904fd7 117 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 118 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
bwang 178:4e721c904fd7 119 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 120 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
bwang 178:4e721c904fd7 121 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 122 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
bwang 178:4e721c904fd7 123 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 124 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
bwang 178:4e721c904fd7 125 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 126 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
bwang 178:4e721c904fd7 127 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 128 |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
bwang 178:4e721c904fd7 129 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 130 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
bwang 178:4e721c904fd7 131 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 132 |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
bwang 178:4e721c904fd7 133 +---------------|----------------|----------------|-----------------|-----------------+
bwang 178:4e721c904fd7 134
bwang 178:4e721c904fd7 135 [..]
bwang 178:4e721c904fd7 136 For STM32F42xxx/43xxx devices
bwang 178:4e721c904fd7 137 +-------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 138 | Latency | HCLK clock frequency (MHz) |
bwang 178:4e721c904fd7 139 | |---------------------------------------------------------------------|
bwang 178:4e721c904fd7 140 | | voltage range | voltage range | voltage range | voltage range |
bwang 178:4e721c904fd7 141 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 178:4e721c904fd7 142 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 143 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
bwang 178:4e721c904fd7 144 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 145 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
bwang 178:4e721c904fd7 146 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 147 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
bwang 178:4e721c904fd7 148 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 149 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
bwang 178:4e721c904fd7 150 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 151 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
bwang 178:4e721c904fd7 152 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 153 |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
bwang 178:4e721c904fd7 154 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 155 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
bwang 178:4e721c904fd7 156 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 157 |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
bwang 178:4e721c904fd7 158 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 159 |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
bwang 178:4e721c904fd7 160 +-------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 161
bwang 178:4e721c904fd7 162 [..]
bwang 178:4e721c904fd7 163 For STM32F401x devices
bwang 178:4e721c904fd7 164 +-------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 165 | Latency | HCLK clock frequency (MHz) |
bwang 178:4e721c904fd7 166 | |---------------------------------------------------------------------|
bwang 178:4e721c904fd7 167 | | voltage range | voltage range | voltage range | voltage range |
bwang 178:4e721c904fd7 168 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 178:4e721c904fd7 169 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 170 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
bwang 178:4e721c904fd7 171 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 172 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
bwang 178:4e721c904fd7 173 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 174 |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
bwang 178:4e721c904fd7 175 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 176 |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
bwang 178:4e721c904fd7 177 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 178 |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
bwang 178:4e721c904fd7 179 +-------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 180
bwang 178:4e721c904fd7 181 [..]
bwang 178:4e721c904fd7 182 For STM32F410xx/STM32F411xE devices
bwang 178:4e721c904fd7 183 +-------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 184 | Latency | HCLK clock frequency (MHz) |
bwang 178:4e721c904fd7 185 | |---------------------------------------------------------------------|
bwang 178:4e721c904fd7 186 | | voltage range | voltage range | voltage range | voltage range |
bwang 178:4e721c904fd7 187 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 178:4e721c904fd7 188 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 189 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
bwang 178:4e721c904fd7 190 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 191 |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
bwang 178:4e721c904fd7 192 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 193 |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
bwang 178:4e721c904fd7 194 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 195 |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
bwang 178:4e721c904fd7 196 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 197 |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
bwang 178:4e721c904fd7 198 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 199 |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
bwang 178:4e721c904fd7 200 |---------------|----------------|----------------|-----------------|-----------------|
bwang 178:4e721c904fd7 201 |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
bwang 178:4e721c904fd7 202 +-------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 203
bwang 178:4e721c904fd7 204 [..]
bwang 178:4e721c904fd7 205 +-------------------------------------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 206 | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
bwang 178:4e721c904fd7 207 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
bwang 178:4e721c904fd7 208 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
bwang 178:4e721c904fd7 209 |Max Parallelism| x32 | x16 | x8 | x64 |
bwang 178:4e721c904fd7 210 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
bwang 178:4e721c904fd7 211 |PSIZE[1:0] | 10 | 01 | 00 | 11 |
bwang 178:4e721c904fd7 212 +-------------------------------------------------------------------------------------------------------------------+
bwang 178:4e721c904fd7 213
bwang 178:4e721c904fd7 214 -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
bwang 178:4e721c904fd7 215 (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
bwang 178:4e721c904fd7 216 (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
bwang 178:4e721c904fd7 217 [..]
bwang 178:4e721c904fd7 218 On STM32F42xxx/43xxx devices:
bwang 178:4e721c904fd7 219 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
bwang 178:4e721c904fd7 220 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
bwang 178:4e721c904fd7 221 (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
bwang 178:4e721c904fd7 222 [..]
bwang 178:4e721c904fd7 223 On STM32F401x devices:
bwang 178:4e721c904fd7 224 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
bwang 178:4e721c904fd7 225 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
bwang 178:4e721c904fd7 226 [..]
bwang 178:4e721c904fd7 227 On STM32F410xx/STM32F411xE devices:
bwang 178:4e721c904fd7 228 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
bwang 178:4e721c904fd7 229 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
bwang 178:4e721c904fd7 230 (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
bwang 178:4e721c904fd7 231
bwang 178:4e721c904fd7 232 For more details please refer product DataSheet
bwang 178:4e721c904fd7 233 You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
bwang 178:4e721c904fd7 234
bwang 178:4e721c904fd7 235 (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
bwang 178:4e721c904fd7 236 (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
bwang 178:4e721c904fd7 237 (+) void FLASH_DataCacheCmd(FunctionalState NewState)
bwang 178:4e721c904fd7 238 (+) void FLASH_InstructionCacheReset(void)
bwang 178:4e721c904fd7 239 (+) void FLASH_DataCacheReset(void)
bwang 178:4e721c904fd7 240
bwang 178:4e721c904fd7 241 [..]
bwang 178:4e721c904fd7 242 The unlock sequence is not needed for these functions.
bwang 178:4e721c904fd7 243
bwang 178:4e721c904fd7 244 @endverbatim
bwang 178:4e721c904fd7 245 * @{
bwang 178:4e721c904fd7 246 */
bwang 178:4e721c904fd7 247
bwang 178:4e721c904fd7 248 /**
bwang 178:4e721c904fd7 249 * @brief Sets the code latency value.
bwang 178:4e721c904fd7 250 * @param FLASH_Latency: specifies the FLASH Latency value.
bwang 178:4e721c904fd7 251 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 252 * @arg FLASH_Latency_0: FLASH Zero Latency cycle
bwang 178:4e721c904fd7 253 * @arg FLASH_Latency_1: FLASH One Latency cycle
bwang 178:4e721c904fd7 254 * @arg FLASH_Latency_2: FLASH Two Latency cycles
bwang 178:4e721c904fd7 255 * @arg FLASH_Latency_3: FLASH Three Latency cycles
bwang 178:4e721c904fd7 256 * @arg FLASH_Latency_4: FLASH Four Latency cycles
bwang 178:4e721c904fd7 257 * @arg FLASH_Latency_5: FLASH Five Latency cycles
bwang 178:4e721c904fd7 258 * @arg FLASH_Latency_6: FLASH Six Latency cycles
bwang 178:4e721c904fd7 259 * @arg FLASH_Latency_7: FLASH Seven Latency cycles
bwang 178:4e721c904fd7 260 * @arg FLASH_Latency_8: FLASH Eight Latency cycles
bwang 178:4e721c904fd7 261 * @arg FLASH_Latency_9: FLASH Nine Latency cycles
bwang 178:4e721c904fd7 262 * @arg FLASH_Latency_10: FLASH Teen Latency cycles
bwang 178:4e721c904fd7 263 * @arg FLASH_Latency_11: FLASH Eleven Latency cycles
bwang 178:4e721c904fd7 264 * @arg FLASH_Latency_12: FLASH Twelve Latency cycles
bwang 178:4e721c904fd7 265 * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
bwang 178:4e721c904fd7 266 * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
bwang 178:4e721c904fd7 267 * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
bwang 178:4e721c904fd7 268 *
bwang 178:4e721c904fd7 269 * @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE and STM32F412xG devices
bwang 178:4e721c904fd7 270 * this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
bwang 178:4e721c904fd7 271 *
bwang 178:4e721c904fd7 272 * @note For STM32F42xxx/43xxx devices this parameter can be a value between
bwang 178:4e721c904fd7 273 * FLASH_Latency_0 and FLASH_Latency_15.
bwang 178:4e721c904fd7 274 *
bwang 178:4e721c904fd7 275 * @retval None
bwang 178:4e721c904fd7 276 */
bwang 178:4e721c904fd7 277 void FLASH_SetLatency(uint32_t FLASH_Latency)
bwang 178:4e721c904fd7 278 {
bwang 178:4e721c904fd7 279 /* Check the parameters */
bwang 178:4e721c904fd7 280 assert_param(IS_FLASH_LATENCY(FLASH_Latency));
bwang 178:4e721c904fd7 281
bwang 178:4e721c904fd7 282 /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
bwang 178:4e721c904fd7 283 *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
bwang 178:4e721c904fd7 284 }
bwang 178:4e721c904fd7 285
bwang 178:4e721c904fd7 286 /**
bwang 178:4e721c904fd7 287 * @brief Enables or disables the Prefetch Buffer.
bwang 178:4e721c904fd7 288 * @param NewState: new state of the Prefetch Buffer.
bwang 178:4e721c904fd7 289 * This parameter can be: ENABLE or DISABLE.
bwang 178:4e721c904fd7 290 * @retval None
bwang 178:4e721c904fd7 291 */
bwang 178:4e721c904fd7 292 void FLASH_PrefetchBufferCmd(FunctionalState NewState)
bwang 178:4e721c904fd7 293 {
bwang 178:4e721c904fd7 294 /* Check the parameters */
bwang 178:4e721c904fd7 295 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 296
bwang 178:4e721c904fd7 297 /* Enable or disable the Prefetch Buffer */
bwang 178:4e721c904fd7 298 if(NewState != DISABLE)
bwang 178:4e721c904fd7 299 {
bwang 178:4e721c904fd7 300 FLASH->ACR |= FLASH_ACR_PRFTEN;
bwang 178:4e721c904fd7 301 }
bwang 178:4e721c904fd7 302 else
bwang 178:4e721c904fd7 303 {
bwang 178:4e721c904fd7 304 FLASH->ACR &= (~FLASH_ACR_PRFTEN);
bwang 178:4e721c904fd7 305 }
bwang 178:4e721c904fd7 306 }
bwang 178:4e721c904fd7 307
bwang 178:4e721c904fd7 308 /**
bwang 178:4e721c904fd7 309 * @brief Enables or disables the Instruction Cache feature.
bwang 178:4e721c904fd7 310 * @param NewState: new state of the Instruction Cache.
bwang 178:4e721c904fd7 311 * This parameter can be: ENABLE or DISABLE.
bwang 178:4e721c904fd7 312 * @retval None
bwang 178:4e721c904fd7 313 */
bwang 178:4e721c904fd7 314 void FLASH_InstructionCacheCmd(FunctionalState NewState)
bwang 178:4e721c904fd7 315 {
bwang 178:4e721c904fd7 316 /* Check the parameters */
bwang 178:4e721c904fd7 317 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 318
bwang 178:4e721c904fd7 319 if(NewState != DISABLE)
bwang 178:4e721c904fd7 320 {
bwang 178:4e721c904fd7 321 FLASH->ACR |= FLASH_ACR_ICEN;
bwang 178:4e721c904fd7 322 }
bwang 178:4e721c904fd7 323 else
bwang 178:4e721c904fd7 324 {
bwang 178:4e721c904fd7 325 FLASH->ACR &= (~FLASH_ACR_ICEN);
bwang 178:4e721c904fd7 326 }
bwang 178:4e721c904fd7 327 }
bwang 178:4e721c904fd7 328
bwang 178:4e721c904fd7 329 /**
bwang 178:4e721c904fd7 330 * @brief Enables or disables the Data Cache feature.
bwang 178:4e721c904fd7 331 * @param NewState: new state of the Data Cache.
bwang 178:4e721c904fd7 332 * This parameter can be: ENABLE or DISABLE.
bwang 178:4e721c904fd7 333 * @retval None
bwang 178:4e721c904fd7 334 */
bwang 178:4e721c904fd7 335 void FLASH_DataCacheCmd(FunctionalState NewState)
bwang 178:4e721c904fd7 336 {
bwang 178:4e721c904fd7 337 /* Check the parameters */
bwang 178:4e721c904fd7 338 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 339
bwang 178:4e721c904fd7 340 if(NewState != DISABLE)
bwang 178:4e721c904fd7 341 {
bwang 178:4e721c904fd7 342 FLASH->ACR |= FLASH_ACR_DCEN;
bwang 178:4e721c904fd7 343 }
bwang 178:4e721c904fd7 344 else
bwang 178:4e721c904fd7 345 {
bwang 178:4e721c904fd7 346 FLASH->ACR &= (~FLASH_ACR_DCEN);
bwang 178:4e721c904fd7 347 }
bwang 178:4e721c904fd7 348 }
bwang 178:4e721c904fd7 349
bwang 178:4e721c904fd7 350 /**
bwang 178:4e721c904fd7 351 * @brief Resets the Instruction Cache.
bwang 178:4e721c904fd7 352 * @note This function must be used only when the Instruction Cache is disabled.
bwang 178:4e721c904fd7 353 * @param None
bwang 178:4e721c904fd7 354 * @retval None
bwang 178:4e721c904fd7 355 */
bwang 178:4e721c904fd7 356 void FLASH_InstructionCacheReset(void)
bwang 178:4e721c904fd7 357 {
bwang 178:4e721c904fd7 358 FLASH->ACR |= FLASH_ACR_ICRST;
bwang 178:4e721c904fd7 359 }
bwang 178:4e721c904fd7 360
bwang 178:4e721c904fd7 361 /**
bwang 178:4e721c904fd7 362 * @brief Resets the Data Cache.
bwang 178:4e721c904fd7 363 * @note This function must be used only when the Data Cache is disabled.
bwang 178:4e721c904fd7 364 * @param None
bwang 178:4e721c904fd7 365 * @retval None
bwang 178:4e721c904fd7 366 */
bwang 178:4e721c904fd7 367 void FLASH_DataCacheReset(void)
bwang 178:4e721c904fd7 368 {
bwang 178:4e721c904fd7 369 FLASH->ACR |= FLASH_ACR_DCRST;
bwang 178:4e721c904fd7 370 }
bwang 178:4e721c904fd7 371
bwang 178:4e721c904fd7 372 /**
bwang 178:4e721c904fd7 373 * @}
bwang 178:4e721c904fd7 374 */
bwang 178:4e721c904fd7 375
bwang 178:4e721c904fd7 376 /** @defgroup FLASH_Group2 FLASH Memory Programming functions
bwang 178:4e721c904fd7 377 * @brief FLASH Memory Programming functions
bwang 178:4e721c904fd7 378 *
bwang 178:4e721c904fd7 379 @verbatim
bwang 178:4e721c904fd7 380 ===============================================================================
bwang 178:4e721c904fd7 381 ##### FLASH Memory Programming functions #####
bwang 178:4e721c904fd7 382 ===============================================================================
bwang 178:4e721c904fd7 383 [..]
bwang 178:4e721c904fd7 384 This group includes the following functions:
bwang 178:4e721c904fd7 385 (+) void FLASH_Unlock(void)
bwang 178:4e721c904fd7 386 (+) void FLASH_Lock(void)
bwang 178:4e721c904fd7 387 (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
bwang 178:4e721c904fd7 388 (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
bwang 178:4e721c904fd7 389 (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
bwang 178:4e721c904fd7 390 (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
bwang 178:4e721c904fd7 391 (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
bwang 178:4e721c904fd7 392 (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
bwang 178:4e721c904fd7 393 The following functions can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 394 (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
bwang 178:4e721c904fd7 395 (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
bwang 178:4e721c904fd7 396 [..]
bwang 178:4e721c904fd7 397 Any operation of erase or program should follow these steps:
bwang 178:4e721c904fd7 398 (#) Call the FLASH_Unlock() function to enable the FLASH control register access
bwang 178:4e721c904fd7 399
bwang 178:4e721c904fd7 400 (#) Call the desired function to erase sector(s) or program data
bwang 178:4e721c904fd7 401
bwang 178:4e721c904fd7 402 (#) Call the FLASH_Lock() function to disable the FLASH control register access
bwang 178:4e721c904fd7 403 (recommended to protect the FLASH memory against possible unwanted operation)
bwang 178:4e721c904fd7 404
bwang 178:4e721c904fd7 405 @endverbatim
bwang 178:4e721c904fd7 406 * @{
bwang 178:4e721c904fd7 407 */
bwang 178:4e721c904fd7 408
bwang 178:4e721c904fd7 409 /**
bwang 178:4e721c904fd7 410 * @brief Unlocks the FLASH control register access
bwang 178:4e721c904fd7 411 * @param None
bwang 178:4e721c904fd7 412 * @retval None
bwang 178:4e721c904fd7 413 */
bwang 178:4e721c904fd7 414 void FLASH_Unlock(void)
bwang 178:4e721c904fd7 415 {
bwang 178:4e721c904fd7 416 if((FLASH->CR & FLASH_CR_LOCK) != RESET)
bwang 178:4e721c904fd7 417 {
bwang 178:4e721c904fd7 418 /* Authorize the FLASH Registers access */
bwang 178:4e721c904fd7 419 FLASH->KEYR = FLASH_KEY1;
bwang 178:4e721c904fd7 420 FLASH->KEYR = FLASH_KEY2;
bwang 178:4e721c904fd7 421 }
bwang 178:4e721c904fd7 422 }
bwang 178:4e721c904fd7 423
bwang 178:4e721c904fd7 424 /**
bwang 178:4e721c904fd7 425 * @brief Locks the FLASH control register access
bwang 178:4e721c904fd7 426 * @param None
bwang 178:4e721c904fd7 427 * @retval None
bwang 178:4e721c904fd7 428 */
bwang 178:4e721c904fd7 429 void FLASH_Lock(void)
bwang 178:4e721c904fd7 430 {
bwang 178:4e721c904fd7 431 /* Set the LOCK Bit to lock the FLASH Registers access */
bwang 178:4e721c904fd7 432 FLASH->CR |= FLASH_CR_LOCK;
bwang 178:4e721c904fd7 433 }
bwang 178:4e721c904fd7 434
bwang 178:4e721c904fd7 435 /**
bwang 178:4e721c904fd7 436 * @brief Erases a specified FLASH Sector.
bwang 178:4e721c904fd7 437 *
bwang 178:4e721c904fd7 438 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 439 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 440 *
bwang 178:4e721c904fd7 441 * @param FLASH_Sector: The Sector number to be erased.
bwang 178:4e721c904fd7 442 *
bwang 178:4e721c904fd7 443 * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
bwang 178:4e721c904fd7 444 * be a value between FLASH_Sector_0 and FLASH_Sector_11.
bwang 178:4e721c904fd7 445 *
bwang 178:4e721c904fd7 446 * For STM32F42xxx/43xxx devices this parameter can be a value between
bwang 178:4e721c904fd7 447 * FLASH_Sector_0 and FLASH_Sector_23.
bwang 178:4e721c904fd7 448 *
bwang 178:4e721c904fd7 449 * For STM32F401xx devices this parameter can be a value between
bwang 178:4e721c904fd7 450 * FLASH_Sector_0 and FLASH_Sector_5.
bwang 178:4e721c904fd7 451 *
bwang 178:4e721c904fd7 452 * For STM32F411xE and STM32F412xG devices this parameter can be a value between
bwang 178:4e721c904fd7 453 * FLASH_Sector_0 and FLASH_Sector_7.
bwang 178:4e721c904fd7 454 *
bwang 178:4e721c904fd7 455 * For STM32F410xx devices this parameter can be a value between
bwang 178:4e721c904fd7 456 * FLASH_Sector_0 and FLASH_Sector_4.
bwang 178:4e721c904fd7 457 *
bwang 178:4e721c904fd7 458 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 178:4e721c904fd7 459 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 460 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 178:4e721c904fd7 461 * the operation will be done by byte (8-bit)
bwang 178:4e721c904fd7 462 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 178:4e721c904fd7 463 * the operation will be done by half word (16-bit)
bwang 178:4e721c904fd7 464 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 178:4e721c904fd7 465 * the operation will be done by word (32-bit)
bwang 178:4e721c904fd7 466 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 178:4e721c904fd7 467 * the operation will be done by double word (64-bit)
bwang 178:4e721c904fd7 468 *
bwang 178:4e721c904fd7 469 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 470 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 471 */
bwang 178:4e721c904fd7 472 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
bwang 178:4e721c904fd7 473 {
bwang 178:4e721c904fd7 474 uint32_t tmp_psize = 0x0;
bwang 178:4e721c904fd7 475 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 476
bwang 178:4e721c904fd7 477 /* Check the parameters */
bwang 178:4e721c904fd7 478 assert_param(IS_FLASH_SECTOR(FLASH_Sector));
bwang 178:4e721c904fd7 479 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 178:4e721c904fd7 480
bwang 178:4e721c904fd7 481 if(VoltageRange == VoltageRange_1)
bwang 178:4e721c904fd7 482 {
bwang 178:4e721c904fd7 483 tmp_psize = FLASH_PSIZE_BYTE;
bwang 178:4e721c904fd7 484 }
bwang 178:4e721c904fd7 485 else if(VoltageRange == VoltageRange_2)
bwang 178:4e721c904fd7 486 {
bwang 178:4e721c904fd7 487 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 178:4e721c904fd7 488 }
bwang 178:4e721c904fd7 489 else if(VoltageRange == VoltageRange_3)
bwang 178:4e721c904fd7 490 {
bwang 178:4e721c904fd7 491 tmp_psize = FLASH_PSIZE_WORD;
bwang 178:4e721c904fd7 492 }
bwang 178:4e721c904fd7 493 else
bwang 178:4e721c904fd7 494 {
bwang 178:4e721c904fd7 495 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 178:4e721c904fd7 496 }
bwang 178:4e721c904fd7 497 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 498 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 499
bwang 178:4e721c904fd7 500 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 501 {
bwang 178:4e721c904fd7 502 /* if the previous operation is completed, proceed to erase the sector */
bwang 178:4e721c904fd7 503 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 504 FLASH->CR |= tmp_psize;
bwang 178:4e721c904fd7 505 FLASH->CR &= SECTOR_MASK;
bwang 178:4e721c904fd7 506 FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
bwang 178:4e721c904fd7 507 FLASH->CR |= FLASH_CR_STRT;
bwang 178:4e721c904fd7 508
bwang 178:4e721c904fd7 509 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 510 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 511
bwang 178:4e721c904fd7 512 /* if the erase operation is completed, disable the SER Bit */
bwang 178:4e721c904fd7 513 FLASH->CR &= (~FLASH_CR_SER);
bwang 178:4e721c904fd7 514 FLASH->CR &= SECTOR_MASK;
bwang 178:4e721c904fd7 515 }
bwang 178:4e721c904fd7 516 /* Return the Erase Status */
bwang 178:4e721c904fd7 517 return status;
bwang 178:4e721c904fd7 518 }
bwang 178:4e721c904fd7 519
bwang 178:4e721c904fd7 520 /**
bwang 178:4e721c904fd7 521 * @brief Erases all FLASH Sectors.
bwang 178:4e721c904fd7 522 *
bwang 178:4e721c904fd7 523 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 524 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 525 *
bwang 178:4e721c904fd7 526 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 178:4e721c904fd7 527 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 528 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 178:4e721c904fd7 529 * the operation will be done by byte (8-bit)
bwang 178:4e721c904fd7 530 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 178:4e721c904fd7 531 * the operation will be done by half word (16-bit)
bwang 178:4e721c904fd7 532 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 178:4e721c904fd7 533 * the operation will be done by word (32-bit)
bwang 178:4e721c904fd7 534 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 178:4e721c904fd7 535 * the operation will be done by double word (64-bit)
bwang 178:4e721c904fd7 536 *
bwang 178:4e721c904fd7 537 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 538 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 539 */
bwang 178:4e721c904fd7 540 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
bwang 178:4e721c904fd7 541 {
bwang 178:4e721c904fd7 542 uint32_t tmp_psize = 0x0;
bwang 178:4e721c904fd7 543 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 544
bwang 178:4e721c904fd7 545 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 546 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 547 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 178:4e721c904fd7 548
bwang 178:4e721c904fd7 549 if(VoltageRange == VoltageRange_1)
bwang 178:4e721c904fd7 550 {
bwang 178:4e721c904fd7 551 tmp_psize = FLASH_PSIZE_BYTE;
bwang 178:4e721c904fd7 552 }
bwang 178:4e721c904fd7 553 else if(VoltageRange == VoltageRange_2)
bwang 178:4e721c904fd7 554 {
bwang 178:4e721c904fd7 555 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 178:4e721c904fd7 556 }
bwang 178:4e721c904fd7 557 else if(VoltageRange == VoltageRange_3)
bwang 178:4e721c904fd7 558 {
bwang 178:4e721c904fd7 559 tmp_psize = FLASH_PSIZE_WORD;
bwang 178:4e721c904fd7 560 }
bwang 178:4e721c904fd7 561 else
bwang 178:4e721c904fd7 562 {
bwang 178:4e721c904fd7 563 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 178:4e721c904fd7 564 }
bwang 178:4e721c904fd7 565 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 566 {
bwang 178:4e721c904fd7 567 /* if the previous operation is completed, proceed to erase all sectors */
bwang 178:4e721c904fd7 568 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
bwang 178:4e721c904fd7 569 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 570 FLASH->CR |= tmp_psize;
bwang 178:4e721c904fd7 571 FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
bwang 178:4e721c904fd7 572 FLASH->CR |= FLASH_CR_STRT;
bwang 178:4e721c904fd7 573
bwang 178:4e721c904fd7 574 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 575 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 576
bwang 178:4e721c904fd7 577 /* if the erase operation is completed, disable the MER Bit */
bwang 178:4e721c904fd7 578 FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
bwang 178:4e721c904fd7 579 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
bwang 178:4e721c904fd7 580
bwang 178:4e721c904fd7 581 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F446xx)
bwang 178:4e721c904fd7 582 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 583 FLASH->CR |= tmp_psize;
bwang 178:4e721c904fd7 584 FLASH->CR |= FLASH_CR_MER;
bwang 178:4e721c904fd7 585 FLASH->CR |= FLASH_CR_STRT;
bwang 178:4e721c904fd7 586
bwang 178:4e721c904fd7 587 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 588 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 589
bwang 178:4e721c904fd7 590 /* if the erase operation is completed, disable the MER Bit */
bwang 178:4e721c904fd7 591 FLASH->CR &= (~FLASH_CR_MER);
bwang 178:4e721c904fd7 592 #endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F446xx */
bwang 178:4e721c904fd7 593
bwang 178:4e721c904fd7 594 }
bwang 178:4e721c904fd7 595 /* Return the Erase Status */
bwang 178:4e721c904fd7 596 return status;
bwang 178:4e721c904fd7 597 }
bwang 178:4e721c904fd7 598
bwang 178:4e721c904fd7 599 /**
bwang 178:4e721c904fd7 600 * @brief Erases all FLASH Sectors in Bank 1.
bwang 178:4e721c904fd7 601 *
bwang 178:4e721c904fd7 602 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 603 *
bwang 178:4e721c904fd7 604 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 605 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 606 *
bwang 178:4e721c904fd7 607 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 178:4e721c904fd7 608 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 609 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 178:4e721c904fd7 610 * the operation will be done by byte (8-bit)
bwang 178:4e721c904fd7 611 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 178:4e721c904fd7 612 * the operation will be done by half word (16-bit)
bwang 178:4e721c904fd7 613 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 178:4e721c904fd7 614 * the operation will be done by word (32-bit)
bwang 178:4e721c904fd7 615 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 178:4e721c904fd7 616 * the operation will be done by double word (64-bit)
bwang 178:4e721c904fd7 617 *
bwang 178:4e721c904fd7 618 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 619 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 620 */
bwang 178:4e721c904fd7 621 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
bwang 178:4e721c904fd7 622 {
bwang 178:4e721c904fd7 623 uint32_t tmp_psize = 0x0;
bwang 178:4e721c904fd7 624 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 625
bwang 178:4e721c904fd7 626 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 627 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 628 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 178:4e721c904fd7 629
bwang 178:4e721c904fd7 630 if(VoltageRange == VoltageRange_1)
bwang 178:4e721c904fd7 631 {
bwang 178:4e721c904fd7 632 tmp_psize = FLASH_PSIZE_BYTE;
bwang 178:4e721c904fd7 633 }
bwang 178:4e721c904fd7 634 else if(VoltageRange == VoltageRange_2)
bwang 178:4e721c904fd7 635 {
bwang 178:4e721c904fd7 636 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 178:4e721c904fd7 637 }
bwang 178:4e721c904fd7 638 else if(VoltageRange == VoltageRange_3)
bwang 178:4e721c904fd7 639 {
bwang 178:4e721c904fd7 640 tmp_psize = FLASH_PSIZE_WORD;
bwang 178:4e721c904fd7 641 }
bwang 178:4e721c904fd7 642 else
bwang 178:4e721c904fd7 643 {
bwang 178:4e721c904fd7 644 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 178:4e721c904fd7 645 }
bwang 178:4e721c904fd7 646 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 647 {
bwang 178:4e721c904fd7 648 /* if the previous operation is completed, proceed to erase all sectors */
bwang 178:4e721c904fd7 649 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 650 FLASH->CR |= tmp_psize;
bwang 178:4e721c904fd7 651 FLASH->CR |= FLASH_CR_MER1;
bwang 178:4e721c904fd7 652 FLASH->CR |= FLASH_CR_STRT;
bwang 178:4e721c904fd7 653
bwang 178:4e721c904fd7 654 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 655 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 656
bwang 178:4e721c904fd7 657 /* if the erase operation is completed, disable the MER Bit */
bwang 178:4e721c904fd7 658 FLASH->CR &= (~FLASH_CR_MER1);
bwang 178:4e721c904fd7 659
bwang 178:4e721c904fd7 660 }
bwang 178:4e721c904fd7 661 /* Return the Erase Status */
bwang 178:4e721c904fd7 662 return status;
bwang 178:4e721c904fd7 663 }
bwang 178:4e721c904fd7 664
bwang 178:4e721c904fd7 665
bwang 178:4e721c904fd7 666 /**
bwang 178:4e721c904fd7 667 * @brief Erases all FLASH Sectors in Bank 2.
bwang 178:4e721c904fd7 668 *
bwang 178:4e721c904fd7 669 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 670 *
bwang 178:4e721c904fd7 671 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 672 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 673 *
bwang 178:4e721c904fd7 674 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 178:4e721c904fd7 675 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 676 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 178:4e721c904fd7 677 * the operation will be done by byte (8-bit)
bwang 178:4e721c904fd7 678 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 178:4e721c904fd7 679 * the operation will be done by half word (16-bit)
bwang 178:4e721c904fd7 680 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 178:4e721c904fd7 681 * the operation will be done by word (32-bit)
bwang 178:4e721c904fd7 682 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 178:4e721c904fd7 683 * the operation will be done by double word (64-bit)
bwang 178:4e721c904fd7 684 *
bwang 178:4e721c904fd7 685 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 686 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 687 */
bwang 178:4e721c904fd7 688 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
bwang 178:4e721c904fd7 689 {
bwang 178:4e721c904fd7 690 uint32_t tmp_psize = 0x0;
bwang 178:4e721c904fd7 691 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 692
bwang 178:4e721c904fd7 693 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 694 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 695 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 178:4e721c904fd7 696
bwang 178:4e721c904fd7 697 if(VoltageRange == VoltageRange_1)
bwang 178:4e721c904fd7 698 {
bwang 178:4e721c904fd7 699 tmp_psize = FLASH_PSIZE_BYTE;
bwang 178:4e721c904fd7 700 }
bwang 178:4e721c904fd7 701 else if(VoltageRange == VoltageRange_2)
bwang 178:4e721c904fd7 702 {
bwang 178:4e721c904fd7 703 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 178:4e721c904fd7 704 }
bwang 178:4e721c904fd7 705 else if(VoltageRange == VoltageRange_3)
bwang 178:4e721c904fd7 706 {
bwang 178:4e721c904fd7 707 tmp_psize = FLASH_PSIZE_WORD;
bwang 178:4e721c904fd7 708 }
bwang 178:4e721c904fd7 709 else
bwang 178:4e721c904fd7 710 {
bwang 178:4e721c904fd7 711 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 178:4e721c904fd7 712 }
bwang 178:4e721c904fd7 713 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 714 {
bwang 178:4e721c904fd7 715 /* if the previous operation is completed, proceed to erase all sectors */
bwang 178:4e721c904fd7 716 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 717 FLASH->CR |= tmp_psize;
bwang 178:4e721c904fd7 718 FLASH->CR |= FLASH_CR_MER2;
bwang 178:4e721c904fd7 719 FLASH->CR |= FLASH_CR_STRT;
bwang 178:4e721c904fd7 720
bwang 178:4e721c904fd7 721 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 722 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 723
bwang 178:4e721c904fd7 724 /* if the erase operation is completed, disable the MER Bit */
bwang 178:4e721c904fd7 725 FLASH->CR &= (~FLASH_CR_MER2);
bwang 178:4e721c904fd7 726
bwang 178:4e721c904fd7 727 }
bwang 178:4e721c904fd7 728 /* Return the Erase Status */
bwang 178:4e721c904fd7 729 return status;
bwang 178:4e721c904fd7 730 }
bwang 178:4e721c904fd7 731
bwang 178:4e721c904fd7 732 /**
bwang 178:4e721c904fd7 733 * @brief Programs a double word (64-bit) at a specified address.
bwang 178:4e721c904fd7 734 * @note This function must be used when the device voltage range is from
bwang 178:4e721c904fd7 735 * 2.7V to 3.6V and an External Vpp is present.
bwang 178:4e721c904fd7 736 *
bwang 178:4e721c904fd7 737 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 738 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 739 *
bwang 178:4e721c904fd7 740 * @param Address: specifies the address to be programmed.
bwang 178:4e721c904fd7 741 * @param Data: specifies the data to be programmed.
bwang 178:4e721c904fd7 742 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 743 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 744 */
bwang 178:4e721c904fd7 745 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
bwang 178:4e721c904fd7 746 {
bwang 178:4e721c904fd7 747 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 748
bwang 178:4e721c904fd7 749 /* Check the parameters */
bwang 178:4e721c904fd7 750 assert_param(IS_FLASH_ADDRESS(Address));
bwang 178:4e721c904fd7 751
bwang 178:4e721c904fd7 752 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 753 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 754
bwang 178:4e721c904fd7 755 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 756 {
bwang 178:4e721c904fd7 757 /* if the previous operation is completed, proceed to program the new data */
bwang 178:4e721c904fd7 758 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 759 FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
bwang 178:4e721c904fd7 760 FLASH->CR |= FLASH_CR_PG;
bwang 178:4e721c904fd7 761
bwang 178:4e721c904fd7 762 *(__IO uint64_t*)Address = Data;
bwang 178:4e721c904fd7 763
bwang 178:4e721c904fd7 764 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 765 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 766
bwang 178:4e721c904fd7 767 /* if the program operation is completed, disable the PG Bit */
bwang 178:4e721c904fd7 768 FLASH->CR &= (~FLASH_CR_PG);
bwang 178:4e721c904fd7 769 }
bwang 178:4e721c904fd7 770 /* Return the Program Status */
bwang 178:4e721c904fd7 771 return status;
bwang 178:4e721c904fd7 772 }
bwang 178:4e721c904fd7 773
bwang 178:4e721c904fd7 774 /**
bwang 178:4e721c904fd7 775 * @brief Programs a word (32-bit) at a specified address.
bwang 178:4e721c904fd7 776 *
bwang 178:4e721c904fd7 777 * @note This function must be used when the device voltage range is from 2.7V to 3.6V.
bwang 178:4e721c904fd7 778 *
bwang 178:4e721c904fd7 779 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 780 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 781 *
bwang 178:4e721c904fd7 782 * @param Address: specifies the address to be programmed.
bwang 178:4e721c904fd7 783 * This parameter can be any address in Program memory zone or in OTP zone.
bwang 178:4e721c904fd7 784 * @param Data: specifies the data to be programmed.
bwang 178:4e721c904fd7 785 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 786 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 787 */
bwang 178:4e721c904fd7 788 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
bwang 178:4e721c904fd7 789 {
bwang 178:4e721c904fd7 790 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 791
bwang 178:4e721c904fd7 792 /* Check the parameters */
bwang 178:4e721c904fd7 793 assert_param(IS_FLASH_ADDRESS(Address));
bwang 178:4e721c904fd7 794
bwang 178:4e721c904fd7 795 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 796 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 797
bwang 178:4e721c904fd7 798 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 799 {
bwang 178:4e721c904fd7 800 /* if the previous operation is completed, proceed to program the new data */
bwang 178:4e721c904fd7 801 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 802 FLASH->CR |= FLASH_PSIZE_WORD;
bwang 178:4e721c904fd7 803 FLASH->CR |= FLASH_CR_PG;
bwang 178:4e721c904fd7 804
bwang 178:4e721c904fd7 805 *(__IO uint32_t*)Address = Data;
bwang 178:4e721c904fd7 806
bwang 178:4e721c904fd7 807 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 808 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 809
bwang 178:4e721c904fd7 810 /* if the program operation is completed, disable the PG Bit */
bwang 178:4e721c904fd7 811 FLASH->CR &= (~FLASH_CR_PG);
bwang 178:4e721c904fd7 812 }
bwang 178:4e721c904fd7 813 /* Return the Program Status */
bwang 178:4e721c904fd7 814 return status;
bwang 178:4e721c904fd7 815 }
bwang 178:4e721c904fd7 816
bwang 178:4e721c904fd7 817 /**
bwang 178:4e721c904fd7 818 * @brief Programs a half word (16-bit) at a specified address.
bwang 178:4e721c904fd7 819 * @note This function must be used when the device voltage range is from 2.1V to 3.6V.
bwang 178:4e721c904fd7 820 *
bwang 178:4e721c904fd7 821 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 822 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 823 *
bwang 178:4e721c904fd7 824 * @param Address: specifies the address to be programmed.
bwang 178:4e721c904fd7 825 * This parameter can be any address in Program memory zone or in OTP zone.
bwang 178:4e721c904fd7 826 * @param Data: specifies the data to be programmed.
bwang 178:4e721c904fd7 827 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 828 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 829 */
bwang 178:4e721c904fd7 830 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
bwang 178:4e721c904fd7 831 {
bwang 178:4e721c904fd7 832 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 833
bwang 178:4e721c904fd7 834 /* Check the parameters */
bwang 178:4e721c904fd7 835 assert_param(IS_FLASH_ADDRESS(Address));
bwang 178:4e721c904fd7 836
bwang 178:4e721c904fd7 837 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 838 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 839
bwang 178:4e721c904fd7 840 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 841 {
bwang 178:4e721c904fd7 842 /* if the previous operation is completed, proceed to program the new data */
bwang 178:4e721c904fd7 843 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 844 FLASH->CR |= FLASH_PSIZE_HALF_WORD;
bwang 178:4e721c904fd7 845 FLASH->CR |= FLASH_CR_PG;
bwang 178:4e721c904fd7 846
bwang 178:4e721c904fd7 847 *(__IO uint16_t*)Address = Data;
bwang 178:4e721c904fd7 848
bwang 178:4e721c904fd7 849 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 850 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 851
bwang 178:4e721c904fd7 852 /* if the program operation is completed, disable the PG Bit */
bwang 178:4e721c904fd7 853 FLASH->CR &= (~FLASH_CR_PG);
bwang 178:4e721c904fd7 854 }
bwang 178:4e721c904fd7 855 /* Return the Program Status */
bwang 178:4e721c904fd7 856 return status;
bwang 178:4e721c904fd7 857 }
bwang 178:4e721c904fd7 858
bwang 178:4e721c904fd7 859 /**
bwang 178:4e721c904fd7 860 * @brief Programs a byte (8-bit) at a specified address.
bwang 178:4e721c904fd7 861 * @note This function can be used within all the device supply voltage ranges.
bwang 178:4e721c904fd7 862 *
bwang 178:4e721c904fd7 863 * @note If an erase and a program operations are requested simultaneously,
bwang 178:4e721c904fd7 864 * the erase operation is performed before the program one.
bwang 178:4e721c904fd7 865 *
bwang 178:4e721c904fd7 866 * @param Address: specifies the address to be programmed.
bwang 178:4e721c904fd7 867 * This parameter can be any address in Program memory zone or in OTP zone.
bwang 178:4e721c904fd7 868 * @param Data: specifies the data to be programmed.
bwang 178:4e721c904fd7 869 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 870 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 871 */
bwang 178:4e721c904fd7 872 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
bwang 178:4e721c904fd7 873 {
bwang 178:4e721c904fd7 874 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 875
bwang 178:4e721c904fd7 876 /* Check the parameters */
bwang 178:4e721c904fd7 877 assert_param(IS_FLASH_ADDRESS(Address));
bwang 178:4e721c904fd7 878
bwang 178:4e721c904fd7 879 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 880 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 881
bwang 178:4e721c904fd7 882 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 883 {
bwang 178:4e721c904fd7 884 /* if the previous operation is completed, proceed to program the new data */
bwang 178:4e721c904fd7 885 FLASH->CR &= CR_PSIZE_MASK;
bwang 178:4e721c904fd7 886 FLASH->CR |= FLASH_PSIZE_BYTE;
bwang 178:4e721c904fd7 887 FLASH->CR |= FLASH_CR_PG;
bwang 178:4e721c904fd7 888
bwang 178:4e721c904fd7 889 *(__IO uint8_t*)Address = Data;
bwang 178:4e721c904fd7 890
bwang 178:4e721c904fd7 891 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 892 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 893
bwang 178:4e721c904fd7 894 /* if the program operation is completed, disable the PG Bit */
bwang 178:4e721c904fd7 895 FLASH->CR &= (~FLASH_CR_PG);
bwang 178:4e721c904fd7 896 }
bwang 178:4e721c904fd7 897
bwang 178:4e721c904fd7 898 /* Return the Program Status */
bwang 178:4e721c904fd7 899 return status;
bwang 178:4e721c904fd7 900 }
bwang 178:4e721c904fd7 901
bwang 178:4e721c904fd7 902 /**
bwang 178:4e721c904fd7 903 * @}
bwang 178:4e721c904fd7 904 */
bwang 178:4e721c904fd7 905
bwang 178:4e721c904fd7 906 /** @defgroup FLASH_Group3 Option Bytes Programming functions
bwang 178:4e721c904fd7 907 * @brief Option Bytes Programming functions
bwang 178:4e721c904fd7 908 *
bwang 178:4e721c904fd7 909 @verbatim
bwang 178:4e721c904fd7 910 ===============================================================================
bwang 178:4e721c904fd7 911 ##### Option Bytes Programming functions #####
bwang 178:4e721c904fd7 912 ===============================================================================
bwang 178:4e721c904fd7 913 [..]
bwang 178:4e721c904fd7 914 This group includes the following functions:
bwang 178:4e721c904fd7 915 (+) void FLASH_OB_Unlock(void)
bwang 178:4e721c904fd7 916 (+) void FLASH_OB_Lock(void)
bwang 178:4e721c904fd7 917 (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang 178:4e721c904fd7 918 (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
bwang 178:4e721c904fd7 919 (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
bwang 178:4e721c904fd7 920 (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
bwang 178:4e721c904fd7 921 (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
bwang 178:4e721c904fd7 922 (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
bwang 178:4e721c904fd7 923 (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang 178:4e721c904fd7 924 (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
bwang 178:4e721c904fd7 925 (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
bwang 178:4e721c904fd7 926 (+) FLASH_Status FLASH_OB_Launch(void)
bwang 178:4e721c904fd7 927 (+) uint32_t FLASH_OB_GetUser(void)
bwang 178:4e721c904fd7 928 (+) uint8_t FLASH_OB_GetWRP(void)
bwang 178:4e721c904fd7 929 (+) uint8_t FLASH_OB_GetWRP1(void)
bwang 178:4e721c904fd7 930 (+) uint8_t FLASH_OB_GetPCROP(void)
bwang 178:4e721c904fd7 931 (+) uint8_t FLASH_OB_GetPCROP1(void)
bwang 178:4e721c904fd7 932 (+) uint8_t FLASH_OB_GetRDP(void)
bwang 178:4e721c904fd7 933 (+) uint8_t FLASH_OB_GetBOR(void)
bwang 178:4e721c904fd7 934 [..]
bwang 178:4e721c904fd7 935 The following function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 936 (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
bwang 178:4e721c904fd7 937 [..]
bwang 178:4e721c904fd7 938 Any operation of erase or program should follow these steps:
bwang 178:4e721c904fd7 939 (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
bwang 178:4e721c904fd7 940 register access
bwang 178:4e721c904fd7 941
bwang 178:4e721c904fd7 942 (#) Call one or several functions to program the desired Option Bytes:
bwang 178:4e721c904fd7 943 (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang 178:4e721c904fd7 944 => to Enable/Disable the desired sector write protection
bwang 178:4e721c904fd7 945 (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
bwang 178:4e721c904fd7 946 Protection Level
bwang 178:4e721c904fd7 947 (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang 178:4e721c904fd7 948 => to configure the user Option Bytes.
bwang 178:4e721c904fd7 949 (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
bwang 178:4e721c904fd7 950
bwang 178:4e721c904fd7 951 (#) Once all needed Option Bytes to be programmed are correctly written,
bwang 178:4e721c904fd7 952 call the FLASH_OB_Launch() function to launch the Option Bytes
bwang 178:4e721c904fd7 953 programming process.
bwang 178:4e721c904fd7 954
bwang 178:4e721c904fd7 955 -@- When changing the IWDG mode from HW to SW or from SW to HW, a system
bwang 178:4e721c904fd7 956 reset is needed to make the change effective.
bwang 178:4e721c904fd7 957
bwang 178:4e721c904fd7 958 (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
bwang 178:4e721c904fd7 959 register access (recommended to protect the Option Bytes against
bwang 178:4e721c904fd7 960 possible unwanted operations)
bwang 178:4e721c904fd7 961
bwang 178:4e721c904fd7 962 @endverbatim
bwang 178:4e721c904fd7 963 * @{
bwang 178:4e721c904fd7 964 */
bwang 178:4e721c904fd7 965
bwang 178:4e721c904fd7 966 /**
bwang 178:4e721c904fd7 967 * @brief Unlocks the FLASH Option Control Registers access.
bwang 178:4e721c904fd7 968 * @param None
bwang 178:4e721c904fd7 969 * @retval None
bwang 178:4e721c904fd7 970 */
bwang 178:4e721c904fd7 971 void FLASH_OB_Unlock(void)
bwang 178:4e721c904fd7 972 {
bwang 178:4e721c904fd7 973 if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
bwang 178:4e721c904fd7 974 {
bwang 178:4e721c904fd7 975 /* Authorizes the Option Byte register programming */
bwang 178:4e721c904fd7 976 FLASH->OPTKEYR = FLASH_OPT_KEY1;
bwang 178:4e721c904fd7 977 FLASH->OPTKEYR = FLASH_OPT_KEY2;
bwang 178:4e721c904fd7 978 }
bwang 178:4e721c904fd7 979 }
bwang 178:4e721c904fd7 980
bwang 178:4e721c904fd7 981 /**
bwang 178:4e721c904fd7 982 * @brief Locks the FLASH Option Control Registers access.
bwang 178:4e721c904fd7 983 * @param None
bwang 178:4e721c904fd7 984 * @retval None
bwang 178:4e721c904fd7 985 */
bwang 178:4e721c904fd7 986 void FLASH_OB_Lock(void)
bwang 178:4e721c904fd7 987 {
bwang 178:4e721c904fd7 988 /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
bwang 178:4e721c904fd7 989 FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
bwang 178:4e721c904fd7 990 }
bwang 178:4e721c904fd7 991
bwang 178:4e721c904fd7 992 /**
bwang 178:4e721c904fd7 993 * @brief Enables or disables the write protection of the desired sectors, for the first
bwang 178:4e721c904fd7 994 * 1 Mb of the Flash
bwang 178:4e721c904fd7 995 *
bwang 178:4e721c904fd7 996 * @note When the memory read protection level is selected (RDP level = 1),
bwang 178:4e721c904fd7 997 * it is not possible to program or erase the flash sector i if CortexM4
bwang 178:4e721c904fd7 998 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
bwang 178:4e721c904fd7 999 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
bwang 178:4e721c904fd7 1000 *
bwang 178:4e721c904fd7 1001 * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
bwang 178:4e721c904fd7 1002 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1003 * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
bwang 178:4e721c904fd7 1004 * @arg OB_WRP_Sector_All
bwang 178:4e721c904fd7 1005 * @param Newstate: new state of the Write Protection.
bwang 178:4e721c904fd7 1006 * This parameter can be: ENABLE or DISABLE.
bwang 178:4e721c904fd7 1007 * @retval None
bwang 178:4e721c904fd7 1008 */
bwang 178:4e721c904fd7 1009 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang 178:4e721c904fd7 1010 {
bwang 178:4e721c904fd7 1011 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1012
bwang 178:4e721c904fd7 1013 /* Check the parameters */
bwang 178:4e721c904fd7 1014 assert_param(IS_OB_WRP(OB_WRP));
bwang 178:4e721c904fd7 1015 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 1016
bwang 178:4e721c904fd7 1017 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 1018
bwang 178:4e721c904fd7 1019 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 1020 {
bwang 178:4e721c904fd7 1021 if(NewState != DISABLE)
bwang 178:4e721c904fd7 1022 {
bwang 178:4e721c904fd7 1023 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
bwang 178:4e721c904fd7 1024 }
bwang 178:4e721c904fd7 1025 else
bwang 178:4e721c904fd7 1026 {
bwang 178:4e721c904fd7 1027 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
bwang 178:4e721c904fd7 1028 }
bwang 178:4e721c904fd7 1029 }
bwang 178:4e721c904fd7 1030 }
bwang 178:4e721c904fd7 1031
bwang 178:4e721c904fd7 1032 /**
bwang 178:4e721c904fd7 1033 * @brief Enables or disables the write protection of the desired sectors, for the second
bwang 178:4e721c904fd7 1034 * 1 Mb of the Flash
bwang 178:4e721c904fd7 1035 *
bwang 178:4e721c904fd7 1036 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 1037 *
bwang 178:4e721c904fd7 1038 * @note When the memory read out protection is selected (RDP level = 1),
bwang 178:4e721c904fd7 1039 * it is not possible to program or erase the flash sector i if CortexM4
bwang 178:4e721c904fd7 1040 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
bwang 178:4e721c904fd7 1041 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
bwang 178:4e721c904fd7 1042 *
bwang 178:4e721c904fd7 1043 * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
bwang 178:4e721c904fd7 1044 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1045 * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
bwang 178:4e721c904fd7 1046 * @arg OB_WRP_Sector_All
bwang 178:4e721c904fd7 1047 * @param Newstate: new state of the Write Protection.
bwang 178:4e721c904fd7 1048 * This parameter can be: ENABLE or DISABLE.
bwang 178:4e721c904fd7 1049 * @retval None
bwang 178:4e721c904fd7 1050 */
bwang 178:4e721c904fd7 1051 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
bwang 178:4e721c904fd7 1052 {
bwang 178:4e721c904fd7 1053 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1054
bwang 178:4e721c904fd7 1055 /* Check the parameters */
bwang 178:4e721c904fd7 1056 assert_param(IS_OB_WRP(OB_WRP));
bwang 178:4e721c904fd7 1057 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 1058
bwang 178:4e721c904fd7 1059 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 1060
bwang 178:4e721c904fd7 1061 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 1062 {
bwang 178:4e721c904fd7 1063 if(NewState != DISABLE)
bwang 178:4e721c904fd7 1064 {
bwang 178:4e721c904fd7 1065 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
bwang 178:4e721c904fd7 1066 }
bwang 178:4e721c904fd7 1067 else
bwang 178:4e721c904fd7 1068 {
bwang 178:4e721c904fd7 1069 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
bwang 178:4e721c904fd7 1070 }
bwang 178:4e721c904fd7 1071 }
bwang 178:4e721c904fd7 1072 }
bwang 178:4e721c904fd7 1073
bwang 178:4e721c904fd7 1074 /**
bwang 178:4e721c904fd7 1075 * @brief Select the Protection Mode (SPRMOD).
bwang 178:4e721c904fd7 1076 *
bwang 178:4e721c904fd7 1077 * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
bwang 178:4e721c904fd7 1078 *
bwang 178:4e721c904fd7 1079 * @note After PCROP activation, Option Byte modification is not possible.
bwang 178:4e721c904fd7 1080 * Exception made for the global Read Out Protection modification level (level1 to level0)
bwang 178:4e721c904fd7 1081 * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
bwang 178:4e721c904fd7 1082 *
bwang 178:4e721c904fd7 1083 * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
bwang 178:4e721c904fd7 1084 *
bwang 178:4e721c904fd7 1085 * @note Some Precautions should be taken when activating the PCROP feature :
bwang 178:4e721c904fd7 1086 * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
bwang 178:4e721c904fd7 1087 * and WRPi = 1 (default value), then the user sector i is read/write protected.
bwang 178:4e721c904fd7 1088 * In order to avoid activation of PCROP Mode for undesired sectors, please follow the
bwang 178:4e721c904fd7 1089 * below safety sequence :
bwang 178:4e721c904fd7 1090 * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
bwang 178:4e721c904fd7 1091 * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
bwang 178:4e721c904fd7 1092 * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
bwang 178:4e721c904fd7 1093 * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
bwang 178:4e721c904fd7 1094 *
bwang 178:4e721c904fd7 1095 * @param OB_PCROP: Select the Protection Mode of nWPRi bits
bwang 178:4e721c904fd7 1096 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1097 * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
bwang 178:4e721c904fd7 1098 * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
bwang 178:4e721c904fd7 1099 * @retval None
bwang 178:4e721c904fd7 1100 */
bwang 178:4e721c904fd7 1101 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
bwang 178:4e721c904fd7 1102 {
bwang 178:4e721c904fd7 1103 uint8_t optiontmp = 0xFF;
bwang 178:4e721c904fd7 1104
bwang 178:4e721c904fd7 1105 /* Check the parameters */
bwang 178:4e721c904fd7 1106 assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
bwang 178:4e721c904fd7 1107
bwang 178:4e721c904fd7 1108 /* Mask SPRMOD bit */
bwang 178:4e721c904fd7 1109 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
bwang 178:4e721c904fd7 1110 /* Update Option Byte */
bwang 178:4e721c904fd7 1111 *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp);
bwang 178:4e721c904fd7 1112
bwang 178:4e721c904fd7 1113 }
bwang 178:4e721c904fd7 1114
bwang 178:4e721c904fd7 1115 /**
bwang 178:4e721c904fd7 1116 * @brief Enables or disables the read/write protection (PCROP) of the desired
bwang 178:4e721c904fd7 1117 * sectors, for the first 1 MB of the Flash.
bwang 178:4e721c904fd7 1118 *
bwang 178:4e721c904fd7 1119 * @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE
bwang 178:4e721c904fd7 1120 * and STM32F412xG devices.
bwang 178:4e721c904fd7 1121 *
bwang 178:4e721c904fd7 1122 * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
bwang 178:4e721c904fd7 1123 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1124 * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
bwang 178:4e721c904fd7 1125 * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
bwang 178:4e721c904fd7 1126 * OB_PCROP_Sector5 for STM32F401xx/411xE devices.
bwang 178:4e721c904fd7 1127 * @arg OB_PCROP_Sector_All
bwang 178:4e721c904fd7 1128 * @param Newstate: new state of the Write Protection.
bwang 178:4e721c904fd7 1129 * This parameter can be: ENABLE or DISABLE.
bwang 178:4e721c904fd7 1130 * @retval None
bwang 178:4e721c904fd7 1131 */
bwang 178:4e721c904fd7 1132 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
bwang 178:4e721c904fd7 1133 {
bwang 178:4e721c904fd7 1134 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1135
bwang 178:4e721c904fd7 1136 /* Check the parameters */
bwang 178:4e721c904fd7 1137 assert_param(IS_OB_PCROP(OB_PCROP));
bwang 178:4e721c904fd7 1138 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 1139
bwang 178:4e721c904fd7 1140 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 1141
bwang 178:4e721c904fd7 1142 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 1143 {
bwang 178:4e721c904fd7 1144 if(NewState != DISABLE)
bwang 178:4e721c904fd7 1145 {
bwang 178:4e721c904fd7 1146 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
bwang 178:4e721c904fd7 1147 }
bwang 178:4e721c904fd7 1148 else
bwang 178:4e721c904fd7 1149 {
bwang 178:4e721c904fd7 1150 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
bwang 178:4e721c904fd7 1151 }
bwang 178:4e721c904fd7 1152 }
bwang 178:4e721c904fd7 1153 }
bwang 178:4e721c904fd7 1154
bwang 178:4e721c904fd7 1155 /**
bwang 178:4e721c904fd7 1156 * @brief Enables or disables the read/write protection (PCROP) of the desired
bwang 178:4e721c904fd7 1157 * sectors
bwang 178:4e721c904fd7 1158 *
bwang 178:4e721c904fd7 1159 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 1160 *
bwang 178:4e721c904fd7 1161 * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
bwang 178:4e721c904fd7 1162 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1163 * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
bwang 178:4e721c904fd7 1164 * @arg OB_PCROP_Sector_All
bwang 178:4e721c904fd7 1165 * @param Newstate: new state of the Write Protection.
bwang 178:4e721c904fd7 1166 * This parameter can be: ENABLE or DISABLE.
bwang 178:4e721c904fd7 1167 * @retval None
bwang 178:4e721c904fd7 1168 */
bwang 178:4e721c904fd7 1169 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
bwang 178:4e721c904fd7 1170 {
bwang 178:4e721c904fd7 1171 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1172
bwang 178:4e721c904fd7 1173 /* Check the parameters */
bwang 178:4e721c904fd7 1174 assert_param(IS_OB_PCROP(OB_PCROP));
bwang 178:4e721c904fd7 1175 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 1176
bwang 178:4e721c904fd7 1177 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 1178
bwang 178:4e721c904fd7 1179 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 1180 {
bwang 178:4e721c904fd7 1181 if(NewState != DISABLE)
bwang 178:4e721c904fd7 1182 {
bwang 178:4e721c904fd7 1183 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
bwang 178:4e721c904fd7 1184 }
bwang 178:4e721c904fd7 1185 else
bwang 178:4e721c904fd7 1186 {
bwang 178:4e721c904fd7 1187 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
bwang 178:4e721c904fd7 1188 }
bwang 178:4e721c904fd7 1189 }
bwang 178:4e721c904fd7 1190 }
bwang 178:4e721c904fd7 1191
bwang 178:4e721c904fd7 1192
bwang 178:4e721c904fd7 1193 /**
bwang 178:4e721c904fd7 1194 * @brief Sets the read protection level.
bwang 178:4e721c904fd7 1195 * @param OB_RDP: specifies the read protection level.
bwang 178:4e721c904fd7 1196 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1197 * @arg OB_RDP_Level_0: No protection
bwang 178:4e721c904fd7 1198 * @arg OB_RDP_Level_1: Read protection of the memory
bwang 178:4e721c904fd7 1199 * @arg OB_RDP_Level_2: Full chip protection
bwang 178:4e721c904fd7 1200 *
bwang 178:4e721c904fd7 1201 * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
bwang 178:4e721c904fd7 1202 *
bwang 178:4e721c904fd7 1203 * @retval None
bwang 178:4e721c904fd7 1204 */
bwang 178:4e721c904fd7 1205 void FLASH_OB_RDPConfig(uint8_t OB_RDP)
bwang 178:4e721c904fd7 1206 {
bwang 178:4e721c904fd7 1207 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1208
bwang 178:4e721c904fd7 1209 /* Check the parameters */
bwang 178:4e721c904fd7 1210 assert_param(IS_OB_RDP(OB_RDP));
bwang 178:4e721c904fd7 1211
bwang 178:4e721c904fd7 1212 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 1213
bwang 178:4e721c904fd7 1214 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 1215 {
bwang 178:4e721c904fd7 1216 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
bwang 178:4e721c904fd7 1217
bwang 178:4e721c904fd7 1218 }
bwang 178:4e721c904fd7 1219 }
bwang 178:4e721c904fd7 1220
bwang 178:4e721c904fd7 1221 /**
bwang 178:4e721c904fd7 1222 * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
bwang 178:4e721c904fd7 1223 * @param OB_IWDG: Selects the IWDG mode
bwang 178:4e721c904fd7 1224 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1225 * @arg OB_IWDG_SW: Software IWDG selected
bwang 178:4e721c904fd7 1226 * @arg OB_IWDG_HW: Hardware IWDG selected
bwang 178:4e721c904fd7 1227 * @param OB_STOP: Reset event when entering STOP mode.
bwang 178:4e721c904fd7 1228 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1229 * @arg OB_STOP_NoRST: No reset generated when entering in STOP
bwang 178:4e721c904fd7 1230 * @arg OB_STOP_RST: Reset generated when entering in STOP
bwang 178:4e721c904fd7 1231 * @param OB_STDBY: Reset event when entering Standby mode.
bwang 178:4e721c904fd7 1232 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1233 * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
bwang 178:4e721c904fd7 1234 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
bwang 178:4e721c904fd7 1235 * @retval None
bwang 178:4e721c904fd7 1236 */
bwang 178:4e721c904fd7 1237 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang 178:4e721c904fd7 1238 {
bwang 178:4e721c904fd7 1239 uint8_t optiontmp = 0xFF;
bwang 178:4e721c904fd7 1240 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1241
bwang 178:4e721c904fd7 1242 /* Check the parameters */
bwang 178:4e721c904fd7 1243 assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
bwang 178:4e721c904fd7 1244 assert_param(IS_OB_STOP_SOURCE(OB_STOP));
bwang 178:4e721c904fd7 1245 assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
bwang 178:4e721c904fd7 1246
bwang 178:4e721c904fd7 1247 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 1248 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 1249
bwang 178:4e721c904fd7 1250 if(status == FLASH_COMPLETE2)
bwang 178:4e721c904fd7 1251 {
bwang 178:4e721c904fd7 1252 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
bwang 178:4e721c904fd7 1253 /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
bwang 178:4e721c904fd7 1254 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
bwang 178:4e721c904fd7 1255 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
bwang 178:4e721c904fd7 1256
bwang 178:4e721c904fd7 1257 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F446xx)
bwang 178:4e721c904fd7 1258 /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
bwang 178:4e721c904fd7 1259 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
bwang 178:4e721c904fd7 1260 #endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
bwang 178:4e721c904fd7 1261
bwang 178:4e721c904fd7 1262 /* Update User Option Byte */
bwang 178:4e721c904fd7 1263 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
bwang 178:4e721c904fd7 1264 }
bwang 178:4e721c904fd7 1265 }
bwang 178:4e721c904fd7 1266
bwang 178:4e721c904fd7 1267 /**
bwang 178:4e721c904fd7 1268 * @brief Configure the Dual Bank Boot.
bwang 178:4e721c904fd7 1269 *
bwang 178:4e721c904fd7 1270 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 1271 *
bwang 178:4e721c904fd7 1272 * @param OB_BOOT: specifies the Dual Bank Boot Option byte.
bwang 178:4e721c904fd7 1273 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1274 * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
bwang 178:4e721c904fd7 1275 * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
bwang 178:4e721c904fd7 1276 * @retval None
bwang 178:4e721c904fd7 1277 */
bwang 178:4e721c904fd7 1278 void FLASH_OB_BootConfig(uint8_t OB_BOOT)
bwang 178:4e721c904fd7 1279 {
bwang 178:4e721c904fd7 1280 /* Check the parameters */
bwang 178:4e721c904fd7 1281 assert_param(IS_OB_BOOT(OB_BOOT));
bwang 178:4e721c904fd7 1282
bwang 178:4e721c904fd7 1283 /* Set Dual Bank Boot */
bwang 178:4e721c904fd7 1284 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
bwang 178:4e721c904fd7 1285 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
bwang 178:4e721c904fd7 1286
bwang 178:4e721c904fd7 1287 }
bwang 178:4e721c904fd7 1288
bwang 178:4e721c904fd7 1289 /**
bwang 178:4e721c904fd7 1290 * @brief Sets the BOR Level.
bwang 178:4e721c904fd7 1291 * @param OB_BOR: specifies the Option Bytes BOR Reset Level.
bwang 178:4e721c904fd7 1292 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1293 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
bwang 178:4e721c904fd7 1294 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
bwang 178:4e721c904fd7 1295 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
bwang 178:4e721c904fd7 1296 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
bwang 178:4e721c904fd7 1297 * @retval None
bwang 178:4e721c904fd7 1298 */
bwang 178:4e721c904fd7 1299 void FLASH_OB_BORConfig(uint8_t OB_BOR)
bwang 178:4e721c904fd7 1300 {
bwang 178:4e721c904fd7 1301 /* Check the parameters */
bwang 178:4e721c904fd7 1302 assert_param(IS_OB_BOR(OB_BOR));
bwang 178:4e721c904fd7 1303
bwang 178:4e721c904fd7 1304 /* Set the BOR Level */
bwang 178:4e721c904fd7 1305 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
bwang 178:4e721c904fd7 1306 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
bwang 178:4e721c904fd7 1307
bwang 178:4e721c904fd7 1308 }
bwang 178:4e721c904fd7 1309
bwang 178:4e721c904fd7 1310 /**
bwang 178:4e721c904fd7 1311 * @brief Launch the option byte loading.
bwang 178:4e721c904fd7 1312 * @param None
bwang 178:4e721c904fd7 1313 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 1314 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 1315 */
bwang 178:4e721c904fd7 1316 FLASH_Status FLASH_OB_Launch(void)
bwang 178:4e721c904fd7 1317 {
bwang 178:4e721c904fd7 1318 FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1319
bwang 178:4e721c904fd7 1320 /* Set the OPTSTRT bit in OPTCR register */
bwang 178:4e721c904fd7 1321 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
bwang 178:4e721c904fd7 1322
bwang 178:4e721c904fd7 1323 /* Wait for last operation to be completed */
bwang 178:4e721c904fd7 1324 status = FLASH_WaitForLastOperation2();
bwang 178:4e721c904fd7 1325
bwang 178:4e721c904fd7 1326 return status;
bwang 178:4e721c904fd7 1327 }
bwang 178:4e721c904fd7 1328
bwang 178:4e721c904fd7 1329 /**
bwang 178:4e721c904fd7 1330 * @brief Returns the FLASH User Option Bytes values.
bwang 178:4e721c904fd7 1331 * @param None
bwang 178:4e721c904fd7 1332 * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
bwang 178:4e721c904fd7 1333 * and RST_STDBY(Bit2).
bwang 178:4e721c904fd7 1334 */
bwang 178:4e721c904fd7 1335 uint8_t FLASH_OB_GetUser(void)
bwang 178:4e721c904fd7 1336 {
bwang 178:4e721c904fd7 1337 /* Return the User Option Byte */
bwang 178:4e721c904fd7 1338 return (uint8_t)(FLASH->OPTCR >> 5);
bwang 178:4e721c904fd7 1339 }
bwang 178:4e721c904fd7 1340
bwang 178:4e721c904fd7 1341 /**
bwang 178:4e721c904fd7 1342 * @brief Returns the FLASH Write Protection Option Bytes value.
bwang 178:4e721c904fd7 1343 * @param None
bwang 178:4e721c904fd7 1344 * @retval The FLASH Write Protection Option Bytes value
bwang 178:4e721c904fd7 1345 */
bwang 178:4e721c904fd7 1346 uint16_t FLASH_OB_GetWRP(void)
bwang 178:4e721c904fd7 1347 {
bwang 178:4e721c904fd7 1348 /* Return the FLASH write protection Register value */
bwang 178:4e721c904fd7 1349 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
bwang 178:4e721c904fd7 1350 }
bwang 178:4e721c904fd7 1351
bwang 178:4e721c904fd7 1352 /**
bwang 178:4e721c904fd7 1353 * @brief Returns the FLASH Write Protection Option Bytes value.
bwang 178:4e721c904fd7 1354 *
bwang 178:4e721c904fd7 1355 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 1356 *
bwang 178:4e721c904fd7 1357 * @param None
bwang 178:4e721c904fd7 1358 * @retval The FLASH Write Protection Option Bytes value
bwang 178:4e721c904fd7 1359 */
bwang 178:4e721c904fd7 1360 uint16_t FLASH_OB_GetWRP1(void)
bwang 178:4e721c904fd7 1361 {
bwang 178:4e721c904fd7 1362 /* Return the FLASH write protection Register value */
bwang 178:4e721c904fd7 1363 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
bwang 178:4e721c904fd7 1364 }
bwang 178:4e721c904fd7 1365
bwang 178:4e721c904fd7 1366 /**
bwang 178:4e721c904fd7 1367 * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
bwang 178:4e721c904fd7 1368 *
bwang 178:4e721c904fd7 1369 * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
bwang 178:4e721c904fd7 1370 *
bwang 178:4e721c904fd7 1371 * @param None
bwang 178:4e721c904fd7 1372 * @retval The FLASH PC Read/Write Protection Option Bytes value
bwang 178:4e721c904fd7 1373 */
bwang 178:4e721c904fd7 1374 uint16_t FLASH_OB_GetPCROP(void)
bwang 178:4e721c904fd7 1375 {
bwang 178:4e721c904fd7 1376 /* Return the FLASH PC Read/write protection Register value */
bwang 178:4e721c904fd7 1377 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
bwang 178:4e721c904fd7 1378 }
bwang 178:4e721c904fd7 1379
bwang 178:4e721c904fd7 1380 /**
bwang 178:4e721c904fd7 1381 * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
bwang 178:4e721c904fd7 1382 *
bwang 178:4e721c904fd7 1383 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 178:4e721c904fd7 1384 *
bwang 178:4e721c904fd7 1385 * @param None
bwang 178:4e721c904fd7 1386 * @retval The FLASH PC Read/Write Protection Option Bytes value
bwang 178:4e721c904fd7 1387 */
bwang 178:4e721c904fd7 1388 uint16_t FLASH_OB_GetPCROP1(void)
bwang 178:4e721c904fd7 1389 {
bwang 178:4e721c904fd7 1390 /* Return the FLASH write protection Register value */
bwang 178:4e721c904fd7 1391 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
bwang 178:4e721c904fd7 1392 }
bwang 178:4e721c904fd7 1393
bwang 178:4e721c904fd7 1394 /**
bwang 178:4e721c904fd7 1395 * @brief Returns the FLASH Read Protection level.
bwang 178:4e721c904fd7 1396 * @param None
bwang 178:4e721c904fd7 1397 * @retval FLASH ReadOut Protection Status:
bwang 178:4e721c904fd7 1398 * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
bwang 178:4e721c904fd7 1399 * - RESET, when OB_RDP_Level_0 is set
bwang 178:4e721c904fd7 1400 */
bwang 178:4e721c904fd7 1401 FlagStatus FLASH_OB_GetRDP(void)
bwang 178:4e721c904fd7 1402 {
bwang 178:4e721c904fd7 1403 FlagStatus readstatus = RESET;
bwang 178:4e721c904fd7 1404
bwang 178:4e721c904fd7 1405 if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
bwang 178:4e721c904fd7 1406 {
bwang 178:4e721c904fd7 1407 readstatus = SET;
bwang 178:4e721c904fd7 1408 }
bwang 178:4e721c904fd7 1409 else
bwang 178:4e721c904fd7 1410 {
bwang 178:4e721c904fd7 1411 readstatus = RESET;
bwang 178:4e721c904fd7 1412 }
bwang 178:4e721c904fd7 1413 return readstatus;
bwang 178:4e721c904fd7 1414 }
bwang 178:4e721c904fd7 1415
bwang 178:4e721c904fd7 1416 /**
bwang 178:4e721c904fd7 1417 * @brief Returns the FLASH BOR level.
bwang 178:4e721c904fd7 1418 * @param None
bwang 178:4e721c904fd7 1419 * @retval The FLASH BOR level:
bwang 178:4e721c904fd7 1420 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
bwang 178:4e721c904fd7 1421 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
bwang 178:4e721c904fd7 1422 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
bwang 178:4e721c904fd7 1423 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
bwang 178:4e721c904fd7 1424 */
bwang 178:4e721c904fd7 1425 uint8_t FLASH_OB_GetBOR(void)
bwang 178:4e721c904fd7 1426 {
bwang 178:4e721c904fd7 1427 /* Return the FLASH BOR level */
bwang 178:4e721c904fd7 1428 return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
bwang 178:4e721c904fd7 1429 }
bwang 178:4e721c904fd7 1430
bwang 178:4e721c904fd7 1431 /**
bwang 178:4e721c904fd7 1432 * @}
bwang 178:4e721c904fd7 1433 */
bwang 178:4e721c904fd7 1434
bwang 178:4e721c904fd7 1435 /** @defgroup FLASH_Group4 Interrupts and flags management functions
bwang 178:4e721c904fd7 1436 * @brief Interrupts and flags management functions
bwang 178:4e721c904fd7 1437 *
bwang 178:4e721c904fd7 1438 @verbatim
bwang 178:4e721c904fd7 1439 ===============================================================================
bwang 178:4e721c904fd7 1440 ##### Interrupts and flags management functions #####
bwang 178:4e721c904fd7 1441 ===============================================================================
bwang 178:4e721c904fd7 1442 @endverbatim
bwang 178:4e721c904fd7 1443 * @{
bwang 178:4e721c904fd7 1444 */
bwang 178:4e721c904fd7 1445
bwang 178:4e721c904fd7 1446 /**
bwang 178:4e721c904fd7 1447 * @brief Enables or disables the specified FLASH interrupts.
bwang 178:4e721c904fd7 1448 * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
bwang 178:4e721c904fd7 1449 * This parameter can be any combination of the following values:
bwang 178:4e721c904fd7 1450 * @arg FLASH_IT_ERR: FLASH Error Interrupt
bwang 178:4e721c904fd7 1451 * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
bwang 178:4e721c904fd7 1452 * @retval None
bwang 178:4e721c904fd7 1453 */
bwang 178:4e721c904fd7 1454 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
bwang 178:4e721c904fd7 1455 {
bwang 178:4e721c904fd7 1456 /* Check the parameters */
bwang 178:4e721c904fd7 1457 assert_param(IS_FLASH_IT(FLASH_IT));
bwang 178:4e721c904fd7 1458 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 178:4e721c904fd7 1459
bwang 178:4e721c904fd7 1460 if(NewState != DISABLE)
bwang 178:4e721c904fd7 1461 {
bwang 178:4e721c904fd7 1462 /* Enable the interrupt sources */
bwang 178:4e721c904fd7 1463 FLASH->CR |= FLASH_IT;
bwang 178:4e721c904fd7 1464 }
bwang 178:4e721c904fd7 1465 else
bwang 178:4e721c904fd7 1466 {
bwang 178:4e721c904fd7 1467 /* Disable the interrupt sources */
bwang 178:4e721c904fd7 1468 FLASH->CR &= ~(uint32_t)FLASH_IT;
bwang 178:4e721c904fd7 1469 }
bwang 178:4e721c904fd7 1470 }
bwang 178:4e721c904fd7 1471
bwang 178:4e721c904fd7 1472 /**
bwang 178:4e721c904fd7 1473 * @brief Checks whether the specified FLASH flag is set or not.
bwang 178:4e721c904fd7 1474 * @param FLASH_FLAG: specifies the FLASH flag to check.
bwang 178:4e721c904fd7 1475 * This parameter can be one of the following values:
bwang 178:4e721c904fd7 1476 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bwang 178:4e721c904fd7 1477 * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
bwang 178:4e721c904fd7 1478 * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
bwang 178:4e721c904fd7 1479 * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
bwang 178:4e721c904fd7 1480 * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
bwang 178:4e721c904fd7 1481 * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
bwang 178:4e721c904fd7 1482 * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
bwang 178:4e721c904fd7 1483 * @arg FLASH_FLAG_BSY: FLASH Busy flag
bwang 178:4e721c904fd7 1484 * @retval The new state of FLASH_FLAG (SET or RESET).
bwang 178:4e721c904fd7 1485 */
bwang 178:4e721c904fd7 1486 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
bwang 178:4e721c904fd7 1487 {
bwang 178:4e721c904fd7 1488 FlagStatus bitstatus = RESET;
bwang 178:4e721c904fd7 1489 /* Check the parameters */
bwang 178:4e721c904fd7 1490 assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
bwang 178:4e721c904fd7 1491
bwang 178:4e721c904fd7 1492 if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
bwang 178:4e721c904fd7 1493 {
bwang 178:4e721c904fd7 1494 bitstatus = SET;
bwang 178:4e721c904fd7 1495 }
bwang 178:4e721c904fd7 1496 else
bwang 178:4e721c904fd7 1497 {
bwang 178:4e721c904fd7 1498 bitstatus = RESET;
bwang 178:4e721c904fd7 1499 }
bwang 178:4e721c904fd7 1500 /* Return the new state of FLASH_FLAG (SET or RESET) */
bwang 178:4e721c904fd7 1501 return bitstatus;
bwang 178:4e721c904fd7 1502 }
bwang 178:4e721c904fd7 1503
bwang 178:4e721c904fd7 1504 /**
bwang 178:4e721c904fd7 1505 * @brief Clears the FLASH's pending flags.
bwang 178:4e721c904fd7 1506 * @param FLASH_FLAG: specifies the FLASH flags to clear.
bwang 178:4e721c904fd7 1507 * This parameter can be any combination of the following values:
bwang 178:4e721c904fd7 1508 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bwang 178:4e721c904fd7 1509 * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
bwang 178:4e721c904fd7 1510 * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
bwang 178:4e721c904fd7 1511 * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
bwang 178:4e721c904fd7 1512 * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
bwang 178:4e721c904fd7 1513 * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
bwang 178:4e721c904fd7 1514 * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
bwang 178:4e721c904fd7 1515 * @retval None
bwang 178:4e721c904fd7 1516 */
bwang 178:4e721c904fd7 1517 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
bwang 178:4e721c904fd7 1518 {
bwang 178:4e721c904fd7 1519 /* Check the parameters */
bwang 178:4e721c904fd7 1520 assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
bwang 178:4e721c904fd7 1521
bwang 178:4e721c904fd7 1522 /* Clear the flags */
bwang 178:4e721c904fd7 1523 FLASH->SR = FLASH_FLAG;
bwang 178:4e721c904fd7 1524 }
bwang 178:4e721c904fd7 1525
bwang 178:4e721c904fd7 1526 /**
bwang 178:4e721c904fd7 1527 * @brief Returns the FLASH Status.
bwang 178:4e721c904fd7 1528 * @param None
bwang 178:4e721c904fd7 1529 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 1530 * FLASH_ERROR_WRP2, FLASH_ERROR_RD2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 1531 */
bwang 178:4e721c904fd7 1532 FLASH_Status FLASH_GetStatus(void)
bwang 178:4e721c904fd7 1533 {
bwang 178:4e721c904fd7 1534 FLASH_Status flashstatus = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1535
bwang 178:4e721c904fd7 1536 if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
bwang 178:4e721c904fd7 1537 {
bwang 178:4e721c904fd7 1538 flashstatus = FLASH_BUSY2;
bwang 178:4e721c904fd7 1539 }
bwang 178:4e721c904fd7 1540 else
bwang 178:4e721c904fd7 1541 {
bwang 178:4e721c904fd7 1542 if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
bwang 178:4e721c904fd7 1543 {
bwang 178:4e721c904fd7 1544 flashstatus = FLASH_ERROR_WRP2;
bwang 178:4e721c904fd7 1545 }
bwang 178:4e721c904fd7 1546 else
bwang 178:4e721c904fd7 1547 {
bwang 178:4e721c904fd7 1548 if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
bwang 178:4e721c904fd7 1549 {
bwang 178:4e721c904fd7 1550 flashstatus = FLASH_ERROR_RD2;
bwang 178:4e721c904fd7 1551 }
bwang 178:4e721c904fd7 1552 else
bwang 178:4e721c904fd7 1553 {
bwang 178:4e721c904fd7 1554 if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
bwang 178:4e721c904fd7 1555 {
bwang 178:4e721c904fd7 1556 flashstatus = FLASH_ERROR_PROGRAM2;
bwang 178:4e721c904fd7 1557 }
bwang 178:4e721c904fd7 1558 else
bwang 178:4e721c904fd7 1559 {
bwang 178:4e721c904fd7 1560 if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
bwang 178:4e721c904fd7 1561 {
bwang 178:4e721c904fd7 1562 flashstatus = FLASH_ERROR_OPERATION2;
bwang 178:4e721c904fd7 1563 }
bwang 178:4e721c904fd7 1564 else
bwang 178:4e721c904fd7 1565 {
bwang 178:4e721c904fd7 1566 flashstatus = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1567 }
bwang 178:4e721c904fd7 1568 }
bwang 178:4e721c904fd7 1569 }
bwang 178:4e721c904fd7 1570 }
bwang 178:4e721c904fd7 1571 }
bwang 178:4e721c904fd7 1572 /* Return the FLASH Status */
bwang 178:4e721c904fd7 1573 return flashstatus;
bwang 178:4e721c904fd7 1574 }
bwang 178:4e721c904fd7 1575
bwang 178:4e721c904fd7 1576 /**
bwang 178:4e721c904fd7 1577 * @brief Waits for a FLASH operation to complete.
bwang 178:4e721c904fd7 1578 * @param None
bwang 178:4e721c904fd7 1579 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 178:4e721c904fd7 1580 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 178:4e721c904fd7 1581 */
bwang 178:4e721c904fd7 1582 FLASH_Status FLASH_WaitForLastOperation2(void)
bwang 178:4e721c904fd7 1583 {
bwang 178:4e721c904fd7 1584 __IO FLASH_Status status = FLASH_COMPLETE2;
bwang 178:4e721c904fd7 1585
bwang 178:4e721c904fd7 1586 /* Check for the FLASH Status */
bwang 178:4e721c904fd7 1587 status = FLASH_GetStatus();
bwang 178:4e721c904fd7 1588
bwang 178:4e721c904fd7 1589 /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
bwang 178:4e721c904fd7 1590 Even if the FLASH operation fails, the BUSY flag will be reset and an error
bwang 178:4e721c904fd7 1591 flag will be set */
bwang 178:4e721c904fd7 1592 while(status == FLASH_BUSY2)
bwang 178:4e721c904fd7 1593 {
bwang 178:4e721c904fd7 1594 status = FLASH_GetStatus();
bwang 178:4e721c904fd7 1595 }
bwang 178:4e721c904fd7 1596 /* Return the operation status */
bwang 178:4e721c904fd7 1597 return status;
bwang 178:4e721c904fd7 1598 }
bwang 178:4e721c904fd7 1599
bwang 178:4e721c904fd7 1600 /**
bwang 178:4e721c904fd7 1601 * @}
bwang 178:4e721c904fd7 1602 */
bwang 178:4e721c904fd7 1603
bwang 178:4e721c904fd7 1604 /**
bwang 178:4e721c904fd7 1605 * @}
bwang 178:4e721c904fd7 1606 */
bwang 178:4e721c904fd7 1607
bwang 178:4e721c904fd7 1608 /**
bwang 178:4e721c904fd7 1609 * @}
bwang 178:4e721c904fd7 1610 */
bwang 178:4e721c904fd7 1611
bwang 178:4e721c904fd7 1612 /**
bwang 178:4e721c904fd7 1613 * @}
bwang 178:4e721c904fd7 1614 */
bwang 178:4e721c904fd7 1615
bwang 178:4e721c904fd7 1616 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/