dc_motor_control - bad dc motor controller with current mode

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Bayley Wang / Mbed 2 deprecated dc_motor_control

bad dc motor controller with current mode

PreferenceWriter/stm32f4xx_flash.c@0:2b1edabdd26b, 2019-02-03 (annotated)

Committer:: bwang
Date:: Sun Feb 03 03:38:05 2019 +0000
Revision:: 0:2b1edabdd26b

first commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
bwang	0:2b1edabdd26b	1	/**
bwang	0:2b1edabdd26b	2	******************************************************************************
bwang	0:2b1edabdd26b	3	* @file stm32f4xx_flash.c
bwang	0:2b1edabdd26b	4	* @author MCD Application Team
bwang	0:2b1edabdd26b	5	* @version V1.7.1
bwang	0:2b1edabdd26b	6	* @date 20-May-2016
bwang	0:2b1edabdd26b	7	* @brief This file provides firmware functions to manage the following
bwang	0:2b1edabdd26b	8	* functionalities of the FLASH peripheral:
bwang	0:2b1edabdd26b	9	* + FLASH Interface configuration
bwang	0:2b1edabdd26b	10	* + FLASH Memory Programming
bwang	0:2b1edabdd26b	11	* + Option Bytes Programming
bwang	0:2b1edabdd26b	12	* + Interrupts and flags management
bwang	0:2b1edabdd26b	13	*
bwang	0:2b1edabdd26b	14	@verbatim
bwang	0:2b1edabdd26b	15	===============================================================================
bwang	0:2b1edabdd26b	16	##### How to use this driver #####
bwang	0:2b1edabdd26b	17	===============================================================================
bwang	0:2b1edabdd26b	18	[..]
bwang	0:2b1edabdd26b	19	This driver provides functions to configure and program the FLASH memory
bwang	0:2b1edabdd26b	20	of all STM32F4xx devices. These functions are split in 4 groups:
bwang	0:2b1edabdd26b	21
bwang	0:2b1edabdd26b	22	(#) FLASH Interface configuration functions: this group includes the
bwang	0:2b1edabdd26b	23	management of the following features:
bwang	0:2b1edabdd26b	24	(++) Set the latency
bwang	0:2b1edabdd26b	25	(++) Enable/Disable the prefetch buffer
bwang	0:2b1edabdd26b	26	(++) Enable/Disable the Instruction cache and the Data cache
bwang	0:2b1edabdd26b	27	(++) Reset the Instruction cache and the Data cache
bwang	0:2b1edabdd26b	28
bwang	0:2b1edabdd26b	29	(#) FLASH Memory Programming functions: this group includes all needed
bwang	0:2b1edabdd26b	30	functions to erase and program the main memory:
bwang	0:2b1edabdd26b	31	(++) Lock and Unlock the FLASH interface
bwang	0:2b1edabdd26b	32	(++) Erase function: Erase sector, erase all sectors
bwang	0:2b1edabdd26b	33	(++) Program functions: byte, half word, word and double word
bwang	0:2b1edabdd26b	34
bwang	0:2b1edabdd26b	35	(#) Option Bytes Programming functions: this group includes all needed
bwang	0:2b1edabdd26b	36	functions to manage the Option Bytes:
bwang	0:2b1edabdd26b	37	(++) Set/Reset the write protection
bwang	0:2b1edabdd26b	38	(++) Set the Read protection Level
bwang	0:2b1edabdd26b	39	(++) Set the BOR level
bwang	0:2b1edabdd26b	40	(++) Program the user Option Bytes
bwang	0:2b1edabdd26b	41	(++) Launch the Option Bytes loader
bwang	0:2b1edabdd26b	42
bwang	0:2b1edabdd26b	43	(#) Interrupts and flags management functions: this group
bwang	0:2b1edabdd26b	44	includes all needed functions to:
bwang	0:2b1edabdd26b	45	(++) Enable/Disable the FLASH interrupt sources
bwang	0:2b1edabdd26b	46	(++) Get flags status
bwang	0:2b1edabdd26b	47	(++) Clear flags
bwang	0:2b1edabdd26b	48	(++) Get FLASH operation status
bwang	0:2b1edabdd26b	49	(++) Wait for last FLASH operation
bwang	0:2b1edabdd26b	50	@endverbatim
bwang	0:2b1edabdd26b	51	******************************************************************************
bwang	0:2b1edabdd26b	52	* @attention
bwang	0:2b1edabdd26b	53	*
bwang	0:2b1edabdd26b	54	* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
bwang	0:2b1edabdd26b	55	*
bwang	0:2b1edabdd26b	56	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
bwang	0:2b1edabdd26b	57	* You may not use this file except in compliance with the License.
bwang	0:2b1edabdd26b	58	* You may obtain a copy of the License at:
bwang	0:2b1edabdd26b	59	*
bwang	0:2b1edabdd26b	60	* http://www.st.com/software_license_agreement_liberty_v2
bwang	0:2b1edabdd26b	61	*
bwang	0:2b1edabdd26b	62	* Unless required by applicable law or agreed to in writing, software
bwang	0:2b1edabdd26b	63	* distributed under the License is distributed on an "AS IS" BASIS,
bwang	0:2b1edabdd26b	64	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bwang	0:2b1edabdd26b	65	* See the License for the specific language governing permissions and
bwang	0:2b1edabdd26b	66	* limitations under the License.
bwang	0:2b1edabdd26b	67	*
bwang	0:2b1edabdd26b	68	******************************************************************************
bwang	0:2b1edabdd26b	69	*/
bwang	0:2b1edabdd26b	70
bwang	0:2b1edabdd26b	71	/* Includes ------------------------------------------------------------------*/
bwang	0:2b1edabdd26b	72	#include "stm32f4xx_flash.h"
bwang	0:2b1edabdd26b	73
bwang	0:2b1edabdd26b	74	/** @addtogroup STM32F4xx_StdPeriph_Driver
bwang	0:2b1edabdd26b	75	* @{
bwang	0:2b1edabdd26b	76	*/
bwang	0:2b1edabdd26b	77
bwang	0:2b1edabdd26b	78	/** @defgroup FLASH
bwang	0:2b1edabdd26b	79	* @brief FLASH driver modules
bwang	0:2b1edabdd26b	80	* @{
bwang	0:2b1edabdd26b	81	*/
bwang	0:2b1edabdd26b	82
bwang	0:2b1edabdd26b	83	/* Private typedef -----------------------------------------------------------*/
bwang	0:2b1edabdd26b	84	/* Private define ------------------------------------------------------------*/
bwang	0:2b1edabdd26b	85	#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
bwang	0:2b1edabdd26b	86
bwang	0:2b1edabdd26b	87	/* Private macro -------------------------------------------------------------*/
bwang	0:2b1edabdd26b	88	/* Private variables ---------------------------------------------------------*/
bwang	0:2b1edabdd26b	89	/* Private function prototypes -----------------------------------------------*/
bwang	0:2b1edabdd26b	90	/* Private functions ---------------------------------------------------------*/
bwang	0:2b1edabdd26b	91
bwang	0:2b1edabdd26b	92	/** @defgroup FLASH_Private_Functions
bwang	0:2b1edabdd26b	93	* @{
bwang	0:2b1edabdd26b	94	*/
bwang	0:2b1edabdd26b	95
bwang	0:2b1edabdd26b	96	/** @defgroup FLASH_Group1 FLASH Interface configuration functions
bwang	0:2b1edabdd26b	97	* @brief FLASH Interface configuration functions
bwang	0:2b1edabdd26b	98	*
bwang	0:2b1edabdd26b	99
bwang	0:2b1edabdd26b	100	@verbatim
bwang	0:2b1edabdd26b	101	===============================================================================
bwang	0:2b1edabdd26b	102	##### FLASH Interface configuration functions #####
bwang	0:2b1edabdd26b	103	===============================================================================
bwang	0:2b1edabdd26b	104	[..]
bwang	0:2b1edabdd26b	105	This group includes the following functions:
bwang	0:2b1edabdd26b	106	(+) void FLASH_SetLatency(uint32_t FLASH_Latency)
bwang	0:2b1edabdd26b	107	To correctly read data from FLASH memory, the number of wait states (LATENCY)
bwang	0:2b1edabdd26b	108	must be correctly programmed according to the frequency of the CPU clock
bwang	0:2b1edabdd26b	109	(HCLK) and the supply voltage of the device.
bwang	0:2b1edabdd26b	110	[..]
bwang	0:2b1edabdd26b	111	For STM32F405xx/07xx and STM32F415xx/17xx devices
bwang	0:2b1edabdd26b	112	+-------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	113	\| Latency \| HCLK clock frequency (MHz) \|
bwang	0:2b1edabdd26b	114	\| \|---------------------------------------------------------------------\|
bwang	0:2b1edabdd26b	115	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
bwang	0:2b1edabdd26b	116	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
bwang	0:2b1edabdd26b	117	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	118	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
bwang	0:2b1edabdd26b	119	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	120	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
bwang	0:2b1edabdd26b	121	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	122	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
bwang	0:2b1edabdd26b	123	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	124	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
bwang	0:2b1edabdd26b	125	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	126	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
bwang	0:2b1edabdd26b	127	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	128	\|5WS(6CPU cycle)\|150< HCLK <= 168\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
bwang	0:2b1edabdd26b	129	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	130	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
bwang	0:2b1edabdd26b	131	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	132	\|7WS(8CPU cycle)\| NA \| NA \|154 < HCLK <= 168\|140 < HCLK <= 160\|
bwang	0:2b1edabdd26b	133	+---------------\|----------------\|----------------\|-----------------\|-----------------+
bwang	0:2b1edabdd26b	134
bwang	0:2b1edabdd26b	135	[..]
bwang	0:2b1edabdd26b	136	For STM32F42xxx/43xxx devices
bwang	0:2b1edabdd26b	137	+-------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	138	\| Latency \| HCLK clock frequency (MHz) \|
bwang	0:2b1edabdd26b	139	\| \|---------------------------------------------------------------------\|
bwang	0:2b1edabdd26b	140	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
bwang	0:2b1edabdd26b	141	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
bwang	0:2b1edabdd26b	142	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	143	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
bwang	0:2b1edabdd26b	144	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	145	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
bwang	0:2b1edabdd26b	146	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	147	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
bwang	0:2b1edabdd26b	148	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	149	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
bwang	0:2b1edabdd26b	150	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	151	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
bwang	0:2b1edabdd26b	152	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	153	\|5WS(6CPU cycle)\|120< HCLK <= 180\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
bwang	0:2b1edabdd26b	154	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	155	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
bwang	0:2b1edabdd26b	156	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	157	\|7WS(8CPU cycle)\| NA \|168< HCLK <= 180\|154 < HCLK <= 176\|140 < HCLK <= 160\|
bwang	0:2b1edabdd26b	158	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	159	\|8WS(9CPU cycle)\| NA \| NA \|176 < HCLK <= 180\|160 < HCLK <= 168\|
bwang	0:2b1edabdd26b	160	+-------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	161
bwang	0:2b1edabdd26b	162	[..]
bwang	0:2b1edabdd26b	163	For STM32F401x devices
bwang	0:2b1edabdd26b	164	+-------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	165	\| Latency \| HCLK clock frequency (MHz) \|
bwang	0:2b1edabdd26b	166	\| \|---------------------------------------------------------------------\|
bwang	0:2b1edabdd26b	167	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
bwang	0:2b1edabdd26b	168	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
bwang	0:2b1edabdd26b	169	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	170	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
bwang	0:2b1edabdd26b	171	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	172	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
bwang	0:2b1edabdd26b	173	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	174	\|2WS(3CPU cycle)\|60 < HCLK <= 84 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
bwang	0:2b1edabdd26b	175	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	176	\|3WS(4CPU cycle)\| NA \|72 < HCLK <= 84 \|66 < HCLK <= 84 \|60 < HCLK <= 80 \|
bwang	0:2b1edabdd26b	177	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	178	\|4WS(5CPU cycle)\| NA \| NA \| NA \|80 < HCLK <= 84 \|
bwang	0:2b1edabdd26b	179	+-------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	180
bwang	0:2b1edabdd26b	181	[..]
bwang	0:2b1edabdd26b	182	For STM32F410xx/STM32F411xE devices
bwang	0:2b1edabdd26b	183	+-------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	184	\| Latency \| HCLK clock frequency (MHz) \|
bwang	0:2b1edabdd26b	185	\| \|---------------------------------------------------------------------\|
bwang	0:2b1edabdd26b	186	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
bwang	0:2b1edabdd26b	187	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
bwang	0:2b1edabdd26b	188	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	189	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 18 \|0 < HCLK <= 16 \|
bwang	0:2b1edabdd26b	190	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	191	\|1WS(2CPU cycle)\|30 < HCLK <= 64 \|24 < HCLK <= 48 \|18 < HCLK <= 36 \|16 < HCLK <= 32 \|
bwang	0:2b1edabdd26b	192	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	193	\|2WS(3CPU cycle)\|64 < HCLK <= 90 \|48 < HCLK <= 72 \|36 < HCLK <= 54 \|32 < HCLK <= 48 \|
bwang	0:2b1edabdd26b	194	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	195	\|3WS(4CPU cycle)\|90 < HCLK <= 100\|72 < HCLK <= 96 \|54 < HCLK <= 72 \|48 < HCLK <= 64 \|
bwang	0:2b1edabdd26b	196	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	197	\|4WS(5CPU cycle)\| NA \|96 < HCLK <= 100\|72 < HCLK <= 90 \|64 < HCLK <= 80 \|
bwang	0:2b1edabdd26b	198	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	199	\|5WS(6CPU cycle)\| NA \| NA \|90 < HCLK <= 100 \|80 < HCLK <= 96 \|
bwang	0:2b1edabdd26b	200	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
bwang	0:2b1edabdd26b	201	\|6WS(7CPU cycle)\| NA \| NA \| NA \|96 < HCLK <= 100 \|
bwang	0:2b1edabdd26b	202	+-------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	203
bwang	0:2b1edabdd26b	204	[..]
bwang	0:2b1edabdd26b	205	+-------------------------------------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	206	\| \| voltage range \| voltage range \| voltage range \| voltage range \| voltage range 2.7 V - 3.6 V \|
bwang	0:2b1edabdd26b	207	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \| with External Vpp = 9V \|
bwang	0:2b1edabdd26b	208	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|-----------------------------\|
bwang	0:2b1edabdd26b	209	\|Max Parallelism\| x32 \| x16 \| x8 \| x64 \|
bwang	0:2b1edabdd26b	210	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|-----------------------------\|
bwang	0:2b1edabdd26b	211	\|PSIZE[1:0] \| 10 \| 01 \| 00 \| 11 \|
bwang	0:2b1edabdd26b	212	+-------------------------------------------------------------------------------------------------------------------+
bwang	0:2b1edabdd26b	213
bwang	0:2b1edabdd26b	214	-@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
bwang	0:2b1edabdd26b	215	(++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
bwang	0:2b1edabdd26b	216	(++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
bwang	0:2b1edabdd26b	217	[..]
bwang	0:2b1edabdd26b	218	On STM32F42xxx/43xxx devices:
bwang	0:2b1edabdd26b	219	(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
bwang	0:2b1edabdd26b	220	(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
bwang	0:2b1edabdd26b	221	(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
bwang	0:2b1edabdd26b	222	[..]
bwang	0:2b1edabdd26b	223	On STM32F401x devices:
bwang	0:2b1edabdd26b	224	(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
bwang	0:2b1edabdd26b	225	(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
bwang	0:2b1edabdd26b	226	[..]
bwang	0:2b1edabdd26b	227	On STM32F410xx/STM32F411xE devices:
bwang	0:2b1edabdd26b	228	(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
bwang	0:2b1edabdd26b	229	(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
bwang	0:2b1edabdd26b	230	(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
bwang	0:2b1edabdd26b	231
bwang	0:2b1edabdd26b	232	For more details please refer product DataSheet
bwang	0:2b1edabdd26b	233	You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
bwang	0:2b1edabdd26b	234
bwang	0:2b1edabdd26b	235	(+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
bwang	0:2b1edabdd26b	236	(+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
bwang	0:2b1edabdd26b	237	(+) void FLASH_DataCacheCmd(FunctionalState NewState)
bwang	0:2b1edabdd26b	238	(+) void FLASH_InstructionCacheReset(void)
bwang	0:2b1edabdd26b	239	(+) void FLASH_DataCacheReset(void)
bwang	0:2b1edabdd26b	240
bwang	0:2b1edabdd26b	241	[..]
bwang	0:2b1edabdd26b	242	The unlock sequence is not needed for these functions.
bwang	0:2b1edabdd26b	243
bwang	0:2b1edabdd26b	244	@endverbatim
bwang	0:2b1edabdd26b	245	* @{
bwang	0:2b1edabdd26b	246	*/
bwang	0:2b1edabdd26b	247
bwang	0:2b1edabdd26b	248	/**
bwang	0:2b1edabdd26b	249	* @brief Sets the code latency value.
bwang	0:2b1edabdd26b	250	* @param FLASH_Latency: specifies the FLASH Latency value.
bwang	0:2b1edabdd26b	251	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	252	* @arg FLASH_Latency_0: FLASH Zero Latency cycle
bwang	0:2b1edabdd26b	253	* @arg FLASH_Latency_1: FLASH One Latency cycle
bwang	0:2b1edabdd26b	254	* @arg FLASH_Latency_2: FLASH Two Latency cycles
bwang	0:2b1edabdd26b	255	* @arg FLASH_Latency_3: FLASH Three Latency cycles
bwang	0:2b1edabdd26b	256	* @arg FLASH_Latency_4: FLASH Four Latency cycles
bwang	0:2b1edabdd26b	257	* @arg FLASH_Latency_5: FLASH Five Latency cycles
bwang	0:2b1edabdd26b	258	* @arg FLASH_Latency_6: FLASH Six Latency cycles
bwang	0:2b1edabdd26b	259	* @arg FLASH_Latency_7: FLASH Seven Latency cycles
bwang	0:2b1edabdd26b	260	* @arg FLASH_Latency_8: FLASH Eight Latency cycles
bwang	0:2b1edabdd26b	261	* @arg FLASH_Latency_9: FLASH Nine Latency cycles
bwang	0:2b1edabdd26b	262	* @arg FLASH_Latency_10: FLASH Teen Latency cycles
bwang	0:2b1edabdd26b	263	* @arg FLASH_Latency_11: FLASH Eleven Latency cycles
bwang	0:2b1edabdd26b	264	* @arg FLASH_Latency_12: FLASH Twelve Latency cycles
bwang	0:2b1edabdd26b	265	* @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
bwang	0:2b1edabdd26b	266	* @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
bwang	0:2b1edabdd26b	267	* @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
bwang	0:2b1edabdd26b	268	*
bwang	0:2b1edabdd26b	269	* @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE and STM32F412xG devices
bwang	0:2b1edabdd26b	270	* this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
bwang	0:2b1edabdd26b	271	*
bwang	0:2b1edabdd26b	272	* @note For STM32F42xxx/43xxx devices this parameter can be a value between
bwang	0:2b1edabdd26b	273	* FLASH_Latency_0 and FLASH_Latency_15.
bwang	0:2b1edabdd26b	274	*
bwang	0:2b1edabdd26b	275	* @retval None
bwang	0:2b1edabdd26b	276	*/
bwang	0:2b1edabdd26b	277	void FLASH_SetLatency(uint32_t FLASH_Latency)
bwang	0:2b1edabdd26b	278	{
bwang	0:2b1edabdd26b	279	/* Check the parameters */
bwang	0:2b1edabdd26b	280	assert_param(IS_FLASH_LATENCY(FLASH_Latency));
bwang	0:2b1edabdd26b	281
bwang	0:2b1edabdd26b	282	/* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
bwang	0:2b1edabdd26b	283	(__IO uint8_t )ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
bwang	0:2b1edabdd26b	284	}
bwang	0:2b1edabdd26b	285
bwang	0:2b1edabdd26b	286	/**
bwang	0:2b1edabdd26b	287	* @brief Enables or disables the Prefetch Buffer.
bwang	0:2b1edabdd26b	288	* @param NewState: new state of the Prefetch Buffer.
bwang	0:2b1edabdd26b	289	* This parameter can be: ENABLE or DISABLE.
bwang	0:2b1edabdd26b	290	* @retval None
bwang	0:2b1edabdd26b	291	*/
bwang	0:2b1edabdd26b	292	void FLASH_PrefetchBufferCmd(FunctionalState NewState)
bwang	0:2b1edabdd26b	293	{
bwang	0:2b1edabdd26b	294	/* Check the parameters */
bwang	0:2b1edabdd26b	295	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	296
bwang	0:2b1edabdd26b	297	/* Enable or disable the Prefetch Buffer */
bwang	0:2b1edabdd26b	298	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	299	{
bwang	0:2b1edabdd26b	300	FLASH->ACR \|= FLASH_ACR_PRFTEN;
bwang	0:2b1edabdd26b	301	}
bwang	0:2b1edabdd26b	302	else
bwang	0:2b1edabdd26b	303	{
bwang	0:2b1edabdd26b	304	FLASH->ACR &= (~FLASH_ACR_PRFTEN);
bwang	0:2b1edabdd26b	305	}
bwang	0:2b1edabdd26b	306	}
bwang	0:2b1edabdd26b	307
bwang	0:2b1edabdd26b	308	/**
bwang	0:2b1edabdd26b	309	* @brief Enables or disables the Instruction Cache feature.
bwang	0:2b1edabdd26b	310	* @param NewState: new state of the Instruction Cache.
bwang	0:2b1edabdd26b	311	* This parameter can be: ENABLE or DISABLE.
bwang	0:2b1edabdd26b	312	* @retval None
bwang	0:2b1edabdd26b	313	*/
bwang	0:2b1edabdd26b	314	void FLASH_InstructionCacheCmd(FunctionalState NewState)
bwang	0:2b1edabdd26b	315	{
bwang	0:2b1edabdd26b	316	/* Check the parameters */
bwang	0:2b1edabdd26b	317	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	318
bwang	0:2b1edabdd26b	319	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	320	{
bwang	0:2b1edabdd26b	321	FLASH->ACR \|= FLASH_ACR_ICEN;
bwang	0:2b1edabdd26b	322	}
bwang	0:2b1edabdd26b	323	else
bwang	0:2b1edabdd26b	324	{
bwang	0:2b1edabdd26b	325	FLASH->ACR &= (~FLASH_ACR_ICEN);
bwang	0:2b1edabdd26b	326	}
bwang	0:2b1edabdd26b	327	}
bwang	0:2b1edabdd26b	328
bwang	0:2b1edabdd26b	329	/**
bwang	0:2b1edabdd26b	330	* @brief Enables or disables the Data Cache feature.
bwang	0:2b1edabdd26b	331	* @param NewState: new state of the Data Cache.
bwang	0:2b1edabdd26b	332	* This parameter can be: ENABLE or DISABLE.
bwang	0:2b1edabdd26b	333	* @retval None
bwang	0:2b1edabdd26b	334	*/
bwang	0:2b1edabdd26b	335	void FLASH_DataCacheCmd(FunctionalState NewState)
bwang	0:2b1edabdd26b	336	{
bwang	0:2b1edabdd26b	337	/* Check the parameters */
bwang	0:2b1edabdd26b	338	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	339
bwang	0:2b1edabdd26b	340	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	341	{
bwang	0:2b1edabdd26b	342	FLASH->ACR \|= FLASH_ACR_DCEN;
bwang	0:2b1edabdd26b	343	}
bwang	0:2b1edabdd26b	344	else
bwang	0:2b1edabdd26b	345	{
bwang	0:2b1edabdd26b	346	FLASH->ACR &= (~FLASH_ACR_DCEN);
bwang	0:2b1edabdd26b	347	}
bwang	0:2b1edabdd26b	348	}
bwang	0:2b1edabdd26b	349
bwang	0:2b1edabdd26b	350	/**
bwang	0:2b1edabdd26b	351	* @brief Resets the Instruction Cache.
bwang	0:2b1edabdd26b	352	* @note This function must be used only when the Instruction Cache is disabled.
bwang	0:2b1edabdd26b	353	* @param None
bwang	0:2b1edabdd26b	354	* @retval None
bwang	0:2b1edabdd26b	355	*/
bwang	0:2b1edabdd26b	356	void FLASH_InstructionCacheReset(void)
bwang	0:2b1edabdd26b	357	{
bwang	0:2b1edabdd26b	358	FLASH->ACR \|= FLASH_ACR_ICRST;
bwang	0:2b1edabdd26b	359	}
bwang	0:2b1edabdd26b	360
bwang	0:2b1edabdd26b	361	/**
bwang	0:2b1edabdd26b	362	* @brief Resets the Data Cache.
bwang	0:2b1edabdd26b	363	* @note This function must be used only when the Data Cache is disabled.
bwang	0:2b1edabdd26b	364	* @param None
bwang	0:2b1edabdd26b	365	* @retval None
bwang	0:2b1edabdd26b	366	*/
bwang	0:2b1edabdd26b	367	void FLASH_DataCacheReset(void)
bwang	0:2b1edabdd26b	368	{
bwang	0:2b1edabdd26b	369	FLASH->ACR \|= FLASH_ACR_DCRST;
bwang	0:2b1edabdd26b	370	}
bwang	0:2b1edabdd26b	371
bwang	0:2b1edabdd26b	372	/**
bwang	0:2b1edabdd26b	373	* @}
bwang	0:2b1edabdd26b	374	*/
bwang	0:2b1edabdd26b	375
bwang	0:2b1edabdd26b	376	/** @defgroup FLASH_Group2 FLASH Memory Programming functions
bwang	0:2b1edabdd26b	377	* @brief FLASH Memory Programming functions
bwang	0:2b1edabdd26b	378	*
bwang	0:2b1edabdd26b	379	@verbatim
bwang	0:2b1edabdd26b	380	===============================================================================
bwang	0:2b1edabdd26b	381	##### FLASH Memory Programming functions #####
bwang	0:2b1edabdd26b	382	===============================================================================
bwang	0:2b1edabdd26b	383	[..]
bwang	0:2b1edabdd26b	384	This group includes the following functions:
bwang	0:2b1edabdd26b	385	(+) void FLASH_Unlock(void)
bwang	0:2b1edabdd26b	386	(+) void FLASH_Lock(void)
bwang	0:2b1edabdd26b	387	(+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
bwang	0:2b1edabdd26b	388	(+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
bwang	0:2b1edabdd26b	389	(+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
bwang	0:2b1edabdd26b	390	(+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
bwang	0:2b1edabdd26b	391	(+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
bwang	0:2b1edabdd26b	392	(+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
bwang	0:2b1edabdd26b	393	The following functions can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	394	(+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
bwang	0:2b1edabdd26b	395	(+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
bwang	0:2b1edabdd26b	396	[..]
bwang	0:2b1edabdd26b	397	Any operation of erase or program should follow these steps:
bwang	0:2b1edabdd26b	398	(#) Call the FLASH_Unlock() function to enable the FLASH control register access
bwang	0:2b1edabdd26b	399
bwang	0:2b1edabdd26b	400	(#) Call the desired function to erase sector(s) or program data
bwang	0:2b1edabdd26b	401
bwang	0:2b1edabdd26b	402	(#) Call the FLASH_Lock() function to disable the FLASH control register access
bwang	0:2b1edabdd26b	403	(recommended to protect the FLASH memory against possible unwanted operation)
bwang	0:2b1edabdd26b	404
bwang	0:2b1edabdd26b	405	@endverbatim
bwang	0:2b1edabdd26b	406	* @{
bwang	0:2b1edabdd26b	407	*/
bwang	0:2b1edabdd26b	408
bwang	0:2b1edabdd26b	409	/**
bwang	0:2b1edabdd26b	410	* @brief Unlocks the FLASH control register access
bwang	0:2b1edabdd26b	411	* @param None
bwang	0:2b1edabdd26b	412	* @retval None
bwang	0:2b1edabdd26b	413	*/
bwang	0:2b1edabdd26b	414	void FLASH_Unlock(void)
bwang	0:2b1edabdd26b	415	{
bwang	0:2b1edabdd26b	416	if((FLASH->CR & FLASH_CR_LOCK) != RESET)
bwang	0:2b1edabdd26b	417	{
bwang	0:2b1edabdd26b	418	/* Authorize the FLASH Registers access */
bwang	0:2b1edabdd26b	419	FLASH->KEYR = FLASH_KEY1;
bwang	0:2b1edabdd26b	420	FLASH->KEYR = FLASH_KEY2;
bwang	0:2b1edabdd26b	421	}
bwang	0:2b1edabdd26b	422	}
bwang	0:2b1edabdd26b	423
bwang	0:2b1edabdd26b	424	/**
bwang	0:2b1edabdd26b	425	* @brief Locks the FLASH control register access
bwang	0:2b1edabdd26b	426	* @param None
bwang	0:2b1edabdd26b	427	* @retval None
bwang	0:2b1edabdd26b	428	*/
bwang	0:2b1edabdd26b	429	void FLASH_Lock(void)
bwang	0:2b1edabdd26b	430	{
bwang	0:2b1edabdd26b	431	/* Set the LOCK Bit to lock the FLASH Registers access */
bwang	0:2b1edabdd26b	432	FLASH->CR \|= FLASH_CR_LOCK;
bwang	0:2b1edabdd26b	433	}
bwang	0:2b1edabdd26b	434
bwang	0:2b1edabdd26b	435	/**
bwang	0:2b1edabdd26b	436	* @brief Erases a specified FLASH Sector.
bwang	0:2b1edabdd26b	437	*
bwang	0:2b1edabdd26b	438	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	439	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	440	*
bwang	0:2b1edabdd26b	441	* @param FLASH_Sector: The Sector number to be erased.
bwang	0:2b1edabdd26b	442	*
bwang	0:2b1edabdd26b	443	* @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
bwang	0:2b1edabdd26b	444	* be a value between FLASH_Sector_0 and FLASH_Sector_11.
bwang	0:2b1edabdd26b	445	*
bwang	0:2b1edabdd26b	446	* For STM32F42xxx/43xxx devices this parameter can be a value between
bwang	0:2b1edabdd26b	447	* FLASH_Sector_0 and FLASH_Sector_23.
bwang	0:2b1edabdd26b	448	*
bwang	0:2b1edabdd26b	449	* For STM32F401xx devices this parameter can be a value between
bwang	0:2b1edabdd26b	450	* FLASH_Sector_0 and FLASH_Sector_5.
bwang	0:2b1edabdd26b	451	*
bwang	0:2b1edabdd26b	452	* For STM32F411xE and STM32F412xG devices this parameter can be a value between
bwang	0:2b1edabdd26b	453	* FLASH_Sector_0 and FLASH_Sector_7.
bwang	0:2b1edabdd26b	454	*
bwang	0:2b1edabdd26b	455	* For STM32F410xx devices this parameter can be a value between
bwang	0:2b1edabdd26b	456	* FLASH_Sector_0 and FLASH_Sector_4.
bwang	0:2b1edabdd26b	457	*
bwang	0:2b1edabdd26b	458	* @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang	0:2b1edabdd26b	459	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	460	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang	0:2b1edabdd26b	461	* the operation will be done by byte (8-bit)
bwang	0:2b1edabdd26b	462	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang	0:2b1edabdd26b	463	* the operation will be done by half word (16-bit)
bwang	0:2b1edabdd26b	464	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang	0:2b1edabdd26b	465	* the operation will be done by word (32-bit)
bwang	0:2b1edabdd26b	466	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang	0:2b1edabdd26b	467	* the operation will be done by double word (64-bit)
bwang	0:2b1edabdd26b	468	*
bwang	0:2b1edabdd26b	469	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	470	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	471	*/
bwang	0:2b1edabdd26b	472	FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
bwang	0:2b1edabdd26b	473	{
bwang	0:2b1edabdd26b	474	uint32_t tmp_psize = 0x0;
bwang	0:2b1edabdd26b	475	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	476
bwang	0:2b1edabdd26b	477	/* Check the parameters */
bwang	0:2b1edabdd26b	478	assert_param(IS_FLASH_SECTOR(FLASH_Sector));
bwang	0:2b1edabdd26b	479	assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang	0:2b1edabdd26b	480
bwang	0:2b1edabdd26b	481	if(VoltageRange == VoltageRange_1)
bwang	0:2b1edabdd26b	482	{
bwang	0:2b1edabdd26b	483	tmp_psize = FLASH_PSIZE_BYTE;
bwang	0:2b1edabdd26b	484	}
bwang	0:2b1edabdd26b	485	else if(VoltageRange == VoltageRange_2)
bwang	0:2b1edabdd26b	486	{
bwang	0:2b1edabdd26b	487	tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang	0:2b1edabdd26b	488	}
bwang	0:2b1edabdd26b	489	else if(VoltageRange == VoltageRange_3)
bwang	0:2b1edabdd26b	490	{
bwang	0:2b1edabdd26b	491	tmp_psize = FLASH_PSIZE_WORD;
bwang	0:2b1edabdd26b	492	}
bwang	0:2b1edabdd26b	493	else
bwang	0:2b1edabdd26b	494	{
bwang	0:2b1edabdd26b	495	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang	0:2b1edabdd26b	496	}
bwang	0:2b1edabdd26b	497	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	498	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	499
bwang	0:2b1edabdd26b	500	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	501	{
bwang	0:2b1edabdd26b	502	/* if the previous operation is completed, proceed to erase the sector */
bwang	0:2b1edabdd26b	503	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	504	FLASH->CR \|= tmp_psize;
bwang	0:2b1edabdd26b	505	FLASH->CR &= SECTOR_MASK;
bwang	0:2b1edabdd26b	506	FLASH->CR \|= FLASH_CR_SER \| FLASH_Sector;
bwang	0:2b1edabdd26b	507	FLASH->CR \|= FLASH_CR_STRT;
bwang	0:2b1edabdd26b	508
bwang	0:2b1edabdd26b	509	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	510	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	511
bwang	0:2b1edabdd26b	512	/* if the erase operation is completed, disable the SER Bit */
bwang	0:2b1edabdd26b	513	FLASH->CR &= (~FLASH_CR_SER);
bwang	0:2b1edabdd26b	514	FLASH->CR &= SECTOR_MASK;
bwang	0:2b1edabdd26b	515	}
bwang	0:2b1edabdd26b	516	/* Return the Erase Status */
bwang	0:2b1edabdd26b	517	return status;
bwang	0:2b1edabdd26b	518	}
bwang	0:2b1edabdd26b	519
bwang	0:2b1edabdd26b	520	/**
bwang	0:2b1edabdd26b	521	* @brief Erases all FLASH Sectors.
bwang	0:2b1edabdd26b	522	*
bwang	0:2b1edabdd26b	523	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	524	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	525	*
bwang	0:2b1edabdd26b	526	* @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang	0:2b1edabdd26b	527	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	528	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang	0:2b1edabdd26b	529	* the operation will be done by byte (8-bit)
bwang	0:2b1edabdd26b	530	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang	0:2b1edabdd26b	531	* the operation will be done by half word (16-bit)
bwang	0:2b1edabdd26b	532	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang	0:2b1edabdd26b	533	* the operation will be done by word (32-bit)
bwang	0:2b1edabdd26b	534	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang	0:2b1edabdd26b	535	* the operation will be done by double word (64-bit)
bwang	0:2b1edabdd26b	536	*
bwang	0:2b1edabdd26b	537	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	538	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	539	*/
bwang	0:2b1edabdd26b	540	FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
bwang	0:2b1edabdd26b	541	{
bwang	0:2b1edabdd26b	542	uint32_t tmp_psize = 0x0;
bwang	0:2b1edabdd26b	543	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	544
bwang	0:2b1edabdd26b	545	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	546	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	547	assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang	0:2b1edabdd26b	548
bwang	0:2b1edabdd26b	549	if(VoltageRange == VoltageRange_1)
bwang	0:2b1edabdd26b	550	{
bwang	0:2b1edabdd26b	551	tmp_psize = FLASH_PSIZE_BYTE;
bwang	0:2b1edabdd26b	552	}
bwang	0:2b1edabdd26b	553	else if(VoltageRange == VoltageRange_2)
bwang	0:2b1edabdd26b	554	{
bwang	0:2b1edabdd26b	555	tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang	0:2b1edabdd26b	556	}
bwang	0:2b1edabdd26b	557	else if(VoltageRange == VoltageRange_3)
bwang	0:2b1edabdd26b	558	{
bwang	0:2b1edabdd26b	559	tmp_psize = FLASH_PSIZE_WORD;
bwang	0:2b1edabdd26b	560	}
bwang	0:2b1edabdd26b	561	else
bwang	0:2b1edabdd26b	562	{
bwang	0:2b1edabdd26b	563	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang	0:2b1edabdd26b	564	}
bwang	0:2b1edabdd26b	565	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	566	{
bwang	0:2b1edabdd26b	567	/* if the previous operation is completed, proceed to erase all sectors */
bwang	0:2b1edabdd26b	568	#if defined(STM32F427_437xx) \|\| defined(STM32F429_439xx) \|\| defined(STM32F469_479xx)
bwang	0:2b1edabdd26b	569	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	570	FLASH->CR \|= tmp_psize;
bwang	0:2b1edabdd26b	571	FLASH->CR \|= (FLASH_CR_MER1 \| FLASH_CR_MER2);
bwang	0:2b1edabdd26b	572	FLASH->CR \|= FLASH_CR_STRT;
bwang	0:2b1edabdd26b	573
bwang	0:2b1edabdd26b	574	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	575	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	576
bwang	0:2b1edabdd26b	577	/* if the erase operation is completed, disable the MER Bit */
bwang	0:2b1edabdd26b	578	FLASH->CR &= ~(FLASH_CR_MER1 \| FLASH_CR_MER2);
bwang	0:2b1edabdd26b	579	#endif /* STM32F427_437xx \|\| STM32F429_439xx \|\| STM32F469_479xx */
bwang	0:2b1edabdd26b	580
bwang	0:2b1edabdd26b	581	#if defined(STM32F40_41xxx) \|\| defined(STM32F401xx) \|\| defined(STM32F410xx) \|\| defined(STM32F411xE) \|\| defined(STM32F412xG) \|\| defined(STM32F446xx)
bwang	0:2b1edabdd26b	582	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	583	FLASH->CR \|= tmp_psize;
bwang	0:2b1edabdd26b	584	FLASH->CR \|= FLASH_CR_MER;
bwang	0:2b1edabdd26b	585	FLASH->CR \|= FLASH_CR_STRT;
bwang	0:2b1edabdd26b	586
bwang	0:2b1edabdd26b	587	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	588	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	589
bwang	0:2b1edabdd26b	590	/* if the erase operation is completed, disable the MER Bit */
bwang	0:2b1edabdd26b	591	FLASH->CR &= (~FLASH_CR_MER);
bwang	0:2b1edabdd26b	592	#endif /* STM32F40_41xxx \|\| STM32F401xx \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F412xG \|\| STM32F446xx */
bwang	0:2b1edabdd26b	593
bwang	0:2b1edabdd26b	594	}
bwang	0:2b1edabdd26b	595	/* Return the Erase Status */
bwang	0:2b1edabdd26b	596	return status;
bwang	0:2b1edabdd26b	597	}
bwang	0:2b1edabdd26b	598
bwang	0:2b1edabdd26b	599	/**
bwang	0:2b1edabdd26b	600	* @brief Erases all FLASH Sectors in Bank 1.
bwang	0:2b1edabdd26b	601	*
bwang	0:2b1edabdd26b	602	* @note This function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	603	*
bwang	0:2b1edabdd26b	604	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	605	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	606	*
bwang	0:2b1edabdd26b	607	* @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang	0:2b1edabdd26b	608	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	609	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang	0:2b1edabdd26b	610	* the operation will be done by byte (8-bit)
bwang	0:2b1edabdd26b	611	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang	0:2b1edabdd26b	612	* the operation will be done by half word (16-bit)
bwang	0:2b1edabdd26b	613	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang	0:2b1edabdd26b	614	* the operation will be done by word (32-bit)
bwang	0:2b1edabdd26b	615	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang	0:2b1edabdd26b	616	* the operation will be done by double word (64-bit)
bwang	0:2b1edabdd26b	617	*
bwang	0:2b1edabdd26b	618	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	619	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	620	*/
bwang	0:2b1edabdd26b	621	FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
bwang	0:2b1edabdd26b	622	{
bwang	0:2b1edabdd26b	623	uint32_t tmp_psize = 0x0;
bwang	0:2b1edabdd26b	624	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	625
bwang	0:2b1edabdd26b	626	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	627	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	628	assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang	0:2b1edabdd26b	629
bwang	0:2b1edabdd26b	630	if(VoltageRange == VoltageRange_1)
bwang	0:2b1edabdd26b	631	{
bwang	0:2b1edabdd26b	632	tmp_psize = FLASH_PSIZE_BYTE;
bwang	0:2b1edabdd26b	633	}
bwang	0:2b1edabdd26b	634	else if(VoltageRange == VoltageRange_2)
bwang	0:2b1edabdd26b	635	{
bwang	0:2b1edabdd26b	636	tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang	0:2b1edabdd26b	637	}
bwang	0:2b1edabdd26b	638	else if(VoltageRange == VoltageRange_3)
bwang	0:2b1edabdd26b	639	{
bwang	0:2b1edabdd26b	640	tmp_psize = FLASH_PSIZE_WORD;
bwang	0:2b1edabdd26b	641	}
bwang	0:2b1edabdd26b	642	else
bwang	0:2b1edabdd26b	643	{
bwang	0:2b1edabdd26b	644	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang	0:2b1edabdd26b	645	}
bwang	0:2b1edabdd26b	646	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	647	{
bwang	0:2b1edabdd26b	648	/* if the previous operation is completed, proceed to erase all sectors */
bwang	0:2b1edabdd26b	649	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	650	FLASH->CR \|= tmp_psize;
bwang	0:2b1edabdd26b	651	FLASH->CR \|= FLASH_CR_MER1;
bwang	0:2b1edabdd26b	652	FLASH->CR \|= FLASH_CR_STRT;
bwang	0:2b1edabdd26b	653
bwang	0:2b1edabdd26b	654	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	655	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	656
bwang	0:2b1edabdd26b	657	/* if the erase operation is completed, disable the MER Bit */
bwang	0:2b1edabdd26b	658	FLASH->CR &= (~FLASH_CR_MER1);
bwang	0:2b1edabdd26b	659
bwang	0:2b1edabdd26b	660	}
bwang	0:2b1edabdd26b	661	/* Return the Erase Status */
bwang	0:2b1edabdd26b	662	return status;
bwang	0:2b1edabdd26b	663	}
bwang	0:2b1edabdd26b	664
bwang	0:2b1edabdd26b	665
bwang	0:2b1edabdd26b	666	/**
bwang	0:2b1edabdd26b	667	* @brief Erases all FLASH Sectors in Bank 2.
bwang	0:2b1edabdd26b	668	*
bwang	0:2b1edabdd26b	669	* @note This function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	670	*
bwang	0:2b1edabdd26b	671	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	672	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	673	*
bwang	0:2b1edabdd26b	674	* @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang	0:2b1edabdd26b	675	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	676	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang	0:2b1edabdd26b	677	* the operation will be done by byte (8-bit)
bwang	0:2b1edabdd26b	678	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang	0:2b1edabdd26b	679	* the operation will be done by half word (16-bit)
bwang	0:2b1edabdd26b	680	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang	0:2b1edabdd26b	681	* the operation will be done by word (32-bit)
bwang	0:2b1edabdd26b	682	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang	0:2b1edabdd26b	683	* the operation will be done by double word (64-bit)
bwang	0:2b1edabdd26b	684	*
bwang	0:2b1edabdd26b	685	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	686	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	687	*/
bwang	0:2b1edabdd26b	688	FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
bwang	0:2b1edabdd26b	689	{
bwang	0:2b1edabdd26b	690	uint32_t tmp_psize = 0x0;
bwang	0:2b1edabdd26b	691	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	692
bwang	0:2b1edabdd26b	693	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	694	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	695	assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang	0:2b1edabdd26b	696
bwang	0:2b1edabdd26b	697	if(VoltageRange == VoltageRange_1)
bwang	0:2b1edabdd26b	698	{
bwang	0:2b1edabdd26b	699	tmp_psize = FLASH_PSIZE_BYTE;
bwang	0:2b1edabdd26b	700	}
bwang	0:2b1edabdd26b	701	else if(VoltageRange == VoltageRange_2)
bwang	0:2b1edabdd26b	702	{
bwang	0:2b1edabdd26b	703	tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang	0:2b1edabdd26b	704	}
bwang	0:2b1edabdd26b	705	else if(VoltageRange == VoltageRange_3)
bwang	0:2b1edabdd26b	706	{
bwang	0:2b1edabdd26b	707	tmp_psize = FLASH_PSIZE_WORD;
bwang	0:2b1edabdd26b	708	}
bwang	0:2b1edabdd26b	709	else
bwang	0:2b1edabdd26b	710	{
bwang	0:2b1edabdd26b	711	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang	0:2b1edabdd26b	712	}
bwang	0:2b1edabdd26b	713	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	714	{
bwang	0:2b1edabdd26b	715	/* if the previous operation is completed, proceed to erase all sectors */
bwang	0:2b1edabdd26b	716	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	717	FLASH->CR \|= tmp_psize;
bwang	0:2b1edabdd26b	718	FLASH->CR \|= FLASH_CR_MER2;
bwang	0:2b1edabdd26b	719	FLASH->CR \|= FLASH_CR_STRT;
bwang	0:2b1edabdd26b	720
bwang	0:2b1edabdd26b	721	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	722	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	723
bwang	0:2b1edabdd26b	724	/* if the erase operation is completed, disable the MER Bit */
bwang	0:2b1edabdd26b	725	FLASH->CR &= (~FLASH_CR_MER2);
bwang	0:2b1edabdd26b	726
bwang	0:2b1edabdd26b	727	}
bwang	0:2b1edabdd26b	728	/* Return the Erase Status */
bwang	0:2b1edabdd26b	729	return status;
bwang	0:2b1edabdd26b	730	}
bwang	0:2b1edabdd26b	731
bwang	0:2b1edabdd26b	732	/**
bwang	0:2b1edabdd26b	733	* @brief Programs a double word (64-bit) at a specified address.
bwang	0:2b1edabdd26b	734	* @note This function must be used when the device voltage range is from
bwang	0:2b1edabdd26b	735	* 2.7V to 3.6V and an External Vpp is present.
bwang	0:2b1edabdd26b	736	*
bwang	0:2b1edabdd26b	737	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	738	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	739	*
bwang	0:2b1edabdd26b	740	* @param Address: specifies the address to be programmed.
bwang	0:2b1edabdd26b	741	* @param Data: specifies the data to be programmed.
bwang	0:2b1edabdd26b	742	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	743	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	744	*/
bwang	0:2b1edabdd26b	745	FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
bwang	0:2b1edabdd26b	746	{
bwang	0:2b1edabdd26b	747	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	748
bwang	0:2b1edabdd26b	749	/* Check the parameters */
bwang	0:2b1edabdd26b	750	assert_param(IS_FLASH_ADDRESS(Address));
bwang	0:2b1edabdd26b	751
bwang	0:2b1edabdd26b	752	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	753	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	754
bwang	0:2b1edabdd26b	755	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	756	{
bwang	0:2b1edabdd26b	757	/* if the previous operation is completed, proceed to program the new data */
bwang	0:2b1edabdd26b	758	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	759	FLASH->CR \|= FLASH_PSIZE_DOUBLE_WORD;
bwang	0:2b1edabdd26b	760	FLASH->CR \|= FLASH_CR_PG;
bwang	0:2b1edabdd26b	761
bwang	0:2b1edabdd26b	762	(__IO uint64_t)Address = Data;
bwang	0:2b1edabdd26b	763
bwang	0:2b1edabdd26b	764	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	765	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	766
bwang	0:2b1edabdd26b	767	/* if the program operation is completed, disable the PG Bit */
bwang	0:2b1edabdd26b	768	FLASH->CR &= (~FLASH_CR_PG);
bwang	0:2b1edabdd26b	769	}
bwang	0:2b1edabdd26b	770	/* Return the Program Status */
bwang	0:2b1edabdd26b	771	return status;
bwang	0:2b1edabdd26b	772	}
bwang	0:2b1edabdd26b	773
bwang	0:2b1edabdd26b	774	/**
bwang	0:2b1edabdd26b	775	* @brief Programs a word (32-bit) at a specified address.
bwang	0:2b1edabdd26b	776	*
bwang	0:2b1edabdd26b	777	* @note This function must be used when the device voltage range is from 2.7V to 3.6V.
bwang	0:2b1edabdd26b	778	*
bwang	0:2b1edabdd26b	779	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	780	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	781	*
bwang	0:2b1edabdd26b	782	* @param Address: specifies the address to be programmed.
bwang	0:2b1edabdd26b	783	* This parameter can be any address in Program memory zone or in OTP zone.
bwang	0:2b1edabdd26b	784	* @param Data: specifies the data to be programmed.
bwang	0:2b1edabdd26b	785	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	786	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	787	*/
bwang	0:2b1edabdd26b	788	FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
bwang	0:2b1edabdd26b	789	{
bwang	0:2b1edabdd26b	790	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	791
bwang	0:2b1edabdd26b	792	/* Check the parameters */
bwang	0:2b1edabdd26b	793	assert_param(IS_FLASH_ADDRESS(Address));
bwang	0:2b1edabdd26b	794
bwang	0:2b1edabdd26b	795	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	796	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	797
bwang	0:2b1edabdd26b	798	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	799	{
bwang	0:2b1edabdd26b	800	/* if the previous operation is completed, proceed to program the new data */
bwang	0:2b1edabdd26b	801	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	802	FLASH->CR \|= FLASH_PSIZE_WORD;
bwang	0:2b1edabdd26b	803	FLASH->CR \|= FLASH_CR_PG;
bwang	0:2b1edabdd26b	804
bwang	0:2b1edabdd26b	805	(__IO uint32_t)Address = Data;
bwang	0:2b1edabdd26b	806
bwang	0:2b1edabdd26b	807	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	808	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	809
bwang	0:2b1edabdd26b	810	/* if the program operation is completed, disable the PG Bit */
bwang	0:2b1edabdd26b	811	FLASH->CR &= (~FLASH_CR_PG);
bwang	0:2b1edabdd26b	812	}
bwang	0:2b1edabdd26b	813	/* Return the Program Status */
bwang	0:2b1edabdd26b	814	return status;
bwang	0:2b1edabdd26b	815	}
bwang	0:2b1edabdd26b	816
bwang	0:2b1edabdd26b	817	/**
bwang	0:2b1edabdd26b	818	* @brief Programs a half word (16-bit) at a specified address.
bwang	0:2b1edabdd26b	819	* @note This function must be used when the device voltage range is from 2.1V to 3.6V.
bwang	0:2b1edabdd26b	820	*
bwang	0:2b1edabdd26b	821	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	822	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	823	*
bwang	0:2b1edabdd26b	824	* @param Address: specifies the address to be programmed.
bwang	0:2b1edabdd26b	825	* This parameter can be any address in Program memory zone or in OTP zone.
bwang	0:2b1edabdd26b	826	* @param Data: specifies the data to be programmed.
bwang	0:2b1edabdd26b	827	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	828	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	829	*/
bwang	0:2b1edabdd26b	830	FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
bwang	0:2b1edabdd26b	831	{
bwang	0:2b1edabdd26b	832	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	833
bwang	0:2b1edabdd26b	834	/* Check the parameters */
bwang	0:2b1edabdd26b	835	assert_param(IS_FLASH_ADDRESS(Address));
bwang	0:2b1edabdd26b	836
bwang	0:2b1edabdd26b	837	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	838	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	839
bwang	0:2b1edabdd26b	840	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	841	{
bwang	0:2b1edabdd26b	842	/* if the previous operation is completed, proceed to program the new data */
bwang	0:2b1edabdd26b	843	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	844	FLASH->CR \|= FLASH_PSIZE_HALF_WORD;
bwang	0:2b1edabdd26b	845	FLASH->CR \|= FLASH_CR_PG;
bwang	0:2b1edabdd26b	846
bwang	0:2b1edabdd26b	847	(__IO uint16_t)Address = Data;
bwang	0:2b1edabdd26b	848
bwang	0:2b1edabdd26b	849	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	850	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	851
bwang	0:2b1edabdd26b	852	/* if the program operation is completed, disable the PG Bit */
bwang	0:2b1edabdd26b	853	FLASH->CR &= (~FLASH_CR_PG);
bwang	0:2b1edabdd26b	854	}
bwang	0:2b1edabdd26b	855	/* Return the Program Status */
bwang	0:2b1edabdd26b	856	return status;
bwang	0:2b1edabdd26b	857	}
bwang	0:2b1edabdd26b	858
bwang	0:2b1edabdd26b	859	/**
bwang	0:2b1edabdd26b	860	* @brief Programs a byte (8-bit) at a specified address.
bwang	0:2b1edabdd26b	861	* @note This function can be used within all the device supply voltage ranges.
bwang	0:2b1edabdd26b	862	*
bwang	0:2b1edabdd26b	863	* @note If an erase and a program operations are requested simultaneously,
bwang	0:2b1edabdd26b	864	* the erase operation is performed before the program one.
bwang	0:2b1edabdd26b	865	*
bwang	0:2b1edabdd26b	866	* @param Address: specifies the address to be programmed.
bwang	0:2b1edabdd26b	867	* This parameter can be any address in Program memory zone or in OTP zone.
bwang	0:2b1edabdd26b	868	* @param Data: specifies the data to be programmed.
bwang	0:2b1edabdd26b	869	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	870	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	871	*/
bwang	0:2b1edabdd26b	872	FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
bwang	0:2b1edabdd26b	873	{
bwang	0:2b1edabdd26b	874	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	875
bwang	0:2b1edabdd26b	876	/* Check the parameters */
bwang	0:2b1edabdd26b	877	assert_param(IS_FLASH_ADDRESS(Address));
bwang	0:2b1edabdd26b	878
bwang	0:2b1edabdd26b	879	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	880	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	881
bwang	0:2b1edabdd26b	882	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	883	{
bwang	0:2b1edabdd26b	884	/* if the previous operation is completed, proceed to program the new data */
bwang	0:2b1edabdd26b	885	FLASH->CR &= CR_PSIZE_MASK;
bwang	0:2b1edabdd26b	886	FLASH->CR \|= FLASH_PSIZE_BYTE;
bwang	0:2b1edabdd26b	887	FLASH->CR \|= FLASH_CR_PG;
bwang	0:2b1edabdd26b	888
bwang	0:2b1edabdd26b	889	(__IO uint8_t)Address = Data;
bwang	0:2b1edabdd26b	890
bwang	0:2b1edabdd26b	891	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	892	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	893
bwang	0:2b1edabdd26b	894	/* if the program operation is completed, disable the PG Bit */
bwang	0:2b1edabdd26b	895	FLASH->CR &= (~FLASH_CR_PG);
bwang	0:2b1edabdd26b	896	}
bwang	0:2b1edabdd26b	897
bwang	0:2b1edabdd26b	898	/* Return the Program Status */
bwang	0:2b1edabdd26b	899	return status;
bwang	0:2b1edabdd26b	900	}
bwang	0:2b1edabdd26b	901
bwang	0:2b1edabdd26b	902	/**
bwang	0:2b1edabdd26b	903	* @}
bwang	0:2b1edabdd26b	904	*/
bwang	0:2b1edabdd26b	905
bwang	0:2b1edabdd26b	906	/** @defgroup FLASH_Group3 Option Bytes Programming functions
bwang	0:2b1edabdd26b	907	* @brief Option Bytes Programming functions
bwang	0:2b1edabdd26b	908	*
bwang	0:2b1edabdd26b	909	@verbatim
bwang	0:2b1edabdd26b	910	===============================================================================
bwang	0:2b1edabdd26b	911	##### Option Bytes Programming functions #####
bwang	0:2b1edabdd26b	912	===============================================================================
bwang	0:2b1edabdd26b	913	[..]
bwang	0:2b1edabdd26b	914	This group includes the following functions:
bwang	0:2b1edabdd26b	915	(+) void FLASH_OB_Unlock(void)
bwang	0:2b1edabdd26b	916	(+) void FLASH_OB_Lock(void)
bwang	0:2b1edabdd26b	917	(+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang	0:2b1edabdd26b	918	(+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
bwang	0:2b1edabdd26b	919	(+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
bwang	0:2b1edabdd26b	920	(+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
bwang	0:2b1edabdd26b	921	(+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
bwang	0:2b1edabdd26b	922	(+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
bwang	0:2b1edabdd26b	923	(+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang	0:2b1edabdd26b	924	(+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
bwang	0:2b1edabdd26b	925	(+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
bwang	0:2b1edabdd26b	926	(+) FLASH_Status FLASH_OB_Launch(void)
bwang	0:2b1edabdd26b	927	(+) uint32_t FLASH_OB_GetUser(void)
bwang	0:2b1edabdd26b	928	(+) uint8_t FLASH_OB_GetWRP(void)
bwang	0:2b1edabdd26b	929	(+) uint8_t FLASH_OB_GetWRP1(void)
bwang	0:2b1edabdd26b	930	(+) uint8_t FLASH_OB_GetPCROP(void)
bwang	0:2b1edabdd26b	931	(+) uint8_t FLASH_OB_GetPCROP1(void)
bwang	0:2b1edabdd26b	932	(+) uint8_t FLASH_OB_GetRDP(void)
bwang	0:2b1edabdd26b	933	(+) uint8_t FLASH_OB_GetBOR(void)
bwang	0:2b1edabdd26b	934	[..]
bwang	0:2b1edabdd26b	935	The following function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	936	(+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
bwang	0:2b1edabdd26b	937	[..]
bwang	0:2b1edabdd26b	938	Any operation of erase or program should follow these steps:
bwang	0:2b1edabdd26b	939	(#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
bwang	0:2b1edabdd26b	940	register access
bwang	0:2b1edabdd26b	941
bwang	0:2b1edabdd26b	942	(#) Call one or several functions to program the desired Option Bytes:
bwang	0:2b1edabdd26b	943	(++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang	0:2b1edabdd26b	944	=> to Enable/Disable the desired sector write protection
bwang	0:2b1edabdd26b	945	(++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
bwang	0:2b1edabdd26b	946	Protection Level
bwang	0:2b1edabdd26b	947	(++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang	0:2b1edabdd26b	948	=> to configure the user Option Bytes.
bwang	0:2b1edabdd26b	949	(++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
bwang	0:2b1edabdd26b	950
bwang	0:2b1edabdd26b	951	(#) Once all needed Option Bytes to be programmed are correctly written,
bwang	0:2b1edabdd26b	952	call the FLASH_OB_Launch() function to launch the Option Bytes
bwang	0:2b1edabdd26b	953	programming process.
bwang	0:2b1edabdd26b	954
bwang	0:2b1edabdd26b	955	-@- When changing the IWDG mode from HW to SW or from SW to HW, a system
bwang	0:2b1edabdd26b	956	reset is needed to make the change effective.
bwang	0:2b1edabdd26b	957
bwang	0:2b1edabdd26b	958	(#) Call the FLASH_OB_Lock() function to disable the FLASH option control
bwang	0:2b1edabdd26b	959	register access (recommended to protect the Option Bytes against
bwang	0:2b1edabdd26b	960	possible unwanted operations)
bwang	0:2b1edabdd26b	961
bwang	0:2b1edabdd26b	962	@endverbatim
bwang	0:2b1edabdd26b	963	* @{
bwang	0:2b1edabdd26b	964	*/
bwang	0:2b1edabdd26b	965
bwang	0:2b1edabdd26b	966	/**
bwang	0:2b1edabdd26b	967	* @brief Unlocks the FLASH Option Control Registers access.
bwang	0:2b1edabdd26b	968	* @param None
bwang	0:2b1edabdd26b	969	* @retval None
bwang	0:2b1edabdd26b	970	*/
bwang	0:2b1edabdd26b	971	void FLASH_OB_Unlock(void)
bwang	0:2b1edabdd26b	972	{
bwang	0:2b1edabdd26b	973	if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
bwang	0:2b1edabdd26b	974	{
bwang	0:2b1edabdd26b	975	/* Authorizes the Option Byte register programming */
bwang	0:2b1edabdd26b	976	FLASH->OPTKEYR = FLASH_OPT_KEY1;
bwang	0:2b1edabdd26b	977	FLASH->OPTKEYR = FLASH_OPT_KEY2;
bwang	0:2b1edabdd26b	978	}
bwang	0:2b1edabdd26b	979	}
bwang	0:2b1edabdd26b	980
bwang	0:2b1edabdd26b	981	/**
bwang	0:2b1edabdd26b	982	* @brief Locks the FLASH Option Control Registers access.
bwang	0:2b1edabdd26b	983	* @param None
bwang	0:2b1edabdd26b	984	* @retval None
bwang	0:2b1edabdd26b	985	*/
bwang	0:2b1edabdd26b	986	void FLASH_OB_Lock(void)
bwang	0:2b1edabdd26b	987	{
bwang	0:2b1edabdd26b	988	/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
bwang	0:2b1edabdd26b	989	FLASH->OPTCR \|= FLASH_OPTCR_OPTLOCK;
bwang	0:2b1edabdd26b	990	}
bwang	0:2b1edabdd26b	991
bwang	0:2b1edabdd26b	992	/**
bwang	0:2b1edabdd26b	993	* @brief Enables or disables the write protection of the desired sectors, for the first
bwang	0:2b1edabdd26b	994	* 1 Mb of the Flash
bwang	0:2b1edabdd26b	995	*
bwang	0:2b1edabdd26b	996	* @note When the memory read protection level is selected (RDP level = 1),
bwang	0:2b1edabdd26b	997	* it is not possible to program or erase the flash sector i if CortexM4
bwang	0:2b1edabdd26b	998	* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
bwang	0:2b1edabdd26b	999	* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
bwang	0:2b1edabdd26b	1000	*
bwang	0:2b1edabdd26b	1001	* @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
bwang	0:2b1edabdd26b	1002	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1003	* @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
bwang	0:2b1edabdd26b	1004	* @arg OB_WRP_Sector_All
bwang	0:2b1edabdd26b	1005	* @param Newstate: new state of the Write Protection.
bwang	0:2b1edabdd26b	1006	* This parameter can be: ENABLE or DISABLE.
bwang	0:2b1edabdd26b	1007	* @retval None
bwang	0:2b1edabdd26b	1008	*/
bwang	0:2b1edabdd26b	1009	void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang	0:2b1edabdd26b	1010	{
bwang	0:2b1edabdd26b	1011	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1012
bwang	0:2b1edabdd26b	1013	/* Check the parameters */
bwang	0:2b1edabdd26b	1014	assert_param(IS_OB_WRP(OB_WRP));
bwang	0:2b1edabdd26b	1015	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	1016
bwang	0:2b1edabdd26b	1017	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	1018
bwang	0:2b1edabdd26b	1019	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	1020	{
bwang	0:2b1edabdd26b	1021	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	1022	{
bwang	0:2b1edabdd26b	1023	(__IO uint16_t)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
bwang	0:2b1edabdd26b	1024	}
bwang	0:2b1edabdd26b	1025	else
bwang	0:2b1edabdd26b	1026	{
bwang	0:2b1edabdd26b	1027	(__IO uint16_t)OPTCR_BYTE2_ADDRESS \|= (uint16_t)OB_WRP;
bwang	0:2b1edabdd26b	1028	}
bwang	0:2b1edabdd26b	1029	}
bwang	0:2b1edabdd26b	1030	}
bwang	0:2b1edabdd26b	1031
bwang	0:2b1edabdd26b	1032	/**
bwang	0:2b1edabdd26b	1033	* @brief Enables or disables the write protection of the desired sectors, for the second
bwang	0:2b1edabdd26b	1034	* 1 Mb of the Flash
bwang	0:2b1edabdd26b	1035	*
bwang	0:2b1edabdd26b	1036	* @note This function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	1037	*
bwang	0:2b1edabdd26b	1038	* @note When the memory read out protection is selected (RDP level = 1),
bwang	0:2b1edabdd26b	1039	* it is not possible to program or erase the flash sector i if CortexM4
bwang	0:2b1edabdd26b	1040	* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
bwang	0:2b1edabdd26b	1041	* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
bwang	0:2b1edabdd26b	1042	*
bwang	0:2b1edabdd26b	1043	* @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
bwang	0:2b1edabdd26b	1044	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1045	* @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
bwang	0:2b1edabdd26b	1046	* @arg OB_WRP_Sector_All
bwang	0:2b1edabdd26b	1047	* @param Newstate: new state of the Write Protection.
bwang	0:2b1edabdd26b	1048	* This parameter can be: ENABLE or DISABLE.
bwang	0:2b1edabdd26b	1049	* @retval None
bwang	0:2b1edabdd26b	1050	*/
bwang	0:2b1edabdd26b	1051	void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
bwang	0:2b1edabdd26b	1052	{
bwang	0:2b1edabdd26b	1053	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1054
bwang	0:2b1edabdd26b	1055	/* Check the parameters */
bwang	0:2b1edabdd26b	1056	assert_param(IS_OB_WRP(OB_WRP));
bwang	0:2b1edabdd26b	1057	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	1058
bwang	0:2b1edabdd26b	1059	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	1060
bwang	0:2b1edabdd26b	1061	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	1062	{
bwang	0:2b1edabdd26b	1063	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	1064	{
bwang	0:2b1edabdd26b	1065	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
bwang	0:2b1edabdd26b	1066	}
bwang	0:2b1edabdd26b	1067	else
bwang	0:2b1edabdd26b	1068	{
bwang	0:2b1edabdd26b	1069	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS \|= (uint16_t)OB_WRP;
bwang	0:2b1edabdd26b	1070	}
bwang	0:2b1edabdd26b	1071	}
bwang	0:2b1edabdd26b	1072	}
bwang	0:2b1edabdd26b	1073
bwang	0:2b1edabdd26b	1074	/**
bwang	0:2b1edabdd26b	1075	* @brief Select the Protection Mode (SPRMOD).
bwang	0:2b1edabdd26b	1076	*
bwang	0:2b1edabdd26b	1077	* @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
bwang	0:2b1edabdd26b	1078	*
bwang	0:2b1edabdd26b	1079	* @note After PCROP activation, Option Byte modification is not possible.
bwang	0:2b1edabdd26b	1080	* Exception made for the global Read Out Protection modification level (level1 to level0)
bwang	0:2b1edabdd26b	1081	* @note Once SPRMOD bit is active unprotection of a protected sector is not possible
bwang	0:2b1edabdd26b	1082	*
bwang	0:2b1edabdd26b	1083	* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
bwang	0:2b1edabdd26b	1084	*
bwang	0:2b1edabdd26b	1085	* @note Some Precautions should be taken when activating the PCROP feature :
bwang	0:2b1edabdd26b	1086	* The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
bwang	0:2b1edabdd26b	1087	* and WRPi = 1 (default value), then the user sector i is read/write protected.
bwang	0:2b1edabdd26b	1088	* In order to avoid activation of PCROP Mode for undesired sectors, please follow the
bwang	0:2b1edabdd26b	1089	* below safety sequence :
bwang	0:2b1edabdd26b	1090	* - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
bwang	0:2b1edabdd26b	1091	* for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
bwang	0:2b1edabdd26b	1092	* - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
bwang	0:2b1edabdd26b	1093	* - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
bwang	0:2b1edabdd26b	1094	*
bwang	0:2b1edabdd26b	1095	* @param OB_PCROP: Select the Protection Mode of nWPRi bits
bwang	0:2b1edabdd26b	1096	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1097	* @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
bwang	0:2b1edabdd26b	1098	* @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
bwang	0:2b1edabdd26b	1099	* @retval None
bwang	0:2b1edabdd26b	1100	*/
bwang	0:2b1edabdd26b	1101	void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
bwang	0:2b1edabdd26b	1102	{
bwang	0:2b1edabdd26b	1103	uint8_t optiontmp = 0xFF;
bwang	0:2b1edabdd26b	1104
bwang	0:2b1edabdd26b	1105	/* Check the parameters */
bwang	0:2b1edabdd26b	1106	assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
bwang	0:2b1edabdd26b	1107
bwang	0:2b1edabdd26b	1108	/* Mask SPRMOD bit */
bwang	0:2b1edabdd26b	1109	optiontmp = (uint8_t)(((__IO uint8_t )OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
bwang	0:2b1edabdd26b	1110	/* Update Option Byte */
bwang	0:2b1edabdd26b	1111	(__IO uint8_t )OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP \| optiontmp);
bwang	0:2b1edabdd26b	1112
bwang	0:2b1edabdd26b	1113	}
bwang	0:2b1edabdd26b	1114
bwang	0:2b1edabdd26b	1115	/**
bwang	0:2b1edabdd26b	1116	* @brief Enables or disables the read/write protection (PCROP) of the desired
bwang	0:2b1edabdd26b	1117	* sectors, for the first 1 MB of the Flash.
bwang	0:2b1edabdd26b	1118	*
bwang	0:2b1edabdd26b	1119	* @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE
bwang	0:2b1edabdd26b	1120	* and STM32F412xG devices.
bwang	0:2b1edabdd26b	1121	*
bwang	0:2b1edabdd26b	1122	* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
bwang	0:2b1edabdd26b	1123	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1124	* @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
bwang	0:2b1edabdd26b	1125	* STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
bwang	0:2b1edabdd26b	1126	* OB_PCROP_Sector5 for STM32F401xx/411xE devices.
bwang	0:2b1edabdd26b	1127	* @arg OB_PCROP_Sector_All
bwang	0:2b1edabdd26b	1128	* @param Newstate: new state of the Write Protection.
bwang	0:2b1edabdd26b	1129	* This parameter can be: ENABLE or DISABLE.
bwang	0:2b1edabdd26b	1130	* @retval None
bwang	0:2b1edabdd26b	1131	*/
bwang	0:2b1edabdd26b	1132	void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
bwang	0:2b1edabdd26b	1133	{
bwang	0:2b1edabdd26b	1134	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1135
bwang	0:2b1edabdd26b	1136	/* Check the parameters */
bwang	0:2b1edabdd26b	1137	assert_param(IS_OB_PCROP(OB_PCROP));
bwang	0:2b1edabdd26b	1138	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	1139
bwang	0:2b1edabdd26b	1140	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	1141
bwang	0:2b1edabdd26b	1142	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	1143	{
bwang	0:2b1edabdd26b	1144	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	1145	{
bwang	0:2b1edabdd26b	1146	(__IO uint16_t)OPTCR_BYTE2_ADDRESS \|= (uint16_t)OB_PCROP;
bwang	0:2b1edabdd26b	1147	}
bwang	0:2b1edabdd26b	1148	else
bwang	0:2b1edabdd26b	1149	{
bwang	0:2b1edabdd26b	1150	(__IO uint16_t)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
bwang	0:2b1edabdd26b	1151	}
bwang	0:2b1edabdd26b	1152	}
bwang	0:2b1edabdd26b	1153	}
bwang	0:2b1edabdd26b	1154
bwang	0:2b1edabdd26b	1155	/**
bwang	0:2b1edabdd26b	1156	* @brief Enables or disables the read/write protection (PCROP) of the desired
bwang	0:2b1edabdd26b	1157	* sectors
bwang	0:2b1edabdd26b	1158	*
bwang	0:2b1edabdd26b	1159	* @note This function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	1160	*
bwang	0:2b1edabdd26b	1161	* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
bwang	0:2b1edabdd26b	1162	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1163	* @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
bwang	0:2b1edabdd26b	1164	* @arg OB_PCROP_Sector_All
bwang	0:2b1edabdd26b	1165	* @param Newstate: new state of the Write Protection.
bwang	0:2b1edabdd26b	1166	* This parameter can be: ENABLE or DISABLE.
bwang	0:2b1edabdd26b	1167	* @retval None
bwang	0:2b1edabdd26b	1168	*/
bwang	0:2b1edabdd26b	1169	void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
bwang	0:2b1edabdd26b	1170	{
bwang	0:2b1edabdd26b	1171	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1172
bwang	0:2b1edabdd26b	1173	/* Check the parameters */
bwang	0:2b1edabdd26b	1174	assert_param(IS_OB_PCROP(OB_PCROP));
bwang	0:2b1edabdd26b	1175	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	1176
bwang	0:2b1edabdd26b	1177	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	1178
bwang	0:2b1edabdd26b	1179	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	1180	{
bwang	0:2b1edabdd26b	1181	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	1182	{
bwang	0:2b1edabdd26b	1183	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS \|= (uint16_t)OB_PCROP;
bwang	0:2b1edabdd26b	1184	}
bwang	0:2b1edabdd26b	1185	else
bwang	0:2b1edabdd26b	1186	{
bwang	0:2b1edabdd26b	1187	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
bwang	0:2b1edabdd26b	1188	}
bwang	0:2b1edabdd26b	1189	}
bwang	0:2b1edabdd26b	1190	}
bwang	0:2b1edabdd26b	1191
bwang	0:2b1edabdd26b	1192
bwang	0:2b1edabdd26b	1193	/**
bwang	0:2b1edabdd26b	1194	* @brief Sets the read protection level.
bwang	0:2b1edabdd26b	1195	* @param OB_RDP: specifies the read protection level.
bwang	0:2b1edabdd26b	1196	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1197	* @arg OB_RDP_Level_0: No protection
bwang	0:2b1edabdd26b	1198	* @arg OB_RDP_Level_1: Read protection of the memory
bwang	0:2b1edabdd26b	1199	* @arg OB_RDP_Level_2: Full chip protection
bwang	0:2b1edabdd26b	1200	*
bwang	0:2b1edabdd26b	1201	* /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
bwang	0:2b1edabdd26b	1202	*
bwang	0:2b1edabdd26b	1203	* @retval None
bwang	0:2b1edabdd26b	1204	*/
bwang	0:2b1edabdd26b	1205	void FLASH_OB_RDPConfig(uint8_t OB_RDP)
bwang	0:2b1edabdd26b	1206	{
bwang	0:2b1edabdd26b	1207	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1208
bwang	0:2b1edabdd26b	1209	/* Check the parameters */
bwang	0:2b1edabdd26b	1210	assert_param(IS_OB_RDP(OB_RDP));
bwang	0:2b1edabdd26b	1211
bwang	0:2b1edabdd26b	1212	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	1213
bwang	0:2b1edabdd26b	1214	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	1215	{
bwang	0:2b1edabdd26b	1216	(__IO uint8_t)OPTCR_BYTE1_ADDRESS = OB_RDP;
bwang	0:2b1edabdd26b	1217
bwang	0:2b1edabdd26b	1218	}
bwang	0:2b1edabdd26b	1219	}
bwang	0:2b1edabdd26b	1220
bwang	0:2b1edabdd26b	1221	/**
bwang	0:2b1edabdd26b	1222	* @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
bwang	0:2b1edabdd26b	1223	* @param OB_IWDG: Selects the IWDG mode
bwang	0:2b1edabdd26b	1224	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1225	* @arg OB_IWDG_SW: Software IWDG selected
bwang	0:2b1edabdd26b	1226	* @arg OB_IWDG_HW: Hardware IWDG selected
bwang	0:2b1edabdd26b	1227	* @param OB_STOP: Reset event when entering STOP mode.
bwang	0:2b1edabdd26b	1228	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1229	* @arg OB_STOP_NoRST: No reset generated when entering in STOP
bwang	0:2b1edabdd26b	1230	* @arg OB_STOP_RST: Reset generated when entering in STOP
bwang	0:2b1edabdd26b	1231	* @param OB_STDBY: Reset event when entering Standby mode.
bwang	0:2b1edabdd26b	1232	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1233	* @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
bwang	0:2b1edabdd26b	1234	* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
bwang	0:2b1edabdd26b	1235	* @retval None
bwang	0:2b1edabdd26b	1236	*/
bwang	0:2b1edabdd26b	1237	void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang	0:2b1edabdd26b	1238	{
bwang	0:2b1edabdd26b	1239	uint8_t optiontmp = 0xFF;
bwang	0:2b1edabdd26b	1240	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1241
bwang	0:2b1edabdd26b	1242	/* Check the parameters */
bwang	0:2b1edabdd26b	1243	assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
bwang	0:2b1edabdd26b	1244	assert_param(IS_OB_STOP_SOURCE(OB_STOP));
bwang	0:2b1edabdd26b	1245	assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
bwang	0:2b1edabdd26b	1246
bwang	0:2b1edabdd26b	1247	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	1248	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	1249
bwang	0:2b1edabdd26b	1250	if(status == FLASH_COMPLETE2)
bwang	0:2b1edabdd26b	1251	{
bwang	0:2b1edabdd26b	1252	#if defined(STM32F427_437xx) \|\| defined(STM32F429_439xx) \|\| defined(STM32F469_479xx)
bwang	0:2b1edabdd26b	1253	/* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
bwang	0:2b1edabdd26b	1254	optiontmp = (uint8_t)(((__IO uint8_t )OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
bwang	0:2b1edabdd26b	1255	#endif /* STM32F427_437xx \|\| STM32F429_439xx \|\| STM32F469_479xx */
bwang	0:2b1edabdd26b	1256
bwang	0:2b1edabdd26b	1257	#if defined(STM32F40_41xxx) \|\| defined(STM32F401xx) \|\| defined(STM32F410xx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
bwang	0:2b1edabdd26b	1258	/* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
bwang	0:2b1edabdd26b	1259	optiontmp = (uint8_t)(((__IO uint8_t )OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
bwang	0:2b1edabdd26b	1260	#endif /* STM32F40_41xxx \|\| STM32F401xx \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx */
bwang	0:2b1edabdd26b	1261
bwang	0:2b1edabdd26b	1262	/* Update User Option Byte */
bwang	0:2b1edabdd26b	1263	(__IO uint8_t )OPTCR_BYTE0_ADDRESS = OB_IWDG \| (uint8_t)(OB_STDBY \| (uint8_t)(OB_STOP \| ((uint8_t)optiontmp)));
bwang	0:2b1edabdd26b	1264	}
bwang	0:2b1edabdd26b	1265	}
bwang	0:2b1edabdd26b	1266
bwang	0:2b1edabdd26b	1267	/**
bwang	0:2b1edabdd26b	1268	* @brief Configure the Dual Bank Boot.
bwang	0:2b1edabdd26b	1269	*
bwang	0:2b1edabdd26b	1270	* @note This function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	1271	*
bwang	0:2b1edabdd26b	1272	* @param OB_BOOT: specifies the Dual Bank Boot Option byte.
bwang	0:2b1edabdd26b	1273	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1274	* @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
bwang	0:2b1edabdd26b	1275	* @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
bwang	0:2b1edabdd26b	1276	* @retval None
bwang	0:2b1edabdd26b	1277	*/
bwang	0:2b1edabdd26b	1278	void FLASH_OB_BootConfig(uint8_t OB_BOOT)
bwang	0:2b1edabdd26b	1279	{
bwang	0:2b1edabdd26b	1280	/* Check the parameters */
bwang	0:2b1edabdd26b	1281	assert_param(IS_OB_BOOT(OB_BOOT));
bwang	0:2b1edabdd26b	1282
bwang	0:2b1edabdd26b	1283	/* Set Dual Bank Boot */
bwang	0:2b1edabdd26b	1284	(__IO uint8_t )OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
bwang	0:2b1edabdd26b	1285	(__IO uint8_t )OPTCR_BYTE0_ADDRESS \|= OB_BOOT;
bwang	0:2b1edabdd26b	1286
bwang	0:2b1edabdd26b	1287	}
bwang	0:2b1edabdd26b	1288
bwang	0:2b1edabdd26b	1289	/**
bwang	0:2b1edabdd26b	1290	* @brief Sets the BOR Level.
bwang	0:2b1edabdd26b	1291	* @param OB_BOR: specifies the Option Bytes BOR Reset Level.
bwang	0:2b1edabdd26b	1292	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1293	* @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
bwang	0:2b1edabdd26b	1294	* @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
bwang	0:2b1edabdd26b	1295	* @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
bwang	0:2b1edabdd26b	1296	* @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
bwang	0:2b1edabdd26b	1297	* @retval None
bwang	0:2b1edabdd26b	1298	*/
bwang	0:2b1edabdd26b	1299	void FLASH_OB_BORConfig(uint8_t OB_BOR)
bwang	0:2b1edabdd26b	1300	{
bwang	0:2b1edabdd26b	1301	/* Check the parameters */
bwang	0:2b1edabdd26b	1302	assert_param(IS_OB_BOR(OB_BOR));
bwang	0:2b1edabdd26b	1303
bwang	0:2b1edabdd26b	1304	/* Set the BOR Level */
bwang	0:2b1edabdd26b	1305	(__IO uint8_t )OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
bwang	0:2b1edabdd26b	1306	(__IO uint8_t )OPTCR_BYTE0_ADDRESS \|= OB_BOR;
bwang	0:2b1edabdd26b	1307
bwang	0:2b1edabdd26b	1308	}
bwang	0:2b1edabdd26b	1309
bwang	0:2b1edabdd26b	1310	/**
bwang	0:2b1edabdd26b	1311	* @brief Launch the option byte loading.
bwang	0:2b1edabdd26b	1312	* @param None
bwang	0:2b1edabdd26b	1313	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	1314	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	1315	*/
bwang	0:2b1edabdd26b	1316	FLASH_Status FLASH_OB_Launch(void)
bwang	0:2b1edabdd26b	1317	{
bwang	0:2b1edabdd26b	1318	FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1319
bwang	0:2b1edabdd26b	1320	/* Set the OPTSTRT bit in OPTCR register */
bwang	0:2b1edabdd26b	1321	(__IO uint8_t )OPTCR_BYTE0_ADDRESS \|= FLASH_OPTCR_OPTSTRT;
bwang	0:2b1edabdd26b	1322
bwang	0:2b1edabdd26b	1323	/* Wait for last operation to be completed */
bwang	0:2b1edabdd26b	1324	status = FLASH_WaitForLastOperation2();
bwang	0:2b1edabdd26b	1325
bwang	0:2b1edabdd26b	1326	return status;
bwang	0:2b1edabdd26b	1327	}
bwang	0:2b1edabdd26b	1328
bwang	0:2b1edabdd26b	1329	/**
bwang	0:2b1edabdd26b	1330	* @brief Returns the FLASH User Option Bytes values.
bwang	0:2b1edabdd26b	1331	* @param None
bwang	0:2b1edabdd26b	1332	* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
bwang	0:2b1edabdd26b	1333	* and RST_STDBY(Bit2).
bwang	0:2b1edabdd26b	1334	*/
bwang	0:2b1edabdd26b	1335	uint8_t FLASH_OB_GetUser(void)
bwang	0:2b1edabdd26b	1336	{
bwang	0:2b1edabdd26b	1337	/* Return the User Option Byte */
bwang	0:2b1edabdd26b	1338	return (uint8_t)(FLASH->OPTCR >> 5);
bwang	0:2b1edabdd26b	1339	}
bwang	0:2b1edabdd26b	1340
bwang	0:2b1edabdd26b	1341	/**
bwang	0:2b1edabdd26b	1342	* @brief Returns the FLASH Write Protection Option Bytes value.
bwang	0:2b1edabdd26b	1343	* @param None
bwang	0:2b1edabdd26b	1344	* @retval The FLASH Write Protection Option Bytes value
bwang	0:2b1edabdd26b	1345	*/
bwang	0:2b1edabdd26b	1346	uint16_t FLASH_OB_GetWRP(void)
bwang	0:2b1edabdd26b	1347	{
bwang	0:2b1edabdd26b	1348	/* Return the FLASH write protection Register value */
bwang	0:2b1edabdd26b	1349	return ((__IO uint16_t )(OPTCR_BYTE2_ADDRESS));
bwang	0:2b1edabdd26b	1350	}
bwang	0:2b1edabdd26b	1351
bwang	0:2b1edabdd26b	1352	/**
bwang	0:2b1edabdd26b	1353	* @brief Returns the FLASH Write Protection Option Bytes value.
bwang	0:2b1edabdd26b	1354	*
bwang	0:2b1edabdd26b	1355	* @note This function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	1356	*
bwang	0:2b1edabdd26b	1357	* @param None
bwang	0:2b1edabdd26b	1358	* @retval The FLASH Write Protection Option Bytes value
bwang	0:2b1edabdd26b	1359	*/
bwang	0:2b1edabdd26b	1360	uint16_t FLASH_OB_GetWRP1(void)
bwang	0:2b1edabdd26b	1361	{
bwang	0:2b1edabdd26b	1362	/* Return the FLASH write protection Register value */
bwang	0:2b1edabdd26b	1363	return ((__IO uint16_t )(OPTCR1_BYTE2_ADDRESS));
bwang	0:2b1edabdd26b	1364	}
bwang	0:2b1edabdd26b	1365
bwang	0:2b1edabdd26b	1366	/**
bwang	0:2b1edabdd26b	1367	* @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
bwang	0:2b1edabdd26b	1368	*
bwang	0:2b1edabdd26b	1369	* @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
bwang	0:2b1edabdd26b	1370	*
bwang	0:2b1edabdd26b	1371	* @param None
bwang	0:2b1edabdd26b	1372	* @retval The FLASH PC Read/Write Protection Option Bytes value
bwang	0:2b1edabdd26b	1373	*/
bwang	0:2b1edabdd26b	1374	uint16_t FLASH_OB_GetPCROP(void)
bwang	0:2b1edabdd26b	1375	{
bwang	0:2b1edabdd26b	1376	/* Return the FLASH PC Read/write protection Register value */
bwang	0:2b1edabdd26b	1377	return ((__IO uint16_t )(OPTCR_BYTE2_ADDRESS));
bwang	0:2b1edabdd26b	1378	}
bwang	0:2b1edabdd26b	1379
bwang	0:2b1edabdd26b	1380	/**
bwang	0:2b1edabdd26b	1381	* @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
bwang	0:2b1edabdd26b	1382	*
bwang	0:2b1edabdd26b	1383	* @note This function can be used only for STM32F42xxx/43xxx devices.
bwang	0:2b1edabdd26b	1384	*
bwang	0:2b1edabdd26b	1385	* @param None
bwang	0:2b1edabdd26b	1386	* @retval The FLASH PC Read/Write Protection Option Bytes value
bwang	0:2b1edabdd26b	1387	*/
bwang	0:2b1edabdd26b	1388	uint16_t FLASH_OB_GetPCROP1(void)
bwang	0:2b1edabdd26b	1389	{
bwang	0:2b1edabdd26b	1390	/* Return the FLASH write protection Register value */
bwang	0:2b1edabdd26b	1391	return ((__IO uint16_t )(OPTCR1_BYTE2_ADDRESS));
bwang	0:2b1edabdd26b	1392	}
bwang	0:2b1edabdd26b	1393
bwang	0:2b1edabdd26b	1394	/**
bwang	0:2b1edabdd26b	1395	* @brief Returns the FLASH Read Protection level.
bwang	0:2b1edabdd26b	1396	* @param None
bwang	0:2b1edabdd26b	1397	* @retval FLASH ReadOut Protection Status:
bwang	0:2b1edabdd26b	1398	* - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
bwang	0:2b1edabdd26b	1399	* - RESET, when OB_RDP_Level_0 is set
bwang	0:2b1edabdd26b	1400	*/
bwang	0:2b1edabdd26b	1401	FlagStatus FLASH_OB_GetRDP(void)
bwang	0:2b1edabdd26b	1402	{
bwang	0:2b1edabdd26b	1403	FlagStatus readstatus = RESET;
bwang	0:2b1edabdd26b	1404
bwang	0:2b1edabdd26b	1405	if (((__IO uint8_t)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
bwang	0:2b1edabdd26b	1406	{
bwang	0:2b1edabdd26b	1407	readstatus = SET;
bwang	0:2b1edabdd26b	1408	}
bwang	0:2b1edabdd26b	1409	else
bwang	0:2b1edabdd26b	1410	{
bwang	0:2b1edabdd26b	1411	readstatus = RESET;
bwang	0:2b1edabdd26b	1412	}
bwang	0:2b1edabdd26b	1413	return readstatus;
bwang	0:2b1edabdd26b	1414	}
bwang	0:2b1edabdd26b	1415
bwang	0:2b1edabdd26b	1416	/**
bwang	0:2b1edabdd26b	1417	* @brief Returns the FLASH BOR level.
bwang	0:2b1edabdd26b	1418	* @param None
bwang	0:2b1edabdd26b	1419	* @retval The FLASH BOR level:
bwang	0:2b1edabdd26b	1420	* - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
bwang	0:2b1edabdd26b	1421	* - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
bwang	0:2b1edabdd26b	1422	* - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
bwang	0:2b1edabdd26b	1423	* - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
bwang	0:2b1edabdd26b	1424	*/
bwang	0:2b1edabdd26b	1425	uint8_t FLASH_OB_GetBOR(void)
bwang	0:2b1edabdd26b	1426	{
bwang	0:2b1edabdd26b	1427	/* Return the FLASH BOR level */
bwang	0:2b1edabdd26b	1428	return (uint8_t)((__IO uint8_t )(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
bwang	0:2b1edabdd26b	1429	}
bwang	0:2b1edabdd26b	1430
bwang	0:2b1edabdd26b	1431	/**
bwang	0:2b1edabdd26b	1432	* @}
bwang	0:2b1edabdd26b	1433	*/
bwang	0:2b1edabdd26b	1434
bwang	0:2b1edabdd26b	1435	/** @defgroup FLASH_Group4 Interrupts and flags management functions
bwang	0:2b1edabdd26b	1436	* @brief Interrupts and flags management functions
bwang	0:2b1edabdd26b	1437	*
bwang	0:2b1edabdd26b	1438	@verbatim
bwang	0:2b1edabdd26b	1439	===============================================================================
bwang	0:2b1edabdd26b	1440	##### Interrupts and flags management functions #####
bwang	0:2b1edabdd26b	1441	===============================================================================
bwang	0:2b1edabdd26b	1442	@endverbatim
bwang	0:2b1edabdd26b	1443	* @{
bwang	0:2b1edabdd26b	1444	*/
bwang	0:2b1edabdd26b	1445
bwang	0:2b1edabdd26b	1446	/**
bwang	0:2b1edabdd26b	1447	* @brief Enables or disables the specified FLASH interrupts.
bwang	0:2b1edabdd26b	1448	* @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
bwang	0:2b1edabdd26b	1449	* This parameter can be any combination of the following values:
bwang	0:2b1edabdd26b	1450	* @arg FLASH_IT_ERR: FLASH Error Interrupt
bwang	0:2b1edabdd26b	1451	* @arg FLASH_IT_EOP: FLASH end of operation Interrupt
bwang	0:2b1edabdd26b	1452	* @retval None
bwang	0:2b1edabdd26b	1453	*/
bwang	0:2b1edabdd26b	1454	void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
bwang	0:2b1edabdd26b	1455	{
bwang	0:2b1edabdd26b	1456	/* Check the parameters */
bwang	0:2b1edabdd26b	1457	assert_param(IS_FLASH_IT(FLASH_IT));
bwang	0:2b1edabdd26b	1458	assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang	0:2b1edabdd26b	1459
bwang	0:2b1edabdd26b	1460	if(NewState != DISABLE)
bwang	0:2b1edabdd26b	1461	{
bwang	0:2b1edabdd26b	1462	/* Enable the interrupt sources */
bwang	0:2b1edabdd26b	1463	FLASH->CR \|= FLASH_IT;
bwang	0:2b1edabdd26b	1464	}
bwang	0:2b1edabdd26b	1465	else
bwang	0:2b1edabdd26b	1466	{
bwang	0:2b1edabdd26b	1467	/* Disable the interrupt sources */
bwang	0:2b1edabdd26b	1468	FLASH->CR &= ~(uint32_t)FLASH_IT;
bwang	0:2b1edabdd26b	1469	}
bwang	0:2b1edabdd26b	1470	}
bwang	0:2b1edabdd26b	1471
bwang	0:2b1edabdd26b	1472	/**
bwang	0:2b1edabdd26b	1473	* @brief Checks whether the specified FLASH flag is set or not.
bwang	0:2b1edabdd26b	1474	* @param FLASH_FLAG: specifies the FLASH flag to check.
bwang	0:2b1edabdd26b	1475	* This parameter can be one of the following values:
bwang	0:2b1edabdd26b	1476	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bwang	0:2b1edabdd26b	1477	* @arg FLASH_FLAG_OPERR: FLASH operation Error flag
bwang	0:2b1edabdd26b	1478	* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
bwang	0:2b1edabdd26b	1479	* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
bwang	0:2b1edabdd26b	1480	* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
bwang	0:2b1edabdd26b	1481	* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
bwang	0:2b1edabdd26b	1482	* @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
bwang	0:2b1edabdd26b	1483	* @arg FLASH_FLAG_BSY: FLASH Busy flag
bwang	0:2b1edabdd26b	1484	* @retval The new state of FLASH_FLAG (SET or RESET).
bwang	0:2b1edabdd26b	1485	*/
bwang	0:2b1edabdd26b	1486	FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
bwang	0:2b1edabdd26b	1487	{
bwang	0:2b1edabdd26b	1488	FlagStatus bitstatus = RESET;
bwang	0:2b1edabdd26b	1489	/* Check the parameters */
bwang	0:2b1edabdd26b	1490	assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
bwang	0:2b1edabdd26b	1491
bwang	0:2b1edabdd26b	1492	if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
bwang	0:2b1edabdd26b	1493	{
bwang	0:2b1edabdd26b	1494	bitstatus = SET;
bwang	0:2b1edabdd26b	1495	}
bwang	0:2b1edabdd26b	1496	else
bwang	0:2b1edabdd26b	1497	{
bwang	0:2b1edabdd26b	1498	bitstatus = RESET;
bwang	0:2b1edabdd26b	1499	}
bwang	0:2b1edabdd26b	1500	/* Return the new state of FLASH_FLAG (SET or RESET) */
bwang	0:2b1edabdd26b	1501	return bitstatus;
bwang	0:2b1edabdd26b	1502	}
bwang	0:2b1edabdd26b	1503
bwang	0:2b1edabdd26b	1504	/**
bwang	0:2b1edabdd26b	1505	* @brief Clears the FLASH's pending flags.
bwang	0:2b1edabdd26b	1506	* @param FLASH_FLAG: specifies the FLASH flags to clear.
bwang	0:2b1edabdd26b	1507	* This parameter can be any combination of the following values:
bwang	0:2b1edabdd26b	1508	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bwang	0:2b1edabdd26b	1509	* @arg FLASH_FLAG_OPERR: FLASH operation Error flag
bwang	0:2b1edabdd26b	1510	* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
bwang	0:2b1edabdd26b	1511	* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
bwang	0:2b1edabdd26b	1512	* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
bwang	0:2b1edabdd26b	1513	* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
bwang	0:2b1edabdd26b	1514	* @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
bwang	0:2b1edabdd26b	1515	* @retval None
bwang	0:2b1edabdd26b	1516	*/
bwang	0:2b1edabdd26b	1517	void FLASH_ClearFlag(uint32_t FLASH_FLAG)
bwang	0:2b1edabdd26b	1518	{
bwang	0:2b1edabdd26b	1519	/* Check the parameters */
bwang	0:2b1edabdd26b	1520	assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
bwang	0:2b1edabdd26b	1521
bwang	0:2b1edabdd26b	1522	/* Clear the flags */
bwang	0:2b1edabdd26b	1523	FLASH->SR = FLASH_FLAG;
bwang	0:2b1edabdd26b	1524	}
bwang	0:2b1edabdd26b	1525
bwang	0:2b1edabdd26b	1526	/**
bwang	0:2b1edabdd26b	1527	* @brief Returns the FLASH Status.
bwang	0:2b1edabdd26b	1528	* @param None
bwang	0:2b1edabdd26b	1529	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	1530	* FLASH_ERROR_WRP2, FLASH_ERROR_RD2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	1531	*/
bwang	0:2b1edabdd26b	1532	FLASH_Status FLASH_GetStatus(void)
bwang	0:2b1edabdd26b	1533	{
bwang	0:2b1edabdd26b	1534	FLASH_Status flashstatus = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1535
bwang	0:2b1edabdd26b	1536	if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
bwang	0:2b1edabdd26b	1537	{
bwang	0:2b1edabdd26b	1538	flashstatus = FLASH_BUSY2;
bwang	0:2b1edabdd26b	1539	}
bwang	0:2b1edabdd26b	1540	else
bwang	0:2b1edabdd26b	1541	{
bwang	0:2b1edabdd26b	1542	if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
bwang	0:2b1edabdd26b	1543	{
bwang	0:2b1edabdd26b	1544	flashstatus = FLASH_ERROR_WRP2;
bwang	0:2b1edabdd26b	1545	}
bwang	0:2b1edabdd26b	1546	else
bwang	0:2b1edabdd26b	1547	{
bwang	0:2b1edabdd26b	1548	if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
bwang	0:2b1edabdd26b	1549	{
bwang	0:2b1edabdd26b	1550	flashstatus = FLASH_ERROR_RD2;
bwang	0:2b1edabdd26b	1551	}
bwang	0:2b1edabdd26b	1552	else
bwang	0:2b1edabdd26b	1553	{
bwang	0:2b1edabdd26b	1554	if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
bwang	0:2b1edabdd26b	1555	{
bwang	0:2b1edabdd26b	1556	flashstatus = FLASH_ERROR_PROGRAM2;
bwang	0:2b1edabdd26b	1557	}
bwang	0:2b1edabdd26b	1558	else
bwang	0:2b1edabdd26b	1559	{
bwang	0:2b1edabdd26b	1560	if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
bwang	0:2b1edabdd26b	1561	{
bwang	0:2b1edabdd26b	1562	flashstatus = FLASH_ERROR_OPERATION2;
bwang	0:2b1edabdd26b	1563	}
bwang	0:2b1edabdd26b	1564	else
bwang	0:2b1edabdd26b	1565	{
bwang	0:2b1edabdd26b	1566	flashstatus = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1567	}
bwang	0:2b1edabdd26b	1568	}
bwang	0:2b1edabdd26b	1569	}
bwang	0:2b1edabdd26b	1570	}
bwang	0:2b1edabdd26b	1571	}
bwang	0:2b1edabdd26b	1572	/* Return the FLASH Status */
bwang	0:2b1edabdd26b	1573	return flashstatus;
bwang	0:2b1edabdd26b	1574	}
bwang	0:2b1edabdd26b	1575
bwang	0:2b1edabdd26b	1576	/**
bwang	0:2b1edabdd26b	1577	* @brief Waits for a FLASH operation to complete.
bwang	0:2b1edabdd26b	1578	* @param None
bwang	0:2b1edabdd26b	1579	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang	0:2b1edabdd26b	1580	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang	0:2b1edabdd26b	1581	*/
bwang	0:2b1edabdd26b	1582	FLASH_Status FLASH_WaitForLastOperation2(void)
bwang	0:2b1edabdd26b	1583	{
bwang	0:2b1edabdd26b	1584	__IO FLASH_Status status = FLASH_COMPLETE2;
bwang	0:2b1edabdd26b	1585
bwang	0:2b1edabdd26b	1586	/* Check for the FLASH Status */
bwang	0:2b1edabdd26b	1587	status = FLASH_GetStatus();
bwang	0:2b1edabdd26b	1588
bwang	0:2b1edabdd26b	1589	/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
bwang	0:2b1edabdd26b	1590	Even if the FLASH operation fails, the BUSY flag will be reset and an error
bwang	0:2b1edabdd26b	1591	flag will be set */
bwang	0:2b1edabdd26b	1592	while(status == FLASH_BUSY2)
bwang	0:2b1edabdd26b	1593	{
bwang	0:2b1edabdd26b	1594	status = FLASH_GetStatus();
bwang	0:2b1edabdd26b	1595	}
bwang	0:2b1edabdd26b	1596	/* Return the operation status */
bwang	0:2b1edabdd26b	1597	return status;
bwang	0:2b1edabdd26b	1598	}
bwang	0:2b1edabdd26b	1599
bwang	0:2b1edabdd26b	1600	/**
bwang	0:2b1edabdd26b	1601	* @}
bwang	0:2b1edabdd26b	1602	*/
bwang	0:2b1edabdd26b	1603
bwang	0:2b1edabdd26b	1604	/**
bwang	0:2b1edabdd26b	1605	* @}
bwang	0:2b1edabdd26b	1606	*/
bwang	0:2b1edabdd26b	1607
bwang	0:2b1edabdd26b	1608	/**
bwang	0:2b1edabdd26b	1609	* @}
bwang	0:2b1edabdd26b	1610	*/
bwang	0:2b1edabdd26b	1611
bwang	0:2b1edabdd26b	1612	/**
bwang	0:2b1edabdd26b	1613	* @}
bwang	0:2b1edabdd26b	1614	*/
bwang	0:2b1edabdd26b	1615
bwang	0:2b1edabdd26b	1616	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	03 Feb 2019
Imports:	3
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	2
Followers:	2

PreferenceWriter/stm32f4xx_flash.c@0:2b1edabdd26b, 2019-02-03 (annotated)

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