Boston Univeristy Rocket Team / Mbed 2 deprecated BURTDAQ
Committer:
burocketteam
Date:
Mon Apr 09 23:31:18 2012 +0000
Revision:
0:cd3d9a71d3b4

        

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burocketteam 0:cd3d9a71d3b4 1 // Pin function definitions for BURT MKII DAQ Main Board r1.0
burocketteam 0:cd3d9a71d3b4 2 #ifndef BURTDAQ_H
burocketteam 0:cd3d9a71d3b4 3 #define BURTDAQ_H
burocketteam 0:cd3d9a71d3b4 4
burocketteam 0:cd3d9a71d3b4 5 // XBee serial port
burocketteam 0:cd3d9a71d3b4 6 #define XBEETX p28
burocketteam 0:cd3d9a71d3b4 7 #define XBEERX p27
burocketteam 0:cd3d9a71d3b4 8
burocketteam 0:cd3d9a71d3b4 9 // LCD serial port
burocketteam 0:cd3d9a71d3b4 10 #define LCDTX p9
burocketteam 0:cd3d9a71d3b4 11 #define LCDRX p10
burocketteam 0:cd3d9a71d3b4 12
burocketteam 0:cd3d9a71d3b4 13 // SPI A
burocketteam 0:cd3d9a71d3b4 14 #define SPIA_MOSI p5
burocketteam 0:cd3d9a71d3b4 15 #define SPIA_MISO p6
burocketteam 0:cd3d9a71d3b4 16 #define SPIA_CLK p7
burocketteam 0:cd3d9a71d3b4 17
burocketteam 0:cd3d9a71d3b4 18 #define SPIA_P1_CS p8 // P0.6
burocketteam 0:cd3d9a71d3b4 19 #define SPIA_P2_CS p14 // P0.16
burocketteam 0:cd3d9a71d3b4 20 #define SPIA_P3_CS p30 // P0.4
burocketteam 0:cd3d9a71d3b4 21 #define SPIA_P4_CS p29 // P0.5
burocketteam 0:cd3d9a71d3b4 22
burocketteam 0:cd3d9a71d3b4 23 #define SPIA_CS_PORT_MASK 0x10070
burocketteam 0:cd3d9a71d3b4 24 #define SPIA_P1_CS_PORT_MASK 0x40
burocketteam 0:cd3d9a71d3b4 25 #define SPIA_P2_CS_PORT_MASK 0x10000
burocketteam 0:cd3d9a71d3b4 26 #define SPIA_P3_CS_PORT_MASK 0x10
burocketteam 0:cd3d9a71d3b4 27 #define SPIA_P4_CS_PORT_MASK 0x20
burocketteam 0:cd3d9a71d3b4 28
burocketteam 0:cd3d9a71d3b4 29 // SPI B
burocketteam 0:cd3d9a71d3b4 30 #define SPIB_MOSI p11
burocketteam 0:cd3d9a71d3b4 31 #define SPIB_MISO p12
burocketteam 0:cd3d9a71d3b4 32 #define SPIB_CLK p13
burocketteam 0:cd3d9a71d3b4 33
burocketteam 0:cd3d9a71d3b4 34 #define SPIB_P1_CS p15
burocketteam 0:cd3d9a71d3b4 35 #define SPIB_P2_CS p16
burocketteam 0:cd3d9a71d3b4 36 #define SPIB_P3_CS p17
burocketteam 0:cd3d9a71d3b4 37 #define SPIB_P4_CS p19
burocketteam 0:cd3d9a71d3b4 38
burocketteam 0:cd3d9a71d3b4 39 // H-Bridge Outputs
burocketteam 0:cd3d9a71d3b4 40 #define MOTOR1 p25
burocketteam 0:cd3d9a71d3b4 41 #define MOTOR2 p24
burocketteam 0:cd3d9a71d3b4 42 #define MOTOR3 p22 // NOTE: Motor3 and Motor4 are mixed up in schematic, so the pins are out of order
burocketteam 0:cd3d9a71d3b4 43 #define MOTOR4 p23
burocketteam 0:cd3d9a71d3b4 44
burocketteam 0:cd3d9a71d3b4 45 // Filter Clock Output
burocketteam 0:cd3d9a71d3b4 46 #define FILTCLK p26
burocketteam 0:cd3d9a71d3b4 47
burocketteam 0:cd3d9a71d3b4 48 #endif