Brunno Oliveira / SX1272Lib

pingpong coragem

Dependents:   SX1272PingPong

sx1272/sx1272.cpp@7:b988b60083a1, 2017-04-24 (annotated)

Committer:
mluis
Date:
Mon Apr 24 09:26:08 2017 +0000
Revision:
7:b988b60083a1
Parent:
0:45c4f0364ca4 
WARNING: Radio API timings changed from micro-seconds to milliseconds; ; Synchronized with https://github.com/Lora-net/LoRaMac-node git revision e506c246652fa44c3f24cecb89d0707b49ece739

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: Actual implementation of a SX1272 radio, inherits Radio
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272.h"
mluis 0:45c4f0364ca4 16
mluis 0:45c4f0364ca4 17 const FskBandwidth_t SX1272::FskBandwidths[] =
mluis 7:b988b60083a1 18 {
mluis 7:b988b60083a1 19 { 2600 , 0x17 },
mluis 0:45c4f0364ca4 20 { 3100 , 0x0F },
mluis 0:45c4f0364ca4 21 { 3900 , 0x07 },
mluis 0:45c4f0364ca4 22 { 5200 , 0x16 },
mluis 0:45c4f0364ca4 23 { 6300 , 0x0E },
mluis 0:45c4f0364ca4 24 { 7800 , 0x06 },
mluis 0:45c4f0364ca4 25 { 10400 , 0x15 },
mluis 0:45c4f0364ca4 26 { 12500 , 0x0D },
mluis 0:45c4f0364ca4 27 { 15600 , 0x05 },
mluis 0:45c4f0364ca4 28 { 20800 , 0x14 },
mluis 0:45c4f0364ca4 29 { 25000 , 0x0C },
mluis 0:45c4f0364ca4 30 { 31300 , 0x04 },
mluis 0:45c4f0364ca4 31 { 41700 , 0x13 },
mluis 0:45c4f0364ca4 32 { 50000 , 0x0B },
mluis 0:45c4f0364ca4 33 { 62500 , 0x03 },
mluis 0:45c4f0364ca4 34 { 83333 , 0x12 },
mluis 0:45c4f0364ca4 35 { 100000, 0x0A },
mluis 0:45c4f0364ca4 36 { 125000, 0x02 },
mluis 0:45c4f0364ca4 37 { 166700, 0x11 },
mluis 0:45c4f0364ca4 38 { 200000, 0x09 },
mluis 0:45c4f0364ca4 39 { 250000, 0x01 },
mluis 7:b988b60083a1 40 { 300000, 0x00 }, // Invalid Bandwidth
mluis 0:45c4f0364ca4 41 };
mluis 0:45c4f0364ca4 42
mluis 0:45c4f0364ca4 43
mluis 0:45c4f0364ca4 44 SX1272::SX1272( RadioEvents_t *events,
mluis 0:45c4f0364ca4 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 0:45c4f0364ca4 47 : Radio( events ),
mluis 0:45c4f0364ca4 48 spi( mosi, miso, sclk ),
mluis 0:45c4f0364ca4 49 nss( nss ),
mluis 0:45c4f0364ca4 50 reset( reset ),
mluis 0:45c4f0364ca4 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 0:45c4f0364ca4 52 isRadioActive( false )
mluis 0:45c4f0364ca4 53 {
mluis 0:45c4f0364ca4 54 wait_ms( 10 );
mluis 7:b988b60083a1 55 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 7:b988b60083a1 56
mluis 0:45c4f0364ca4 57 this->RadioEvents = events;
mluis 7:b988b60083a1 58
mluis 0:45c4f0364ca4 59 this->dioIrq = new DioIrqHandler[6];
mluis 0:45c4f0364ca4 60
mluis 0:45c4f0364ca4 61 this->dioIrq[0] = &SX1272::OnDio0Irq;
mluis 0:45c4f0364ca4 62 this->dioIrq[1] = &SX1272::OnDio1Irq;
mluis 0:45c4f0364ca4 63 this->dioIrq[2] = &SX1272::OnDio2Irq;
mluis 0:45c4f0364ca4 64 this->dioIrq[3] = &SX1272::OnDio3Irq;
mluis 0:45c4f0364ca4 65 this->dioIrq[4] = &SX1272::OnDio4Irq;
mluis 0:45c4f0364ca4 66 this->dioIrq[5] = NULL;
mluis 7:b988b60083a1 67
mluis 0:45c4f0364ca4 68 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 69 }
mluis 0:45c4f0364ca4 70
mluis 0:45c4f0364ca4 71 SX1272::~SX1272( )
mluis 0:45c4f0364ca4 72 {
mluis 7:b988b60083a1 73 delete this->rxtxBuffer;
mluis 0:45c4f0364ca4 74 delete this->dioIrq;
mluis 0:45c4f0364ca4 75 }
mluis 0:45c4f0364ca4 76
mluis 0:45c4f0364ca4 77 void SX1272::Init( RadioEvents_t *events )
mluis 0:45c4f0364ca4 78 {
mluis 0:45c4f0364ca4 79 this->RadioEvents = events;
mluis 0:45c4f0364ca4 80 }
mluis 0:45c4f0364ca4 81
mluis 0:45c4f0364ca4 82 RadioState SX1272::GetStatus( void )
mluis 0:45c4f0364ca4 83 {
mluis 0:45c4f0364ca4 84 return this->settings.State;
mluis 0:45c4f0364ca4 85 }
mluis 0:45c4f0364ca4 86
mluis 0:45c4f0364ca4 87 void SX1272::SetChannel( uint32_t freq )
mluis 0:45c4f0364ca4 88 {
mluis 0:45c4f0364ca4 89 this->settings.Channel = freq;
mluis 0:45c4f0364ca4 90 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 91 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
mluis 0:45c4f0364ca4 92 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 93 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
mluis 0:45c4f0364ca4 94 }
mluis 0:45c4f0364ca4 95
mluis 0:45c4f0364ca4 96 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
mluis 0:45c4f0364ca4 97 {
mluis 0:45c4f0364ca4 98 int16_t rssi = 0;
mluis 7:b988b60083a1 99
mluis 0:45c4f0364ca4 100 SetModem( modem );
mluis 0:45c4f0364ca4 101
mluis 0:45c4f0364ca4 102 SetChannel( freq );
mluis 7:b988b60083a1 103
mluis 0:45c4f0364ca4 104 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 105
mluis 0:45c4f0364ca4 106 wait_ms( 1 );
mluis 7:b988b60083a1 107
mluis 0:45c4f0364ca4 108 rssi = GetRssi( modem );
mluis 7:b988b60083a1 109
mluis 0:45c4f0364ca4 110 Sleep( );
mluis 7:b988b60083a1 111
mluis 0:45c4f0364ca4 112 if( rssi > rssiThresh )
mluis 0:45c4f0364ca4 113 {
mluis 0:45c4f0364ca4 114 return false;
mluis 0:45c4f0364ca4 115 }
mluis 0:45c4f0364ca4 116 return true;
mluis 0:45c4f0364ca4 117 }
mluis 0:45c4f0364ca4 118
mluis 0:45c4f0364ca4 119 uint32_t SX1272::Random( void )
mluis 0:45c4f0364ca4 120 {
mluis 0:45c4f0364ca4 121 uint8_t i;
mluis 0:45c4f0364ca4 122 uint32_t rnd = 0;
mluis 0:45c4f0364ca4 123
mluis 0:45c4f0364ca4 124 /*
mluis 7:b988b60083a1 125 * Radio setup for random number generation
mluis 0:45c4f0364ca4 126 */
mluis 0:45c4f0364ca4 127 // Set LoRa modem ON
mluis 0:45c4f0364ca4 128 SetModem( MODEM_LORA );
mluis 0:45c4f0364ca4 129
mluis 0:45c4f0364ca4 130 // Disable LoRa modem interrupts
mluis 0:45c4f0364ca4 131 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 132 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 133 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 134 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 135 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 136 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 137 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 138 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 139
mluis 0:45c4f0364ca4 140 // Set radio in continuous reception
mluis 0:45c4f0364ca4 141 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 142
mluis 0:45c4f0364ca4 143 for( i = 0; i < 32; i++ )
mluis 0:45c4f0364ca4 144 {
mluis 0:45c4f0364ca4 145 wait_ms( 1 );
mluis 0:45c4f0364ca4 146 // Unfiltered RSSI value reading. Only takes the LSB value
mluis 0:45c4f0364ca4 147 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
mluis 0:45c4f0364ca4 148 }
mluis 0:45c4f0364ca4 149
mluis 0:45c4f0364ca4 150 Sleep( );
mluis 0:45c4f0364ca4 151
mluis 0:45c4f0364ca4 152 return rnd;
mluis 0:45c4f0364ca4 153 }
mluis 0:45c4f0364ca4 154
mluis 0:45c4f0364ca4 155 /*!
mluis 0:45c4f0364ca4 156 * Returns the known FSK bandwidth registers value
mluis 0:45c4f0364ca4 157 *
mluis 0:45c4f0364ca4 158 * \param [IN] bandwidth Bandwidth value in Hz
mluis 0:45c4f0364ca4 159 * \retval regValue Bandwidth register value.
mluis 0:45c4f0364ca4 160 */
mluis 0:45c4f0364ca4 161 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
mluis 0:45c4f0364ca4 162 {
mluis 0:45c4f0364ca4 163 uint8_t i;
mluis 0:45c4f0364ca4 164
mluis 0:45c4f0364ca4 165 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
mluis 0:45c4f0364ca4 166 {
mluis 0:45c4f0364ca4 167 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
mluis 0:45c4f0364ca4 168 {
mluis 0:45c4f0364ca4 169 return FskBandwidths[i].RegValue;
mluis 0:45c4f0364ca4 170 }
mluis 0:45c4f0364ca4 171 }
mluis 0:45c4f0364ca4 172 // ERROR: Value not found
mluis 0:45c4f0364ca4 173 while( 1 );
mluis 0:45c4f0364ca4 174 }
mluis 0:45c4f0364ca4 175
mluis 0:45c4f0364ca4 176 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
mluis 0:45c4f0364ca4 177 uint32_t datarate, uint8_t coderate,
mluis 0:45c4f0364ca4 178 uint32_t bandwidthAfc, uint16_t preambleLen,
mluis 0:45c4f0364ca4 179 uint16_t symbTimeout, bool fixLen,
mluis 0:45c4f0364ca4 180 uint8_t payloadLen,
mluis 0:45c4f0364ca4 181 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
mluis 0:45c4f0364ca4 182 bool iqInverted, bool rxContinuous )
mluis 0:45c4f0364ca4 183 {
mluis 0:45c4f0364ca4 184 SetModem( modem );
mluis 0:45c4f0364ca4 185
mluis 0:45c4f0364ca4 186 switch( modem )
mluis 0:45c4f0364ca4 187 {
mluis 0:45c4f0364ca4 188 case MODEM_FSK:
mluis 0:45c4f0364ca4 189 {
mluis 0:45c4f0364ca4 190 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 191 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 192 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
mluis 0:45c4f0364ca4 193 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 194 this->settings.Fsk.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 195 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 196 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 197 this->settings.Fsk.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 198 this->settings.Fsk.PreambleLen = preambleLen;
mluis 7:b988b60083a1 199 this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
mluis 7:b988b60083a1 200
mluis 0:45c4f0364ca4 201 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 202 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 203 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 204
mluis 0:45c4f0364ca4 205 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
mluis 0:45c4f0364ca4 206 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
mluis 0:45c4f0364ca4 207
mluis 0:45c4f0364ca4 208 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 209 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 7:b988b60083a1 210
mluis 0:45c4f0364ca4 211 if( fixLen == 1 )
mluis 0:45c4f0364ca4 212 {
mluis 0:45c4f0364ca4 213 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 214 }
mluis 7:b988b60083a1 215 else
mluis 7:b988b60083a1 216 {
mluis 7:b988b60083a1 217 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
mluis 7:b988b60083a1 218 }
mluis 7:b988b60083a1 219
mluis 0:45c4f0364ca4 220 Write( REG_PACKETCONFIG1,
mluis 7:b988b60083a1 221 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 222 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 223 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 224 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 225 ( crcOn << 4 ) );
mluis 7:b988b60083a1 226 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
mluis 0:45c4f0364ca4 227 }
mluis 0:45c4f0364ca4 228 break;
mluis 0:45c4f0364ca4 229 case MODEM_LORA:
mluis 0:45c4f0364ca4 230 {
mluis 0:45c4f0364ca4 231 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 232 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 233 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 234 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 235 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 236 this->settings.LoRa.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 237 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 238 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 239 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 240 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 241 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 242
mluis 0:45c4f0364ca4 243 if( datarate > 12 )
mluis 0:45c4f0364ca4 244 {
mluis 0:45c4f0364ca4 245 datarate = 12;
mluis 0:45c4f0364ca4 246 }
mluis 0:45c4f0364ca4 247 else if( datarate < 6 )
mluis 0:45c4f0364ca4 248 {
mluis 0:45c4f0364ca4 249 datarate = 6;
mluis 0:45c4f0364ca4 250 }
mluis 7:b988b60083a1 251
mluis 0:45c4f0364ca4 252 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 253 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 254 {
mluis 0:45c4f0364ca4 255 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 256 }
mluis 0:45c4f0364ca4 257 else
mluis 0:45c4f0364ca4 258 {
mluis 0:45c4f0364ca4 259 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 260 }
mluis 0:45c4f0364ca4 261
mluis 7:b988b60083a1 262 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 263 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 264 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 265 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 266 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 267 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 268 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 7:b988b60083a1 269 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 270 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 271 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 272
mluis 0:45c4f0364ca4 273 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 274 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 275 RFLR_MODEMCONFIG2_SF_MASK &
mluis 0:45c4f0364ca4 276 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
mluis 0:45c4f0364ca4 277 ( datarate << 4 ) |
mluis 0:45c4f0364ca4 278 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
mluis 0:45c4f0364ca4 279
mluis 0:45c4f0364ca4 280 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 7:b988b60083a1 281
mluis 0:45c4f0364ca4 282 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 283 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 284
mluis 0:45c4f0364ca4 285 if( fixLen == 1 )
mluis 0:45c4f0364ca4 286 {
mluis 0:45c4f0364ca4 287 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 288 }
mluis 0:45c4f0364ca4 289
mluis 0:45c4f0364ca4 290 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 291 {
mluis 0:45c4f0364ca4 292 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 293 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 294 }
mluis 0:45c4f0364ca4 295
mluis 0:45c4f0364ca4 296 if( datarate == 6 )
mluis 0:45c4f0364ca4 297 {
mluis 7:b988b60083a1 298 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 299 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 300 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 301 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 7:b988b60083a1 302 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 303 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 304 }
mluis 0:45c4f0364ca4 305 else
mluis 0:45c4f0364ca4 306 {
mluis 0:45c4f0364ca4 307 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 308 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 309 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 310 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 7:b988b60083a1 311 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 312 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 313 }
mluis 0:45c4f0364ca4 314 }
mluis 0:45c4f0364ca4 315 break;
mluis 0:45c4f0364ca4 316 }
mluis 0:45c4f0364ca4 317 }
mluis 0:45c4f0364ca4 318
mluis 7:b988b60083a1 319 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
mluis 0:45c4f0364ca4 320 uint32_t bandwidth, uint32_t datarate,
mluis 0:45c4f0364ca4 321 uint8_t coderate, uint16_t preambleLen,
mluis 7:b988b60083a1 322 bool fixLen, bool crcOn, bool freqHopOn,
mluis 0:45c4f0364ca4 323 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
mluis 0:45c4f0364ca4 324 {
mluis 0:45c4f0364ca4 325 SetModem( modem );
mluis 0:45c4f0364ca4 326
mluis 7:b988b60083a1 327 SetRfTxPower( power );
mluis 0:45c4f0364ca4 328
mluis 0:45c4f0364ca4 329 switch( modem )
mluis 0:45c4f0364ca4 330 {
mluis 0:45c4f0364ca4 331 case MODEM_FSK:
mluis 0:45c4f0364ca4 332 {
mluis 0:45c4f0364ca4 333 this->settings.Fsk.Power = power;
mluis 0:45c4f0364ca4 334 this->settings.Fsk.Fdev = fdev;
mluis 0:45c4f0364ca4 335 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 336 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 337 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 338 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 339 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 340 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 341 this->settings.Fsk.TxTimeout = timeout;
mluis 7:b988b60083a1 342
mluis 0:45c4f0364ca4 343 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 344 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
mluis 0:45c4f0364ca4 345 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
mluis 0:45c4f0364ca4 346
mluis 0:45c4f0364ca4 347 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 348 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 349 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 350
mluis 0:45c4f0364ca4 351 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 352 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 353
mluis 0:45c4f0364ca4 354 Write( REG_PACKETCONFIG1,
mluis 7:b988b60083a1 355 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 356 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 357 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 358 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 359 ( crcOn << 4 ) );
mluis 7:b988b60083a1 360 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
mluis 0:45c4f0364ca4 361 }
mluis 0:45c4f0364ca4 362 break;
mluis 0:45c4f0364ca4 363 case MODEM_LORA:
mluis 0:45c4f0364ca4 364 {
mluis 0:45c4f0364ca4 365 this->settings.LoRa.Power = power;
mluis 0:45c4f0364ca4 366 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 367 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 368 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 369 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 370 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 371 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 372 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 373 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 374 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 375 this->settings.LoRa.TxTimeout = timeout;
mluis 0:45c4f0364ca4 376
mluis 0:45c4f0364ca4 377 if( datarate > 12 )
mluis 0:45c4f0364ca4 378 {
mluis 0:45c4f0364ca4 379 datarate = 12;
mluis 0:45c4f0364ca4 380 }
mluis 0:45c4f0364ca4 381 else if( datarate < 6 )
mluis 0:45c4f0364ca4 382 {
mluis 0:45c4f0364ca4 383 datarate = 6;
mluis 0:45c4f0364ca4 384 }
mluis 0:45c4f0364ca4 385 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 386 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 387 {
mluis 0:45c4f0364ca4 388 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 389 }
mluis 0:45c4f0364ca4 390 else
mluis 0:45c4f0364ca4 391 {
mluis 0:45c4f0364ca4 392 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 393 }
mluis 0:45c4f0364ca4 394
mluis 0:45c4f0364ca4 395 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 396 {
mluis 0:45c4f0364ca4 397 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 398 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 399 }
mluis 0:45c4f0364ca4 400
mluis 7:b988b60083a1 401 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 402 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 403 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 404 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 405 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 406 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 407 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 7:b988b60083a1 408 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 409 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 410 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 411
mluis 0:45c4f0364ca4 412 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 413 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 414 RFLR_MODEMCONFIG2_SF_MASK ) |
mluis 0:45c4f0364ca4 415 ( datarate << 4 ) );
mluis 0:45c4f0364ca4 416
mluis 7:b988b60083a1 417
mluis 0:45c4f0364ca4 418 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 419 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 7:b988b60083a1 420
mluis 0:45c4f0364ca4 421 if( datarate == 6 )
mluis 0:45c4f0364ca4 422 {
mluis 7:b988b60083a1 423 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 424 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 425 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 426 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 7:b988b60083a1 427 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 428 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 429 }
mluis 0:45c4f0364ca4 430 else
mluis 0:45c4f0364ca4 431 {
mluis 0:45c4f0364ca4 432 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 433 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 434 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 435 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 7:b988b60083a1 436 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 437 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 438 }
mluis 0:45c4f0364ca4 439 }
mluis 0:45c4f0364ca4 440 break;
mluis 0:45c4f0364ca4 441 }
mluis 0:45c4f0364ca4 442 }
mluis 0:45c4f0364ca4 443
mluis 7:b988b60083a1 444 uint32_t SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
mluis 0:45c4f0364ca4 445 {
mluis 0:45c4f0364ca4 446 uint32_t airTime = 0;
mluis 0:45c4f0364ca4 447
mluis 0:45c4f0364ca4 448 switch( modem )
mluis 0:45c4f0364ca4 449 {
mluis 0:45c4f0364ca4 450 case MODEM_FSK:
mluis 0:45c4f0364ca4 451 {
mluis 0:45c4f0364ca4 452 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 453 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
mluis 0:45c4f0364ca4 454 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
mluis 0:45c4f0364ca4 455 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
mluis 0:45c4f0364ca4 456 pktLen +
mluis 0:45c4f0364ca4 457 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
mluis 7:b988b60083a1 458 this->settings.Fsk.Datarate ) * 1e3 );
mluis 0:45c4f0364ca4 459 }
mluis 0:45c4f0364ca4 460 break;
mluis 0:45c4f0364ca4 461 case MODEM_LORA:
mluis 0:45c4f0364ca4 462 {
mluis 0:45c4f0364ca4 463 double bw = 0.0;
mluis 0:45c4f0364ca4 464 switch( this->settings.LoRa.Bandwidth )
mluis 0:45c4f0364ca4 465 {
mluis 0:45c4f0364ca4 466 case 0: // 125 kHz
mluis 0:45c4f0364ca4 467 bw = 125e3;
mluis 0:45c4f0364ca4 468 break;
mluis 0:45c4f0364ca4 469 case 1: // 250 kHz
mluis 0:45c4f0364ca4 470 bw = 250e3;
mluis 0:45c4f0364ca4 471 break;
mluis 0:45c4f0364ca4 472 case 2: // 500 kHz
mluis 0:45c4f0364ca4 473 bw = 500e3;
mluis 0:45c4f0364ca4 474 break;
mluis 0:45c4f0364ca4 475 }
mluis 0:45c4f0364ca4 476
mluis 0:45c4f0364ca4 477 // Symbol rate : time for one symbol (secs)
mluis 0:45c4f0364ca4 478 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
mluis 0:45c4f0364ca4 479 double ts = 1 / rs;
mluis 0:45c4f0364ca4 480 // time of preamble
mluis 0:45c4f0364ca4 481 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
mluis 0:45c4f0364ca4 482 // Symbol length of payload and time
mluis 0:45c4f0364ca4 483 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
mluis 0:45c4f0364ca4 484 28 + 16 * this->settings.LoRa.CrcOn -
mluis 0:45c4f0364ca4 485 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
mluis 7:b988b60083a1 486 ( double )( 4 * ( this->settings.LoRa.Datarate -
mluis 7:b988b60083a1 487 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
mluis 0:45c4f0364ca4 488 ( this->settings.LoRa.Coderate + 4 );
mluis 0:45c4f0364ca4 489 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
mluis 0:45c4f0364ca4 490 double tPayload = nPayload * ts;
mluis 7:b988b60083a1 491 // Time on air
mluis 0:45c4f0364ca4 492 double tOnAir = tPreamble + tPayload;
mluis 7:b988b60083a1 493 // return ms secs
mluis 7:b988b60083a1 494 airTime = floor( tOnAir * 1e3 + 0.999 );
mluis 0:45c4f0364ca4 495 }
mluis 0:45c4f0364ca4 496 break;
mluis 0:45c4f0364ca4 497 }
mluis 0:45c4f0364ca4 498 return airTime;
mluis 0:45c4f0364ca4 499 }
mluis 0:45c4f0364ca4 500
mluis 0:45c4f0364ca4 501 void SX1272::Send( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 502 {
mluis 0:45c4f0364ca4 503 uint32_t txTimeout = 0;
mluis 0:45c4f0364ca4 504
mluis 0:45c4f0364ca4 505 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 506 {
mluis 0:45c4f0364ca4 507 case MODEM_FSK:
mluis 0:45c4f0364ca4 508 {
mluis 0:45c4f0364ca4 509 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 510 this->settings.FskPacketHandler.Size = size;
mluis 0:45c4f0364ca4 511
mluis 0:45c4f0364ca4 512 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 513 {
mluis 0:45c4f0364ca4 514 WriteFifo( ( uint8_t* )&size, 1 );
mluis 0:45c4f0364ca4 515 }
mluis 0:45c4f0364ca4 516 else
mluis 0:45c4f0364ca4 517 {
mluis 0:45c4f0364ca4 518 Write( REG_PAYLOADLENGTH, size );
mluis 7:b988b60083a1 519 }
mluis 7:b988b60083a1 520
mluis 0:45c4f0364ca4 521 if( ( size > 0 ) && ( size <= 64 ) )
mluis 0:45c4f0364ca4 522 {
mluis 0:45c4f0364ca4 523 this->settings.FskPacketHandler.ChunkSize = size;
mluis 0:45c4f0364ca4 524 }
mluis 0:45c4f0364ca4 525 else
mluis 0:45c4f0364ca4 526 {
mluis 7:b988b60083a1 527 memcpy( rxtxBuffer, buffer, size );
mluis 0:45c4f0364ca4 528 this->settings.FskPacketHandler.ChunkSize = 32;
mluis 0:45c4f0364ca4 529 }
mluis 0:45c4f0364ca4 530
mluis 0:45c4f0364ca4 531 // Write payload buffer
mluis 0:45c4f0364ca4 532 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 533 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 534 txTimeout = this->settings.Fsk.TxTimeout;
mluis 0:45c4f0364ca4 535 }
mluis 0:45c4f0364ca4 536 break;
mluis 0:45c4f0364ca4 537 case MODEM_LORA:
mluis 0:45c4f0364ca4 538 {
mluis 0:45c4f0364ca4 539 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 540 {
mluis 0:45c4f0364ca4 541 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 0:45c4f0364ca4 542 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 543 }
mluis 0:45c4f0364ca4 544 else
mluis 0:45c4f0364ca4 545 {
mluis 0:45c4f0364ca4 546 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 547 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 7:b988b60083a1 548 }
mluis 7:b988b60083a1 549
mluis 0:45c4f0364ca4 550 this->settings.LoRaPacketHandler.Size = size;
mluis 0:45c4f0364ca4 551
mluis 0:45c4f0364ca4 552 // Initializes the payload size
mluis 0:45c4f0364ca4 553 Write( REG_LR_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 554
mluis 7:b988b60083a1 555 // Full buffer used for Tx
mluis 0:45c4f0364ca4 556 Write( REG_LR_FIFOTXBASEADDR, 0 );
mluis 0:45c4f0364ca4 557 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 558
mluis 0:45c4f0364ca4 559 // FIFO operations can not take place in Sleep mode
mluis 0:45c4f0364ca4 560 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 561 {
mluis 0:45c4f0364ca4 562 Standby( );
mluis 0:45c4f0364ca4 563 wait_ms( 1 );
mluis 0:45c4f0364ca4 564 }
mluis 0:45c4f0364ca4 565 // Write payload buffer
mluis 0:45c4f0364ca4 566 WriteFifo( buffer, size );
mluis 0:45c4f0364ca4 567 txTimeout = this->settings.LoRa.TxTimeout;
mluis 0:45c4f0364ca4 568 }
mluis 0:45c4f0364ca4 569 break;
mluis 0:45c4f0364ca4 570 }
mluis 0:45c4f0364ca4 571
mluis 0:45c4f0364ca4 572 Tx( txTimeout );
mluis 0:45c4f0364ca4 573 }
mluis 0:45c4f0364ca4 574
mluis 0:45c4f0364ca4 575 void SX1272::Sleep( void )
mluis 0:45c4f0364ca4 576 {
mluis 7:b988b60083a1 577 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 578 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 579
mluis 0:45c4f0364ca4 580 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 581 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 582 }
mluis 0:45c4f0364ca4 583
mluis 0:45c4f0364ca4 584 void SX1272::Standby( void )
mluis 0:45c4f0364ca4 585 {
mluis 7:b988b60083a1 586 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 587 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 588
mluis 0:45c4f0364ca4 589 SetOpMode( RF_OPMODE_STANDBY );
mluis 0:45c4f0364ca4 590 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 591 }
mluis 0:45c4f0364ca4 592
mluis 0:45c4f0364ca4 593 void SX1272::Rx( uint32_t timeout )
mluis 0:45c4f0364ca4 594 {
mluis 0:45c4f0364ca4 595 bool rxContinuous = false;
mluis 7:b988b60083a1 596
mluis 0:45c4f0364ca4 597 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 598 {
mluis 0:45c4f0364ca4 599 case MODEM_FSK:
mluis 0:45c4f0364ca4 600 {
mluis 0:45c4f0364ca4 601 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 7:b988b60083a1 602
mluis 0:45c4f0364ca4 603 // DIO0=PayloadReady
mluis 0:45c4f0364ca4 604 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 605 // DIO2=SyncAddr
mluis 0:45c4f0364ca4 606 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 607 // DIO4=Preamble
mluis 0:45c4f0364ca4 608 // DIO5=ModeReady
mluis 0:45c4f0364ca4 609 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 7:b988b60083a1 610 RF_DIOMAPPING1_DIO1_MASK &
mluis 0:45c4f0364ca4 611 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 0:45c4f0364ca4 612 RF_DIOMAPPING1_DIO0_00 |
mluis 7:b988b60083a1 613 RF_DIOMAPPING1_DIO1_00 |
mluis 0:45c4f0364ca4 614 RF_DIOMAPPING1_DIO2_11 );
mluis 7:b988b60083a1 615
mluis 0:45c4f0364ca4 616 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 7:b988b60083a1 617 RF_DIOMAPPING2_MAP_MASK ) |
mluis 0:45c4f0364ca4 618 RF_DIOMAPPING2_DIO4_11 |
mluis 0:45c4f0364ca4 619 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 7:b988b60083a1 620
mluis 0:45c4f0364ca4 621 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 7:b988b60083a1 622
mluis 7:b988b60083a1 623 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
mluis 7:b988b60083a1 624
mluis 0:45c4f0364ca4 625 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 626 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 627 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 628 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 629 }
mluis 0:45c4f0364ca4 630 break;
mluis 0:45c4f0364ca4 631 case MODEM_LORA:
mluis 0:45c4f0364ca4 632 {
mluis 0:45c4f0364ca4 633 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 634 {
mluis 0:45c4f0364ca4 635 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 636 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 637 }
mluis 0:45c4f0364ca4 638 else
mluis 0:45c4f0364ca4 639 {
mluis 0:45c4f0364ca4 640 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 641 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 7:b988b60083a1 642 }
mluis 7:b988b60083a1 643
mluis 0:45c4f0364ca4 644 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 7:b988b60083a1 645
mluis 0:45c4f0364ca4 646 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 647 {
mluis 0:45c4f0364ca4 648 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 649 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 650 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 651 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 652 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 653 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 654 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 655 RFLR_IRQFLAGS_CADDETECTED );
mluis 7:b988b60083a1 656
mluis 0:45c4f0364ca4 657 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 658 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 659 }
mluis 0:45c4f0364ca4 660 else
mluis 0:45c4f0364ca4 661 {
mluis 0:45c4f0364ca4 662 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 663 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 664 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 665 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 666 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 667 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 668 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 669 RFLR_IRQFLAGS_CADDETECTED );
mluis 7:b988b60083a1 670
mluis 0:45c4f0364ca4 671 // DIO0=RxDone
mluis 0:45c4f0364ca4 672 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 673 }
mluis 0:45c4f0364ca4 674 Write( REG_LR_FIFORXBASEADDR, 0 );
mluis 0:45c4f0364ca4 675 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 676 }
mluis 0:45c4f0364ca4 677 break;
mluis 0:45c4f0364ca4 678 }
mluis 0:45c4f0364ca4 679
mluis 7:b988b60083a1 680 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
mluis 0:45c4f0364ca4 681
mluis 0:45c4f0364ca4 682 this->settings.State = RF_RX_RUNNING;
mluis 0:45c4f0364ca4 683 if( timeout != 0 )
mluis 0:45c4f0364ca4 684 {
mluis 7:b988b60083a1 685 rxTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 );
mluis 0:45c4f0364ca4 686 }
mluis 0:45c4f0364ca4 687
mluis 0:45c4f0364ca4 688 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 689 {
mluis 0:45c4f0364ca4 690 SetOpMode( RF_OPMODE_RECEIVER );
mluis 7:b988b60083a1 691
mluis 0:45c4f0364ca4 692 if( rxContinuous == false )
mluis 0:45c4f0364ca4 693 {
mluis 7:b988b60083a1 694 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
mluis 7:b988b60083a1 695 this->settings.Fsk.RxSingleTimeout * 1e3 );
mluis 0:45c4f0364ca4 696 }
mluis 0:45c4f0364ca4 697 }
mluis 0:45c4f0364ca4 698 else
mluis 0:45c4f0364ca4 699 {
mluis 0:45c4f0364ca4 700 if( rxContinuous == true )
mluis 0:45c4f0364ca4 701 {
mluis 0:45c4f0364ca4 702 SetOpMode( RFLR_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 703 }
mluis 0:45c4f0364ca4 704 else
mluis 0:45c4f0364ca4 705 {
mluis 0:45c4f0364ca4 706 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
mluis 0:45c4f0364ca4 707 }
mluis 0:45c4f0364ca4 708 }
mluis 0:45c4f0364ca4 709 }
mluis 0:45c4f0364ca4 710
mluis 0:45c4f0364ca4 711 void SX1272::Tx( uint32_t timeout )
mluis 0:45c4f0364ca4 712 {
mluis 0:45c4f0364ca4 713
mluis 0:45c4f0364ca4 714 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 715 {
mluis 0:45c4f0364ca4 716 case MODEM_FSK:
mluis 0:45c4f0364ca4 717 {
mluis 0:45c4f0364ca4 718 // DIO0=PacketSent
mluis 7:b988b60083a1 719 // DIO1=FifoEmpty
mluis 0:45c4f0364ca4 720 // DIO2=FifoFull
mluis 0:45c4f0364ca4 721 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 722 // DIO4=LowBat
mluis 0:45c4f0364ca4 723 // DIO5=ModeReady
mluis 0:45c4f0364ca4 724 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 7:b988b60083a1 725 RF_DIOMAPPING1_DIO1_MASK &
mluis 7:b988b60083a1 726 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 7:b988b60083a1 727 RF_DIOMAPPING1_DIO1_01 );
mluis 0:45c4f0364ca4 728
mluis 0:45c4f0364ca4 729 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 730 RF_DIOMAPPING2_MAP_MASK ) );
mluis 0:45c4f0364ca4 731 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 732 }
mluis 0:45c4f0364ca4 733 break;
mluis 0:45c4f0364ca4 734 case MODEM_LORA:
mluis 0:45c4f0364ca4 735 {
mluis 0:45c4f0364ca4 736 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 737 {
mluis 0:45c4f0364ca4 738 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 739 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 740 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 741 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 742 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 743 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 744 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 745 RFLR_IRQFLAGS_CADDETECTED );
mluis 7:b988b60083a1 746
mluis 0:45c4f0364ca4 747 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 748 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 749 }
mluis 0:45c4f0364ca4 750 else
mluis 0:45c4f0364ca4 751 {
mluis 0:45c4f0364ca4 752 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 753 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 754 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 755 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 756 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 757 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 758 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 759 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 760
mluis 0:45c4f0364ca4 761 // DIO0=TxDone
mluis 0:45c4f0364ca4 762 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
mluis 0:45c4f0364ca4 763 }
mluis 0:45c4f0364ca4 764 }
mluis 0:45c4f0364ca4 765 break;
mluis 0:45c4f0364ca4 766 }
mluis 0:45c4f0364ca4 767
mluis 0:45c4f0364ca4 768 this->settings.State = RF_TX_RUNNING;
mluis 7:b988b60083a1 769 txTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 );
mluis 0:45c4f0364ca4 770 SetOpMode( RF_OPMODE_TRANSMITTER );
mluis 0:45c4f0364ca4 771 }
mluis 0:45c4f0364ca4 772
mluis 0:45c4f0364ca4 773 void SX1272::StartCad( void )
mluis 0:45c4f0364ca4 774 {
mluis 0:45c4f0364ca4 775 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 776 {
mluis 0:45c4f0364ca4 777 case MODEM_FSK:
mluis 0:45c4f0364ca4 778 {
mluis 7:b988b60083a1 779
mluis 0:45c4f0364ca4 780 }
mluis 0:45c4f0364ca4 781 break;
mluis 0:45c4f0364ca4 782 case MODEM_LORA:
mluis 0:45c4f0364ca4 783 {
mluis 0:45c4f0364ca4 784 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 785 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 786 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 787 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 788 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 789 //RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 790 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
mluis 7:b988b60083a1 791 //RFLR_IRQFLAGS_CADDETECTED
mluis 0:45c4f0364ca4 792 );
mluis 7:b988b60083a1 793
mluis 0:45c4f0364ca4 794 // DIO3=CADDone
mluis 7:b988b60083a1 795 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
mluis 7:b988b60083a1 796
mluis 0:45c4f0364ca4 797 this->settings.State = RF_CAD;
mluis 0:45c4f0364ca4 798 SetOpMode( RFLR_OPMODE_CAD );
mluis 0:45c4f0364ca4 799 }
mluis 0:45c4f0364ca4 800 break;
mluis 0:45c4f0364ca4 801 default:
mluis 0:45c4f0364ca4 802 break;
mluis 0:45c4f0364ca4 803 }
mluis 0:45c4f0364ca4 804 }
mluis 0:45c4f0364ca4 805
mluis 7:b988b60083a1 806 void SX1272::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
mluis 7:b988b60083a1 807 {
mluis 7:b988b60083a1 808 uint32_t timeout = ( uint32_t )( time * 1e6 );
mluis 7:b988b60083a1 809
mluis 7:b988b60083a1 810 SetChannel( freq );
mluis 7:b988b60083a1 811
mluis 7:b988b60083a1 812 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
mluis 7:b988b60083a1 813
mluis 7:b988b60083a1 814 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
mluis 7:b988b60083a1 815 // Disable radio interrupts
mluis 7:b988b60083a1 816 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
mluis 7:b988b60083a1 817 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
mluis 7:b988b60083a1 818
mluis 7:b988b60083a1 819 this->settings.State = RF_TX_RUNNING;
mluis 7:b988b60083a1 820 txTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout );
mluis 7:b988b60083a1 821 SetOpMode( RF_OPMODE_TRANSMITTER );
mluis 7:b988b60083a1 822 }
mluis 7:b988b60083a1 823
mluis 0:45c4f0364ca4 824 int16_t SX1272::GetRssi( RadioModems_t modem )
mluis 0:45c4f0364ca4 825 {
mluis 0:45c4f0364ca4 826 int16_t rssi = 0;
mluis 0:45c4f0364ca4 827
mluis 0:45c4f0364ca4 828 switch( modem )
mluis 0:45c4f0364ca4 829 {
mluis 0:45c4f0364ca4 830 case MODEM_FSK:
mluis 0:45c4f0364ca4 831 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 832 break;
mluis 0:45c4f0364ca4 833 case MODEM_LORA:
mluis 0:45c4f0364ca4 834 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
mluis 0:45c4f0364ca4 835 break;
mluis 0:45c4f0364ca4 836 default:
mluis 0:45c4f0364ca4 837 rssi = -1;
mluis 0:45c4f0364ca4 838 break;
mluis 0:45c4f0364ca4 839 }
mluis 0:45c4f0364ca4 840 return rssi;
mluis 0:45c4f0364ca4 841 }
mluis 0:45c4f0364ca4 842
mluis 0:45c4f0364ca4 843 void SX1272::SetOpMode( uint8_t opMode )
mluis 0:45c4f0364ca4 844 {
mluis 7:b988b60083a1 845 if( opMode == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 846 {
mluis 7:b988b60083a1 847 SetAntSwLowPower( true );
mluis 0:45c4f0364ca4 848 }
mluis 7:b988b60083a1 849 else
mluis 7:b988b60083a1 850 {
mluis 7:b988b60083a1 851 SetAntSwLowPower( false );
mluis 7:b988b60083a1 852 SetAntSw( opMode );
mluis 7:b988b60083a1 853 }
mluis 7:b988b60083a1 854 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
mluis 0:45c4f0364ca4 855 }
mluis 0:45c4f0364ca4 856
mluis 0:45c4f0364ca4 857 void SX1272::SetModem( RadioModems_t modem )
mluis 0:45c4f0364ca4 858 {
mluis 7:b988b60083a1 859 if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
mluis 7:b988b60083a1 860 {
mluis 7:b988b60083a1 861 this->settings.Modem = MODEM_LORA;
mluis 7:b988b60083a1 862 }
mluis 7:b988b60083a1 863 else
mluis 7:b988b60083a1 864 {
mluis 7:b988b60083a1 865 this->settings.Modem = MODEM_FSK;
mluis 7:b988b60083a1 866 }
mluis 7:b988b60083a1 867
mluis 0:45c4f0364ca4 868 if( this->settings.Modem == modem )
mluis 0:45c4f0364ca4 869 {
mluis 0:45c4f0364ca4 870 return;
mluis 0:45c4f0364ca4 871 }
mluis 0:45c4f0364ca4 872
mluis 0:45c4f0364ca4 873 this->settings.Modem = modem;
mluis 0:45c4f0364ca4 874 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 875 {
mluis 0:45c4f0364ca4 876 default:
mluis 0:45c4f0364ca4 877 case MODEM_FSK:
mluis 7:b988b60083a1 878 Sleep( );
mluis 0:45c4f0364ca4 879 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 7:b988b60083a1 880
mluis 0:45c4f0364ca4 881 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 882 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 0:45c4f0364ca4 883 break;
mluis 0:45c4f0364ca4 884 case MODEM_LORA:
mluis 7:b988b60083a1 885 Sleep( );
mluis 0:45c4f0364ca4 886 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 0:45c4f0364ca4 887
mluis 0:45c4f0364ca4 888 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 889 Write( REG_DIOMAPPING2, 0x00 );
mluis 0:45c4f0364ca4 890 break;
mluis 0:45c4f0364ca4 891 }
mluis 0:45c4f0364ca4 892 }
mluis 0:45c4f0364ca4 893
mluis 0:45c4f0364ca4 894 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 0:45c4f0364ca4 895 {
mluis 0:45c4f0364ca4 896 this->SetModem( modem );
mluis 0:45c4f0364ca4 897
mluis 0:45c4f0364ca4 898 switch( modem )
mluis 0:45c4f0364ca4 899 {
mluis 0:45c4f0364ca4 900 case MODEM_FSK:
mluis 0:45c4f0364ca4 901 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 902 {
mluis 0:45c4f0364ca4 903 this->Write( REG_PAYLOADLENGTH, max );
mluis 0:45c4f0364ca4 904 }
mluis 0:45c4f0364ca4 905 break;
mluis 0:45c4f0364ca4 906 case MODEM_LORA:
mluis 0:45c4f0364ca4 907 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 0:45c4f0364ca4 908 break;
mluis 0:45c4f0364ca4 909 }
mluis 0:45c4f0364ca4 910 }
mluis 0:45c4f0364ca4 911
mluis 7:b988b60083a1 912 void SX1272::SetPublicNetwork( bool enable )
mluis 7:b988b60083a1 913 {
mluis 7:b988b60083a1 914 SetModem( MODEM_LORA );
mluis 7:b988b60083a1 915 this->settings.LoRa.PublicNetwork = enable;
mluis 7:b988b60083a1 916 if( enable == true )
mluis 7:b988b60083a1 917 {
mluis 7:b988b60083a1 918 // Change LoRa modem SyncWord
mluis 7:b988b60083a1 919 Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
mluis 7:b988b60083a1 920 }
mluis 7:b988b60083a1 921 else
mluis 7:b988b60083a1 922 {
mluis 7:b988b60083a1 923 // Change LoRa modem SyncWord
mluis 7:b988b60083a1 924 Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
mluis 7:b988b60083a1 925 }
mluis 7:b988b60083a1 926 }
mluis 7:b988b60083a1 927
mluis 0:45c4f0364ca4 928 void SX1272::OnTimeoutIrq( void )
mluis 0:45c4f0364ca4 929 {
mluis 0:45c4f0364ca4 930 switch( this->settings.State )
mluis 0:45c4f0364ca4 931 {
mluis 0:45c4f0364ca4 932 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 933 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 934 {
mluis 0:45c4f0364ca4 935 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 936 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 937 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 938 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 939
mluis 0:45c4f0364ca4 940 // Clear Irqs
mluis 7:b988b60083a1 941 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 942 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 943 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 944 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 945
mluis 0:45c4f0364ca4 946 if( this->settings.Fsk.RxContinuous == true )
mluis 0:45c4f0364ca4 947 {
mluis 0:45c4f0364ca4 948 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 949 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 7:b988b60083a1 950 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
mluis 7:b988b60083a1 951 this->settings.Fsk.RxSingleTimeout * 1e3 );
mluis 0:45c4f0364ca4 952 }
mluis 0:45c4f0364ca4 953 else
mluis 0:45c4f0364ca4 954 {
mluis 0:45c4f0364ca4 955 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 956 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 957 }
mluis 0:45c4f0364ca4 958 }
mluis 0:45c4f0364ca4 959 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 960 {
mluis 0:45c4f0364ca4 961 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 962 }
mluis 0:45c4f0364ca4 963 break;
mluis 0:45c4f0364ca4 964 case RF_TX_RUNNING:
mluis 7:b988b60083a1 965 // Tx timeout shouldn't happen.
mluis 7:b988b60083a1 966 // But it has been observed that when it happens it is a result of a corrupted SPI transfer
mluis 7:b988b60083a1 967 // it depends on the platform design.
mluis 7:b988b60083a1 968 //
mluis 7:b988b60083a1 969 // The workaround is to put the radio in a known state. Thus, we re-initialize it.
mluis 7:b988b60083a1 970
mluis 7:b988b60083a1 971 // BEGIN WORKAROUND
mluis 7:b988b60083a1 972
mluis 7:b988b60083a1 973 // Reset the radio
mluis 7:b988b60083a1 974 Reset( );
mluis 7:b988b60083a1 975
mluis 7:b988b60083a1 976 // Initialize radio default values
mluis 7:b988b60083a1 977 SetOpMode( RF_OPMODE_SLEEP );
mluis 7:b988b60083a1 978
mluis 7:b988b60083a1 979 RadioRegistersInit( );
mluis 7:b988b60083a1 980
mluis 7:b988b60083a1 981 SetModem( MODEM_FSK );
mluis 7:b988b60083a1 982
mluis 7:b988b60083a1 983 // Restore previous network type setting.
mluis 7:b988b60083a1 984 SetPublicNetwork( this->settings.LoRa.PublicNetwork );
mluis 7:b988b60083a1 985 // END WORKAROUND
mluis 7:b988b60083a1 986
mluis 0:45c4f0364ca4 987 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 988 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
mluis 0:45c4f0364ca4 989 {
mluis 0:45c4f0364ca4 990 this->RadioEvents->TxTimeout( );
mluis 0:45c4f0364ca4 991 }
mluis 0:45c4f0364ca4 992 break;
mluis 0:45c4f0364ca4 993 default:
mluis 0:45c4f0364ca4 994 break;
mluis 0:45c4f0364ca4 995 }
mluis 0:45c4f0364ca4 996 }
mluis 0:45c4f0364ca4 997
mluis 0:45c4f0364ca4 998 void SX1272::OnDio0Irq( void )
mluis 0:45c4f0364ca4 999 {
mluis 0:45c4f0364ca4 1000 volatile uint8_t irqFlags = 0;
mluis 0:45c4f0364ca4 1001
mluis 0:45c4f0364ca4 1002 switch( this->settings.State )
mluis 7:b988b60083a1 1003 {
mluis 0:45c4f0364ca4 1004 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1005 //TimerStop( &RxTimeoutTimer );
mluis 0:45c4f0364ca4 1006 // RxDone interrupt
mluis 0:45c4f0364ca4 1007 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1008 {
mluis 0:45c4f0364ca4 1009 case MODEM_FSK:
mluis 0:45c4f0364ca4 1010 if( this->settings.Fsk.CrcOn == true )
mluis 0:45c4f0364ca4 1011 {
mluis 0:45c4f0364ca4 1012 irqFlags = Read( REG_IRQFLAGS2 );
mluis 0:45c4f0364ca4 1013 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
mluis 0:45c4f0364ca4 1014 {
mluis 0:45c4f0364ca4 1015 // Clear Irqs
mluis 7:b988b60083a1 1016 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1017 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1018 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1019 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 7:b988b60083a1 1020
mluis 7:b988b60083a1 1021 rxTimeoutTimer.detach( );
mluis 7:b988b60083a1 1022
mluis 0:45c4f0364ca4 1023 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1024 {
mluis 7:b988b60083a1 1025 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1026 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1027 }
mluis 0:45c4f0364ca4 1028 else
mluis 0:45c4f0364ca4 1029 {
mluis 0:45c4f0364ca4 1030 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1031 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 7:b988b60083a1 1032 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
mluis 7:b988b60083a1 1033 this->settings.Fsk.RxSingleTimeout * 1e3 );
mluis 0:45c4f0364ca4 1034 }
mluis 7:b988b60083a1 1035
mluis 0:45c4f0364ca4 1036 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1037 {
mluis 0:45c4f0364ca4 1038 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1039 }
mluis 0:45c4f0364ca4 1040 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1041 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1042 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1043 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1044 break;
mluis 0:45c4f0364ca4 1045 }
mluis 0:45c4f0364ca4 1046 }
mluis 0:45c4f0364ca4 1047
mluis 0:45c4f0364ca4 1048 // Read received packet size
mluis 0:45c4f0364ca4 1049 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1050 {
mluis 0:45c4f0364ca4 1051 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1052 {
mluis 0:45c4f0364ca4 1053 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1054 }
mluis 0:45c4f0364ca4 1055 else
mluis 0:45c4f0364ca4 1056 {
mluis 0:45c4f0364ca4 1057 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1058 }
mluis 7:b988b60083a1 1059 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1060 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1061 }
mluis 0:45c4f0364ca4 1062 else
mluis 0:45c4f0364ca4 1063 {
mluis 7:b988b60083a1 1064 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1065 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1066 }
mluis 0:45c4f0364ca4 1067
mluis 7:b988b60083a1 1068 rxTimeoutTimer.detach( );
mluis 7:b988b60083a1 1069
mluis 0:45c4f0364ca4 1070 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1071 {
mluis 0:45c4f0364ca4 1072 this->settings.State = RF_IDLE;
mluis 7:b988b60083a1 1073 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1074 }
mluis 0:45c4f0364ca4 1075 else
mluis 0:45c4f0364ca4 1076 {
mluis 0:45c4f0364ca4 1077 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1078 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 7:b988b60083a1 1079 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
mluis 7:b988b60083a1 1080 this->settings.Fsk.RxSingleTimeout * 1e3 );
mluis 0:45c4f0364ca4 1081 }
mluis 0:45c4f0364ca4 1082
mluis 0:45c4f0364ca4 1083 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1084 {
mluis 7:b988b60083a1 1085 this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 7:b988b60083a1 1086 }
mluis 0:45c4f0364ca4 1087 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1088 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1089 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1090 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1091 break;
mluis 0:45c4f0364ca4 1092 case MODEM_LORA:
mluis 0:45c4f0364ca4 1093 {
mluis 0:45c4f0364ca4 1094 int8_t snr = 0;
mluis 0:45c4f0364ca4 1095
mluis 0:45c4f0364ca4 1096 // Clear Irq
mluis 0:45c4f0364ca4 1097 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
mluis 0:45c4f0364ca4 1098
mluis 0:45c4f0364ca4 1099 irqFlags = Read( REG_LR_IRQFLAGS );
mluis 0:45c4f0364ca4 1100 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
mluis 0:45c4f0364ca4 1101 {
mluis 0:45c4f0364ca4 1102 // Clear Irq
mluis 0:45c4f0364ca4 1103 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
mluis 0:45c4f0364ca4 1104
mluis 0:45c4f0364ca4 1105 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1106 {
mluis 0:45c4f0364ca4 1107 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1108 }
mluis 0:45c4f0364ca4 1109 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1110
mluis 0:45c4f0364ca4 1111 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1112 {
mluis 0:45c4f0364ca4 1113 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1114 }
mluis 0:45c4f0364ca4 1115 break;
mluis 0:45c4f0364ca4 1116 }
mluis 0:45c4f0364ca4 1117
mluis 0:45c4f0364ca4 1118 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
mluis 0:45c4f0364ca4 1119 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
mluis 0:45c4f0364ca4 1120 {
mluis 0:45c4f0364ca4 1121 // Invert and divide by 4
mluis 0:45c4f0364ca4 1122 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1123 snr = -snr;
mluis 0:45c4f0364ca4 1124 }
mluis 0:45c4f0364ca4 1125 else
mluis 0:45c4f0364ca4 1126 {
mluis 0:45c4f0364ca4 1127 // Divide by 4
mluis 0:45c4f0364ca4 1128 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1129 }
mluis 0:45c4f0364ca4 1130
mluis 0:45c4f0364ca4 1131 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 0:45c4f0364ca4 1132 if( snr < 0 )
mluis 0:45c4f0364ca4 1133 {
mluis 0:45c4f0364ca4 1134 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
mluis 0:45c4f0364ca4 1135 snr;
mluis 0:45c4f0364ca4 1136 }
mluis 0:45c4f0364ca4 1137 else
mluis 7:b988b60083a1 1138 {
mluis 0:45c4f0364ca4 1139 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
mluis 0:45c4f0364ca4 1140 }
mluis 0:45c4f0364ca4 1141
mluis 0:45c4f0364ca4 1142 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
mluis 7:b988b60083a1 1143 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 7:b988b60083a1 1144
mluis 0:45c4f0364ca4 1145 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1146 {
mluis 0:45c4f0364ca4 1147 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1148 }
mluis 0:45c4f0364ca4 1149 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1150
mluis 0:45c4f0364ca4 1151 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1152 {
mluis 7:b988b60083a1 1153 this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
mluis 0:45c4f0364ca4 1154 }
mluis 0:45c4f0364ca4 1155 }
mluis 0:45c4f0364ca4 1156 break;
mluis 0:45c4f0364ca4 1157 default:
mluis 0:45c4f0364ca4 1158 break;
mluis 0:45c4f0364ca4 1159 }
mluis 0:45c4f0364ca4 1160 break;
mluis 0:45c4f0364ca4 1161 case RF_TX_RUNNING:
mluis 7:b988b60083a1 1162 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1163 // TxDone interrupt
mluis 0:45c4f0364ca4 1164 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1165 {
mluis 0:45c4f0364ca4 1166 case MODEM_LORA:
mluis 0:45c4f0364ca4 1167 // Clear Irq
mluis 0:45c4f0364ca4 1168 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
mluis 0:45c4f0364ca4 1169 // Intentional fall through
mluis 0:45c4f0364ca4 1170 case MODEM_FSK:
mluis 0:45c4f0364ca4 1171 default:
mluis 0:45c4f0364ca4 1172 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1173 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
mluis 0:45c4f0364ca4 1174 {
mluis 0:45c4f0364ca4 1175 this->RadioEvents->TxDone( );
mluis 7:b988b60083a1 1176 }
mluis 0:45c4f0364ca4 1177 break;
mluis 0:45c4f0364ca4 1178 }
mluis 0:45c4f0364ca4 1179 break;
mluis 0:45c4f0364ca4 1180 default:
mluis 0:45c4f0364ca4 1181 break;
mluis 0:45c4f0364ca4 1182 }
mluis 0:45c4f0364ca4 1183 }
mluis 0:45c4f0364ca4 1184
mluis 0:45c4f0364ca4 1185 void SX1272::OnDio1Irq( void )
mluis 0:45c4f0364ca4 1186 {
mluis 0:45c4f0364ca4 1187 switch( this->settings.State )
mluis 7:b988b60083a1 1188 {
mluis 0:45c4f0364ca4 1189 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1190 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1191 {
mluis 0:45c4f0364ca4 1192 case MODEM_FSK:
mluis 0:45c4f0364ca4 1193 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1194 // Read received packet size
mluis 0:45c4f0364ca4 1195 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1196 {
mluis 0:45c4f0364ca4 1197 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1198 {
mluis 0:45c4f0364ca4 1199 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1200 }
mluis 0:45c4f0364ca4 1201 else
mluis 0:45c4f0364ca4 1202 {
mluis 0:45c4f0364ca4 1203 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1204 }
mluis 0:45c4f0364ca4 1205 }
mluis 0:45c4f0364ca4 1206
mluis 0:45c4f0364ca4 1207 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
mluis 0:45c4f0364ca4 1208 {
mluis 7:b988b60083a1 1209 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
mluis 0:45c4f0364ca4 1210 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
mluis 0:45c4f0364ca4 1211 }
mluis 0:45c4f0364ca4 1212 else
mluis 0:45c4f0364ca4 1213 {
mluis 7:b988b60083a1 1214 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1215 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1216 }
mluis 0:45c4f0364ca4 1217 break;
mluis 0:45c4f0364ca4 1218 case MODEM_LORA:
mluis 0:45c4f0364ca4 1219 // Sync time out
mluis 0:45c4f0364ca4 1220 rxTimeoutTimer.detach( );
mluis 7:b988b60083a1 1221 // Clear Irq
mluis 7:b988b60083a1 1222 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
mluis 7:b988b60083a1 1223
mluis 0:45c4f0364ca4 1224 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1225 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1226 {
mluis 0:45c4f0364ca4 1227 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1228 }
mluis 0:45c4f0364ca4 1229 break;
mluis 0:45c4f0364ca4 1230 default:
mluis 0:45c4f0364ca4 1231 break;
mluis 0:45c4f0364ca4 1232 }
mluis 0:45c4f0364ca4 1233 break;
mluis 0:45c4f0364ca4 1234 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1235 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1236 {
mluis 0:45c4f0364ca4 1237 case MODEM_FSK:
mluis 7:b988b60083a1 1238 // FifoEmpty interrupt
mluis 0:45c4f0364ca4 1239 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
mluis 0:45c4f0364ca4 1240 {
mluis 7:b988b60083a1 1241 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 1242 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 1243 }
mluis 7:b988b60083a1 1244 else
mluis 0:45c4f0364ca4 1245 {
mluis 0:45c4f0364ca4 1246 // Write the last chunk of data
mluis 7:b988b60083a1 1247 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1248 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
mluis 0:45c4f0364ca4 1249 }
mluis 0:45c4f0364ca4 1250 break;
mluis 0:45c4f0364ca4 1251 case MODEM_LORA:
mluis 0:45c4f0364ca4 1252 break;
mluis 0:45c4f0364ca4 1253 default:
mluis 0:45c4f0364ca4 1254 break;
mluis 0:45c4f0364ca4 1255 }
mluis 0:45c4f0364ca4 1256 break;
mluis 0:45c4f0364ca4 1257 default:
mluis 0:45c4f0364ca4 1258 break;
mluis 0:45c4f0364ca4 1259 }
mluis 0:45c4f0364ca4 1260 }
mluis 0:45c4f0364ca4 1261
mluis 0:45c4f0364ca4 1262 void SX1272::OnDio2Irq( void )
mluis 0:45c4f0364ca4 1263 {
mluis 0:45c4f0364ca4 1264 switch( this->settings.State )
mluis 7:b988b60083a1 1265 {
mluis 0:45c4f0364ca4 1266 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1267 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1268 {
mluis 0:45c4f0364ca4 1269 case MODEM_FSK:
mluis 7:b988b60083a1 1270 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
mluis 7:b988b60083a1 1271 if( this->dioIrq[4] == NULL )
mluis 7:b988b60083a1 1272 {
mluis 7:b988b60083a1 1273 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 7:b988b60083a1 1274 }
mluis 7:b988b60083a1 1275
mluis 0:45c4f0364ca4 1276 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
mluis 0:45c4f0364ca4 1277 {
mluis 0:45c4f0364ca4 1278 rxTimeoutSyncWord.detach( );
mluis 7:b988b60083a1 1279
mluis 0:45c4f0364ca4 1280 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 7:b988b60083a1 1281
mluis 0:45c4f0364ca4 1282 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 1283
mluis 0:45c4f0364ca4 1284 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
mluis 0:45c4f0364ca4 1285 ( uint16_t )Read( REG_AFCLSB ) ) *
mluis 0:45c4f0364ca4 1286 ( double )FREQ_STEP;
mluis 0:45c4f0364ca4 1287 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
mluis 0:45c4f0364ca4 1288 }
mluis 0:45c4f0364ca4 1289 break;
mluis 0:45c4f0364ca4 1290 case MODEM_LORA:
mluis 0:45c4f0364ca4 1291 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1292 {
mluis 0:45c4f0364ca4 1293 // Clear Irq
mluis 0:45c4f0364ca4 1294 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 7:b988b60083a1 1295
mluis 0:45c4f0364ca4 1296 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1297 {
mluis 0:45c4f0364ca4 1298 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1299 }
mluis 0:45c4f0364ca4 1300 }
mluis 0:45c4f0364ca4 1301 break;
mluis 0:45c4f0364ca4 1302 default:
mluis 0:45c4f0364ca4 1303 break;
mluis 0:45c4f0364ca4 1304 }
mluis 0:45c4f0364ca4 1305 break;
mluis 0:45c4f0364ca4 1306 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1307 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1308 {
mluis 0:45c4f0364ca4 1309 case MODEM_FSK:
mluis 0:45c4f0364ca4 1310 break;
mluis 0:45c4f0364ca4 1311 case MODEM_LORA:
mluis 0:45c4f0364ca4 1312 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1313 {
mluis 0:45c4f0364ca4 1314 // Clear Irq
mluis 0:45c4f0364ca4 1315 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 7:b988b60083a1 1316
mluis 0:45c4f0364ca4 1317 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1318 {
mluis 0:45c4f0364ca4 1319 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1320 }
mluis 0:45c4f0364ca4 1321 }
mluis 0:45c4f0364ca4 1322 break;
mluis 0:45c4f0364ca4 1323 default:
mluis 0:45c4f0364ca4 1324 break;
mluis 0:45c4f0364ca4 1325 }
mluis 0:45c4f0364ca4 1326 break;
mluis 0:45c4f0364ca4 1327 default:
mluis 0:45c4f0364ca4 1328 break;
mluis 0:45c4f0364ca4 1329 }
mluis 0:45c4f0364ca4 1330 }
mluis 0:45c4f0364ca4 1331
mluis 0:45c4f0364ca4 1332 void SX1272::OnDio3Irq( void )
mluis 0:45c4f0364ca4 1333 {
mluis 0:45c4f0364ca4 1334 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1335 {
mluis 0:45c4f0364ca4 1336 case MODEM_FSK:
mluis 0:45c4f0364ca4 1337 break;
mluis 0:45c4f0364ca4 1338 case MODEM_LORA:
mluis 0:45c4f0364ca4 1339 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 0:45c4f0364ca4 1340 {
mluis 0:45c4f0364ca4 1341 // Clear Irq
mluis 0:45c4f0364ca4 1342 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1343 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1344 {
mluis 0:45c4f0364ca4 1345 this->RadioEvents->CadDone( true );
mluis 0:45c4f0364ca4 1346 }
mluis 0:45c4f0364ca4 1347 }
mluis 0:45c4f0364ca4 1348 else
mluis 7:b988b60083a1 1349 {
mluis 0:45c4f0364ca4 1350 // Clear Irq
mluis 0:45c4f0364ca4 1351 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1352 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1353 {
mluis 0:45c4f0364ca4 1354 this->RadioEvents->CadDone( false );
mluis 0:45c4f0364ca4 1355 }
mluis 0:45c4f0364ca4 1356 }
mluis 0:45c4f0364ca4 1357 break;
mluis 0:45c4f0364ca4 1358 default:
mluis 0:45c4f0364ca4 1359 break;
mluis 0:45c4f0364ca4 1360 }
mluis 0:45c4f0364ca4 1361 }
mluis 0:45c4f0364ca4 1362
mluis 0:45c4f0364ca4 1363 void SX1272::OnDio4Irq( void )
mluis 0:45c4f0364ca4 1364 {
mluis 0:45c4f0364ca4 1365 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1366 {
mluis 0:45c4f0364ca4 1367 case MODEM_FSK:
mluis 0:45c4f0364ca4 1368 {
mluis 0:45c4f0364ca4 1369 if( this->settings.FskPacketHandler.PreambleDetected == false )
mluis 0:45c4f0364ca4 1370 {
mluis 0:45c4f0364ca4 1371 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 7:b988b60083a1 1372 }
mluis 0:45c4f0364ca4 1373 }
mluis 0:45c4f0364ca4 1374 break;
mluis 0:45c4f0364ca4 1375 case MODEM_LORA:
mluis 0:45c4f0364ca4 1376 break;
mluis 0:45c4f0364ca4 1377 default:
mluis 0:45c4f0364ca4 1378 break;
mluis 0:45c4f0364ca4 1379 }
mluis 0:45c4f0364ca4 1380 }
mluis 0:45c4f0364ca4 1381
mluis 0:45c4f0364ca4 1382 void SX1272::OnDio5Irq( void )
mluis 0:45c4f0364ca4 1383 {
mluis 0:45c4f0364ca4 1384 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1385 {
mluis 0:45c4f0364ca4 1386 case MODEM_FSK:
mluis 0:45c4f0364ca4 1387 break;
mluis 0:45c4f0364ca4 1388 case MODEM_LORA:
mluis 0:45c4f0364ca4 1389 break;
mluis 0:45c4f0364ca4 1390 default:
mluis 0:45c4f0364ca4 1391 break;
mluis 0:45c4f0364ca4 1392 }
mluis 0:45c4f0364ca4 1393 }