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MRF24J40.cpp
00001 /* mbed MRF24J40 (IEEE 802.15.4 tranceiver) Library 00002 * Copyright (c) 2011 Jeroen Hilgers 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a copy 00005 * of this software and associated documentation files (the "Software"), to deal 00006 * in the Software without restriction, including without limitation the rights 00007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 00008 * copies of the Software, and to permit persons to whom the Software is 00009 * furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included in 00012 * all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 00015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 00016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 00017 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 00018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 00019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 00020 * THE SOFTWARE. 00021 */ 00022 00023 #include "MRF24J40.h" 00024 00025 // MRF20J40 Short address control register mapping. 00026 #define RXMCR 0x00 00027 #define PANIDL 0x01 00028 #define PANIDH 0x02 00029 #define SADRL 0x03 00030 #define SADRH 0x04 00031 #define EADR0 0x05 00032 #define EADR1 0x06 00033 #define EADR2 0x07 00034 #define EADR3 0x08 00035 #define EADR4 0x09 00036 #define EADR5 0x0a 00037 #define EADR6 0x0b 00038 #define EADR7 0x0c 00039 #define RXFLUSH 0x0d 00040 00041 #define TXNMTRIG 0x1b 00042 #define TXSR 0x24 00043 00044 #define ISRSTS 0x31 00045 #define INTMSK 0x32 00046 #define GPIO 0x33 00047 #define TRISGPIO 0x34 00048 00049 #define RFCTL 0x36 00050 00051 #define BBREG2 0x3A 00052 00053 #define BBREG6 0x3E 00054 #define RSSITHCCA 0x3F 00055 00056 // MRF20J40 Long address control register mapping. 00057 #define RFCTRL0 0x200 00058 00059 #define RFCTRL2 0x202 00060 #define RFCTRL3 0x203 00061 00062 #define RFCTRL6 0x206 00063 #define RFCTRL7 0x207 00064 #define RFCTRL8 0x208 00065 00066 #define CLKINTCR 0x211 00067 #define CLCCTRL 0x220 00068 00069 MRF24J40::MRF24J40(PinName mosi, PinName miso, PinName sck, PinName cs, PinName reset) ://, PinName irq, PinName wake) : 00070 mSpi(mosi, miso, sck), // mosi, miso, sclk 00071 mCs(cs), 00072 mReset(reset) 00073 // mIrq(irq), 00074 // mWake(wake) 00075 { 00076 mSpi.format(8, 0); // 8 bits, cpol=0; cpha=0 00077 mSpi.frequency(500000); 00078 Reset(); 00079 } 00080 00081 /* 00082 void MRF24J40::DebugDump(Serial &ser) 00083 { 00084 ser.printf("MRF24J40 registers:\r"); 00085 ser.printf("RXMCR=0x%X\r", MrfReadShort(RXMCR)); 00086 ser.printf("RXFLUSH=0x%X\r", MrfReadShort(RXFLUSH)); 00087 ser.printf("TXNMTRIG=0x%X\r", MrfReadShort(TXNMTRIG)); 00088 ser.printf("TXSR=0x%X\r", MrfReadShort(TXSR)); 00089 ser.printf("ISRSTS=0x%X\r", MrfReadShort(ISRSTS)); 00090 ser.printf("INTMSK=0x%X\r", MrfReadShort(INTMSK)); 00091 ser.printf("GPIO=0x%X\r", MrfReadShort(GPIO)); 00092 ser.printf("TRISGPIO=0x%X\r", MrfReadShort(TRISGPIO)); 00093 ser.printf("RFCTL=0x%X\r", MrfReadShort(RFCTL)); 00094 ser.printf("BBREG2=0x%X\r", MrfReadShort(BBREG2)); 00095 ser.printf("BBREG6=0x%X\r", MrfReadShort(BBREG6)); 00096 ser.printf("RSSITHCCA=0x%X\r", MrfReadShort(RSSITHCCA)); 00097 00098 00099 ser.printf("RFCTRL0=0x%X\r", MrfReadLong(RFCTRL0)); 00100 ser.printf("RFCTRL2=0x%X\r", MrfReadLong(RFCTRL2)); 00101 ser.printf("RFCTRL3=0x%X\r", MrfReadLong(RFCTRL3)); 00102 ser.printf("RFCTRL6=0x%X\r", MrfReadLong(RFCTRL6)); 00103 ser.printf("RFCTRL7=0x%X\r", MrfReadLong(RFCTRL7)); 00104 ser.printf("RFCTRL8=0x%X\r", MrfReadLong(RFCTRL8)); 00105 ser.printf("CLKINTCR=0x%X\r", MrfReadLong(CLKINTCR)); 00106 ser.printf("CLCCTRL=0x%X\r", MrfReadLong(CLCCTRL)); 00107 ser.printf("\r"); 00108 } 00109 */ 00110 00111 void MRF24J40::Reset(void) 00112 { 00113 mCs = 1; 00114 // Pulse hardware reset. 00115 mReset = 0; 00116 wait_us(100); 00117 mReset = 1; 00118 wait_us(100); 00119 00120 // Reset RF module. 00121 WriteShort(RFCTL, 0x04); 00122 WriteShort(RFCTL, 0x00); 00123 00124 WriteShort(RFCTL, 0x00); 00125 00126 WriteShort(PANIDL, 0xAA); 00127 WriteShort(PANIDH, 0xAA); 00128 WriteShort(SADRL, 0xAA); 00129 WriteShort(SADRH, 0xAA); 00130 00131 // Flush RX fifo. 00132 WriteShort(RXFLUSH, 0x01); 00133 00134 // Write MAC addresses here. We don't care. 00135 00136 WriteLong(RFCTRL2, 0x80); // Enable RF PLL. 00137 00138 WriteLong(RFCTRL3, 0x00); // Full power. 00139 WriteLong(RFCTRL6, 0x80); // Enable TX filter (recommended) 00140 WriteLong(RFCTRL8, 0x10); // Enhanced VCO (recommended) 00141 00142 WriteShort(BBREG2,0x78); // Clear Channel Assesment use carrier sense. 00143 WriteShort(BBREG6,0x40); // Calculate RSSI for Rx packet. 00144 WriteShort(RSSITHCCA,0x00);// RSSI threshold for CCA. 00145 00146 WriteLong(RFCTRL0, 0x00); // Channel 11. 00147 00148 WriteShort(RXMCR, 0x01); // Don't check address upon reception. 00149 // MrfWriteShort(RXMCR, 0x00); // Check address upon reception. 00150 00151 // Reset RF module with new settings. 00152 WriteShort(RFCTL, 0x04); 00153 WriteShort(RFCTL, 0x00); 00154 } 00155 00156 void MRF24J40::Send(uint8_t *data, uint8_t length) 00157 { 00158 uint8_t i; 00159 00160 WriteLong(0x000, 0); // No addresses in header. 00161 WriteLong(0x001, length); // 11 bytes 00162 for(i=0; i<length; i++) 00163 WriteLong(0x002+i, data[i]); 00164 00165 WriteShort(TXNMTRIG, 0x01); 00166 } 00167 00168 uint8_t MRF24J40::Receive(uint8_t *data, uint8_t maxLength) 00169 { 00170 uint8_t i, length; 00171 uint8_t lqi, rssi; 00172 00173 if(ReadShort(ISRSTS)& 0x08) 00174 { 00175 length = ReadLong(0x300); 00176 lqi = ReadLong(0x301 + length); 00177 rssi = ReadLong(0x302 + length); 00178 for(i=0; i<length; i++) 00179 if(i<maxLength) 00180 *data++ = ReadLong(0x301 + (uint16_t)i); 00181 else 00182 ReadLong(0x301 + (uint16_t)i); 00183 if(length < maxLength) 00184 return length; 00185 } 00186 return 0; 00187 } 00188 00189 uint8_t MRF24J40::ReadShort (uint8_t address) 00190 { 00191 uint8_t value; 00192 mCs = 0; 00193 wait_us(1); 00194 mSpi.write((address<<1) & 0x7E); 00195 wait_us(1); 00196 value = mSpi.write(0xFF); 00197 wait_us(1); 00198 mCs = 1; 00199 wait_us(1); 00200 return value; 00201 } 00202 00203 void MRF24J40::WriteShort (uint8_t address, uint8_t data) 00204 { 00205 mCs = 0; 00206 wait_us(1); 00207 mSpi.write(((address<<1) & 0x7E) | 0x01); 00208 wait_us(1); 00209 mSpi.write(data); 00210 wait_us(1); 00211 mCs = 1; 00212 wait_us(1); 00213 } 00214 00215 uint8_t MRF24J40::ReadLong (uint16_t address) 00216 { 00217 uint8_t value; 00218 mCs = 0; 00219 wait_us(1); 00220 mSpi.write((address>>3) | 0x80); 00221 wait_us(1); 00222 mSpi.write((address<<5) & 0xE0); 00223 wait_us(1); 00224 value = mSpi.write(0xFF); 00225 wait_us(1); 00226 mCs = 1; 00227 wait_us(1); 00228 return value; 00229 } 00230 00231 void MRF24J40::WriteLong (uint16_t address, uint8_t data) 00232 { 00233 mCs = 0; 00234 wait_us(1); 00235 mSpi.write((address>>3) | 0x80); 00236 wait_us(1); 00237 mSpi.write(((address<<5) & 0xE0) | 0x10); 00238 wait_us(1); 00239 mSpi.write(data); 00240 wait_us(1); 00241 mCs = 1; 00242 wait_us(1); 00243 } 00244 00245 void MRF24J40::SetChannel(uint8_t channel) 00246 { 00247 WriteLong(RFCTRL0, (channel & 0x0F)<<4 | 0x03); // Set channel, leave RFOPT bits at recommended 00248 00249 //Reset the board by first writing a 4 to RFCTL, then writing a 0 00250 WriteShort(RFCTL, 0x04); 00251 WriteShort(RFCTL, 0x00); 00252 wait(0.5); 00253 }
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