fds
nRF24L01P.h@1:c41959327807, 2019-12-09 (annotated)
- Committer:
- Ucial
- Date:
- Mon Dec 09 06:23:05 2019 +0000
- Revision:
- 1:c41959327807
- Parent:
- 0:4caead137300
- Child:
- 2:6c547cdb94e6
library changed
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Ucial | 0:4caead137300 | 1 | #ifndef __NRF24L01P_H__ |
Ucial | 0:4caead137300 | 2 | #define __NRF24L01P_H__ |
Ucial | 0:4caead137300 | 3 | |
Ucial | 0:4caead137300 | 4 | #include "mbed.h" |
Ucial | 0:4caead137300 | 5 | |
Ucial | 0:4caead137300 | 6 | #define TX 1 |
Ucial | 0:4caead137300 | 7 | #define RX 2 |
Ucial | 0:4caead137300 | 8 | |
Ucial | 0:4caead137300 | 9 | #define RX_DR 6 |
Ucial | 0:4caead137300 | 10 | #define TX_DS 5 |
Ucial | 0:4caead137300 | 11 | #define MAX_RT 4 |
Ucial | 0:4caead137300 | 12 | #define TX_FULL 0 |
Ucial | 0:4caead137300 | 13 | |
Ucial | 0:4caead137300 | 14 | |
Ucial | 0:4caead137300 | 15 | #define NRF_READ_REG 0x00 // ¶Á¼Ä´æÆ÷Ö¸Áî |
Ucial | 0:4caead137300 | 16 | #define NRF_WRITE_REG 0x20 // д¼Ä´æÆ÷Ö¸Áî |
Ucial | 0:4caead137300 | 17 | #define ACTIVATE 0x50 // follow with 0x73 to activate feature register |
Ucial | 0:4caead137300 | 18 | #define R_RX_PL_WID 0x60 // ¶Á½ÓÊÕ»º³åÇøµÄ³¤¶È |
Ucial | 0:4caead137300 | 19 | #define RD_RX_PLOAD 0x61 // ¶ÁÈ¡½ÓÊÕÊý¾ÝÖ¸Áî |
Ucial | 0:4caead137300 | 20 | #define WR_TX_PLOAD 0xA0 // д´ý·¢Êý¾ÝÖ¸Áî |
Ucial | 0:4caead137300 | 21 | #define W_ACK_PAYLOAD 0xA8 // Used in RX mode. |
Ucial | 0:4caead137300 | 22 | #define FLUSH_TX 0xE1 // ³åÏ´·¢ËÍ FIFOÖ¸Áî |
Ucial | 0:4caead137300 | 23 | #define FLUSH_RX 0xE2 // ³åÏ´½ÓÊÕ FIFOÖ¸Áî |
Ucial | 0:4caead137300 | 24 | #define REUSE_TX_PL 0xE3 // ¶¨ÒåÖظ´×°ÔØÊý¾ÝÖ¸Áî |
Ucial | 0:4caead137300 | 25 | #define NOP 0xFF // ±£Áô |
Ucial | 0:4caead137300 | 26 | |
Ucial | 0:4caead137300 | 27 | #define CONFIG 0x00 // ÅäÖÃÊÕ·¢×´Ì¬£¬CRCУÑéģʽÒÔ¼°ÊÕ·¢×´Ì¬ÏìÓ¦·½Ê½ |
Ucial | 0:4caead137300 | 28 | #define EN_AA 0x01 // ×Ô¶¯Ó¦´ð¹¦ÄÜÉèÖà |
Ucial | 0:4caead137300 | 29 | #define EN_RXADDR 0x02 // ¿ÉÓÃÐŵÀÉèÖà |
Ucial | 0:4caead137300 | 30 | #define SETUP_AW 0x03 // ÊÕ·¢µØÖ·¿í¶ÈÉèÖà |
Ucial | 0:4caead137300 | 31 | #define SETUP_RETR 0x04 // ×Ô¶¯ÖØ·¢¹¦ÄÜÉèÖà |
Ucial | 0:4caead137300 | 32 | #define RF_CH 0x05 // ¹¤×÷ƵÂÊÉèÖà |
Ucial | 0:4caead137300 | 33 | #define RF_SETUP 0x06 // ·¢ÉäËÙÂÊ¡¢¹¦ºÄ¹¦ÄÜÉèÖà |
Ucial | 0:4caead137300 | 34 | #define NRFRegSTATUS 0x07 // ״̬¼Ä´æÆ÷ |
Ucial | 0:4caead137300 | 35 | #define OBSERVE_TX 0x08 // ·¢Ëͼà²â¹¦ÄÜ |
Ucial | 0:4caead137300 | 36 | #define CD 0x09 // µØÖ·¼ì²â |
Ucial | 0:4caead137300 | 37 | #define RX_ADDR_P0 0x0A // ƵµÀ0½ÓÊÕÊý¾ÝµØÖ· |
Ucial | 0:4caead137300 | 38 | #define RX_ADDR_P1 0x0B // ƵµÀ1½ÓÊÕÊý¾ÝµØÖ· |
Ucial | 0:4caead137300 | 39 | #define RX_ADDR_P2 0x0C // ƵµÀ2½ÓÊÕÊý¾ÝµØÖ· |
Ucial | 0:4caead137300 | 40 | #define RX_ADDR_P3 0x0D // ƵµÀ3½ÓÊÕÊý¾ÝµØÖ· |
Ucial | 0:4caead137300 | 41 | #define RX_ADDR_P4 0x0E // ƵµÀ4½ÓÊÕÊý¾ÝµØÖ· |
Ucial | 0:4caead137300 | 42 | #define RX_ADDR_P5 0x0F // ƵµÀ5½ÓÊÕÊý¾ÝµØÖ· |
Ucial | 0:4caead137300 | 43 | #define TX_ADDR 0x10 // ·¢Ë͵ØÖ·¼Ä´æÆ÷ |
Ucial | 0:4caead137300 | 44 | #define RX_PW_P0 0x11 // ½ÓÊÕƵµÀ0½ÓÊÕÊý¾Ý³¤¶È |
Ucial | 0:4caead137300 | 45 | #define RX_PW_P1 0x12 // ½ÓÊÕƵµÀ1½ÓÊÕÊý¾Ý³¤¶È |
Ucial | 0:4caead137300 | 46 | #define RX_PW_P2 0x13 // ½ÓÊÕƵµÀ2½ÓÊÕÊý¾Ý³¤¶È |
Ucial | 0:4caead137300 | 47 | #define RX_PW_P3 0x14 // ½ÓÊÕƵµÀ3½ÓÊÕÊý¾Ý³¤¶È |
Ucial | 0:4caead137300 | 48 | #define RX_PW_P4 0x15 // ½ÓÊÕƵµÀ4½ÓÊÕÊý¾Ý³¤¶È |
Ucial | 0:4caead137300 | 49 | #define RX_PW_P5 0x16 // ½ÓÊÕƵµÀ5½ÓÊÕÊý¾Ý³¤¶È |
Ucial | 0:4caead137300 | 50 | #define FIFO_STATUS 0x17 // FIFOÕ»ÈëÕ»³ö״̬¼Ä´æÆ÷ÉèÖà |
Ucial | 0:4caead137300 | 51 | |
Ucial | 0:4caead137300 | 52 | #define DYNPD 0x1C // per pipe DPL control |
Ucial | 0:4caead137300 | 53 | #define FEATURE 0x1D // ¡°Feature¡± register address |
Ucial | 1:c41959327807 | 54 | |
Ucial | 1:c41959327807 | 55 | |
Ucial | 1:c41959327807 | 56 | |
Ucial | 0:4caead137300 | 57 | extern uint8_t NRF24L01_RXDATA[32]; |
Ucial | 0:4caead137300 | 58 | extern uint8_t NRF24L01_TXDATA[32]; |
Ucial | 0:4caead137300 | 59 | |
Ucial | 0:4caead137300 | 60 | class nRF24L01P { |
Ucial | 0:4caead137300 | 61 | |
Ucial | 0:4caead137300 | 62 | public: |
Ucial | 0:4caead137300 | 63 | |
Ucial | 0:4caead137300 | 64 | nRF24L01P(PinName mosi, PinName miso, PinName sck, PinName csn, PinName ce, PinName irq = NC); |
Ucial | 0:4caead137300 | 65 | |
Ucial | 0:4caead137300 | 66 | |
Ucial | 1:c41959327807 | 67 | |
Ucial | 0:4caead137300 | 68 | uint8_t NRF_Read_Reg(uint8_t reg); |
Ucial | 0:4caead137300 | 69 | uint8_t NRF_Write_Reg(uint8_t reg, uint8_t value); |
Ucial | 0:4caead137300 | 70 | uint8_t NRF_Read_Buff(uint8_t reg, uint8_t *pBuf, uint8_t uchars); |
Ucial | 0:4caead137300 | 71 | uint8_t NRF_Write_Buf(uint8_t reg, uint8_t *pBuf, uint8_t uchars); |
Ucial | 1:c41959327807 | 72 | |
Ucial | 0:4caead137300 | 73 | void NRF24L01_Set_TX(void); |
Ucial | 0:4caead137300 | 74 | void NRF24L01_Set_RX(void); |
Ucial | 0:4caead137300 | 75 | |
Ucial | 0:4caead137300 | 76 | void NRF24L01_Check(void); |
Ucial | 0:4caead137300 | 77 | void NRF24L01_Init(uint8_t Chanal,uint8_t Mode); |
Ucial | 1:c41959327807 | 78 | void NRF_Send_TX(uint8_t * tx_buf, uint8_t len); |
Ucial | 0:4caead137300 | 79 | void NRF24L01_IRQ(void); |
Ucial | 0:4caead137300 | 80 | |
Ucial | 1:c41959327807 | 81 | |
Ucial | 1:c41959327807 | 82 | void Nrf_Connect(void); |
Ucial | 1:c41959327807 | 83 | |
Ucial | 0:4caead137300 | 84 | SPI spi_; |
Ucial | 0:4caead137300 | 85 | DigitalOut nCS_; |
Ucial | 0:4caead137300 | 86 | DigitalOut ce_; |
Ucial | 0:4caead137300 | 87 | DigitalOut check_led; |
Ucial | 0:4caead137300 | 88 | InterruptIn nIRQ_; |
Ucial | 0:4caead137300 | 89 | }; |
Ucial | 0:4caead137300 | 90 | |
Ucial | 0:4caead137300 | 91 | #endif |