cebri alyac / mbed-rtos

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Dependents:   Asservissement_Gyro

rtx/TARGET_ARM7/HAL_CM.c@0:77205fc699b9, 2022-05-08 (annotated)

Committer:
braichi13
Date:
Sun May 08 14:39:47 2022 +0000
Revision:
0:77205fc699b9
Programme du Gyropode

Who changed what in which revision?

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braichi13 0:77205fc699b9 1 /*----------------------------------------------------------------------------
braichi13 0:77205fc699b9 2 * RL-ARM - RTX
braichi13 0:77205fc699b9 3 *----------------------------------------------------------------------------
braichi13 0:77205fc699b9 4 * Name: HAL_CM.C
braichi13 0:77205fc699b9 5 * Purpose: Hardware Abstraction Layer for ARM7TDMI
braichi13 0:77205fc699b9 6 * Rev.: V1.0
braichi13 0:77205fc699b9 7 *----------------------------------------------------------------------------
braichi13 0:77205fc699b9 8 *
braichi13 0:77205fc699b9 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
braichi13 0:77205fc699b9 10 * All rights reserved.
braichi13 0:77205fc699b9 11 * Redistribution and use in source and binary forms, with or without
braichi13 0:77205fc699b9 12 * modification, are permitted provided that the following conditions are met:
braichi13 0:77205fc699b9 13 * - Redistributions of source code must retain the above copyright
braichi13 0:77205fc699b9 14 * notice, this list of conditions and the following disclaimer.
braichi13 0:77205fc699b9 15 * - Redistributions in binary form must reproduce the above copyright
braichi13 0:77205fc699b9 16 * notice, this list of conditions and the following disclaimer in the
braichi13 0:77205fc699b9 17 * documentation and/or other materials provided with the distribution.
braichi13 0:77205fc699b9 18 * - Neither the name of ARM nor the names of its contributors may be used
braichi13 0:77205fc699b9 19 * to endorse or promote products derived from this software without
braichi13 0:77205fc699b9 20 * specific prior written permission.
braichi13 0:77205fc699b9 21 *
braichi13 0:77205fc699b9 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
braichi13 0:77205fc699b9 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
braichi13 0:77205fc699b9 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
braichi13 0:77205fc699b9 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
braichi13 0:77205fc699b9 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
braichi13 0:77205fc699b9 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
braichi13 0:77205fc699b9 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
braichi13 0:77205fc699b9 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
braichi13 0:77205fc699b9 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
braichi13 0:77205fc699b9 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
braichi13 0:77205fc699b9 32 * POSSIBILITY OF SUCH DAMAGE.
braichi13 0:77205fc699b9 33 *---------------------------------------------------------------------------*/
braichi13 0:77205fc699b9 34
braichi13 0:77205fc699b9 35 #include "rt_TypeDef.h"
braichi13 0:77205fc699b9 36 #include "RTX_Conf.h"
braichi13 0:77205fc699b9 37 #include "rt_HAL_CM.h"
braichi13 0:77205fc699b9 38
braichi13 0:77205fc699b9 39
braichi13 0:77205fc699b9 40 /*----------------------------------------------------------------------------
braichi13 0:77205fc699b9 41 * Global Variables
braichi13 0:77205fc699b9 42 *---------------------------------------------------------------------------*/
braichi13 0:77205fc699b9 43
braichi13 0:77205fc699b9 44 #ifdef DBG_MSG
braichi13 0:77205fc699b9 45 BIT dbg_msg;
braichi13 0:77205fc699b9 46 #endif
braichi13 0:77205fc699b9 47
braichi13 0:77205fc699b9 48 /*----------------------------------------------------------------------------
braichi13 0:77205fc699b9 49 * Functions
braichi13 0:77205fc699b9 50 *---------------------------------------------------------------------------*/
braichi13 0:77205fc699b9 51
braichi13 0:77205fc699b9 52
braichi13 0:77205fc699b9 53 /*--------------------------- rt_init_stack ---------------------------------*/
braichi13 0:77205fc699b9 54
braichi13 0:77205fc699b9 55 void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
braichi13 0:77205fc699b9 56 /* Prepare TCB and saved context for a first time start of a task. */
braichi13 0:77205fc699b9 57 U32 *stk,i,size;
braichi13 0:77205fc699b9 58
braichi13 0:77205fc699b9 59 /* Prepare a complete interrupt frame for first task start */
braichi13 0:77205fc699b9 60 size = p_TCB->priv_stack >> 2;
braichi13 0:77205fc699b9 61
braichi13 0:77205fc699b9 62 /* Write to the top of stack. */
braichi13 0:77205fc699b9 63 stk = &p_TCB->stack[size];
braichi13 0:77205fc699b9 64
braichi13 0:77205fc699b9 65 /* Auto correct to 8-byte ARM stack alignment. */
braichi13 0:77205fc699b9 66 if ((U32)stk & 0x04) {
braichi13 0:77205fc699b9 67 stk--;
braichi13 0:77205fc699b9 68 }
braichi13 0:77205fc699b9 69
braichi13 0:77205fc699b9 70 stk -= 16;
braichi13 0:77205fc699b9 71
braichi13 0:77205fc699b9 72 /* Default xPSR and initial PC */
braichi13 0:77205fc699b9 73 stk[15] = (U32)task_body + 4; /* add 4 byte offset because SUB PC, LR - 4 */
braichi13 0:77205fc699b9 74 stk[0] = INITIAL_xPSR;
braichi13 0:77205fc699b9 75
braichi13 0:77205fc699b9 76 /* Clear R0-R13/LR registers. */
braichi13 0:77205fc699b9 77 for (i = 1; i < 14; i++) {
braichi13 0:77205fc699b9 78 stk[i] = 0;
braichi13 0:77205fc699b9 79 }
braichi13 0:77205fc699b9 80
braichi13 0:77205fc699b9 81 /* Assign a void pointer to R0. */
braichi13 0:77205fc699b9 82 stk[TCB_STACK_R0_OFFSET_DWORDS] = (U32)p_TCB->msg;
braichi13 0:77205fc699b9 83
braichi13 0:77205fc699b9 84 /* Initial Task stack pointer. */
braichi13 0:77205fc699b9 85 p_TCB->tsk_stack = (U32)stk;
braichi13 0:77205fc699b9 86
braichi13 0:77205fc699b9 87 /* Task entry point. */
braichi13 0:77205fc699b9 88 p_TCB->ptask = task_body;
braichi13 0:77205fc699b9 89
braichi13 0:77205fc699b9 90 /* Set a magic word for checking of stack overflow.
braichi13 0:77205fc699b9 91 For the main thread (ID: 0x01) the stack is in a memory area shared with the
braichi13 0:77205fc699b9 92 heap, therefore the last word of the stack is a moving target.
braichi13 0:77205fc699b9 93 We want to do stack/heap collision detection instead.
braichi13 0:77205fc699b9 94 */
braichi13 0:77205fc699b9 95 if (p_TCB->task_id != 0x01)
braichi13 0:77205fc699b9 96 p_TCB->stack[0] = MAGIC_WORD;
braichi13 0:77205fc699b9 97 }
braichi13 0:77205fc699b9 98
braichi13 0:77205fc699b9 99
braichi13 0:77205fc699b9 100 /*--------------------------- rt_ret_val ----------------------------------*/
braichi13 0:77205fc699b9 101
braichi13 0:77205fc699b9 102 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
braichi13 0:77205fc699b9 103 /* Get pointer to task return value registers (R0..R3) in Stack */
braichi13 0:77205fc699b9 104
braichi13 0:77205fc699b9 105 /* Stack Frame: CPSR,R0-R13,PC */
braichi13 0:77205fc699b9 106 return (U32 *)(p_TCB->tsk_stack + TCB_STACK_R0_OFFSET_BYTES);
braichi13 0:77205fc699b9 107 }
braichi13 0:77205fc699b9 108
braichi13 0:77205fc699b9 109 void rt_ret_val (P_TCB p_TCB, U32 v0) {
braichi13 0:77205fc699b9 110 U32 *ret;
braichi13 0:77205fc699b9 111
braichi13 0:77205fc699b9 112 ret = rt_ret_regs(p_TCB);
braichi13 0:77205fc699b9 113 ret[0] = v0;
braichi13 0:77205fc699b9 114 }
braichi13 0:77205fc699b9 115
braichi13 0:77205fc699b9 116 void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
braichi13 0:77205fc699b9 117 U32 *ret;
braichi13 0:77205fc699b9 118
braichi13 0:77205fc699b9 119 ret = rt_ret_regs(p_TCB);
braichi13 0:77205fc699b9 120 ret[0] = v0;
braichi13 0:77205fc699b9 121 ret[1] = v1;
braichi13 0:77205fc699b9 122 }
braichi13 0:77205fc699b9 123
braichi13 0:77205fc699b9 124
braichi13 0:77205fc699b9 125 /*--------------------------- dbg_init --------------------------------------*/
braichi13 0:77205fc699b9 126
braichi13 0:77205fc699b9 127 #ifdef DBG_MSG
braichi13 0:77205fc699b9 128 void dbg_init (void) {
braichi13 0:77205fc699b9 129 if ((DEMCR & DEMCR_TRCENA) &&
braichi13 0:77205fc699b9 130 (ITM_CONTROL & ITM_ITMENA) &&
braichi13 0:77205fc699b9 131 (ITM_ENABLE & (1UL << 31))) {
braichi13 0:77205fc699b9 132 dbg_msg = __TRUE;
braichi13 0:77205fc699b9 133 }
braichi13 0:77205fc699b9 134 }
braichi13 0:77205fc699b9 135 #endif
braichi13 0:77205fc699b9 136
braichi13 0:77205fc699b9 137 /*--------------------------- dbg_task_notify -------------------------------*/
braichi13 0:77205fc699b9 138
braichi13 0:77205fc699b9 139 #ifdef DBG_MSG
braichi13 0:77205fc699b9 140 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
braichi13 0:77205fc699b9 141 while (ITM_PORT31_U32 == 0);
braichi13 0:77205fc699b9 142 ITM_PORT31_U32 = (U32)p_tcb->ptask;
braichi13 0:77205fc699b9 143 while (ITM_PORT31_U32 == 0);
braichi13 0:77205fc699b9 144 ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
braichi13 0:77205fc699b9 145 }
braichi13 0:77205fc699b9 146 #endif
braichi13 0:77205fc699b9 147
braichi13 0:77205fc699b9 148 /*--------------------------- dbg_task_switch -------------------------------*/
braichi13 0:77205fc699b9 149
braichi13 0:77205fc699b9 150 #ifdef DBG_MSG
braichi13 0:77205fc699b9 151 void dbg_task_switch (U32 task_id) {
braichi13 0:77205fc699b9 152 while (ITM_PORT31_U32 == 0);
braichi13 0:77205fc699b9 153 ITM_PORT31_U8 = task_id;
braichi13 0:77205fc699b9 154 }
braichi13 0:77205fc699b9 155 #endif
braichi13 0:77205fc699b9 156
braichi13 0:77205fc699b9 157
braichi13 0:77205fc699b9 158 /*----------------------------------------------------------------------------
braichi13 0:77205fc699b9 159 * end of file
braichi13 0:77205fc699b9 160 *---------------------------------------------------------------------------*/
braichi13 0:77205fc699b9 161