cebri alyac / FastPWM

yes

Device/FastPWM_STM_TIM_PinOut.cpp@0:c60399891edd, 2022-05-08 (annotated)

Committer:
braichi13
Date:
Sun May 08 14:39:57 2022 +0000
Revision:
0:c60399891edd
Yes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
braichi13 0:c60399891edd 1 #include "mbed.h"
braichi13 0:c60399891edd 2
braichi13 0:c60399891edd 3 #if defined (TARGET_NUCLEO_F030R8) || (TARGET_DISCO_F051R8)
braichi13 0:c60399891edd 4 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
braichi13 0:c60399891edd 5 switch (pin) {
braichi13 0:c60399891edd 6 // Channels 1
braichi13 0:c60399891edd 7 case PA_4: case PA_6: case PB_1: case PB_4: case PB_8: case PB_9: case PB_14: case PC_6: case PB_6: case PB_7:
braichi13 0:c60399891edd 8 return &pwm->CCR1;
braichi13 0:c60399891edd 9
braichi13 0:c60399891edd 10 // Channels 2
braichi13 0:c60399891edd 11 case PA_7: case PB_5: case PC_7:
braichi13 0:c60399891edd 12 return &pwm->CCR2;
braichi13 0:c60399891edd 13
braichi13 0:c60399891edd 14 // Channels 3
braichi13 0:c60399891edd 15 case PB_0: case PC_8:
braichi13 0:c60399891edd 16 return &pwm->CCR3;
braichi13 0:c60399891edd 17
braichi13 0:c60399891edd 18 // Channels 4
braichi13 0:c60399891edd 19 case PC_9:
braichi13 0:c60399891edd 20 return &pwm->CCR4;
braichi13 0:c60399891edd 21 }
braichi13 0:c60399891edd 22 return NULL;
braichi13 0:c60399891edd 23 }
braichi13 0:c60399891edd 24 #endif
braichi13 0:c60399891edd 25
braichi13 0:c60399891edd 26 #if defined (TARGET_NUCLEO_F103RB) || (TARGET_DISCO_F100RB)
braichi13 0:c60399891edd 27 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
braichi13 0:c60399891edd 28 switch (pin) {
braichi13 0:c60399891edd 29 // Channels 1 : PWMx/1
braichi13 0:c60399891edd 30 case PA_6: case PA_8: case PA_15: case PB_4: case PC_6: case PB_13:
braichi13 0:c60399891edd 31 return &pwm->CCR1;
braichi13 0:c60399891edd 32
braichi13 0:c60399891edd 33 // Channels 2 : PWMx/2
braichi13 0:c60399891edd 34 case PA_1: case PA_7: case PA_9: case PB_3: case PB_5: case PC_7: case PB_14:
braichi13 0:c60399891edd 35 return &pwm->CCR2;
braichi13 0:c60399891edd 36
braichi13 0:c60399891edd 37 // Channels 3 : PWMx/3
braichi13 0:c60399891edd 38 case PA_2: case PA_10: case PB_0: case PB_10: case PC_8: case PB_15:
braichi13 0:c60399891edd 39 return &pwm->CCR3;
braichi13 0:c60399891edd 40
braichi13 0:c60399891edd 41 // Channels 4 : PWMx/4
braichi13 0:c60399891edd 42 case PA_3: case PA_11: case PB_1: case PB_11: case PC_9:
braichi13 0:c60399891edd 43 return &pwm->CCR4;
braichi13 0:c60399891edd 44 }
braichi13 0:c60399891edd 45 return NULL;
braichi13 0:c60399891edd 46 }
braichi13 0:c60399891edd 47 #endif
braichi13 0:c60399891edd 48
braichi13 0:c60399891edd 49 #if defined TARGET_NUCLEO_F072RB
braichi13 0:c60399891edd 50 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
braichi13 0:c60399891edd 51 switch (pin) {
braichi13 0:c60399891edd 52 // Channels 1 : PWMx/1
braichi13 0:c60399891edd 53 case PA_2: case PA_6: case PA_4: case PA_7: case PA_8: case PB_1: case PB_4: case PB_8: case PB_9: case PB_14: case PC_6:
braichi13 0:c60399891edd 54 // Channels 1N : PWMx/1N
braichi13 0:c60399891edd 55 case PA_1: case PB_6: case PB_7: case PB_13:
braichi13 0:c60399891edd 56 return &pwm->CCR1;
braichi13 0:c60399891edd 57
braichi13 0:c60399891edd 58 // Channels 2 : PWMx/2
braichi13 0:c60399891edd 59 case PA_3: case PA_9: case PB_5: case PC_7: case PB_15:
braichi13 0:c60399891edd 60 return &pwm->CCR2;
braichi13 0:c60399891edd 61
braichi13 0:c60399891edd 62 // Channels 3 : PWMx/3
braichi13 0:c60399891edd 63 case PA_10: case PB_0: case PC_8:
braichi13 0:c60399891edd 64 return &pwm->CCR3;
braichi13 0:c60399891edd 65
braichi13 0:c60399891edd 66 // Channels 4 : PWMx/4
braichi13 0:c60399891edd 67 case PA_11: case PC_9:
braichi13 0:c60399891edd 68 return &pwm->CCR4;
braichi13 0:c60399891edd 69 }
braichi13 0:c60399891edd 70 return NULL;
braichi13 0:c60399891edd 71 }
braichi13 0:c60399891edd 72 #endif
braichi13 0:c60399891edd 73
braichi13 0:c60399891edd 74
braichi13 0:c60399891edd 75
braichi13 0:c60399891edd 76 #if defined (TARGET_NUCLEO_L152RE)
braichi13 0:c60399891edd 77 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
braichi13 0:c60399891edd 78 switch (pin) {
braichi13 0:c60399891edd 79 // Channels 1 : PWMx/1
braichi13 0:c60399891edd 80 case PA_6: case PB_4: case PB_12: case PB_13: case PC_6:
braichi13 0:c60399891edd 81 return &pwm->CCR1;
braichi13 0:c60399891edd 82
braichi13 0:c60399891edd 83 // Channels 2 : PWMx/2
braichi13 0:c60399891edd 84 case PA_1: case PA_7: case PB_3: case PB_5: case PB_14: case PB_7: case PC_7:
braichi13 0:c60399891edd 85 return &pwm->CCR2;
braichi13 0:c60399891edd 86
braichi13 0:c60399891edd 87 // Channels 3 : PWMx/3
braichi13 0:c60399891edd 88 case PA_2: case PB_0: case PB_8: case PB_10: case PC_8:
braichi13 0:c60399891edd 89 return &pwm->CCR3;
braichi13 0:c60399891edd 90
braichi13 0:c60399891edd 91 // Channels 4 : PWMx/4
braichi13 0:c60399891edd 92 case PA_3: case PB_1:case PB_9: case PB_11: case PC_9:
braichi13 0:c60399891edd 93 return &pwm->CCR4;
braichi13 0:c60399891edd 94 default:
braichi13 0:c60399891edd 95 /* NOP */
braichi13 0:c60399891edd 96 break;
braichi13 0:c60399891edd 97 }
braichi13 0:c60399891edd 98 return NULL;
braichi13 0:c60399891edd 99 }
braichi13 0:c60399891edd 100 #endif
braichi13 0:c60399891edd 101
braichi13 0:c60399891edd 102