Nicolas Borla / Mbed OS BBR_1Ebene

BBR 1 Ebene

mbed-os/targets/TARGET_STM/pinmap.c@0:fbdae7e6d805, 2018-05-14 (annotated)

Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:fbdae7e6d805 1 /* mbed Microcontroller Library
borlanic 0:fbdae7e6d805 2 *******************************************************************************
borlanic 0:fbdae7e6d805 3 * Copyright (c) 2017, STMicroelectronics
borlanic 0:fbdae7e6d805 4 * All rights reserved.
borlanic 0:fbdae7e6d805 5 *
borlanic 0:fbdae7e6d805 6 * Redistribution and use in source and binary forms, with or without
borlanic 0:fbdae7e6d805 7 * modification, are permitted provided that the following conditions are met:
borlanic 0:fbdae7e6d805 8 *
borlanic 0:fbdae7e6d805 9 * 1. Redistributions of source code must retain the above copyright notice,
borlanic 0:fbdae7e6d805 10 * this list of conditions and the following disclaimer.
borlanic 0:fbdae7e6d805 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
borlanic 0:fbdae7e6d805 12 * this list of conditions and the following disclaimer in the documentation
borlanic 0:fbdae7e6d805 13 * and/or other materials provided with the distribution.
borlanic 0:fbdae7e6d805 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
borlanic 0:fbdae7e6d805 15 * may be used to endorse or promote products derived from this software
borlanic 0:fbdae7e6d805 16 * without specific prior written permission.
borlanic 0:fbdae7e6d805 17 *
borlanic 0:fbdae7e6d805 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
borlanic 0:fbdae7e6d805 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
borlanic 0:fbdae7e6d805 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
borlanic 0:fbdae7e6d805 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
borlanic 0:fbdae7e6d805 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
borlanic 0:fbdae7e6d805 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
borlanic 0:fbdae7e6d805 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
borlanic 0:fbdae7e6d805 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
borlanic 0:fbdae7e6d805 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
borlanic 0:fbdae7e6d805 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
borlanic 0:fbdae7e6d805 28 *******************************************************************************
borlanic 0:fbdae7e6d805 29 */
borlanic 0:fbdae7e6d805 30 #include "mbed_assert.h"
borlanic 0:fbdae7e6d805 31 #include "pinmap.h"
borlanic 0:fbdae7e6d805 32 #include "PortNames.h"
borlanic 0:fbdae7e6d805 33 #include "mbed_error.h"
borlanic 0:fbdae7e6d805 34 #include "pin_device.h"
borlanic 0:fbdae7e6d805 35
borlanic 0:fbdae7e6d805 36 extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
borlanic 0:fbdae7e6d805 37
borlanic 0:fbdae7e6d805 38 const uint32_t ll_pin_defines[16] = {
borlanic 0:fbdae7e6d805 39 LL_GPIO_PIN_0,
borlanic 0:fbdae7e6d805 40 LL_GPIO_PIN_1,
borlanic 0:fbdae7e6d805 41 LL_GPIO_PIN_2,
borlanic 0:fbdae7e6d805 42 LL_GPIO_PIN_3,
borlanic 0:fbdae7e6d805 43 LL_GPIO_PIN_4,
borlanic 0:fbdae7e6d805 44 LL_GPIO_PIN_5,
borlanic 0:fbdae7e6d805 45 LL_GPIO_PIN_6,
borlanic 0:fbdae7e6d805 46 LL_GPIO_PIN_7,
borlanic 0:fbdae7e6d805 47 LL_GPIO_PIN_8,
borlanic 0:fbdae7e6d805 48 LL_GPIO_PIN_9,
borlanic 0:fbdae7e6d805 49 LL_GPIO_PIN_10,
borlanic 0:fbdae7e6d805 50 LL_GPIO_PIN_11,
borlanic 0:fbdae7e6d805 51 LL_GPIO_PIN_12,
borlanic 0:fbdae7e6d805 52 LL_GPIO_PIN_13,
borlanic 0:fbdae7e6d805 53 LL_GPIO_PIN_14,
borlanic 0:fbdae7e6d805 54 LL_GPIO_PIN_15
borlanic 0:fbdae7e6d805 55 };
borlanic 0:fbdae7e6d805 56
borlanic 0:fbdae7e6d805 57 /**
borlanic 0:fbdae7e6d805 58 * Configure pin (mode, speed, output type and pull-up/pull-down)
borlanic 0:fbdae7e6d805 59 */
borlanic 0:fbdae7e6d805 60 void pin_function(PinName pin, int data)
borlanic 0:fbdae7e6d805 61 {
borlanic 0:fbdae7e6d805 62 MBED_ASSERT(pin != (PinName)NC);
borlanic 0:fbdae7e6d805 63
borlanic 0:fbdae7e6d805 64 // Get the pin informations
borlanic 0:fbdae7e6d805 65 uint32_t mode = STM_PIN_FUNCTION(data);
borlanic 0:fbdae7e6d805 66 uint32_t afnum = STM_PIN_AFNUM(data);
borlanic 0:fbdae7e6d805 67 uint32_t port = STM_PORT(pin);
borlanic 0:fbdae7e6d805 68 uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
borlanic 0:fbdae7e6d805 69 uint32_t ll_mode = 0;
borlanic 0:fbdae7e6d805 70
borlanic 0:fbdae7e6d805 71 // Enable GPIO clock
borlanic 0:fbdae7e6d805 72 GPIO_TypeDef *gpio = Set_GPIO_Clock(port);
borlanic 0:fbdae7e6d805 73
borlanic 0:fbdae7e6d805 74 /* Set default speed to high.
borlanic 0:fbdae7e6d805 75 * For most families there are dedicated registers so it is
borlanic 0:fbdae7e6d805 76 * not so important, register can be set at any time.
borlanic 0:fbdae7e6d805 77 * But for families like F1, speed only applies to output.
borlanic 0:fbdae7e6d805 78 */
borlanic 0:fbdae7e6d805 79 #if defined (TARGET_STM32F1)
borlanic 0:fbdae7e6d805 80 if (mode == STM_PIN_OUTPUT) {
borlanic 0:fbdae7e6d805 81 #endif
borlanic 0:fbdae7e6d805 82 LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH);
borlanic 0:fbdae7e6d805 83 #if defined (TARGET_STM32F1)
borlanic 0:fbdae7e6d805 84 }
borlanic 0:fbdae7e6d805 85 #endif
borlanic 0:fbdae7e6d805 86
borlanic 0:fbdae7e6d805 87 switch (mode) {
borlanic 0:fbdae7e6d805 88 case STM_PIN_INPUT:
borlanic 0:fbdae7e6d805 89 ll_mode = LL_GPIO_MODE_INPUT;
borlanic 0:fbdae7e6d805 90 break;
borlanic 0:fbdae7e6d805 91 case STM_PIN_OUTPUT:
borlanic 0:fbdae7e6d805 92 ll_mode = LL_GPIO_MODE_OUTPUT;
borlanic 0:fbdae7e6d805 93 break;
borlanic 0:fbdae7e6d805 94 case STM_PIN_ALTERNATE:
borlanic 0:fbdae7e6d805 95 ll_mode = LL_GPIO_MODE_ALTERNATE;
borlanic 0:fbdae7e6d805 96 // In case of ALT function, also set he afnum
borlanic 0:fbdae7e6d805 97 stm_pin_SetAFPin(gpio, pin, afnum);
borlanic 0:fbdae7e6d805 98 break;
borlanic 0:fbdae7e6d805 99 case STM_PIN_ANALOG:
borlanic 0:fbdae7e6d805 100 ll_mode = LL_GPIO_MODE_ANALOG;
borlanic 0:fbdae7e6d805 101 break;
borlanic 0:fbdae7e6d805 102 default:
borlanic 0:fbdae7e6d805 103 MBED_ASSERT(0);
borlanic 0:fbdae7e6d805 104 break;
borlanic 0:fbdae7e6d805 105 }
borlanic 0:fbdae7e6d805 106 LL_GPIO_SetPinMode(gpio, ll_pin, ll_mode);
borlanic 0:fbdae7e6d805 107
borlanic 0:fbdae7e6d805 108 #if defined(GPIO_ASCR_ASC0)
borlanic 0:fbdae7e6d805 109 /* For families where Analog Control ASC0 register is present */
borlanic 0:fbdae7e6d805 110 if (STM_PIN_ANALOG_CONTROL(data)) {
borlanic 0:fbdae7e6d805 111 LL_GPIO_EnablePinAnalogControl(gpio, ll_pin);
borlanic 0:fbdae7e6d805 112 } else {
borlanic 0:fbdae7e6d805 113 LL_GPIO_DisablePinAnalogControl(gpio, ll_pin);
borlanic 0:fbdae7e6d805 114 }
borlanic 0:fbdae7e6d805 115 #endif
borlanic 0:fbdae7e6d805 116
borlanic 0:fbdae7e6d805 117 /* For now by default use Speed HIGH for output or alt modes */
borlanic 0:fbdae7e6d805 118 if ((mode == STM_PIN_OUTPUT) ||(mode == STM_PIN_ALTERNATE)) {
borlanic 0:fbdae7e6d805 119 if (STM_PIN_OD(data)) {
borlanic 0:fbdae7e6d805 120 LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN);
borlanic 0:fbdae7e6d805 121 } else {
borlanic 0:fbdae7e6d805 122 LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_PUSHPULL);
borlanic 0:fbdae7e6d805 123 }
borlanic 0:fbdae7e6d805 124 }
borlanic 0:fbdae7e6d805 125
borlanic 0:fbdae7e6d805 126 stm_pin_PullConfig(gpio, ll_pin, STM_PIN_PUPD(data));
borlanic 0:fbdae7e6d805 127
borlanic 0:fbdae7e6d805 128 stm_pin_DisconnectDebug(pin);
borlanic 0:fbdae7e6d805 129 }
borlanic 0:fbdae7e6d805 130
borlanic 0:fbdae7e6d805 131 /**
borlanic 0:fbdae7e6d805 132 * Configure pin pull-up/pull-down
borlanic 0:fbdae7e6d805 133 */
borlanic 0:fbdae7e6d805 134 void pin_mode(PinName pin, PinMode mode)
borlanic 0:fbdae7e6d805 135 {
borlanic 0:fbdae7e6d805 136 MBED_ASSERT(pin != (PinName)NC);
borlanic 0:fbdae7e6d805 137
borlanic 0:fbdae7e6d805 138 uint32_t port_index = STM_PORT(pin);
borlanic 0:fbdae7e6d805 139 uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
borlanic 0:fbdae7e6d805 140 // Enable GPIO clock
borlanic 0:fbdae7e6d805 141 GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
borlanic 0:fbdae7e6d805 142 uint32_t function = LL_GPIO_GetPinMode(gpio, ll_pin);
borlanic 0:fbdae7e6d805 143
borlanic 0:fbdae7e6d805 144 if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE))
borlanic 0:fbdae7e6d805 145 {
borlanic 0:fbdae7e6d805 146 if ((mode == OpenDrainNoPull) || (mode == OpenDrainPullUp) || (mode == OpenDrainPullDown)) {
borlanic 0:fbdae7e6d805 147 LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN);
borlanic 0:fbdae7e6d805 148 } else {
borlanic 0:fbdae7e6d805 149 LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_PUSHPULL);
borlanic 0:fbdae7e6d805 150 }
borlanic 0:fbdae7e6d805 151 }
borlanic 0:fbdae7e6d805 152
borlanic 0:fbdae7e6d805 153 if ((mode == OpenDrainPullUp) || (mode == PullUp)) {
borlanic 0:fbdae7e6d805 154 stm_pin_PullConfig(gpio, ll_pin, GPIO_PULLUP);
borlanic 0:fbdae7e6d805 155 } else if ((mode == OpenDrainPullDown) || (mode == PullDown)) {
borlanic 0:fbdae7e6d805 156 stm_pin_PullConfig(gpio, ll_pin, GPIO_PULLDOWN);
borlanic 0:fbdae7e6d805 157 } else {
borlanic 0:fbdae7e6d805 158 stm_pin_PullConfig(gpio, ll_pin, GPIO_NOPULL);
borlanic 0:fbdae7e6d805 159 }
borlanic 0:fbdae7e6d805 160 }