Nicolas Borla / Mbed OS BBR_1Ebene

BBR 1 Ebene

mbed-os/platform/mbed_application.c@0:fbdae7e6d805, 2018-05-14 (annotated)

Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:fbdae7e6d805 1 /* mbed Microcontroller Library
borlanic 0:fbdae7e6d805 2 * Copyright (c) 2017-2017 ARM Limited
borlanic 0:fbdae7e6d805 3 *
borlanic 0:fbdae7e6d805 4 * Licensed under the Apache License, Version 2.0 (the "License");
borlanic 0:fbdae7e6d805 5 * you may not use this file except in compliance with the License.
borlanic 0:fbdae7e6d805 6 * You may obtain a copy of the License at
borlanic 0:fbdae7e6d805 7 *
borlanic 0:fbdae7e6d805 8 * http://www.apache.org/licenses/LICENSE-2.0
borlanic 0:fbdae7e6d805 9 *
borlanic 0:fbdae7e6d805 10 * Unless required by applicable law or agreed to in writing, software
borlanic 0:fbdae7e6d805 11 * distributed under the License is distributed on an "AS IS" BASIS,
borlanic 0:fbdae7e6d805 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
borlanic 0:fbdae7e6d805 13 * See the License for the specific language governing permissions and
borlanic 0:fbdae7e6d805 14 * limitations under the License.
borlanic 0:fbdae7e6d805 15 */
borlanic 0:fbdae7e6d805 16
borlanic 0:fbdae7e6d805 17 #include <stdlib.h>
borlanic 0:fbdae7e6d805 18 #include <stdarg.h>
borlanic 0:fbdae7e6d805 19 #include "device.h"
borlanic 0:fbdae7e6d805 20 #include "platform/mbed_application.h"
borlanic 0:fbdae7e6d805 21
borlanic 0:fbdae7e6d805 22 #if MBED_APPLICATION_SUPPORT
borlanic 0:fbdae7e6d805 23
borlanic 0:fbdae7e6d805 24 static void powerdown_nvic(void);
borlanic 0:fbdae7e6d805 25 static void powerdown_scb(uint32_t vtor);
borlanic 0:fbdae7e6d805 26 static void start_new_application(void *sp, void *pc);
borlanic 0:fbdae7e6d805 27
borlanic 0:fbdae7e6d805 28 void mbed_start_application(uintptr_t address)
borlanic 0:fbdae7e6d805 29 {
borlanic 0:fbdae7e6d805 30 void *sp;
borlanic 0:fbdae7e6d805 31 void *pc;
borlanic 0:fbdae7e6d805 32
borlanic 0:fbdae7e6d805 33 // Interrupts are re-enabled in start_new_application
borlanic 0:fbdae7e6d805 34 __disable_irq();
borlanic 0:fbdae7e6d805 35
borlanic 0:fbdae7e6d805 36 SysTick->CTRL = 0x00000000;
borlanic 0:fbdae7e6d805 37 powerdown_nvic();
borlanic 0:fbdae7e6d805 38 powerdown_scb(address);
borlanic 0:fbdae7e6d805 39
borlanic 0:fbdae7e6d805 40 sp = *((void**)address + 0);
borlanic 0:fbdae7e6d805 41 pc = *((void**)address + 1);
borlanic 0:fbdae7e6d805 42 start_new_application(sp, pc);
borlanic 0:fbdae7e6d805 43 }
borlanic 0:fbdae7e6d805 44
borlanic 0:fbdae7e6d805 45 static void powerdown_nvic()
borlanic 0:fbdae7e6d805 46 {
borlanic 0:fbdae7e6d805 47 int isr_groups_32;
borlanic 0:fbdae7e6d805 48 int i;
borlanic 0:fbdae7e6d805 49 int j;
borlanic 0:fbdae7e6d805 50
borlanic 0:fbdae7e6d805 51 isr_groups_32 = ((SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos) + 1;
borlanic 0:fbdae7e6d805 52 for (i = 0; i < isr_groups_32; i++) {
borlanic 0:fbdae7e6d805 53 NVIC->ICER[i] = 0xFFFFFFFF;
borlanic 0:fbdae7e6d805 54 NVIC->ICPR[i] = 0xFFFFFFFF;
borlanic 0:fbdae7e6d805 55 for (j = 0; j < 8; j++) {
borlanic 0:fbdae7e6d805 56 NVIC->IP[i * 8 + j] = 0x00000000;
borlanic 0:fbdae7e6d805 57 }
borlanic 0:fbdae7e6d805 58 }
borlanic 0:fbdae7e6d805 59 }
borlanic 0:fbdae7e6d805 60
borlanic 0:fbdae7e6d805 61 static void powerdown_scb(uint32_t vtor)
borlanic 0:fbdae7e6d805 62 {
borlanic 0:fbdae7e6d805 63 int i;
borlanic 0:fbdae7e6d805 64
borlanic 0:fbdae7e6d805 65 // SCB->CPUID - Read only CPU ID register
borlanic 0:fbdae7e6d805 66 SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk;
borlanic 0:fbdae7e6d805 67 SCB->VTOR = vtor;
borlanic 0:fbdae7e6d805 68 SCB->AIRCR = 0x05FA | 0x0000;
borlanic 0:fbdae7e6d805 69 SCB->SCR = 0x00000000;
borlanic 0:fbdae7e6d805 70 // SCB->CCR - Implementation defined value
borlanic 0:fbdae7e6d805 71 for (i = 0; i < 12; i++) {
borlanic 0:fbdae7e6d805 72 #if defined(__CORTEX_M7)
borlanic 0:fbdae7e6d805 73 SCB->SHPR[i] = 0x00;
borlanic 0:fbdae7e6d805 74 #else
borlanic 0:fbdae7e6d805 75 SCB->SHP[i] = 0x00;
borlanic 0:fbdae7e6d805 76 #endif
borlanic 0:fbdae7e6d805 77 }
borlanic 0:fbdae7e6d805 78 SCB->SHCSR = 0x00000000;
borlanic 0:fbdae7e6d805 79 SCB->CFSR = 0xFFFFFFFF;
borlanic 0:fbdae7e6d805 80 SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk;
borlanic 0:fbdae7e6d805 81 SCB->DFSR = SCB_DFSR_EXTERNAL_Msk | SCB_DFSR_VCATCH_Msk |
borlanic 0:fbdae7e6d805 82 SCB_DFSR_DWTTRAP_Msk | SCB_DFSR_BKPT_Msk | SCB_DFSR_HALTED_Msk;
borlanic 0:fbdae7e6d805 83 // SCB->MMFAR - Implementation defined value
borlanic 0:fbdae7e6d805 84 // SCB->BFAR - Implementation defined value
borlanic 0:fbdae7e6d805 85 // SCB->AFSR - Implementation defined value
borlanic 0:fbdae7e6d805 86 // SCB->PFR - Read only processor feature register
borlanic 0:fbdae7e6d805 87 // SCB->DFR - Read only debug feature registers
borlanic 0:fbdae7e6d805 88 // SCB->ADR - Read only auxiliary feature registers
borlanic 0:fbdae7e6d805 89 // SCB->MMFR - Read only memory model feature registers
borlanic 0:fbdae7e6d805 90 // SCB->ISAR - Read only instruction set attribute registers
borlanic 0:fbdae7e6d805 91 // SCB->CPACR - Implementation defined value
borlanic 0:fbdae7e6d805 92 }
borlanic 0:fbdae7e6d805 93
borlanic 0:fbdae7e6d805 94 #if defined (__CC_ARM)
borlanic 0:fbdae7e6d805 95
borlanic 0:fbdae7e6d805 96 __asm static void start_new_application(void *sp, void *pc)
borlanic 0:fbdae7e6d805 97 {
borlanic 0:fbdae7e6d805 98 MOV R2, #0
borlanic 0:fbdae7e6d805 99 MSR CONTROL, R2 // Switch to main stack
borlanic 0:fbdae7e6d805 100 MOV SP, R0
borlanic 0:fbdae7e6d805 101 MSR PRIMASK, R2 // Enable interrupts
borlanic 0:fbdae7e6d805 102 BX R1
borlanic 0:fbdae7e6d805 103 }
borlanic 0:fbdae7e6d805 104
borlanic 0:fbdae7e6d805 105 #elif defined (__GNUC__) || defined (__ICCARM__)
borlanic 0:fbdae7e6d805 106
borlanic 0:fbdae7e6d805 107 void start_new_application(void *sp, void *pc)
borlanic 0:fbdae7e6d805 108 {
borlanic 0:fbdae7e6d805 109 __asm volatile (
borlanic 0:fbdae7e6d805 110 "mov r2, #0 \n"
borlanic 0:fbdae7e6d805 111 "msr control, r2 \n" // Switch to main stack
borlanic 0:fbdae7e6d805 112 "mov sp, %0 \n"
borlanic 0:fbdae7e6d805 113 "msr primask, r2 \n" // Enable interrupts
borlanic 0:fbdae7e6d805 114 "bx %1 \n"
borlanic 0:fbdae7e6d805 115 :
borlanic 0:fbdae7e6d805 116 : "l" (sp), "l" (pc)
borlanic 0:fbdae7e6d805 117 : "r2", "cc", "memory"
borlanic 0:fbdae7e6d805 118 );
borlanic 0:fbdae7e6d805 119 }
borlanic 0:fbdae7e6d805 120
borlanic 0:fbdae7e6d805 121 #else
borlanic 0:fbdae7e6d805 122
borlanic 0:fbdae7e6d805 123 #error "Unsupported toolchain"
borlanic 0:fbdae7e6d805 124
borlanic 0:fbdae7e6d805 125 #endif
borlanic 0:fbdae7e6d805 126
borlanic 0:fbdae7e6d805 127 #endif /* MBED_APPLICATION_SUPPORT */