BBR 1 Ebene

Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

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borlanic 0:fbdae7e6d805 1 /* mbed Microcontroller Library
borlanic 0:fbdae7e6d805 2 * Copyright (c) 2018 ARM Limited
borlanic 0:fbdae7e6d805 3 *
borlanic 0:fbdae7e6d805 4 * Licensed under the Apache License, Version 2.0 (the "License");
borlanic 0:fbdae7e6d805 5 * you may not use this file except in compliance with the License.
borlanic 0:fbdae7e6d805 6 * You may obtain a copy of the License at
borlanic 0:fbdae7e6d805 7 *
borlanic 0:fbdae7e6d805 8 * http://www.apache.org/licenses/LICENSE-2.0
borlanic 0:fbdae7e6d805 9 *
borlanic 0:fbdae7e6d805 10 * Unless required by applicable law or agreed to in writing, software
borlanic 0:fbdae7e6d805 11 * distributed under the License is distributed on an "AS IS" BASIS,
borlanic 0:fbdae7e6d805 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
borlanic 0:fbdae7e6d805 13 * See the License for the specific language governing permissions and
borlanic 0:fbdae7e6d805 14 * limitations under the License.
borlanic 0:fbdae7e6d805 15 */
borlanic 0:fbdae7e6d805 16 #ifndef RTE_COMPONENTS_H
borlanic 0:fbdae7e6d805 17 #define RTE_COMPONENTS_H
borlanic 0:fbdae7e6d805 18
borlanic 0:fbdae7e6d805 19 #define CMSIS_device_header <cmsis.h>
borlanic 0:fbdae7e6d805 20
borlanic 0:fbdae7e6d805 21 #ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE
borlanic 0:fbdae7e6d805 22 #define MBED_CONF_TZ_PROCESS_STACK_SIZE 512
borlanic 0:fbdae7e6d805 23 #endif
borlanic 0:fbdae7e6d805 24 #ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS
borlanic 0:fbdae7e6d805 25 #define MBED_CONF_TZ_PROCESS_STACK_SLOTS 8
borlanic 0:fbdae7e6d805 26 #endif
borlanic 0:fbdae7e6d805 27
borlanic 0:fbdae7e6d805 28 #define TZ_PROCESS_STACK_SLOTS MBED_CONF_TZ_PROCESS_STACK_SLOTS
borlanic 0:fbdae7e6d805 29 #define TZ_PROCESS_STACK_SIZE MBED_CONF_TZ_PROCESS_STACK_SIZE
borlanic 0:fbdae7e6d805 30
borlanic 0:fbdae7e6d805 31 #endif
borlanic 0:fbdae7e6d805 32
borlanic 0:fbdae7e6d805 33