Nicolas Borla / Mbed OS BBR_1Ebene

BBR 1 Ebene

EncoderCounter.cpp@0:fbdae7e6d805, 2018-05-14 (annotated)

Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:fbdae7e6d805 1 /*
borlanic 0:fbdae7e6d805 2 * EncoderCounter.cpp
borlanic 0:fbdae7e6d805 3 * Copyright (c) 2018, ZHAW
borlanic 0:fbdae7e6d805 4 * All rights reserved.
borlanic 0:fbdae7e6d805 5 */
borlanic 0:fbdae7e6d805 6
borlanic 0:fbdae7e6d805 7 #include "EncoderCounter.h"
borlanic 0:fbdae7e6d805 8
borlanic 0:fbdae7e6d805 9 using namespace std;
borlanic 0:fbdae7e6d805 10
borlanic 0:fbdae7e6d805 11 /**
borlanic 0:fbdae7e6d805 12 * Creates and initializes the driver to read the quadrature
borlanic 0:fbdae7e6d805 13 * encoder counter of the STM32 microcontroller.
borlanic 0:fbdae7e6d805 14 * @param a the input pin for the channel A.
borlanic 0:fbdae7e6d805 15 * @param b the input pin for the channel B.
borlanic 0:fbdae7e6d805 16 */
borlanic 0:fbdae7e6d805 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
borlanic 0:fbdae7e6d805 18
borlanic 0:fbdae7e6d805 19 // check pins
borlanic 0:fbdae7e6d805 20
borlanic 0:fbdae7e6d805 21 if ((a == PA_1) && (b == PA_0)) {
borlanic 0:fbdae7e6d805 22
borlanic 0:fbdae7e6d805 23 // pinmap OK for TIM2 CH1 and CH2
borlanic 0:fbdae7e6d805 24
borlanic 0:fbdae7e6d805 25 TIM = TIM2;
borlanic 0:fbdae7e6d805 26
borlanic 0:fbdae7e6d805 27 // configure general purpose I/O registers
borlanic 0:fbdae7e6d805 28
borlanic 0:fbdae7e6d805 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
borlanic 0:fbdae7e6d805 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
borlanic 0:fbdae7e6d805 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
borlanic 0:fbdae7e6d805 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
borlanic 0:fbdae7e6d805 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
borlanic 0:fbdae7e6d805 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
borlanic 0:fbdae7e6d805 35
borlanic 0:fbdae7e6d805 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
borlanic 0:fbdae7e6d805 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
borlanic 0:fbdae7e6d805 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
borlanic 0:fbdae7e6d805 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
borlanic 0:fbdae7e6d805 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
borlanic 0:fbdae7e6d805 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
borlanic 0:fbdae7e6d805 42
borlanic 0:fbdae7e6d805 43 // configure reset and clock control registers
borlanic 0:fbdae7e6d805 44
borlanic 0:fbdae7e6d805 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
borlanic 0:fbdae7e6d805 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
borlanic 0:fbdae7e6d805 47
borlanic 0:fbdae7e6d805 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
borlanic 0:fbdae7e6d805 49
borlanic 0:fbdae7e6d805 50 } else if ((a == PA_6) && (b == PC_7)) {
borlanic 0:fbdae7e6d805 51
borlanic 0:fbdae7e6d805 52 // pinmap OK for TIM3 CH1 and CH2
borlanic 0:fbdae7e6d805 53
borlanic 0:fbdae7e6d805 54 TIM = TIM3;
borlanic 0:fbdae7e6d805 55
borlanic 0:fbdae7e6d805 56 // configure reset and clock control registers
borlanic 0:fbdae7e6d805 57
borlanic 0:fbdae7e6d805 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
borlanic 0:fbdae7e6d805 59
borlanic 0:fbdae7e6d805 60 // configure general purpose I/O registers
borlanic 0:fbdae7e6d805 61
borlanic 0:fbdae7e6d805 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
borlanic 0:fbdae7e6d805 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
borlanic 0:fbdae7e6d805 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
borlanic 0:fbdae7e6d805 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
borlanic 0:fbdae7e6d805 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
borlanic 0:fbdae7e6d805 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
borlanic 0:fbdae7e6d805 68
borlanic 0:fbdae7e6d805 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
borlanic 0:fbdae7e6d805 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
borlanic 0:fbdae7e6d805 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
borlanic 0:fbdae7e6d805 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
borlanic 0:fbdae7e6d805 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
borlanic 0:fbdae7e6d805 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
borlanic 0:fbdae7e6d805 75
borlanic 0:fbdae7e6d805 76 // configure reset and clock control registers
borlanic 0:fbdae7e6d805 77
borlanic 0:fbdae7e6d805 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
borlanic 0:fbdae7e6d805 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
borlanic 0:fbdae7e6d805 80
borlanic 0:fbdae7e6d805 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
borlanic 0:fbdae7e6d805 82
borlanic 0:fbdae7e6d805 83 } else if ((a == PB_6) && (b == PB_7)) {
borlanic 0:fbdae7e6d805 84
borlanic 0:fbdae7e6d805 85 // pinmap OK for TIM4 CH1 and CH2
borlanic 0:fbdae7e6d805 86
borlanic 0:fbdae7e6d805 87 TIM = TIM4;
borlanic 0:fbdae7e6d805 88
borlanic 0:fbdae7e6d805 89 // configure reset and clock control registers
borlanic 0:fbdae7e6d805 90
borlanic 0:fbdae7e6d805 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
borlanic 0:fbdae7e6d805 92
borlanic 0:fbdae7e6d805 93 // configure general purpose I/O registers
borlanic 0:fbdae7e6d805 94
borlanic 0:fbdae7e6d805 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
borlanic 0:fbdae7e6d805 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
borlanic 0:fbdae7e6d805 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
borlanic 0:fbdae7e6d805 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
borlanic 0:fbdae7e6d805 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
borlanic 0:fbdae7e6d805 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
borlanic 0:fbdae7e6d805 101
borlanic 0:fbdae7e6d805 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
borlanic 0:fbdae7e6d805 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
borlanic 0:fbdae7e6d805 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
borlanic 0:fbdae7e6d805 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
borlanic 0:fbdae7e6d805 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
borlanic 0:fbdae7e6d805 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
borlanic 0:fbdae7e6d805 108
borlanic 0:fbdae7e6d805 109 // configure reset and clock control registers
borlanic 0:fbdae7e6d805 110
borlanic 0:fbdae7e6d805 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
borlanic 0:fbdae7e6d805 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
borlanic 0:fbdae7e6d805 113
borlanic 0:fbdae7e6d805 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
borlanic 0:fbdae7e6d805 115
borlanic 0:fbdae7e6d805 116 } else {
borlanic 0:fbdae7e6d805 117
borlanic 0:fbdae7e6d805 118 printf("pinmap not found for peripheral\n");
borlanic 0:fbdae7e6d805 119 }
borlanic 0:fbdae7e6d805 120
borlanic 0:fbdae7e6d805 121 // configure general purpose timer 3 or 4
borlanic 0:fbdae7e6d805 122
borlanic 0:fbdae7e6d805 123 TIM->CR1 = 0x0000; // counter disable
borlanic 0:fbdae7e6d805 124 TIM->CR2 = 0x0000; // reset master mode selection
borlanic 0:fbdae7e6d805 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
borlanic 0:fbdae7e6d805 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
borlanic 0:fbdae7e6d805 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
borlanic 0:fbdae7e6d805 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
borlanic 0:fbdae7e6d805 129 TIM->CNT = 0x0000; // reset counter value
borlanic 0:fbdae7e6d805 130 TIM->ARR = 0xFFFF; // auto reload register
borlanic 0:fbdae7e6d805 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
borlanic 0:fbdae7e6d805 132 }
borlanic 0:fbdae7e6d805 133
borlanic 0:fbdae7e6d805 134 EncoderCounter::~EncoderCounter() {}
borlanic 0:fbdae7e6d805 135
borlanic 0:fbdae7e6d805 136 /**
borlanic 0:fbdae7e6d805 137 * Resets the counter value to zero.
borlanic 0:fbdae7e6d805 138 */
borlanic 0:fbdae7e6d805 139 void EncoderCounter::reset() {
borlanic 0:fbdae7e6d805 140
borlanic 0:fbdae7e6d805 141 TIM->CNT = 0x0000;
borlanic 0:fbdae7e6d805 142 }
borlanic 0:fbdae7e6d805 143
borlanic 0:fbdae7e6d805 144 /**
borlanic 0:fbdae7e6d805 145 * Resets the counter value to a given offset value.
borlanic 0:fbdae7e6d805 146 * @param offset the offset value to reset the counter to.
borlanic 0:fbdae7e6d805 147 */
borlanic 0:fbdae7e6d805 148 void EncoderCounter::reset(int16_t offset) {
borlanic 0:fbdae7e6d805 149
borlanic 0:fbdae7e6d805 150 TIM->CNT = -offset;
borlanic 0:fbdae7e6d805 151 }
borlanic 0:fbdae7e6d805 152
borlanic 0:fbdae7e6d805 153 /**
borlanic 0:fbdae7e6d805 154 * Reads the quadrature encoder counter value.
borlanic 0:fbdae7e6d805 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
borlanic 0:fbdae7e6d805 156 */
borlanic 0:fbdae7e6d805 157 int16_t EncoderCounter::read() {
borlanic 0:fbdae7e6d805 158
borlanic 0:fbdae7e6d805 159 return static_cast<int16_t>(-TIM->CNT);
borlanic 0:fbdae7e6d805 160 }
borlanic 0:fbdae7e6d805 161
borlanic 0:fbdae7e6d805 162 /**
borlanic 0:fbdae7e6d805 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
borlanic 0:fbdae7e6d805 164 */
borlanic 0:fbdae7e6d805 165 EncoderCounter::operator int16_t() {
borlanic 0:fbdae7e6d805 166
borlanic 0:fbdae7e6d805 167 return read();
borlanic 0:fbdae7e6d805 168 }
borlanic 0:fbdae7e6d805 169
borlanic 0:fbdae7e6d805 170
borlanic 0:fbdae7e6d805 171