Lee Shen / FTHR_USB_serial_qSPI

max32630fthr quad spi , unexpected spi behavior

FTHR_USB_serial/mbed-os/cmsis/core_cm4.h@0:a35c40f49345, 2018-03-13 (annotated)

Committer:
boonshen
Date:
Tue Mar 13 21:12:00 2018 +0000
Revision:
0:a35c40f49345
MAX32630FTHR QuadSPI test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
boonshen 0:a35c40f49345 1 /**************************************************************************//**
boonshen 0:a35c40f49345 2 * @file core_cm4.h
boonshen 0:a35c40f49345 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
boonshen 0:a35c40f49345 4 * @version V5.0.2
boonshen 0:a35c40f49345 5 * @date 13. February 2017
boonshen 0:a35c40f49345 6 ******************************************************************************/
boonshen 0:a35c40f49345 7 /*
boonshen 0:a35c40f49345 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
boonshen 0:a35c40f49345 9 *
boonshen 0:a35c40f49345 10 * SPDX-License-Identifier: Apache-2.0
boonshen 0:a35c40f49345 11 *
boonshen 0:a35c40f49345 12 * Licensed under the Apache License, Version 2.0 (the License); you may
boonshen 0:a35c40f49345 13 * not use this file except in compliance with the License.
boonshen 0:a35c40f49345 14 * You may obtain a copy of the License at
boonshen 0:a35c40f49345 15 *
boonshen 0:a35c40f49345 16 * www.apache.org/licenses/LICENSE-2.0
boonshen 0:a35c40f49345 17 *
boonshen 0:a35c40f49345 18 * Unless required by applicable law or agreed to in writing, software
boonshen 0:a35c40f49345 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
boonshen 0:a35c40f49345 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
boonshen 0:a35c40f49345 21 * See the License for the specific language governing permissions and
boonshen 0:a35c40f49345 22 * limitations under the License.
boonshen 0:a35c40f49345 23 */
boonshen 0:a35c40f49345 24
boonshen 0:a35c40f49345 25 #if defined ( __ICCARM__ )
boonshen 0:a35c40f49345 26 #pragma system_include /* treat file as system include file for MISRA check */
boonshen 0:a35c40f49345 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen 0:a35c40f49345 28 #pragma clang system_header /* treat file as system include file */
boonshen 0:a35c40f49345 29 #endif
boonshen 0:a35c40f49345 30
boonshen 0:a35c40f49345 31 #ifndef __CORE_CM4_H_GENERIC
boonshen 0:a35c40f49345 32 #define __CORE_CM4_H_GENERIC
boonshen 0:a35c40f49345 33
boonshen 0:a35c40f49345 34 #include <stdint.h>
boonshen 0:a35c40f49345 35
boonshen 0:a35c40f49345 36 #ifdef __cplusplus
boonshen 0:a35c40f49345 37 extern "C" {
boonshen 0:a35c40f49345 38 #endif
boonshen 0:a35c40f49345 39
boonshen 0:a35c40f49345 40 /**
boonshen 0:a35c40f49345 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
boonshen 0:a35c40f49345 42 CMSIS violates the following MISRA-C:2004 rules:
boonshen 0:a35c40f49345 43
boonshen 0:a35c40f49345 44 \li Required Rule 8.5, object/function definition in header file.<br>
boonshen 0:a35c40f49345 45 Function definitions in header files are used to allow 'inlining'.
boonshen 0:a35c40f49345 46
boonshen 0:a35c40f49345 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
boonshen 0:a35c40f49345 48 Unions are used for effective representation of core registers.
boonshen 0:a35c40f49345 49
boonshen 0:a35c40f49345 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
boonshen 0:a35c40f49345 51 Function-like macros are used to allow more efficient code.
boonshen 0:a35c40f49345 52 */
boonshen 0:a35c40f49345 53
boonshen 0:a35c40f49345 54
boonshen 0:a35c40f49345 55 /*******************************************************************************
boonshen 0:a35c40f49345 56 * CMSIS definitions
boonshen 0:a35c40f49345 57 ******************************************************************************/
boonshen 0:a35c40f49345 58 /**
boonshen 0:a35c40f49345 59 \ingroup Cortex_M4
boonshen 0:a35c40f49345 60 @{
boonshen 0:a35c40f49345 61 */
boonshen 0:a35c40f49345 62
boonshen 0:a35c40f49345 63 /* CMSIS CM4 definitions */
boonshen 0:a35c40f49345 64 #define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
boonshen 0:a35c40f49345 65 #define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
boonshen 0:a35c40f49345 66 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
boonshen 0:a35c40f49345 67 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
boonshen 0:a35c40f49345 68
boonshen 0:a35c40f49345 69 #define __CORTEX_M (4U) /*!< Cortex-M Core */
boonshen 0:a35c40f49345 70
boonshen 0:a35c40f49345 71 /** __FPU_USED indicates whether an FPU is used or not.
boonshen 0:a35c40f49345 72 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
boonshen 0:a35c40f49345 73 */
boonshen 0:a35c40f49345 74 #if defined ( __CC_ARM )
boonshen 0:a35c40f49345 75 #if defined __TARGET_FPU_VFP
boonshen 0:a35c40f49345 76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen 0:a35c40f49345 77 #define __FPU_USED 1U
boonshen 0:a35c40f49345 78 #else
boonshen 0:a35c40f49345 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 80 #define __FPU_USED 0U
boonshen 0:a35c40f49345 81 #endif
boonshen 0:a35c40f49345 82 #else
boonshen 0:a35c40f49345 83 #define __FPU_USED 0U
boonshen 0:a35c40f49345 84 #endif
boonshen 0:a35c40f49345 85
boonshen 0:a35c40f49345 86 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen 0:a35c40f49345 87 #if defined __ARM_PCS_VFP
boonshen 0:a35c40f49345 88 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen 0:a35c40f49345 89 #define __FPU_USED 1U
boonshen 0:a35c40f49345 90 #else
boonshen 0:a35c40f49345 91 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 92 #define __FPU_USED 0U
boonshen 0:a35c40f49345 93 #endif
boonshen 0:a35c40f49345 94 #else
boonshen 0:a35c40f49345 95 #define __FPU_USED 0U
boonshen 0:a35c40f49345 96 #endif
boonshen 0:a35c40f49345 97
boonshen 0:a35c40f49345 98 #elif defined ( __GNUC__ )
boonshen 0:a35c40f49345 99 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
boonshen 0:a35c40f49345 100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen 0:a35c40f49345 101 #define __FPU_USED 1U
boonshen 0:a35c40f49345 102 #else
boonshen 0:a35c40f49345 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 104 #define __FPU_USED 0U
boonshen 0:a35c40f49345 105 #endif
boonshen 0:a35c40f49345 106 #else
boonshen 0:a35c40f49345 107 #define __FPU_USED 0U
boonshen 0:a35c40f49345 108 #endif
boonshen 0:a35c40f49345 109
boonshen 0:a35c40f49345 110 #elif defined ( __ICCARM__ )
boonshen 0:a35c40f49345 111 #if defined __ARMVFP__
boonshen 0:a35c40f49345 112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen 0:a35c40f49345 113 #define __FPU_USED 1U
boonshen 0:a35c40f49345 114 #else
boonshen 0:a35c40f49345 115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 116 #define __FPU_USED 0U
boonshen 0:a35c40f49345 117 #endif
boonshen 0:a35c40f49345 118 #else
boonshen 0:a35c40f49345 119 #define __FPU_USED 0U
boonshen 0:a35c40f49345 120 #endif
boonshen 0:a35c40f49345 121
boonshen 0:a35c40f49345 122 #elif defined ( __TI_ARM__ )
boonshen 0:a35c40f49345 123 #if defined __TI_VFP_SUPPORT__
boonshen 0:a35c40f49345 124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen 0:a35c40f49345 125 #define __FPU_USED 1U
boonshen 0:a35c40f49345 126 #else
boonshen 0:a35c40f49345 127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 128 #define __FPU_USED 0U
boonshen 0:a35c40f49345 129 #endif
boonshen 0:a35c40f49345 130 #else
boonshen 0:a35c40f49345 131 #define __FPU_USED 0U
boonshen 0:a35c40f49345 132 #endif
boonshen 0:a35c40f49345 133
boonshen 0:a35c40f49345 134 #elif defined ( __TASKING__ )
boonshen 0:a35c40f49345 135 #if defined __FPU_VFP__
boonshen 0:a35c40f49345 136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen 0:a35c40f49345 137 #define __FPU_USED 1U
boonshen 0:a35c40f49345 138 #else
boonshen 0:a35c40f49345 139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 140 #define __FPU_USED 0U
boonshen 0:a35c40f49345 141 #endif
boonshen 0:a35c40f49345 142 #else
boonshen 0:a35c40f49345 143 #define __FPU_USED 0U
boonshen 0:a35c40f49345 144 #endif
boonshen 0:a35c40f49345 145
boonshen 0:a35c40f49345 146 #elif defined ( __CSMC__ )
boonshen 0:a35c40f49345 147 #if ( __CSMC__ & 0x400U)
boonshen 0:a35c40f49345 148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen 0:a35c40f49345 149 #define __FPU_USED 1U
boonshen 0:a35c40f49345 150 #else
boonshen 0:a35c40f49345 151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 152 #define __FPU_USED 0U
boonshen 0:a35c40f49345 153 #endif
boonshen 0:a35c40f49345 154 #else
boonshen 0:a35c40f49345 155 #define __FPU_USED 0U
boonshen 0:a35c40f49345 156 #endif
boonshen 0:a35c40f49345 157
boonshen 0:a35c40f49345 158 #endif
boonshen 0:a35c40f49345 159
boonshen 0:a35c40f49345 160 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
boonshen 0:a35c40f49345 161
boonshen 0:a35c40f49345 162
boonshen 0:a35c40f49345 163 #ifdef __cplusplus
boonshen 0:a35c40f49345 164 }
boonshen 0:a35c40f49345 165 #endif
boonshen 0:a35c40f49345 166
boonshen 0:a35c40f49345 167 #endif /* __CORE_CM4_H_GENERIC */
boonshen 0:a35c40f49345 168
boonshen 0:a35c40f49345 169 #ifndef __CMSIS_GENERIC
boonshen 0:a35c40f49345 170
boonshen 0:a35c40f49345 171 #ifndef __CORE_CM4_H_DEPENDANT
boonshen 0:a35c40f49345 172 #define __CORE_CM4_H_DEPENDANT
boonshen 0:a35c40f49345 173
boonshen 0:a35c40f49345 174 #ifdef __cplusplus
boonshen 0:a35c40f49345 175 extern "C" {
boonshen 0:a35c40f49345 176 #endif
boonshen 0:a35c40f49345 177
boonshen 0:a35c40f49345 178 /* check device defines and use defaults */
boonshen 0:a35c40f49345 179 #if defined __CHECK_DEVICE_DEFINES
boonshen 0:a35c40f49345 180 #ifndef __CM4_REV
boonshen 0:a35c40f49345 181 #define __CM4_REV 0x0000U
boonshen 0:a35c40f49345 182 #warning "__CM4_REV not defined in device header file; using default!"
boonshen 0:a35c40f49345 183 #endif
boonshen 0:a35c40f49345 184
boonshen 0:a35c40f49345 185 #ifndef __FPU_PRESENT
boonshen 0:a35c40f49345 186 #define __FPU_PRESENT 0U
boonshen 0:a35c40f49345 187 #warning "__FPU_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 188 #endif
boonshen 0:a35c40f49345 189
boonshen 0:a35c40f49345 190 #ifndef __MPU_PRESENT
boonshen 0:a35c40f49345 191 #define __MPU_PRESENT 0U
boonshen 0:a35c40f49345 192 #warning "__MPU_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 193 #endif
boonshen 0:a35c40f49345 194
boonshen 0:a35c40f49345 195 #ifndef __NVIC_PRIO_BITS
boonshen 0:a35c40f49345 196 #define __NVIC_PRIO_BITS 3U
boonshen 0:a35c40f49345 197 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
boonshen 0:a35c40f49345 198 #endif
boonshen 0:a35c40f49345 199
boonshen 0:a35c40f49345 200 #ifndef __Vendor_SysTickConfig
boonshen 0:a35c40f49345 201 #define __Vendor_SysTickConfig 0U
boonshen 0:a35c40f49345 202 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
boonshen 0:a35c40f49345 203 #endif
boonshen 0:a35c40f49345 204 #endif
boonshen 0:a35c40f49345 205
boonshen 0:a35c40f49345 206 /* IO definitions (access restrictions to peripheral registers) */
boonshen 0:a35c40f49345 207 /**
boonshen 0:a35c40f49345 208 \defgroup CMSIS_glob_defs CMSIS Global Defines
boonshen 0:a35c40f49345 209
boonshen 0:a35c40f49345 210 <strong>IO Type Qualifiers</strong> are used
boonshen 0:a35c40f49345 211 \li to specify the access to peripheral variables.
boonshen 0:a35c40f49345 212 \li for automatic generation of peripheral register debug information.
boonshen 0:a35c40f49345 213 */
boonshen 0:a35c40f49345 214 #ifdef __cplusplus
boonshen 0:a35c40f49345 215 #define __I volatile /*!< Defines 'read only' permissions */
boonshen 0:a35c40f49345 216 #else
boonshen 0:a35c40f49345 217 #define __I volatile const /*!< Defines 'read only' permissions */
boonshen 0:a35c40f49345 218 #endif
boonshen 0:a35c40f49345 219 #define __O volatile /*!< Defines 'write only' permissions */
boonshen 0:a35c40f49345 220 #define __IO volatile /*!< Defines 'read / write' permissions */
boonshen 0:a35c40f49345 221
boonshen 0:a35c40f49345 222 /* following defines should be used for structure members */
boonshen 0:a35c40f49345 223 #define __IM volatile const /*! Defines 'read only' structure member permissions */
boonshen 0:a35c40f49345 224 #define __OM volatile /*! Defines 'write only' structure member permissions */
boonshen 0:a35c40f49345 225 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
boonshen 0:a35c40f49345 226
boonshen 0:a35c40f49345 227 /*@} end of group Cortex_M4 */
boonshen 0:a35c40f49345 228
boonshen 0:a35c40f49345 229
boonshen 0:a35c40f49345 230
boonshen 0:a35c40f49345 231 /*******************************************************************************
boonshen 0:a35c40f49345 232 * Register Abstraction
boonshen 0:a35c40f49345 233 Core Register contain:
boonshen 0:a35c40f49345 234 - Core Register
boonshen 0:a35c40f49345 235 - Core NVIC Register
boonshen 0:a35c40f49345 236 - Core SCB Register
boonshen 0:a35c40f49345 237 - Core SysTick Register
boonshen 0:a35c40f49345 238 - Core Debug Register
boonshen 0:a35c40f49345 239 - Core MPU Register
boonshen 0:a35c40f49345 240 - Core FPU Register
boonshen 0:a35c40f49345 241 ******************************************************************************/
boonshen 0:a35c40f49345 242 /**
boonshen 0:a35c40f49345 243 \defgroup CMSIS_core_register Defines and Type Definitions
boonshen 0:a35c40f49345 244 \brief Type definitions and defines for Cortex-M processor based devices.
boonshen 0:a35c40f49345 245 */
boonshen 0:a35c40f49345 246
boonshen 0:a35c40f49345 247 /**
boonshen 0:a35c40f49345 248 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 249 \defgroup CMSIS_CORE Status and Control Registers
boonshen 0:a35c40f49345 250 \brief Core Register type definitions.
boonshen 0:a35c40f49345 251 @{
boonshen 0:a35c40f49345 252 */
boonshen 0:a35c40f49345 253
boonshen 0:a35c40f49345 254 /**
boonshen 0:a35c40f49345 255 \brief Union type to access the Application Program Status Register (APSR).
boonshen 0:a35c40f49345 256 */
boonshen 0:a35c40f49345 257 typedef union
boonshen 0:a35c40f49345 258 {
boonshen 0:a35c40f49345 259 struct
boonshen 0:a35c40f49345 260 {
boonshen 0:a35c40f49345 261 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
boonshen 0:a35c40f49345 262 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
boonshen 0:a35c40f49345 263 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
boonshen 0:a35c40f49345 264 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
boonshen 0:a35c40f49345 265 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
boonshen 0:a35c40f49345 266 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
boonshen 0:a35c40f49345 267 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
boonshen 0:a35c40f49345 268 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
boonshen 0:a35c40f49345 269 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 270 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 271 } APSR_Type;
boonshen 0:a35c40f49345 272
boonshen 0:a35c40f49345 273 /* APSR Register Definitions */
boonshen 0:a35c40f49345 274 #define APSR_N_Pos 31U /*!< APSR: N Position */
boonshen 0:a35c40f49345 275 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
boonshen 0:a35c40f49345 276
boonshen 0:a35c40f49345 277 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
boonshen 0:a35c40f49345 278 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
boonshen 0:a35c40f49345 279
boonshen 0:a35c40f49345 280 #define APSR_C_Pos 29U /*!< APSR: C Position */
boonshen 0:a35c40f49345 281 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
boonshen 0:a35c40f49345 282
boonshen 0:a35c40f49345 283 #define APSR_V_Pos 28U /*!< APSR: V Position */
boonshen 0:a35c40f49345 284 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
boonshen 0:a35c40f49345 285
boonshen 0:a35c40f49345 286 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
boonshen 0:a35c40f49345 287 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
boonshen 0:a35c40f49345 288
boonshen 0:a35c40f49345 289 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
boonshen 0:a35c40f49345 290 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
boonshen 0:a35c40f49345 291
boonshen 0:a35c40f49345 292
boonshen 0:a35c40f49345 293 /**
boonshen 0:a35c40f49345 294 \brief Union type to access the Interrupt Program Status Register (IPSR).
boonshen 0:a35c40f49345 295 */
boonshen 0:a35c40f49345 296 typedef union
boonshen 0:a35c40f49345 297 {
boonshen 0:a35c40f49345 298 struct
boonshen 0:a35c40f49345 299 {
boonshen 0:a35c40f49345 300 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
boonshen 0:a35c40f49345 301 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
boonshen 0:a35c40f49345 302 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 303 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 304 } IPSR_Type;
boonshen 0:a35c40f49345 305
boonshen 0:a35c40f49345 306 /* IPSR Register Definitions */
boonshen 0:a35c40f49345 307 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
boonshen 0:a35c40f49345 308 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
boonshen 0:a35c40f49345 309
boonshen 0:a35c40f49345 310
boonshen 0:a35c40f49345 311 /**
boonshen 0:a35c40f49345 312 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
boonshen 0:a35c40f49345 313 */
boonshen 0:a35c40f49345 314 typedef union
boonshen 0:a35c40f49345 315 {
boonshen 0:a35c40f49345 316 struct
boonshen 0:a35c40f49345 317 {
boonshen 0:a35c40f49345 318 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
boonshen 0:a35c40f49345 319 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
boonshen 0:a35c40f49345 320 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
boonshen 0:a35c40f49345 321 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
boonshen 0:a35c40f49345 322 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
boonshen 0:a35c40f49345 323 uint32_t T:1; /*!< bit: 24 Thumb bit */
boonshen 0:a35c40f49345 324 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
boonshen 0:a35c40f49345 325 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
boonshen 0:a35c40f49345 326 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
boonshen 0:a35c40f49345 327 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
boonshen 0:a35c40f49345 328 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
boonshen 0:a35c40f49345 329 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
boonshen 0:a35c40f49345 330 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 331 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 332 } xPSR_Type;
boonshen 0:a35c40f49345 333
boonshen 0:a35c40f49345 334 /* xPSR Register Definitions */
boonshen 0:a35c40f49345 335 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
boonshen 0:a35c40f49345 336 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
boonshen 0:a35c40f49345 337
boonshen 0:a35c40f49345 338 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
boonshen 0:a35c40f49345 339 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
boonshen 0:a35c40f49345 340
boonshen 0:a35c40f49345 341 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
boonshen 0:a35c40f49345 342 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
boonshen 0:a35c40f49345 343
boonshen 0:a35c40f49345 344 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
boonshen 0:a35c40f49345 345 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
boonshen 0:a35c40f49345 346
boonshen 0:a35c40f49345 347 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
boonshen 0:a35c40f49345 348 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
boonshen 0:a35c40f49345 349
boonshen 0:a35c40f49345 350 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
boonshen 0:a35c40f49345 351 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
boonshen 0:a35c40f49345 352
boonshen 0:a35c40f49345 353 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
boonshen 0:a35c40f49345 354 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
boonshen 0:a35c40f49345 355
boonshen 0:a35c40f49345 356 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
boonshen 0:a35c40f49345 357 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
boonshen 0:a35c40f49345 358
boonshen 0:a35c40f49345 359 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
boonshen 0:a35c40f49345 360 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
boonshen 0:a35c40f49345 361
boonshen 0:a35c40f49345 362 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
boonshen 0:a35c40f49345 363 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
boonshen 0:a35c40f49345 364
boonshen 0:a35c40f49345 365
boonshen 0:a35c40f49345 366 /**
boonshen 0:a35c40f49345 367 \brief Union type to access the Control Registers (CONTROL).
boonshen 0:a35c40f49345 368 */
boonshen 0:a35c40f49345 369 typedef union
boonshen 0:a35c40f49345 370 {
boonshen 0:a35c40f49345 371 struct
boonshen 0:a35c40f49345 372 {
boonshen 0:a35c40f49345 373 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
boonshen 0:a35c40f49345 374 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
boonshen 0:a35c40f49345 375 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
boonshen 0:a35c40f49345 376 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
boonshen 0:a35c40f49345 377 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 378 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 379 } CONTROL_Type;
boonshen 0:a35c40f49345 380
boonshen 0:a35c40f49345 381 /* CONTROL Register Definitions */
boonshen 0:a35c40f49345 382 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
boonshen 0:a35c40f49345 383 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
boonshen 0:a35c40f49345 384
boonshen 0:a35c40f49345 385 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
boonshen 0:a35c40f49345 386 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
boonshen 0:a35c40f49345 387
boonshen 0:a35c40f49345 388 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
boonshen 0:a35c40f49345 389 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
boonshen 0:a35c40f49345 390
boonshen 0:a35c40f49345 391 /*@} end of group CMSIS_CORE */
boonshen 0:a35c40f49345 392
boonshen 0:a35c40f49345 393
boonshen 0:a35c40f49345 394 /**
boonshen 0:a35c40f49345 395 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 396 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
boonshen 0:a35c40f49345 397 \brief Type definitions for the NVIC Registers
boonshen 0:a35c40f49345 398 @{
boonshen 0:a35c40f49345 399 */
boonshen 0:a35c40f49345 400
boonshen 0:a35c40f49345 401 /**
boonshen 0:a35c40f49345 402 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
boonshen 0:a35c40f49345 403 */
boonshen 0:a35c40f49345 404 typedef struct
boonshen 0:a35c40f49345 405 {
boonshen 0:a35c40f49345 406 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
boonshen 0:a35c40f49345 407 uint32_t RESERVED0[24U];
boonshen 0:a35c40f49345 408 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
boonshen 0:a35c40f49345 409 uint32_t RSERVED1[24U];
boonshen 0:a35c40f49345 410 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
boonshen 0:a35c40f49345 411 uint32_t RESERVED2[24U];
boonshen 0:a35c40f49345 412 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
boonshen 0:a35c40f49345 413 uint32_t RESERVED3[24U];
boonshen 0:a35c40f49345 414 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
boonshen 0:a35c40f49345 415 uint32_t RESERVED4[56U];
boonshen 0:a35c40f49345 416 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
boonshen 0:a35c40f49345 417 uint32_t RESERVED5[644U];
boonshen 0:a35c40f49345 418 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
boonshen 0:a35c40f49345 419 } NVIC_Type;
boonshen 0:a35c40f49345 420
boonshen 0:a35c40f49345 421 /* Software Triggered Interrupt Register Definitions */
boonshen 0:a35c40f49345 422 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
boonshen 0:a35c40f49345 423 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
boonshen 0:a35c40f49345 424
boonshen 0:a35c40f49345 425 /*@} end of group CMSIS_NVIC */
boonshen 0:a35c40f49345 426
boonshen 0:a35c40f49345 427
boonshen 0:a35c40f49345 428 /**
boonshen 0:a35c40f49345 429 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 430 \defgroup CMSIS_SCB System Control Block (SCB)
boonshen 0:a35c40f49345 431 \brief Type definitions for the System Control Block Registers
boonshen 0:a35c40f49345 432 @{
boonshen 0:a35c40f49345 433 */
boonshen 0:a35c40f49345 434
boonshen 0:a35c40f49345 435 /**
boonshen 0:a35c40f49345 436 \brief Structure type to access the System Control Block (SCB).
boonshen 0:a35c40f49345 437 */
boonshen 0:a35c40f49345 438 typedef struct
boonshen 0:a35c40f49345 439 {
boonshen 0:a35c40f49345 440 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
boonshen 0:a35c40f49345 441 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
boonshen 0:a35c40f49345 442 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
boonshen 0:a35c40f49345 443 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
boonshen 0:a35c40f49345 444 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
boonshen 0:a35c40f49345 445 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
boonshen 0:a35c40f49345 446 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
boonshen 0:a35c40f49345 447 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
boonshen 0:a35c40f49345 448 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
boonshen 0:a35c40f49345 449 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
boonshen 0:a35c40f49345 450 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
boonshen 0:a35c40f49345 451 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
boonshen 0:a35c40f49345 452 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
boonshen 0:a35c40f49345 453 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
boonshen 0:a35c40f49345 454 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
boonshen 0:a35c40f49345 455 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
boonshen 0:a35c40f49345 456 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
boonshen 0:a35c40f49345 457 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
boonshen 0:a35c40f49345 458 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
boonshen 0:a35c40f49345 459 uint32_t RESERVED0[5U];
boonshen 0:a35c40f49345 460 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
boonshen 0:a35c40f49345 461 } SCB_Type;
boonshen 0:a35c40f49345 462
boonshen 0:a35c40f49345 463 /* SCB CPUID Register Definitions */
boonshen 0:a35c40f49345 464 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
boonshen 0:a35c40f49345 465 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
boonshen 0:a35c40f49345 466
boonshen 0:a35c40f49345 467 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
boonshen 0:a35c40f49345 468 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
boonshen 0:a35c40f49345 469
boonshen 0:a35c40f49345 470 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
boonshen 0:a35c40f49345 471 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
boonshen 0:a35c40f49345 472
boonshen 0:a35c40f49345 473 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
boonshen 0:a35c40f49345 474 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
boonshen 0:a35c40f49345 475
boonshen 0:a35c40f49345 476 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
boonshen 0:a35c40f49345 477 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
boonshen 0:a35c40f49345 478
boonshen 0:a35c40f49345 479 /* SCB Interrupt Control State Register Definitions */
boonshen 0:a35c40f49345 480 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
boonshen 0:a35c40f49345 481 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
boonshen 0:a35c40f49345 482
boonshen 0:a35c40f49345 483 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
boonshen 0:a35c40f49345 484 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
boonshen 0:a35c40f49345 485
boonshen 0:a35c40f49345 486 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
boonshen 0:a35c40f49345 487 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
boonshen 0:a35c40f49345 488
boonshen 0:a35c40f49345 489 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
boonshen 0:a35c40f49345 490 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
boonshen 0:a35c40f49345 491
boonshen 0:a35c40f49345 492 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
boonshen 0:a35c40f49345 493 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
boonshen 0:a35c40f49345 494
boonshen 0:a35c40f49345 495 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
boonshen 0:a35c40f49345 496 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
boonshen 0:a35c40f49345 497
boonshen 0:a35c40f49345 498 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
boonshen 0:a35c40f49345 499 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
boonshen 0:a35c40f49345 500
boonshen 0:a35c40f49345 501 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
boonshen 0:a35c40f49345 502 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
boonshen 0:a35c40f49345 503
boonshen 0:a35c40f49345 504 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
boonshen 0:a35c40f49345 505 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
boonshen 0:a35c40f49345 506
boonshen 0:a35c40f49345 507 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
boonshen 0:a35c40f49345 508 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
boonshen 0:a35c40f49345 509
boonshen 0:a35c40f49345 510 /* SCB Vector Table Offset Register Definitions */
boonshen 0:a35c40f49345 511 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
boonshen 0:a35c40f49345 512 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
boonshen 0:a35c40f49345 513
boonshen 0:a35c40f49345 514 /* SCB Application Interrupt and Reset Control Register Definitions */
boonshen 0:a35c40f49345 515 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
boonshen 0:a35c40f49345 516 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
boonshen 0:a35c40f49345 517
boonshen 0:a35c40f49345 518 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
boonshen 0:a35c40f49345 519 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
boonshen 0:a35c40f49345 520
boonshen 0:a35c40f49345 521 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
boonshen 0:a35c40f49345 522 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
boonshen 0:a35c40f49345 523
boonshen 0:a35c40f49345 524 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
boonshen 0:a35c40f49345 525 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
boonshen 0:a35c40f49345 526
boonshen 0:a35c40f49345 527 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
boonshen 0:a35c40f49345 528 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
boonshen 0:a35c40f49345 529
boonshen 0:a35c40f49345 530 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
boonshen 0:a35c40f49345 531 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
boonshen 0:a35c40f49345 532
boonshen 0:a35c40f49345 533 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
boonshen 0:a35c40f49345 534 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
boonshen 0:a35c40f49345 535
boonshen 0:a35c40f49345 536 /* SCB System Control Register Definitions */
boonshen 0:a35c40f49345 537 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
boonshen 0:a35c40f49345 538 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
boonshen 0:a35c40f49345 539
boonshen 0:a35c40f49345 540 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
boonshen 0:a35c40f49345 541 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
boonshen 0:a35c40f49345 542
boonshen 0:a35c40f49345 543 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
boonshen 0:a35c40f49345 544 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
boonshen 0:a35c40f49345 545
boonshen 0:a35c40f49345 546 /* SCB Configuration Control Register Definitions */
boonshen 0:a35c40f49345 547 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
boonshen 0:a35c40f49345 548 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
boonshen 0:a35c40f49345 549
boonshen 0:a35c40f49345 550 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
boonshen 0:a35c40f49345 551 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
boonshen 0:a35c40f49345 552
boonshen 0:a35c40f49345 553 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
boonshen 0:a35c40f49345 554 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
boonshen 0:a35c40f49345 555
boonshen 0:a35c40f49345 556 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
boonshen 0:a35c40f49345 557 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
boonshen 0:a35c40f49345 558
boonshen 0:a35c40f49345 559 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
boonshen 0:a35c40f49345 560 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
boonshen 0:a35c40f49345 561
boonshen 0:a35c40f49345 562 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
boonshen 0:a35c40f49345 563 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
boonshen 0:a35c40f49345 564
boonshen 0:a35c40f49345 565 /* SCB System Handler Control and State Register Definitions */
boonshen 0:a35c40f49345 566 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
boonshen 0:a35c40f49345 567 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
boonshen 0:a35c40f49345 568
boonshen 0:a35c40f49345 569 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
boonshen 0:a35c40f49345 570 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
boonshen 0:a35c40f49345 571
boonshen 0:a35c40f49345 572 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
boonshen 0:a35c40f49345 573 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
boonshen 0:a35c40f49345 574
boonshen 0:a35c40f49345 575 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
boonshen 0:a35c40f49345 576 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
boonshen 0:a35c40f49345 577
boonshen 0:a35c40f49345 578 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
boonshen 0:a35c40f49345 579 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
boonshen 0:a35c40f49345 580
boonshen 0:a35c40f49345 581 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
boonshen 0:a35c40f49345 582 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
boonshen 0:a35c40f49345 583
boonshen 0:a35c40f49345 584 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
boonshen 0:a35c40f49345 585 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
boonshen 0:a35c40f49345 586
boonshen 0:a35c40f49345 587 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
boonshen 0:a35c40f49345 588 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
boonshen 0:a35c40f49345 589
boonshen 0:a35c40f49345 590 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
boonshen 0:a35c40f49345 591 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
boonshen 0:a35c40f49345 592
boonshen 0:a35c40f49345 593 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
boonshen 0:a35c40f49345 594 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
boonshen 0:a35c40f49345 595
boonshen 0:a35c40f49345 596 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
boonshen 0:a35c40f49345 597 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
boonshen 0:a35c40f49345 598
boonshen 0:a35c40f49345 599 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
boonshen 0:a35c40f49345 600 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
boonshen 0:a35c40f49345 601
boonshen 0:a35c40f49345 602 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
boonshen 0:a35c40f49345 603 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
boonshen 0:a35c40f49345 604
boonshen 0:a35c40f49345 605 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
boonshen 0:a35c40f49345 606 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
boonshen 0:a35c40f49345 607
boonshen 0:a35c40f49345 608 /* SCB Configurable Fault Status Register Definitions */
boonshen 0:a35c40f49345 609 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
boonshen 0:a35c40f49345 610 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
boonshen 0:a35c40f49345 611
boonshen 0:a35c40f49345 612 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
boonshen 0:a35c40f49345 613 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
boonshen 0:a35c40f49345 614
boonshen 0:a35c40f49345 615 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
boonshen 0:a35c40f49345 616 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
boonshen 0:a35c40f49345 617
boonshen 0:a35c40f49345 618 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
boonshen 0:a35c40f49345 619 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
boonshen 0:a35c40f49345 620 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
boonshen 0:a35c40f49345 621
boonshen 0:a35c40f49345 622 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
boonshen 0:a35c40f49345 623 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
boonshen 0:a35c40f49345 624
boonshen 0:a35c40f49345 625 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
boonshen 0:a35c40f49345 626 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
boonshen 0:a35c40f49345 627
boonshen 0:a35c40f49345 628 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
boonshen 0:a35c40f49345 629 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
boonshen 0:a35c40f49345 630
boonshen 0:a35c40f49345 631 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
boonshen 0:a35c40f49345 632 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
boonshen 0:a35c40f49345 633
boonshen 0:a35c40f49345 634 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
boonshen 0:a35c40f49345 635 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
boonshen 0:a35c40f49345 636
boonshen 0:a35c40f49345 637 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
boonshen 0:a35c40f49345 638 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
boonshen 0:a35c40f49345 639 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
boonshen 0:a35c40f49345 640
boonshen 0:a35c40f49345 641 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
boonshen 0:a35c40f49345 642 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
boonshen 0:a35c40f49345 643
boonshen 0:a35c40f49345 644 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
boonshen 0:a35c40f49345 645 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
boonshen 0:a35c40f49345 646
boonshen 0:a35c40f49345 647 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
boonshen 0:a35c40f49345 648 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
boonshen 0:a35c40f49345 649
boonshen 0:a35c40f49345 650 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
boonshen 0:a35c40f49345 651 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
boonshen 0:a35c40f49345 652
boonshen 0:a35c40f49345 653 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
boonshen 0:a35c40f49345 654 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
boonshen 0:a35c40f49345 655
boonshen 0:a35c40f49345 656 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
boonshen 0:a35c40f49345 657 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
boonshen 0:a35c40f49345 658
boonshen 0:a35c40f49345 659 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
boonshen 0:a35c40f49345 660 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
boonshen 0:a35c40f49345 661 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
boonshen 0:a35c40f49345 662
boonshen 0:a35c40f49345 663 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
boonshen 0:a35c40f49345 664 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
boonshen 0:a35c40f49345 665
boonshen 0:a35c40f49345 666 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
boonshen 0:a35c40f49345 667 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
boonshen 0:a35c40f49345 668
boonshen 0:a35c40f49345 669 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
boonshen 0:a35c40f49345 670 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
boonshen 0:a35c40f49345 671
boonshen 0:a35c40f49345 672 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
boonshen 0:a35c40f49345 673 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
boonshen 0:a35c40f49345 674
boonshen 0:a35c40f49345 675 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
boonshen 0:a35c40f49345 676 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
boonshen 0:a35c40f49345 677
boonshen 0:a35c40f49345 678 /* SCB Hard Fault Status Register Definitions */
boonshen 0:a35c40f49345 679 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
boonshen 0:a35c40f49345 680 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
boonshen 0:a35c40f49345 681
boonshen 0:a35c40f49345 682 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
boonshen 0:a35c40f49345 683 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
boonshen 0:a35c40f49345 684
boonshen 0:a35c40f49345 685 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
boonshen 0:a35c40f49345 686 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
boonshen 0:a35c40f49345 687
boonshen 0:a35c40f49345 688 /* SCB Debug Fault Status Register Definitions */
boonshen 0:a35c40f49345 689 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
boonshen 0:a35c40f49345 690 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
boonshen 0:a35c40f49345 691
boonshen 0:a35c40f49345 692 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
boonshen 0:a35c40f49345 693 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
boonshen 0:a35c40f49345 694
boonshen 0:a35c40f49345 695 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
boonshen 0:a35c40f49345 696 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
boonshen 0:a35c40f49345 697
boonshen 0:a35c40f49345 698 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
boonshen 0:a35c40f49345 699 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
boonshen 0:a35c40f49345 700
boonshen 0:a35c40f49345 701 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
boonshen 0:a35c40f49345 702 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
boonshen 0:a35c40f49345 703
boonshen 0:a35c40f49345 704 /*@} end of group CMSIS_SCB */
boonshen 0:a35c40f49345 705
boonshen 0:a35c40f49345 706
boonshen 0:a35c40f49345 707 /**
boonshen 0:a35c40f49345 708 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 709 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
boonshen 0:a35c40f49345 710 \brief Type definitions for the System Control and ID Register not in the SCB
boonshen 0:a35c40f49345 711 @{
boonshen 0:a35c40f49345 712 */
boonshen 0:a35c40f49345 713
boonshen 0:a35c40f49345 714 /**
boonshen 0:a35c40f49345 715 \brief Structure type to access the System Control and ID Register not in the SCB.
boonshen 0:a35c40f49345 716 */
boonshen 0:a35c40f49345 717 typedef struct
boonshen 0:a35c40f49345 718 {
boonshen 0:a35c40f49345 719 uint32_t RESERVED0[1U];
boonshen 0:a35c40f49345 720 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
boonshen 0:a35c40f49345 721 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
boonshen 0:a35c40f49345 722 } SCnSCB_Type;
boonshen 0:a35c40f49345 723
boonshen 0:a35c40f49345 724 /* Interrupt Controller Type Register Definitions */
boonshen 0:a35c40f49345 725 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
boonshen 0:a35c40f49345 726 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
boonshen 0:a35c40f49345 727
boonshen 0:a35c40f49345 728 /* Auxiliary Control Register Definitions */
boonshen 0:a35c40f49345 729 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
boonshen 0:a35c40f49345 730 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
boonshen 0:a35c40f49345 731
boonshen 0:a35c40f49345 732 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
boonshen 0:a35c40f49345 733 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
boonshen 0:a35c40f49345 734
boonshen 0:a35c40f49345 735 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
boonshen 0:a35c40f49345 736 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
boonshen 0:a35c40f49345 737
boonshen 0:a35c40f49345 738 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
boonshen 0:a35c40f49345 739 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
boonshen 0:a35c40f49345 740
boonshen 0:a35c40f49345 741 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
boonshen 0:a35c40f49345 742 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
boonshen 0:a35c40f49345 743
boonshen 0:a35c40f49345 744 /*@} end of group CMSIS_SCnotSCB */
boonshen 0:a35c40f49345 745
boonshen 0:a35c40f49345 746
boonshen 0:a35c40f49345 747 /**
boonshen 0:a35c40f49345 748 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 749 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
boonshen 0:a35c40f49345 750 \brief Type definitions for the System Timer Registers.
boonshen 0:a35c40f49345 751 @{
boonshen 0:a35c40f49345 752 */
boonshen 0:a35c40f49345 753
boonshen 0:a35c40f49345 754 /**
boonshen 0:a35c40f49345 755 \brief Structure type to access the System Timer (SysTick).
boonshen 0:a35c40f49345 756 */
boonshen 0:a35c40f49345 757 typedef struct
boonshen 0:a35c40f49345 758 {
boonshen 0:a35c40f49345 759 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
boonshen 0:a35c40f49345 760 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
boonshen 0:a35c40f49345 761 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
boonshen 0:a35c40f49345 762 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
boonshen 0:a35c40f49345 763 } SysTick_Type;
boonshen 0:a35c40f49345 764
boonshen 0:a35c40f49345 765 /* SysTick Control / Status Register Definitions */
boonshen 0:a35c40f49345 766 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
boonshen 0:a35c40f49345 767 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
boonshen 0:a35c40f49345 768
boonshen 0:a35c40f49345 769 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
boonshen 0:a35c40f49345 770 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
boonshen 0:a35c40f49345 771
boonshen 0:a35c40f49345 772 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
boonshen 0:a35c40f49345 773 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
boonshen 0:a35c40f49345 774
boonshen 0:a35c40f49345 775 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
boonshen 0:a35c40f49345 776 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
boonshen 0:a35c40f49345 777
boonshen 0:a35c40f49345 778 /* SysTick Reload Register Definitions */
boonshen 0:a35c40f49345 779 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
boonshen 0:a35c40f49345 780 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
boonshen 0:a35c40f49345 781
boonshen 0:a35c40f49345 782 /* SysTick Current Register Definitions */
boonshen 0:a35c40f49345 783 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
boonshen 0:a35c40f49345 784 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
boonshen 0:a35c40f49345 785
boonshen 0:a35c40f49345 786 /* SysTick Calibration Register Definitions */
boonshen 0:a35c40f49345 787 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
boonshen 0:a35c40f49345 788 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
boonshen 0:a35c40f49345 789
boonshen 0:a35c40f49345 790 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
boonshen 0:a35c40f49345 791 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
boonshen 0:a35c40f49345 792
boonshen 0:a35c40f49345 793 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
boonshen 0:a35c40f49345 794 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
boonshen 0:a35c40f49345 795
boonshen 0:a35c40f49345 796 /*@} end of group CMSIS_SysTick */
boonshen 0:a35c40f49345 797
boonshen 0:a35c40f49345 798
boonshen 0:a35c40f49345 799 /**
boonshen 0:a35c40f49345 800 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 801 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
boonshen 0:a35c40f49345 802 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
boonshen 0:a35c40f49345 803 @{
boonshen 0:a35c40f49345 804 */
boonshen 0:a35c40f49345 805
boonshen 0:a35c40f49345 806 /**
boonshen 0:a35c40f49345 807 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
boonshen 0:a35c40f49345 808 */
boonshen 0:a35c40f49345 809 typedef struct
boonshen 0:a35c40f49345 810 {
boonshen 0:a35c40f49345 811 __OM union
boonshen 0:a35c40f49345 812 {
boonshen 0:a35c40f49345 813 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
boonshen 0:a35c40f49345 814 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
boonshen 0:a35c40f49345 815 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
boonshen 0:a35c40f49345 816 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
boonshen 0:a35c40f49345 817 uint32_t RESERVED0[864U];
boonshen 0:a35c40f49345 818 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
boonshen 0:a35c40f49345 819 uint32_t RESERVED1[15U];
boonshen 0:a35c40f49345 820 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
boonshen 0:a35c40f49345 821 uint32_t RESERVED2[15U];
boonshen 0:a35c40f49345 822 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
boonshen 0:a35c40f49345 823 uint32_t RESERVED3[29U];
boonshen 0:a35c40f49345 824 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
boonshen 0:a35c40f49345 825 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
boonshen 0:a35c40f49345 826 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
boonshen 0:a35c40f49345 827 uint32_t RESERVED4[43U];
boonshen 0:a35c40f49345 828 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
boonshen 0:a35c40f49345 829 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
boonshen 0:a35c40f49345 830 uint32_t RESERVED5[6U];
boonshen 0:a35c40f49345 831 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
boonshen 0:a35c40f49345 832 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
boonshen 0:a35c40f49345 833 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
boonshen 0:a35c40f49345 834 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
boonshen 0:a35c40f49345 835 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
boonshen 0:a35c40f49345 836 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
boonshen 0:a35c40f49345 837 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
boonshen 0:a35c40f49345 838 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
boonshen 0:a35c40f49345 839 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
boonshen 0:a35c40f49345 840 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
boonshen 0:a35c40f49345 841 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
boonshen 0:a35c40f49345 842 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
boonshen 0:a35c40f49345 843 } ITM_Type;
boonshen 0:a35c40f49345 844
boonshen 0:a35c40f49345 845 /* ITM Trace Privilege Register Definitions */
boonshen 0:a35c40f49345 846 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
boonshen 0:a35c40f49345 847 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
boonshen 0:a35c40f49345 848
boonshen 0:a35c40f49345 849 /* ITM Trace Control Register Definitions */
boonshen 0:a35c40f49345 850 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
boonshen 0:a35c40f49345 851 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
boonshen 0:a35c40f49345 852
boonshen 0:a35c40f49345 853 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
boonshen 0:a35c40f49345 854 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
boonshen 0:a35c40f49345 855
boonshen 0:a35c40f49345 856 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
boonshen 0:a35c40f49345 857 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
boonshen 0:a35c40f49345 858
boonshen 0:a35c40f49345 859 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
boonshen 0:a35c40f49345 860 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
boonshen 0:a35c40f49345 861
boonshen 0:a35c40f49345 862 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
boonshen 0:a35c40f49345 863 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
boonshen 0:a35c40f49345 864
boonshen 0:a35c40f49345 865 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
boonshen 0:a35c40f49345 866 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
boonshen 0:a35c40f49345 867
boonshen 0:a35c40f49345 868 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
boonshen 0:a35c40f49345 869 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
boonshen 0:a35c40f49345 870
boonshen 0:a35c40f49345 871 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
boonshen 0:a35c40f49345 872 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
boonshen 0:a35c40f49345 873
boonshen 0:a35c40f49345 874 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
boonshen 0:a35c40f49345 875 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
boonshen 0:a35c40f49345 876
boonshen 0:a35c40f49345 877 /* ITM Integration Write Register Definitions */
boonshen 0:a35c40f49345 878 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
boonshen 0:a35c40f49345 879 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
boonshen 0:a35c40f49345 880
boonshen 0:a35c40f49345 881 /* ITM Integration Read Register Definitions */
boonshen 0:a35c40f49345 882 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
boonshen 0:a35c40f49345 883 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
boonshen 0:a35c40f49345 884
boonshen 0:a35c40f49345 885 /* ITM Integration Mode Control Register Definitions */
boonshen 0:a35c40f49345 886 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
boonshen 0:a35c40f49345 887 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
boonshen 0:a35c40f49345 888
boonshen 0:a35c40f49345 889 /* ITM Lock Status Register Definitions */
boonshen 0:a35c40f49345 890 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
boonshen 0:a35c40f49345 891 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
boonshen 0:a35c40f49345 892
boonshen 0:a35c40f49345 893 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
boonshen 0:a35c40f49345 894 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
boonshen 0:a35c40f49345 895
boonshen 0:a35c40f49345 896 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
boonshen 0:a35c40f49345 897 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
boonshen 0:a35c40f49345 898
boonshen 0:a35c40f49345 899 /*@}*/ /* end of group CMSIS_ITM */
boonshen 0:a35c40f49345 900
boonshen 0:a35c40f49345 901
boonshen 0:a35c40f49345 902 /**
boonshen 0:a35c40f49345 903 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 904 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
boonshen 0:a35c40f49345 905 \brief Type definitions for the Data Watchpoint and Trace (DWT)
boonshen 0:a35c40f49345 906 @{
boonshen 0:a35c40f49345 907 */
boonshen 0:a35c40f49345 908
boonshen 0:a35c40f49345 909 /**
boonshen 0:a35c40f49345 910 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
boonshen 0:a35c40f49345 911 */
boonshen 0:a35c40f49345 912 typedef struct
boonshen 0:a35c40f49345 913 {
boonshen 0:a35c40f49345 914 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
boonshen 0:a35c40f49345 915 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
boonshen 0:a35c40f49345 916 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
boonshen 0:a35c40f49345 917 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
boonshen 0:a35c40f49345 918 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
boonshen 0:a35c40f49345 919 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
boonshen 0:a35c40f49345 920 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
boonshen 0:a35c40f49345 921 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
boonshen 0:a35c40f49345 922 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
boonshen 0:a35c40f49345 923 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
boonshen 0:a35c40f49345 924 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
boonshen 0:a35c40f49345 925 uint32_t RESERVED0[1U];
boonshen 0:a35c40f49345 926 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
boonshen 0:a35c40f49345 927 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
boonshen 0:a35c40f49345 928 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
boonshen 0:a35c40f49345 929 uint32_t RESERVED1[1U];
boonshen 0:a35c40f49345 930 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
boonshen 0:a35c40f49345 931 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
boonshen 0:a35c40f49345 932 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
boonshen 0:a35c40f49345 933 uint32_t RESERVED2[1U];
boonshen 0:a35c40f49345 934 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
boonshen 0:a35c40f49345 935 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
boonshen 0:a35c40f49345 936 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
boonshen 0:a35c40f49345 937 } DWT_Type;
boonshen 0:a35c40f49345 938
boonshen 0:a35c40f49345 939 /* DWT Control Register Definitions */
boonshen 0:a35c40f49345 940 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
boonshen 0:a35c40f49345 941 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
boonshen 0:a35c40f49345 942
boonshen 0:a35c40f49345 943 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
boonshen 0:a35c40f49345 944 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
boonshen 0:a35c40f49345 945
boonshen 0:a35c40f49345 946 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
boonshen 0:a35c40f49345 947 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
boonshen 0:a35c40f49345 948
boonshen 0:a35c40f49345 949 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
boonshen 0:a35c40f49345 950 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
boonshen 0:a35c40f49345 951
boonshen 0:a35c40f49345 952 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
boonshen 0:a35c40f49345 953 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
boonshen 0:a35c40f49345 954
boonshen 0:a35c40f49345 955 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
boonshen 0:a35c40f49345 956 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
boonshen 0:a35c40f49345 957
boonshen 0:a35c40f49345 958 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
boonshen 0:a35c40f49345 959 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
boonshen 0:a35c40f49345 960
boonshen 0:a35c40f49345 961 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
boonshen 0:a35c40f49345 962 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
boonshen 0:a35c40f49345 963
boonshen 0:a35c40f49345 964 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
boonshen 0:a35c40f49345 965 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
boonshen 0:a35c40f49345 966
boonshen 0:a35c40f49345 967 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
boonshen 0:a35c40f49345 968 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
boonshen 0:a35c40f49345 969
boonshen 0:a35c40f49345 970 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
boonshen 0:a35c40f49345 971 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
boonshen 0:a35c40f49345 972
boonshen 0:a35c40f49345 973 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
boonshen 0:a35c40f49345 974 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
boonshen 0:a35c40f49345 975
boonshen 0:a35c40f49345 976 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
boonshen 0:a35c40f49345 977 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
boonshen 0:a35c40f49345 978
boonshen 0:a35c40f49345 979 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
boonshen 0:a35c40f49345 980 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
boonshen 0:a35c40f49345 981
boonshen 0:a35c40f49345 982 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
boonshen 0:a35c40f49345 983 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
boonshen 0:a35c40f49345 984
boonshen 0:a35c40f49345 985 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
boonshen 0:a35c40f49345 986 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
boonshen 0:a35c40f49345 987
boonshen 0:a35c40f49345 988 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
boonshen 0:a35c40f49345 989 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
boonshen 0:a35c40f49345 990
boonshen 0:a35c40f49345 991 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
boonshen 0:a35c40f49345 992 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
boonshen 0:a35c40f49345 993
boonshen 0:a35c40f49345 994 /* DWT CPI Count Register Definitions */
boonshen 0:a35c40f49345 995 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
boonshen 0:a35c40f49345 996 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
boonshen 0:a35c40f49345 997
boonshen 0:a35c40f49345 998 /* DWT Exception Overhead Count Register Definitions */
boonshen 0:a35c40f49345 999 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
boonshen 0:a35c40f49345 1000 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
boonshen 0:a35c40f49345 1001
boonshen 0:a35c40f49345 1002 /* DWT Sleep Count Register Definitions */
boonshen 0:a35c40f49345 1003 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
boonshen 0:a35c40f49345 1004 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
boonshen 0:a35c40f49345 1005
boonshen 0:a35c40f49345 1006 /* DWT LSU Count Register Definitions */
boonshen 0:a35c40f49345 1007 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
boonshen 0:a35c40f49345 1008 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
boonshen 0:a35c40f49345 1009
boonshen 0:a35c40f49345 1010 /* DWT Folded-instruction Count Register Definitions */
boonshen 0:a35c40f49345 1011 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
boonshen 0:a35c40f49345 1012 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
boonshen 0:a35c40f49345 1013
boonshen 0:a35c40f49345 1014 /* DWT Comparator Mask Register Definitions */
boonshen 0:a35c40f49345 1015 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
boonshen 0:a35c40f49345 1016 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
boonshen 0:a35c40f49345 1017
boonshen 0:a35c40f49345 1018 /* DWT Comparator Function Register Definitions */
boonshen 0:a35c40f49345 1019 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
boonshen 0:a35c40f49345 1020 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
boonshen 0:a35c40f49345 1021
boonshen 0:a35c40f49345 1022 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
boonshen 0:a35c40f49345 1023 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
boonshen 0:a35c40f49345 1024
boonshen 0:a35c40f49345 1025 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
boonshen 0:a35c40f49345 1026 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
boonshen 0:a35c40f49345 1027
boonshen 0:a35c40f49345 1028 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
boonshen 0:a35c40f49345 1029 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
boonshen 0:a35c40f49345 1030
boonshen 0:a35c40f49345 1031 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
boonshen 0:a35c40f49345 1032 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
boonshen 0:a35c40f49345 1033
boonshen 0:a35c40f49345 1034 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
boonshen 0:a35c40f49345 1035 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
boonshen 0:a35c40f49345 1036
boonshen 0:a35c40f49345 1037 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
boonshen 0:a35c40f49345 1038 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
boonshen 0:a35c40f49345 1039
boonshen 0:a35c40f49345 1040 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
boonshen 0:a35c40f49345 1041 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
boonshen 0:a35c40f49345 1042
boonshen 0:a35c40f49345 1043 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
boonshen 0:a35c40f49345 1044 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
boonshen 0:a35c40f49345 1045
boonshen 0:a35c40f49345 1046 /*@}*/ /* end of group CMSIS_DWT */
boonshen 0:a35c40f49345 1047
boonshen 0:a35c40f49345 1048
boonshen 0:a35c40f49345 1049 /**
boonshen 0:a35c40f49345 1050 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1051 \defgroup CMSIS_TPI Trace Port Interface (TPI)
boonshen 0:a35c40f49345 1052 \brief Type definitions for the Trace Port Interface (TPI)
boonshen 0:a35c40f49345 1053 @{
boonshen 0:a35c40f49345 1054 */
boonshen 0:a35c40f49345 1055
boonshen 0:a35c40f49345 1056 /**
boonshen 0:a35c40f49345 1057 \brief Structure type to access the Trace Port Interface Register (TPI).
boonshen 0:a35c40f49345 1058 */
boonshen 0:a35c40f49345 1059 typedef struct
boonshen 0:a35c40f49345 1060 {
boonshen 0:a35c40f49345 1061 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
boonshen 0:a35c40f49345 1062 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
boonshen 0:a35c40f49345 1063 uint32_t RESERVED0[2U];
boonshen 0:a35c40f49345 1064 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
boonshen 0:a35c40f49345 1065 uint32_t RESERVED1[55U];
boonshen 0:a35c40f49345 1066 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
boonshen 0:a35c40f49345 1067 uint32_t RESERVED2[131U];
boonshen 0:a35c40f49345 1068 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
boonshen 0:a35c40f49345 1069 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
boonshen 0:a35c40f49345 1070 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
boonshen 0:a35c40f49345 1071 uint32_t RESERVED3[759U];
boonshen 0:a35c40f49345 1072 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
boonshen 0:a35c40f49345 1073 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
boonshen 0:a35c40f49345 1074 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
boonshen 0:a35c40f49345 1075 uint32_t RESERVED4[1U];
boonshen 0:a35c40f49345 1076 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
boonshen 0:a35c40f49345 1077 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
boonshen 0:a35c40f49345 1078 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
boonshen 0:a35c40f49345 1079 uint32_t RESERVED5[39U];
boonshen 0:a35c40f49345 1080 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
boonshen 0:a35c40f49345 1081 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
boonshen 0:a35c40f49345 1082 uint32_t RESERVED7[8U];
boonshen 0:a35c40f49345 1083 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
boonshen 0:a35c40f49345 1084 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
boonshen 0:a35c40f49345 1085 } TPI_Type;
boonshen 0:a35c40f49345 1086
boonshen 0:a35c40f49345 1087 /* TPI Asynchronous Clock Prescaler Register Definitions */
boonshen 0:a35c40f49345 1088 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
boonshen 0:a35c40f49345 1089 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
boonshen 0:a35c40f49345 1090
boonshen 0:a35c40f49345 1091 /* TPI Selected Pin Protocol Register Definitions */
boonshen 0:a35c40f49345 1092 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
boonshen 0:a35c40f49345 1093 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
boonshen 0:a35c40f49345 1094
boonshen 0:a35c40f49345 1095 /* TPI Formatter and Flush Status Register Definitions */
boonshen 0:a35c40f49345 1096 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
boonshen 0:a35c40f49345 1097 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
boonshen 0:a35c40f49345 1098
boonshen 0:a35c40f49345 1099 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
boonshen 0:a35c40f49345 1100 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
boonshen 0:a35c40f49345 1101
boonshen 0:a35c40f49345 1102 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
boonshen 0:a35c40f49345 1103 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
boonshen 0:a35c40f49345 1104
boonshen 0:a35c40f49345 1105 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
boonshen 0:a35c40f49345 1106 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
boonshen 0:a35c40f49345 1107
boonshen 0:a35c40f49345 1108 /* TPI Formatter and Flush Control Register Definitions */
boonshen 0:a35c40f49345 1109 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
boonshen 0:a35c40f49345 1110 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
boonshen 0:a35c40f49345 1111
boonshen 0:a35c40f49345 1112 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
boonshen 0:a35c40f49345 1113 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
boonshen 0:a35c40f49345 1114
boonshen 0:a35c40f49345 1115 /* TPI TRIGGER Register Definitions */
boonshen 0:a35c40f49345 1116 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
boonshen 0:a35c40f49345 1117 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
boonshen 0:a35c40f49345 1118
boonshen 0:a35c40f49345 1119 /* TPI Integration ETM Data Register Definitions (FIFO0) */
boonshen 0:a35c40f49345 1120 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
boonshen 0:a35c40f49345 1121 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
boonshen 0:a35c40f49345 1122
boonshen 0:a35c40f49345 1123 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
boonshen 0:a35c40f49345 1124 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
boonshen 0:a35c40f49345 1125
boonshen 0:a35c40f49345 1126 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
boonshen 0:a35c40f49345 1127 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
boonshen 0:a35c40f49345 1128
boonshen 0:a35c40f49345 1129 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
boonshen 0:a35c40f49345 1130 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
boonshen 0:a35c40f49345 1131
boonshen 0:a35c40f49345 1132 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
boonshen 0:a35c40f49345 1133 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
boonshen 0:a35c40f49345 1134
boonshen 0:a35c40f49345 1135 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
boonshen 0:a35c40f49345 1136 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
boonshen 0:a35c40f49345 1137
boonshen 0:a35c40f49345 1138 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
boonshen 0:a35c40f49345 1139 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
boonshen 0:a35c40f49345 1140
boonshen 0:a35c40f49345 1141 /* TPI ITATBCTR2 Register Definitions */
boonshen 0:a35c40f49345 1142 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
boonshen 0:a35c40f49345 1143 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
boonshen 0:a35c40f49345 1144
boonshen 0:a35c40f49345 1145 /* TPI Integration ITM Data Register Definitions (FIFO1) */
boonshen 0:a35c40f49345 1146 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
boonshen 0:a35c40f49345 1147 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
boonshen 0:a35c40f49345 1148
boonshen 0:a35c40f49345 1149 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
boonshen 0:a35c40f49345 1150 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
boonshen 0:a35c40f49345 1151
boonshen 0:a35c40f49345 1152 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
boonshen 0:a35c40f49345 1153 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
boonshen 0:a35c40f49345 1154
boonshen 0:a35c40f49345 1155 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
boonshen 0:a35c40f49345 1156 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
boonshen 0:a35c40f49345 1157
boonshen 0:a35c40f49345 1158 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
boonshen 0:a35c40f49345 1159 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
boonshen 0:a35c40f49345 1160
boonshen 0:a35c40f49345 1161 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
boonshen 0:a35c40f49345 1162 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
boonshen 0:a35c40f49345 1163
boonshen 0:a35c40f49345 1164 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
boonshen 0:a35c40f49345 1165 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
boonshen 0:a35c40f49345 1166
boonshen 0:a35c40f49345 1167 /* TPI ITATBCTR0 Register Definitions */
boonshen 0:a35c40f49345 1168 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
boonshen 0:a35c40f49345 1169 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
boonshen 0:a35c40f49345 1170
boonshen 0:a35c40f49345 1171 /* TPI Integration Mode Control Register Definitions */
boonshen 0:a35c40f49345 1172 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
boonshen 0:a35c40f49345 1173 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
boonshen 0:a35c40f49345 1174
boonshen 0:a35c40f49345 1175 /* TPI DEVID Register Definitions */
boonshen 0:a35c40f49345 1176 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
boonshen 0:a35c40f49345 1177 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
boonshen 0:a35c40f49345 1178
boonshen 0:a35c40f49345 1179 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
boonshen 0:a35c40f49345 1180 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
boonshen 0:a35c40f49345 1181
boonshen 0:a35c40f49345 1182 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
boonshen 0:a35c40f49345 1183 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
boonshen 0:a35c40f49345 1184
boonshen 0:a35c40f49345 1185 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
boonshen 0:a35c40f49345 1186 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
boonshen 0:a35c40f49345 1187
boonshen 0:a35c40f49345 1188 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
boonshen 0:a35c40f49345 1189 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
boonshen 0:a35c40f49345 1190
boonshen 0:a35c40f49345 1191 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
boonshen 0:a35c40f49345 1192 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
boonshen 0:a35c40f49345 1193
boonshen 0:a35c40f49345 1194 /* TPI DEVTYPE Register Definitions */
boonshen 0:a35c40f49345 1195 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
boonshen 0:a35c40f49345 1196 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
boonshen 0:a35c40f49345 1197
boonshen 0:a35c40f49345 1198 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
boonshen 0:a35c40f49345 1199 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
boonshen 0:a35c40f49345 1200
boonshen 0:a35c40f49345 1201 /*@}*/ /* end of group CMSIS_TPI */
boonshen 0:a35c40f49345 1202
boonshen 0:a35c40f49345 1203
boonshen 0:a35c40f49345 1204 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen 0:a35c40f49345 1205 /**
boonshen 0:a35c40f49345 1206 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1207 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
boonshen 0:a35c40f49345 1208 \brief Type definitions for the Memory Protection Unit (MPU)
boonshen 0:a35c40f49345 1209 @{
boonshen 0:a35c40f49345 1210 */
boonshen 0:a35c40f49345 1211
boonshen 0:a35c40f49345 1212 /**
boonshen 0:a35c40f49345 1213 \brief Structure type to access the Memory Protection Unit (MPU).
boonshen 0:a35c40f49345 1214 */
boonshen 0:a35c40f49345 1215 typedef struct
boonshen 0:a35c40f49345 1216 {
boonshen 0:a35c40f49345 1217 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
boonshen 0:a35c40f49345 1218 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
boonshen 0:a35c40f49345 1219 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
boonshen 0:a35c40f49345 1220 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
boonshen 0:a35c40f49345 1221 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
boonshen 0:a35c40f49345 1222 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
boonshen 0:a35c40f49345 1223 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
boonshen 0:a35c40f49345 1224 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
boonshen 0:a35c40f49345 1225 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
boonshen 0:a35c40f49345 1226 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
boonshen 0:a35c40f49345 1227 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
boonshen 0:a35c40f49345 1228 } MPU_Type;
boonshen 0:a35c40f49345 1229
boonshen 0:a35c40f49345 1230 /* MPU Type Register Definitions */
boonshen 0:a35c40f49345 1231 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
boonshen 0:a35c40f49345 1232 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
boonshen 0:a35c40f49345 1233
boonshen 0:a35c40f49345 1234 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
boonshen 0:a35c40f49345 1235 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
boonshen 0:a35c40f49345 1236
boonshen 0:a35c40f49345 1237 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
boonshen 0:a35c40f49345 1238 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
boonshen 0:a35c40f49345 1239
boonshen 0:a35c40f49345 1240 /* MPU Control Register Definitions */
boonshen 0:a35c40f49345 1241 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
boonshen 0:a35c40f49345 1242 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
boonshen 0:a35c40f49345 1243
boonshen 0:a35c40f49345 1244 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
boonshen 0:a35c40f49345 1245 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
boonshen 0:a35c40f49345 1246
boonshen 0:a35c40f49345 1247 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
boonshen 0:a35c40f49345 1248 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
boonshen 0:a35c40f49345 1249
boonshen 0:a35c40f49345 1250 /* MPU Region Number Register Definitions */
boonshen 0:a35c40f49345 1251 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
boonshen 0:a35c40f49345 1252 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
boonshen 0:a35c40f49345 1253
boonshen 0:a35c40f49345 1254 /* MPU Region Base Address Register Definitions */
boonshen 0:a35c40f49345 1255 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
boonshen 0:a35c40f49345 1256 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
boonshen 0:a35c40f49345 1257
boonshen 0:a35c40f49345 1258 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
boonshen 0:a35c40f49345 1259 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
boonshen 0:a35c40f49345 1260
boonshen 0:a35c40f49345 1261 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
boonshen 0:a35c40f49345 1262 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
boonshen 0:a35c40f49345 1263
boonshen 0:a35c40f49345 1264 /* MPU Region Attribute and Size Register Definitions */
boonshen 0:a35c40f49345 1265 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
boonshen 0:a35c40f49345 1266 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
boonshen 0:a35c40f49345 1267
boonshen 0:a35c40f49345 1268 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
boonshen 0:a35c40f49345 1269 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
boonshen 0:a35c40f49345 1270
boonshen 0:a35c40f49345 1271 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
boonshen 0:a35c40f49345 1272 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
boonshen 0:a35c40f49345 1273
boonshen 0:a35c40f49345 1274 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
boonshen 0:a35c40f49345 1275 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
boonshen 0:a35c40f49345 1276
boonshen 0:a35c40f49345 1277 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
boonshen 0:a35c40f49345 1278 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
boonshen 0:a35c40f49345 1279
boonshen 0:a35c40f49345 1280 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
boonshen 0:a35c40f49345 1281 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
boonshen 0:a35c40f49345 1282
boonshen 0:a35c40f49345 1283 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
boonshen 0:a35c40f49345 1284 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
boonshen 0:a35c40f49345 1285
boonshen 0:a35c40f49345 1286 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
boonshen 0:a35c40f49345 1287 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
boonshen 0:a35c40f49345 1288
boonshen 0:a35c40f49345 1289 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
boonshen 0:a35c40f49345 1290 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
boonshen 0:a35c40f49345 1291
boonshen 0:a35c40f49345 1292 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
boonshen 0:a35c40f49345 1293 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
boonshen 0:a35c40f49345 1294
boonshen 0:a35c40f49345 1295 /*@} end of group CMSIS_MPU */
boonshen 0:a35c40f49345 1296 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
boonshen 0:a35c40f49345 1297
boonshen 0:a35c40f49345 1298
boonshen 0:a35c40f49345 1299 /**
boonshen 0:a35c40f49345 1300 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1301 \defgroup CMSIS_FPU Floating Point Unit (FPU)
boonshen 0:a35c40f49345 1302 \brief Type definitions for the Floating Point Unit (FPU)
boonshen 0:a35c40f49345 1303 @{
boonshen 0:a35c40f49345 1304 */
boonshen 0:a35c40f49345 1305
boonshen 0:a35c40f49345 1306 /**
boonshen 0:a35c40f49345 1307 \brief Structure type to access the Floating Point Unit (FPU).
boonshen 0:a35c40f49345 1308 */
boonshen 0:a35c40f49345 1309 typedef struct
boonshen 0:a35c40f49345 1310 {
boonshen 0:a35c40f49345 1311 uint32_t RESERVED0[1U];
boonshen 0:a35c40f49345 1312 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
boonshen 0:a35c40f49345 1313 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
boonshen 0:a35c40f49345 1314 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
boonshen 0:a35c40f49345 1315 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
boonshen 0:a35c40f49345 1316 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
boonshen 0:a35c40f49345 1317 } FPU_Type;
boonshen 0:a35c40f49345 1318
boonshen 0:a35c40f49345 1319 /* Floating-Point Context Control Register Definitions */
boonshen 0:a35c40f49345 1320 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
boonshen 0:a35c40f49345 1321 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
boonshen 0:a35c40f49345 1322
boonshen 0:a35c40f49345 1323 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
boonshen 0:a35c40f49345 1324 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
boonshen 0:a35c40f49345 1325
boonshen 0:a35c40f49345 1326 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
boonshen 0:a35c40f49345 1327 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
boonshen 0:a35c40f49345 1328
boonshen 0:a35c40f49345 1329 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
boonshen 0:a35c40f49345 1330 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
boonshen 0:a35c40f49345 1331
boonshen 0:a35c40f49345 1332 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
boonshen 0:a35c40f49345 1333 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
boonshen 0:a35c40f49345 1334
boonshen 0:a35c40f49345 1335 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
boonshen 0:a35c40f49345 1336 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
boonshen 0:a35c40f49345 1337
boonshen 0:a35c40f49345 1338 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
boonshen 0:a35c40f49345 1339 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
boonshen 0:a35c40f49345 1340
boonshen 0:a35c40f49345 1341 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
boonshen 0:a35c40f49345 1342 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
boonshen 0:a35c40f49345 1343
boonshen 0:a35c40f49345 1344 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
boonshen 0:a35c40f49345 1345 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
boonshen 0:a35c40f49345 1346
boonshen 0:a35c40f49345 1347 /* Floating-Point Context Address Register Definitions */
boonshen 0:a35c40f49345 1348 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
boonshen 0:a35c40f49345 1349 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
boonshen 0:a35c40f49345 1350
boonshen 0:a35c40f49345 1351 /* Floating-Point Default Status Control Register Definitions */
boonshen 0:a35c40f49345 1352 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
boonshen 0:a35c40f49345 1353 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
boonshen 0:a35c40f49345 1354
boonshen 0:a35c40f49345 1355 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
boonshen 0:a35c40f49345 1356 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
boonshen 0:a35c40f49345 1357
boonshen 0:a35c40f49345 1358 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
boonshen 0:a35c40f49345 1359 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
boonshen 0:a35c40f49345 1360
boonshen 0:a35c40f49345 1361 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
boonshen 0:a35c40f49345 1362 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
boonshen 0:a35c40f49345 1363
boonshen 0:a35c40f49345 1364 /* Media and FP Feature Register 0 Definitions */
boonshen 0:a35c40f49345 1365 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
boonshen 0:a35c40f49345 1366 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
boonshen 0:a35c40f49345 1367
boonshen 0:a35c40f49345 1368 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
boonshen 0:a35c40f49345 1369 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
boonshen 0:a35c40f49345 1370
boonshen 0:a35c40f49345 1371 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
boonshen 0:a35c40f49345 1372 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
boonshen 0:a35c40f49345 1373
boonshen 0:a35c40f49345 1374 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
boonshen 0:a35c40f49345 1375 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
boonshen 0:a35c40f49345 1376
boonshen 0:a35c40f49345 1377 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
boonshen 0:a35c40f49345 1378 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
boonshen 0:a35c40f49345 1379
boonshen 0:a35c40f49345 1380 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
boonshen 0:a35c40f49345 1381 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
boonshen 0:a35c40f49345 1382
boonshen 0:a35c40f49345 1383 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
boonshen 0:a35c40f49345 1384 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
boonshen 0:a35c40f49345 1385
boonshen 0:a35c40f49345 1386 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
boonshen 0:a35c40f49345 1387 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
boonshen 0:a35c40f49345 1388
boonshen 0:a35c40f49345 1389 /* Media and FP Feature Register 1 Definitions */
boonshen 0:a35c40f49345 1390 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
boonshen 0:a35c40f49345 1391 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
boonshen 0:a35c40f49345 1392
boonshen 0:a35c40f49345 1393 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
boonshen 0:a35c40f49345 1394 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
boonshen 0:a35c40f49345 1395
boonshen 0:a35c40f49345 1396 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
boonshen 0:a35c40f49345 1397 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
boonshen 0:a35c40f49345 1398
boonshen 0:a35c40f49345 1399 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
boonshen 0:a35c40f49345 1400 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
boonshen 0:a35c40f49345 1401
boonshen 0:a35c40f49345 1402 /*@} end of group CMSIS_FPU */
boonshen 0:a35c40f49345 1403
boonshen 0:a35c40f49345 1404
boonshen 0:a35c40f49345 1405 /**
boonshen 0:a35c40f49345 1406 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1407 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
boonshen 0:a35c40f49345 1408 \brief Type definitions for the Core Debug Registers
boonshen 0:a35c40f49345 1409 @{
boonshen 0:a35c40f49345 1410 */
boonshen 0:a35c40f49345 1411
boonshen 0:a35c40f49345 1412 /**
boonshen 0:a35c40f49345 1413 \brief Structure type to access the Core Debug Register (CoreDebug).
boonshen 0:a35c40f49345 1414 */
boonshen 0:a35c40f49345 1415 typedef struct
boonshen 0:a35c40f49345 1416 {
boonshen 0:a35c40f49345 1417 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
boonshen 0:a35c40f49345 1418 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
boonshen 0:a35c40f49345 1419 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
boonshen 0:a35c40f49345 1420 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
boonshen 0:a35c40f49345 1421 } CoreDebug_Type;
boonshen 0:a35c40f49345 1422
boonshen 0:a35c40f49345 1423 /* Debug Halting Control and Status Register Definitions */
boonshen 0:a35c40f49345 1424 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
boonshen 0:a35c40f49345 1425 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
boonshen 0:a35c40f49345 1426
boonshen 0:a35c40f49345 1427 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
boonshen 0:a35c40f49345 1428 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
boonshen 0:a35c40f49345 1429
boonshen 0:a35c40f49345 1430 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
boonshen 0:a35c40f49345 1431 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
boonshen 0:a35c40f49345 1432
boonshen 0:a35c40f49345 1433 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
boonshen 0:a35c40f49345 1434 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
boonshen 0:a35c40f49345 1435
boonshen 0:a35c40f49345 1436 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
boonshen 0:a35c40f49345 1437 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
boonshen 0:a35c40f49345 1438
boonshen 0:a35c40f49345 1439 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
boonshen 0:a35c40f49345 1440 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
boonshen 0:a35c40f49345 1441
boonshen 0:a35c40f49345 1442 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
boonshen 0:a35c40f49345 1443 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
boonshen 0:a35c40f49345 1444
boonshen 0:a35c40f49345 1445 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
boonshen 0:a35c40f49345 1446 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
boonshen 0:a35c40f49345 1447
boonshen 0:a35c40f49345 1448 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
boonshen 0:a35c40f49345 1449 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
boonshen 0:a35c40f49345 1450
boonshen 0:a35c40f49345 1451 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
boonshen 0:a35c40f49345 1452 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
boonshen 0:a35c40f49345 1453
boonshen 0:a35c40f49345 1454 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
boonshen 0:a35c40f49345 1455 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
boonshen 0:a35c40f49345 1456
boonshen 0:a35c40f49345 1457 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
boonshen 0:a35c40f49345 1458 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
boonshen 0:a35c40f49345 1459
boonshen 0:a35c40f49345 1460 /* Debug Core Register Selector Register Definitions */
boonshen 0:a35c40f49345 1461 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
boonshen 0:a35c40f49345 1462 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
boonshen 0:a35c40f49345 1463
boonshen 0:a35c40f49345 1464 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
boonshen 0:a35c40f49345 1465 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
boonshen 0:a35c40f49345 1466
boonshen 0:a35c40f49345 1467 /* Debug Exception and Monitor Control Register Definitions */
boonshen 0:a35c40f49345 1468 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
boonshen 0:a35c40f49345 1469 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
boonshen 0:a35c40f49345 1470
boonshen 0:a35c40f49345 1471 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
boonshen 0:a35c40f49345 1472 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
boonshen 0:a35c40f49345 1473
boonshen 0:a35c40f49345 1474 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
boonshen 0:a35c40f49345 1475 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
boonshen 0:a35c40f49345 1476
boonshen 0:a35c40f49345 1477 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
boonshen 0:a35c40f49345 1478 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
boonshen 0:a35c40f49345 1479
boonshen 0:a35c40f49345 1480 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
boonshen 0:a35c40f49345 1481 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
boonshen 0:a35c40f49345 1482
boonshen 0:a35c40f49345 1483 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
boonshen 0:a35c40f49345 1484 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
boonshen 0:a35c40f49345 1485
boonshen 0:a35c40f49345 1486 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
boonshen 0:a35c40f49345 1487 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
boonshen 0:a35c40f49345 1488
boonshen 0:a35c40f49345 1489 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
boonshen 0:a35c40f49345 1490 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
boonshen 0:a35c40f49345 1491
boonshen 0:a35c40f49345 1492 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
boonshen 0:a35c40f49345 1493 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
boonshen 0:a35c40f49345 1494
boonshen 0:a35c40f49345 1495 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
boonshen 0:a35c40f49345 1496 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
boonshen 0:a35c40f49345 1497
boonshen 0:a35c40f49345 1498 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
boonshen 0:a35c40f49345 1499 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
boonshen 0:a35c40f49345 1500
boonshen 0:a35c40f49345 1501 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
boonshen 0:a35c40f49345 1502 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
boonshen 0:a35c40f49345 1503
boonshen 0:a35c40f49345 1504 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
boonshen 0:a35c40f49345 1505 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
boonshen 0:a35c40f49345 1506
boonshen 0:a35c40f49345 1507 /*@} end of group CMSIS_CoreDebug */
boonshen 0:a35c40f49345 1508
boonshen 0:a35c40f49345 1509
boonshen 0:a35c40f49345 1510 /**
boonshen 0:a35c40f49345 1511 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1512 \defgroup CMSIS_core_bitfield Core register bit field macros
boonshen 0:a35c40f49345 1513 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
boonshen 0:a35c40f49345 1514 @{
boonshen 0:a35c40f49345 1515 */
boonshen 0:a35c40f49345 1516
boonshen 0:a35c40f49345 1517 /**
boonshen 0:a35c40f49345 1518 \brief Mask and shift a bit field value for use in a register bit range.
boonshen 0:a35c40f49345 1519 \param[in] field Name of the register bit field.
boonshen 0:a35c40f49345 1520 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
boonshen 0:a35c40f49345 1521 \return Masked and shifted value.
boonshen 0:a35c40f49345 1522 */
boonshen 0:a35c40f49345 1523 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
boonshen 0:a35c40f49345 1524
boonshen 0:a35c40f49345 1525 /**
boonshen 0:a35c40f49345 1526 \brief Mask and shift a register value to extract a bit filed value.
boonshen 0:a35c40f49345 1527 \param[in] field Name of the register bit field.
boonshen 0:a35c40f49345 1528 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
boonshen 0:a35c40f49345 1529 \return Masked and shifted bit field value.
boonshen 0:a35c40f49345 1530 */
boonshen 0:a35c40f49345 1531 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
boonshen 0:a35c40f49345 1532
boonshen 0:a35c40f49345 1533 /*@} end of group CMSIS_core_bitfield */
boonshen 0:a35c40f49345 1534
boonshen 0:a35c40f49345 1535
boonshen 0:a35c40f49345 1536 /**
boonshen 0:a35c40f49345 1537 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1538 \defgroup CMSIS_core_base Core Definitions
boonshen 0:a35c40f49345 1539 \brief Definitions for base addresses, unions, and structures.
boonshen 0:a35c40f49345 1540 @{
boonshen 0:a35c40f49345 1541 */
boonshen 0:a35c40f49345 1542
boonshen 0:a35c40f49345 1543 /* Memory mapping of Core Hardware */
boonshen 0:a35c40f49345 1544 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
boonshen 0:a35c40f49345 1545 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
boonshen 0:a35c40f49345 1546 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
boonshen 0:a35c40f49345 1547 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
boonshen 0:a35c40f49345 1548 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
boonshen 0:a35c40f49345 1549 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
boonshen 0:a35c40f49345 1550 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
boonshen 0:a35c40f49345 1551 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
boonshen 0:a35c40f49345 1552
boonshen 0:a35c40f49345 1553 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
boonshen 0:a35c40f49345 1554 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
boonshen 0:a35c40f49345 1555 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
boonshen 0:a35c40f49345 1556 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
boonshen 0:a35c40f49345 1557 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
boonshen 0:a35c40f49345 1558 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
boonshen 0:a35c40f49345 1559 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
boonshen 0:a35c40f49345 1560 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
boonshen 0:a35c40f49345 1561
boonshen 0:a35c40f49345 1562 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen 0:a35c40f49345 1563 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
boonshen 0:a35c40f49345 1564 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
boonshen 0:a35c40f49345 1565 #endif
boonshen 0:a35c40f49345 1566
boonshen 0:a35c40f49345 1567 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
boonshen 0:a35c40f49345 1568 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
boonshen 0:a35c40f49345 1569
boonshen 0:a35c40f49345 1570 /*@} */
boonshen 0:a35c40f49345 1571
boonshen 0:a35c40f49345 1572
boonshen 0:a35c40f49345 1573
boonshen 0:a35c40f49345 1574 /*******************************************************************************
boonshen 0:a35c40f49345 1575 * Hardware Abstraction Layer
boonshen 0:a35c40f49345 1576 Core Function Interface contains:
boonshen 0:a35c40f49345 1577 - Core NVIC Functions
boonshen 0:a35c40f49345 1578 - Core SysTick Functions
boonshen 0:a35c40f49345 1579 - Core Debug Functions
boonshen 0:a35c40f49345 1580 - Core Register Access Functions
boonshen 0:a35c40f49345 1581 ******************************************************************************/
boonshen 0:a35c40f49345 1582 /**
boonshen 0:a35c40f49345 1583 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
boonshen 0:a35c40f49345 1584 */
boonshen 0:a35c40f49345 1585
boonshen 0:a35c40f49345 1586
boonshen 0:a35c40f49345 1587
boonshen 0:a35c40f49345 1588 /* ########################## NVIC functions #################################### */
boonshen 0:a35c40f49345 1589 /**
boonshen 0:a35c40f49345 1590 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 1591 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
boonshen 0:a35c40f49345 1592 \brief Functions that manage interrupts and exceptions via the NVIC.
boonshen 0:a35c40f49345 1593 @{
boonshen 0:a35c40f49345 1594 */
boonshen 0:a35c40f49345 1595
boonshen 0:a35c40f49345 1596 #ifdef CMSIS_NVIC_VIRTUAL
boonshen 0:a35c40f49345 1597 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1598 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
boonshen 0:a35c40f49345 1599 #endif
boonshen 0:a35c40f49345 1600 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1601 #else
boonshen 0:a35c40f49345 1602 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
boonshen 0:a35c40f49345 1603 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
boonshen 0:a35c40f49345 1604 #define NVIC_EnableIRQ __NVIC_EnableIRQ
boonshen 0:a35c40f49345 1605 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
boonshen 0:a35c40f49345 1606 #define NVIC_DisableIRQ __NVIC_DisableIRQ
boonshen 0:a35c40f49345 1607 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
boonshen 0:a35c40f49345 1608 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
boonshen 0:a35c40f49345 1609 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
boonshen 0:a35c40f49345 1610 #define NVIC_GetActive __NVIC_GetActive
boonshen 0:a35c40f49345 1611 #define NVIC_SetPriority __NVIC_SetPriority
boonshen 0:a35c40f49345 1612 #define NVIC_GetPriority __NVIC_GetPriority
boonshen 0:a35c40f49345 1613 #define NVIC_SystemReset __NVIC_SystemReset
boonshen 0:a35c40f49345 1614 #endif /* CMSIS_NVIC_VIRTUAL */
boonshen 0:a35c40f49345 1615
boonshen 0:a35c40f49345 1616 #ifdef CMSIS_VECTAB_VIRTUAL
boonshen 0:a35c40f49345 1617 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1618 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
boonshen 0:a35c40f49345 1619 #endif
boonshen 0:a35c40f49345 1620 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1621 #else
boonshen 0:a35c40f49345 1622 #define NVIC_SetVector __NVIC_SetVector
boonshen 0:a35c40f49345 1623 #define NVIC_GetVector __NVIC_GetVector
boonshen 0:a35c40f49345 1624 #endif /* (CMSIS_VECTAB_VIRTUAL) */
boonshen 0:a35c40f49345 1625
boonshen 0:a35c40f49345 1626 #define NVIC_USER_IRQ_OFFSET 16
boonshen 0:a35c40f49345 1627
boonshen 0:a35c40f49345 1628
boonshen 0:a35c40f49345 1629
boonshen 0:a35c40f49345 1630 /**
boonshen 0:a35c40f49345 1631 \brief Set Priority Grouping
boonshen 0:a35c40f49345 1632 \details Sets the priority grouping field using the required unlock sequence.
boonshen 0:a35c40f49345 1633 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
boonshen 0:a35c40f49345 1634 Only values from 0..7 are used.
boonshen 0:a35c40f49345 1635 In case of a conflict between priority grouping and available
boonshen 0:a35c40f49345 1636 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
boonshen 0:a35c40f49345 1637 \param [in] PriorityGroup Priority grouping field.
boonshen 0:a35c40f49345 1638 */
boonshen 0:a35c40f49345 1639 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
boonshen 0:a35c40f49345 1640 {
boonshen 0:a35c40f49345 1641 uint32_t reg_value;
boonshen 0:a35c40f49345 1642 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
boonshen 0:a35c40f49345 1643
boonshen 0:a35c40f49345 1644 reg_value = SCB->AIRCR; /* read old register configuration */
boonshen 0:a35c40f49345 1645 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
boonshen 0:a35c40f49345 1646 reg_value = (reg_value |
boonshen 0:a35c40f49345 1647 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
boonshen 0:a35c40f49345 1648 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
boonshen 0:a35c40f49345 1649 SCB->AIRCR = reg_value;
boonshen 0:a35c40f49345 1650 }
boonshen 0:a35c40f49345 1651
boonshen 0:a35c40f49345 1652
boonshen 0:a35c40f49345 1653 /**
boonshen 0:a35c40f49345 1654 \brief Get Priority Grouping
boonshen 0:a35c40f49345 1655 \details Reads the priority grouping field from the NVIC Interrupt Controller.
boonshen 0:a35c40f49345 1656 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
boonshen 0:a35c40f49345 1657 */
boonshen 0:a35c40f49345 1658 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
boonshen 0:a35c40f49345 1659 {
boonshen 0:a35c40f49345 1660 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
boonshen 0:a35c40f49345 1661 }
boonshen 0:a35c40f49345 1662
boonshen 0:a35c40f49345 1663
boonshen 0:a35c40f49345 1664 /**
boonshen 0:a35c40f49345 1665 \brief Enable Interrupt
boonshen 0:a35c40f49345 1666 \details Enables a device specific interrupt in the NVIC interrupt controller.
boonshen 0:a35c40f49345 1667 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1668 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1669 */
boonshen 0:a35c40f49345 1670 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1671 {
boonshen 0:a35c40f49345 1672 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1673 {
boonshen 0:a35c40f49345 1674 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1675 }
boonshen 0:a35c40f49345 1676 }
boonshen 0:a35c40f49345 1677
boonshen 0:a35c40f49345 1678
boonshen 0:a35c40f49345 1679 /**
boonshen 0:a35c40f49345 1680 \brief Get Interrupt Enable status
boonshen 0:a35c40f49345 1681 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
boonshen 0:a35c40f49345 1682 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1683 \return 0 Interrupt is not enabled.
boonshen 0:a35c40f49345 1684 \return 1 Interrupt is enabled.
boonshen 0:a35c40f49345 1685 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1686 */
boonshen 0:a35c40f49345 1687 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1688 {
boonshen 0:a35c40f49345 1689 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1690 {
boonshen 0:a35c40f49345 1691 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1692 }
boonshen 0:a35c40f49345 1693 else
boonshen 0:a35c40f49345 1694 {
boonshen 0:a35c40f49345 1695 return(0U);
boonshen 0:a35c40f49345 1696 }
boonshen 0:a35c40f49345 1697 }
boonshen 0:a35c40f49345 1698
boonshen 0:a35c40f49345 1699
boonshen 0:a35c40f49345 1700 /**
boonshen 0:a35c40f49345 1701 \brief Disable Interrupt
boonshen 0:a35c40f49345 1702 \details Disables a device specific interrupt in the NVIC interrupt controller.
boonshen 0:a35c40f49345 1703 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1704 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1705 */
boonshen 0:a35c40f49345 1706 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1707 {
boonshen 0:a35c40f49345 1708 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1709 {
boonshen 0:a35c40f49345 1710 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1711 __DSB();
boonshen 0:a35c40f49345 1712 __ISB();
boonshen 0:a35c40f49345 1713 }
boonshen 0:a35c40f49345 1714 }
boonshen 0:a35c40f49345 1715
boonshen 0:a35c40f49345 1716
boonshen 0:a35c40f49345 1717 /**
boonshen 0:a35c40f49345 1718 \brief Get Pending Interrupt
boonshen 0:a35c40f49345 1719 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
boonshen 0:a35c40f49345 1720 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1721 \return 0 Interrupt status is not pending.
boonshen 0:a35c40f49345 1722 \return 1 Interrupt status is pending.
boonshen 0:a35c40f49345 1723 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1724 */
boonshen 0:a35c40f49345 1725 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1726 {
boonshen 0:a35c40f49345 1727 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1728 {
boonshen 0:a35c40f49345 1729 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1730 }
boonshen 0:a35c40f49345 1731 else
boonshen 0:a35c40f49345 1732 {
boonshen 0:a35c40f49345 1733 return(0U);
boonshen 0:a35c40f49345 1734 }
boonshen 0:a35c40f49345 1735 }
boonshen 0:a35c40f49345 1736
boonshen 0:a35c40f49345 1737
boonshen 0:a35c40f49345 1738 /**
boonshen 0:a35c40f49345 1739 \brief Set Pending Interrupt
boonshen 0:a35c40f49345 1740 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
boonshen 0:a35c40f49345 1741 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1742 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1743 */
boonshen 0:a35c40f49345 1744 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1745 {
boonshen 0:a35c40f49345 1746 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1747 {
boonshen 0:a35c40f49345 1748 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1749 }
boonshen 0:a35c40f49345 1750 }
boonshen 0:a35c40f49345 1751
boonshen 0:a35c40f49345 1752
boonshen 0:a35c40f49345 1753 /**
boonshen 0:a35c40f49345 1754 \brief Clear Pending Interrupt
boonshen 0:a35c40f49345 1755 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
boonshen 0:a35c40f49345 1756 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1757 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1758 */
boonshen 0:a35c40f49345 1759 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1760 {
boonshen 0:a35c40f49345 1761 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1762 {
boonshen 0:a35c40f49345 1763 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1764 }
boonshen 0:a35c40f49345 1765 }
boonshen 0:a35c40f49345 1766
boonshen 0:a35c40f49345 1767
boonshen 0:a35c40f49345 1768 /**
boonshen 0:a35c40f49345 1769 \brief Get Active Interrupt
boonshen 0:a35c40f49345 1770 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
boonshen 0:a35c40f49345 1771 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1772 \return 0 Interrupt status is not active.
boonshen 0:a35c40f49345 1773 \return 1 Interrupt status is active.
boonshen 0:a35c40f49345 1774 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1775 */
boonshen 0:a35c40f49345 1776 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1777 {
boonshen 0:a35c40f49345 1778 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1779 {
boonshen 0:a35c40f49345 1780 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1781 }
boonshen 0:a35c40f49345 1782 else
boonshen 0:a35c40f49345 1783 {
boonshen 0:a35c40f49345 1784 return(0U);
boonshen 0:a35c40f49345 1785 }
boonshen 0:a35c40f49345 1786 }
boonshen 0:a35c40f49345 1787
boonshen 0:a35c40f49345 1788
boonshen 0:a35c40f49345 1789 /**
boonshen 0:a35c40f49345 1790 \brief Set Interrupt Priority
boonshen 0:a35c40f49345 1791 \details Sets the priority of a device specific interrupt or a processor exception.
boonshen 0:a35c40f49345 1792 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1793 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1794 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1795 \param [in] priority Priority to set.
boonshen 0:a35c40f49345 1796 \note The priority cannot be set for every processor exception.
boonshen 0:a35c40f49345 1797 */
boonshen 0:a35c40f49345 1798 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
boonshen 0:a35c40f49345 1799 {
boonshen 0:a35c40f49345 1800 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1801 {
boonshen 0:a35c40f49345 1802 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
boonshen 0:a35c40f49345 1803 }
boonshen 0:a35c40f49345 1804 else
boonshen 0:a35c40f49345 1805 {
boonshen 0:a35c40f49345 1806 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
boonshen 0:a35c40f49345 1807 }
boonshen 0:a35c40f49345 1808 }
boonshen 0:a35c40f49345 1809
boonshen 0:a35c40f49345 1810
boonshen 0:a35c40f49345 1811 /**
boonshen 0:a35c40f49345 1812 \brief Get Interrupt Priority
boonshen 0:a35c40f49345 1813 \details Reads the priority of a device specific interrupt or a processor exception.
boonshen 0:a35c40f49345 1814 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1815 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1816 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1817 \return Interrupt Priority.
boonshen 0:a35c40f49345 1818 Value is aligned automatically to the implemented priority bits of the microcontroller.
boonshen 0:a35c40f49345 1819 */
boonshen 0:a35c40f49345 1820 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1821 {
boonshen 0:a35c40f49345 1822
boonshen 0:a35c40f49345 1823 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1824 {
boonshen 0:a35c40f49345 1825 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 1826 }
boonshen 0:a35c40f49345 1827 else
boonshen 0:a35c40f49345 1828 {
boonshen 0:a35c40f49345 1829 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 1830 }
boonshen 0:a35c40f49345 1831 }
boonshen 0:a35c40f49345 1832
boonshen 0:a35c40f49345 1833
boonshen 0:a35c40f49345 1834 /**
boonshen 0:a35c40f49345 1835 \brief Encode Priority
boonshen 0:a35c40f49345 1836 \details Encodes the priority for an interrupt with the given priority group,
boonshen 0:a35c40f49345 1837 preemptive priority value, and subpriority value.
boonshen 0:a35c40f49345 1838 In case of a conflict between priority grouping and available
boonshen 0:a35c40f49345 1839 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
boonshen 0:a35c40f49345 1840 \param [in] PriorityGroup Used priority group.
boonshen 0:a35c40f49345 1841 \param [in] PreemptPriority Preemptive priority value (starting from 0).
boonshen 0:a35c40f49345 1842 \param [in] SubPriority Subpriority value (starting from 0).
boonshen 0:a35c40f49345 1843 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
boonshen 0:a35c40f49345 1844 */
boonshen 0:a35c40f49345 1845 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
boonshen 0:a35c40f49345 1846 {
boonshen 0:a35c40f49345 1847 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
boonshen 0:a35c40f49345 1848 uint32_t PreemptPriorityBits;
boonshen 0:a35c40f49345 1849 uint32_t SubPriorityBits;
boonshen 0:a35c40f49345 1850
boonshen 0:a35c40f49345 1851 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
boonshen 0:a35c40f49345 1852 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
boonshen 0:a35c40f49345 1853
boonshen 0:a35c40f49345 1854 return (
boonshen 0:a35c40f49345 1855 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
boonshen 0:a35c40f49345 1856 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
boonshen 0:a35c40f49345 1857 );
boonshen 0:a35c40f49345 1858 }
boonshen 0:a35c40f49345 1859
boonshen 0:a35c40f49345 1860
boonshen 0:a35c40f49345 1861 /**
boonshen 0:a35c40f49345 1862 \brief Decode Priority
boonshen 0:a35c40f49345 1863 \details Decodes an interrupt priority value with a given priority group to
boonshen 0:a35c40f49345 1864 preemptive priority value and subpriority value.
boonshen 0:a35c40f49345 1865 In case of a conflict between priority grouping and available
boonshen 0:a35c40f49345 1866 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
boonshen 0:a35c40f49345 1867 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
boonshen 0:a35c40f49345 1868 \param [in] PriorityGroup Used priority group.
boonshen 0:a35c40f49345 1869 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
boonshen 0:a35c40f49345 1870 \param [out] pSubPriority Subpriority value (starting from 0).
boonshen 0:a35c40f49345 1871 */
boonshen 0:a35c40f49345 1872 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
boonshen 0:a35c40f49345 1873 {
boonshen 0:a35c40f49345 1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
boonshen 0:a35c40f49345 1875 uint32_t PreemptPriorityBits;
boonshen 0:a35c40f49345 1876 uint32_t SubPriorityBits;
boonshen 0:a35c40f49345 1877
boonshen 0:a35c40f49345 1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
boonshen 0:a35c40f49345 1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
boonshen 0:a35c40f49345 1880
boonshen 0:a35c40f49345 1881 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
boonshen 0:a35c40f49345 1882 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
boonshen 0:a35c40f49345 1883 }
boonshen 0:a35c40f49345 1884
boonshen 0:a35c40f49345 1885
boonshen 0:a35c40f49345 1886 /**
boonshen 0:a35c40f49345 1887 \brief Set Interrupt Vector
boonshen 0:a35c40f49345 1888 \details Sets an interrupt vector in SRAM based interrupt vector table.
boonshen 0:a35c40f49345 1889 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1890 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1891 VTOR must been relocated to SRAM before.
boonshen 0:a35c40f49345 1892 \param [in] IRQn Interrupt number
boonshen 0:a35c40f49345 1893 \param [in] vector Address of interrupt handler function
boonshen 0:a35c40f49345 1894 */
boonshen 0:a35c40f49345 1895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
boonshen 0:a35c40f49345 1896 {
boonshen 0:a35c40f49345 1897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
boonshen 0:a35c40f49345 1898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
boonshen 0:a35c40f49345 1899 }
boonshen 0:a35c40f49345 1900
boonshen 0:a35c40f49345 1901
boonshen 0:a35c40f49345 1902 /**
boonshen 0:a35c40f49345 1903 \brief Get Interrupt Vector
boonshen 0:a35c40f49345 1904 \details Reads an interrupt vector from interrupt vector table.
boonshen 0:a35c40f49345 1905 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1906 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1907 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1908 \return Address of interrupt handler function
boonshen 0:a35c40f49345 1909 */
boonshen 0:a35c40f49345 1910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1911 {
boonshen 0:a35c40f49345 1912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
boonshen 0:a35c40f49345 1913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
boonshen 0:a35c40f49345 1914 }
boonshen 0:a35c40f49345 1915
boonshen 0:a35c40f49345 1916
boonshen 0:a35c40f49345 1917 /**
boonshen 0:a35c40f49345 1918 \brief System Reset
boonshen 0:a35c40f49345 1919 \details Initiates a system reset request to reset the MCU.
boonshen 0:a35c40f49345 1920 */
boonshen 0:a35c40f49345 1921 __STATIC_INLINE void __NVIC_SystemReset(void)
boonshen 0:a35c40f49345 1922 {
boonshen 0:a35c40f49345 1923 __DSB(); /* Ensure all outstanding memory accesses included
boonshen 0:a35c40f49345 1924 buffered write are completed before reset */
boonshen 0:a35c40f49345 1925 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
boonshen 0:a35c40f49345 1926 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
boonshen 0:a35c40f49345 1927 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
boonshen 0:a35c40f49345 1928 __DSB(); /* Ensure completion of memory access */
boonshen 0:a35c40f49345 1929
boonshen 0:a35c40f49345 1930 for(;;) /* wait until reset */
boonshen 0:a35c40f49345 1931 {
boonshen 0:a35c40f49345 1932 __NOP();
boonshen 0:a35c40f49345 1933 }
boonshen 0:a35c40f49345 1934 }
boonshen 0:a35c40f49345 1935
boonshen 0:a35c40f49345 1936 /*@} end of CMSIS_Core_NVICFunctions */
boonshen 0:a35c40f49345 1937
boonshen 0:a35c40f49345 1938
boonshen 0:a35c40f49345 1939 /* ########################## FPU functions #################################### */
boonshen 0:a35c40f49345 1940 /**
boonshen 0:a35c40f49345 1941 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 1942 \defgroup CMSIS_Core_FpuFunctions FPU Functions
boonshen 0:a35c40f49345 1943 \brief Function that provides FPU type.
boonshen 0:a35c40f49345 1944 @{
boonshen 0:a35c40f49345 1945 */
boonshen 0:a35c40f49345 1946
boonshen 0:a35c40f49345 1947 /**
boonshen 0:a35c40f49345 1948 \brief get FPU type
boonshen 0:a35c40f49345 1949 \details returns the FPU type
boonshen 0:a35c40f49345 1950 \returns
boonshen 0:a35c40f49345 1951 - \b 0: No FPU
boonshen 0:a35c40f49345 1952 - \b 1: Single precision FPU
boonshen 0:a35c40f49345 1953 - \b 2: Double + Single precision FPU
boonshen 0:a35c40f49345 1954 */
boonshen 0:a35c40f49345 1955 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
boonshen 0:a35c40f49345 1956 {
boonshen 0:a35c40f49345 1957 uint32_t mvfr0;
boonshen 0:a35c40f49345 1958
boonshen 0:a35c40f49345 1959 mvfr0 = FPU->MVFR0;
boonshen 0:a35c40f49345 1960 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
boonshen 0:a35c40f49345 1961 {
boonshen 0:a35c40f49345 1962 return 1U; /* Single precision FPU */
boonshen 0:a35c40f49345 1963 }
boonshen 0:a35c40f49345 1964 else
boonshen 0:a35c40f49345 1965 {
boonshen 0:a35c40f49345 1966 return 0U; /* No FPU */
boonshen 0:a35c40f49345 1967 }
boonshen 0:a35c40f49345 1968 }
boonshen 0:a35c40f49345 1969
boonshen 0:a35c40f49345 1970
boonshen 0:a35c40f49345 1971 /*@} end of CMSIS_Core_FpuFunctions */
boonshen 0:a35c40f49345 1972
boonshen 0:a35c40f49345 1973
boonshen 0:a35c40f49345 1974
boonshen 0:a35c40f49345 1975 /* ################################## SysTick function ############################################ */
boonshen 0:a35c40f49345 1976 /**
boonshen 0:a35c40f49345 1977 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 1978 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
boonshen 0:a35c40f49345 1979 \brief Functions that configure the System.
boonshen 0:a35c40f49345 1980 @{
boonshen 0:a35c40f49345 1981 */
boonshen 0:a35c40f49345 1982
boonshen 0:a35c40f49345 1983 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
boonshen 0:a35c40f49345 1984
boonshen 0:a35c40f49345 1985 /**
boonshen 0:a35c40f49345 1986 \brief System Tick Configuration
boonshen 0:a35c40f49345 1987 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
boonshen 0:a35c40f49345 1988 Counter is in free running mode to generate periodic interrupts.
boonshen 0:a35c40f49345 1989 \param [in] ticks Number of ticks between two interrupts.
boonshen 0:a35c40f49345 1990 \return 0 Function succeeded.
boonshen 0:a35c40f49345 1991 \return 1 Function failed.
boonshen 0:a35c40f49345 1992 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
boonshen 0:a35c40f49345 1993 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
boonshen 0:a35c40f49345 1994 must contain a vendor-specific implementation of this function.
boonshen 0:a35c40f49345 1995 */
boonshen 0:a35c40f49345 1996 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
boonshen 0:a35c40f49345 1997 {
boonshen 0:a35c40f49345 1998 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
boonshen 0:a35c40f49345 1999 {
boonshen 0:a35c40f49345 2000 return (1UL); /* Reload value impossible */
boonshen 0:a35c40f49345 2001 }
boonshen 0:a35c40f49345 2002
boonshen 0:a35c40f49345 2003 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
boonshen 0:a35c40f49345 2004 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
boonshen 0:a35c40f49345 2005 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
boonshen 0:a35c40f49345 2006 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
boonshen 0:a35c40f49345 2007 SysTick_CTRL_TICKINT_Msk |
boonshen 0:a35c40f49345 2008 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
boonshen 0:a35c40f49345 2009 return (0UL); /* Function successful */
boonshen 0:a35c40f49345 2010 }
boonshen 0:a35c40f49345 2011
boonshen 0:a35c40f49345 2012 #endif
boonshen 0:a35c40f49345 2013
boonshen 0:a35c40f49345 2014 /*@} end of CMSIS_Core_SysTickFunctions */
boonshen 0:a35c40f49345 2015
boonshen 0:a35c40f49345 2016
boonshen 0:a35c40f49345 2017
boonshen 0:a35c40f49345 2018 /* ##################################### Debug In/Output function ########################################### */
boonshen 0:a35c40f49345 2019 /**
boonshen 0:a35c40f49345 2020 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 2021 \defgroup CMSIS_core_DebugFunctions ITM Functions
boonshen 0:a35c40f49345 2022 \brief Functions that access the ITM debug interface.
boonshen 0:a35c40f49345 2023 @{
boonshen 0:a35c40f49345 2024 */
boonshen 0:a35c40f49345 2025
boonshen 0:a35c40f49345 2026 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
boonshen 0:a35c40f49345 2027 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
boonshen 0:a35c40f49345 2028
boonshen 0:a35c40f49345 2029
boonshen 0:a35c40f49345 2030 /**
boonshen 0:a35c40f49345 2031 \brief ITM Send Character
boonshen 0:a35c40f49345 2032 \details Transmits a character via the ITM channel 0, and
boonshen 0:a35c40f49345 2033 \li Just returns when no debugger is connected that has booked the output.
boonshen 0:a35c40f49345 2034 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
boonshen 0:a35c40f49345 2035 \param [in] ch Character to transmit.
boonshen 0:a35c40f49345 2036 \returns Character to transmit.
boonshen 0:a35c40f49345 2037 */
boonshen 0:a35c40f49345 2038 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
boonshen 0:a35c40f49345 2039 {
boonshen 0:a35c40f49345 2040 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
boonshen 0:a35c40f49345 2041 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
boonshen 0:a35c40f49345 2042 {
boonshen 0:a35c40f49345 2043 while (ITM->PORT[0U].u32 == 0UL)
boonshen 0:a35c40f49345 2044 {
boonshen 0:a35c40f49345 2045 __NOP();
boonshen 0:a35c40f49345 2046 }
boonshen 0:a35c40f49345 2047 ITM->PORT[0U].u8 = (uint8_t)ch;
boonshen 0:a35c40f49345 2048 }
boonshen 0:a35c40f49345 2049 return (ch);
boonshen 0:a35c40f49345 2050 }
boonshen 0:a35c40f49345 2051
boonshen 0:a35c40f49345 2052
boonshen 0:a35c40f49345 2053 /**
boonshen 0:a35c40f49345 2054 \brief ITM Receive Character
boonshen 0:a35c40f49345 2055 \details Inputs a character via the external variable \ref ITM_RxBuffer.
boonshen 0:a35c40f49345 2056 \return Received character.
boonshen 0:a35c40f49345 2057 \return -1 No character pending.
boonshen 0:a35c40f49345 2058 */
boonshen 0:a35c40f49345 2059 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
boonshen 0:a35c40f49345 2060 {
boonshen 0:a35c40f49345 2061 int32_t ch = -1; /* no character available */
boonshen 0:a35c40f49345 2062
boonshen 0:a35c40f49345 2063 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
boonshen 0:a35c40f49345 2064 {
boonshen 0:a35c40f49345 2065 ch = ITM_RxBuffer;
boonshen 0:a35c40f49345 2066 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
boonshen 0:a35c40f49345 2067 }
boonshen 0:a35c40f49345 2068
boonshen 0:a35c40f49345 2069 return (ch);
boonshen 0:a35c40f49345 2070 }
boonshen 0:a35c40f49345 2071
boonshen 0:a35c40f49345 2072
boonshen 0:a35c40f49345 2073 /**
boonshen 0:a35c40f49345 2074 \brief ITM Check Character
boonshen 0:a35c40f49345 2075 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
boonshen 0:a35c40f49345 2076 \return 0 No character available.
boonshen 0:a35c40f49345 2077 \return 1 Character available.
boonshen 0:a35c40f49345 2078 */
boonshen 0:a35c40f49345 2079 __STATIC_INLINE int32_t ITM_CheckChar (void)
boonshen 0:a35c40f49345 2080 {
boonshen 0:a35c40f49345 2081
boonshen 0:a35c40f49345 2082 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
boonshen 0:a35c40f49345 2083 {
boonshen 0:a35c40f49345 2084 return (0); /* no character available */
boonshen 0:a35c40f49345 2085 }
boonshen 0:a35c40f49345 2086 else
boonshen 0:a35c40f49345 2087 {
boonshen 0:a35c40f49345 2088 return (1); /* character available */
boonshen 0:a35c40f49345 2089 }
boonshen 0:a35c40f49345 2090 }
boonshen 0:a35c40f49345 2091
boonshen 0:a35c40f49345 2092 /*@} end of CMSIS_core_DebugFunctions */
boonshen 0:a35c40f49345 2093
boonshen 0:a35c40f49345 2094
boonshen 0:a35c40f49345 2095
boonshen 0:a35c40f49345 2096
boonshen 0:a35c40f49345 2097 #ifdef __cplusplus
boonshen 0:a35c40f49345 2098 }
boonshen 0:a35c40f49345 2099 #endif
boonshen 0:a35c40f49345 2100
boonshen 0:a35c40f49345 2101 #endif /* __CORE_CM4_H_DEPENDANT */
boonshen 0:a35c40f49345 2102
boonshen 0:a35c40f49345 2103 #endif /* __CMSIS_GENERIC */