Lee Shen / FTHR_USB_serial_qSPI

max32630fthr quad spi , unexpected spi behavior

FTHR_USB_serial/mbed-os/cmsis/core_cm23.h@0:a35c40f49345, 2018-03-13 (annotated)

Committer:
boonshen
Date:
Tue Mar 13 21:12:00 2018 +0000
Revision:
0:a35c40f49345
MAX32630FTHR QuadSPI test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
boonshen 0:a35c40f49345 1 /**************************************************************************//**
boonshen 0:a35c40f49345 2 * @file core_cm23.h
boonshen 0:a35c40f49345 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
boonshen 0:a35c40f49345 4 * @version V5.0.2
boonshen 0:a35c40f49345 5 * @date 13. February 2017
boonshen 0:a35c40f49345 6 ******************************************************************************/
boonshen 0:a35c40f49345 7 /*
boonshen 0:a35c40f49345 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
boonshen 0:a35c40f49345 9 *
boonshen 0:a35c40f49345 10 * SPDX-License-Identifier: Apache-2.0
boonshen 0:a35c40f49345 11 *
boonshen 0:a35c40f49345 12 * Licensed under the Apache License, Version 2.0 (the License); you may
boonshen 0:a35c40f49345 13 * not use this file except in compliance with the License.
boonshen 0:a35c40f49345 14 * You may obtain a copy of the License at
boonshen 0:a35c40f49345 15 *
boonshen 0:a35c40f49345 16 * www.apache.org/licenses/LICENSE-2.0
boonshen 0:a35c40f49345 17 *
boonshen 0:a35c40f49345 18 * Unless required by applicable law or agreed to in writing, software
boonshen 0:a35c40f49345 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
boonshen 0:a35c40f49345 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
boonshen 0:a35c40f49345 21 * See the License for the specific language governing permissions and
boonshen 0:a35c40f49345 22 * limitations under the License.
boonshen 0:a35c40f49345 23 */
boonshen 0:a35c40f49345 24
boonshen 0:a35c40f49345 25 #if defined ( __ICCARM__ )
boonshen 0:a35c40f49345 26 #pragma system_include /* treat file as system include file for MISRA check */
boonshen 0:a35c40f49345 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen 0:a35c40f49345 28 #pragma clang system_header /* treat file as system include file */
boonshen 0:a35c40f49345 29 #endif
boonshen 0:a35c40f49345 30
boonshen 0:a35c40f49345 31 #ifndef __CORE_CM23_H_GENERIC
boonshen 0:a35c40f49345 32 #define __CORE_CM23_H_GENERIC
boonshen 0:a35c40f49345 33
boonshen 0:a35c40f49345 34 #include <stdint.h>
boonshen 0:a35c40f49345 35
boonshen 0:a35c40f49345 36 #ifdef __cplusplus
boonshen 0:a35c40f49345 37 extern "C" {
boonshen 0:a35c40f49345 38 #endif
boonshen 0:a35c40f49345 39
boonshen 0:a35c40f49345 40 /**
boonshen 0:a35c40f49345 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
boonshen 0:a35c40f49345 42 CMSIS violates the following MISRA-C:2004 rules:
boonshen 0:a35c40f49345 43
boonshen 0:a35c40f49345 44 \li Required Rule 8.5, object/function definition in header file.<br>
boonshen 0:a35c40f49345 45 Function definitions in header files are used to allow 'inlining'.
boonshen 0:a35c40f49345 46
boonshen 0:a35c40f49345 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
boonshen 0:a35c40f49345 48 Unions are used for effective representation of core registers.
boonshen 0:a35c40f49345 49
boonshen 0:a35c40f49345 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
boonshen 0:a35c40f49345 51 Function-like macros are used to allow more efficient code.
boonshen 0:a35c40f49345 52 */
boonshen 0:a35c40f49345 53
boonshen 0:a35c40f49345 54
boonshen 0:a35c40f49345 55 /*******************************************************************************
boonshen 0:a35c40f49345 56 * CMSIS definitions
boonshen 0:a35c40f49345 57 ******************************************************************************/
boonshen 0:a35c40f49345 58 /**
boonshen 0:a35c40f49345 59 \ingroup Cortex_M23
boonshen 0:a35c40f49345 60 @{
boonshen 0:a35c40f49345 61 */
boonshen 0:a35c40f49345 62
boonshen 0:a35c40f49345 63 /* CMSIS cmGrebe definitions */
boonshen 0:a35c40f49345 64 #define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
boonshen 0:a35c40f49345 65 #define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
boonshen 0:a35c40f49345 66 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
boonshen 0:a35c40f49345 67 __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
boonshen 0:a35c40f49345 68
boonshen 0:a35c40f49345 69 #define __CORTEX_M (23U) /*!< Cortex-M Core */
boonshen 0:a35c40f49345 70
boonshen 0:a35c40f49345 71 /** __FPU_USED indicates whether an FPU is used or not.
boonshen 0:a35c40f49345 72 This core does not support an FPU at all
boonshen 0:a35c40f49345 73 */
boonshen 0:a35c40f49345 74 #define __FPU_USED 0U
boonshen 0:a35c40f49345 75
boonshen 0:a35c40f49345 76 #if defined ( __CC_ARM )
boonshen 0:a35c40f49345 77 #if defined __TARGET_FPU_VFP
boonshen 0:a35c40f49345 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 79 #endif
boonshen 0:a35c40f49345 80
boonshen 0:a35c40f49345 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen 0:a35c40f49345 82 #if defined __ARM_PCS_VFP
boonshen 0:a35c40f49345 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 84 #endif
boonshen 0:a35c40f49345 85
boonshen 0:a35c40f49345 86 #elif defined ( __GNUC__ )
boonshen 0:a35c40f49345 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
boonshen 0:a35c40f49345 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 89 #endif
boonshen 0:a35c40f49345 90
boonshen 0:a35c40f49345 91 #elif defined ( __ICCARM__ )
boonshen 0:a35c40f49345 92 #if defined __ARMVFP__
boonshen 0:a35c40f49345 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 94 #endif
boonshen 0:a35c40f49345 95
boonshen 0:a35c40f49345 96 #elif defined ( __TI_ARM__ )
boonshen 0:a35c40f49345 97 #if defined __TI_VFP_SUPPORT__
boonshen 0:a35c40f49345 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 99 #endif
boonshen 0:a35c40f49345 100
boonshen 0:a35c40f49345 101 #elif defined ( __TASKING__ )
boonshen 0:a35c40f49345 102 #if defined __FPU_VFP__
boonshen 0:a35c40f49345 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 104 #endif
boonshen 0:a35c40f49345 105
boonshen 0:a35c40f49345 106 #elif defined ( __CSMC__ )
boonshen 0:a35c40f49345 107 #if ( __CSMC__ & 0x400U)
boonshen 0:a35c40f49345 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 109 #endif
boonshen 0:a35c40f49345 110
boonshen 0:a35c40f49345 111 #endif
boonshen 0:a35c40f49345 112
boonshen 0:a35c40f49345 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
boonshen 0:a35c40f49345 114
boonshen 0:a35c40f49345 115
boonshen 0:a35c40f49345 116 #ifdef __cplusplus
boonshen 0:a35c40f49345 117 }
boonshen 0:a35c40f49345 118 #endif
boonshen 0:a35c40f49345 119
boonshen 0:a35c40f49345 120 #endif /* __CORE_CM23_H_GENERIC */
boonshen 0:a35c40f49345 121
boonshen 0:a35c40f49345 122 #ifndef __CMSIS_GENERIC
boonshen 0:a35c40f49345 123
boonshen 0:a35c40f49345 124 #ifndef __CORE_CM23_H_DEPENDANT
boonshen 0:a35c40f49345 125 #define __CORE_CM23_H_DEPENDANT
boonshen 0:a35c40f49345 126
boonshen 0:a35c40f49345 127 #ifdef __cplusplus
boonshen 0:a35c40f49345 128 extern "C" {
boonshen 0:a35c40f49345 129 #endif
boonshen 0:a35c40f49345 130
boonshen 0:a35c40f49345 131 /* check device defines and use defaults */
boonshen 0:a35c40f49345 132 #if defined __CHECK_DEVICE_DEFINES
boonshen 0:a35c40f49345 133 #ifndef __CM23_REV
boonshen 0:a35c40f49345 134 #define __CM23_REV 0x0000U
boonshen 0:a35c40f49345 135 #warning "__CM23_REV not defined in device header file; using default!"
boonshen 0:a35c40f49345 136 #endif
boonshen 0:a35c40f49345 137
boonshen 0:a35c40f49345 138 #ifndef __FPU_PRESENT
boonshen 0:a35c40f49345 139 #define __FPU_PRESENT 0U
boonshen 0:a35c40f49345 140 #warning "__FPU_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 141 #endif
boonshen 0:a35c40f49345 142
boonshen 0:a35c40f49345 143 #ifndef __MPU_PRESENT
boonshen 0:a35c40f49345 144 #define __MPU_PRESENT 0U
boonshen 0:a35c40f49345 145 #warning "__MPU_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 146 #endif
boonshen 0:a35c40f49345 147
boonshen 0:a35c40f49345 148 #ifndef __SAUREGION_PRESENT
boonshen 0:a35c40f49345 149 #define __SAUREGION_PRESENT 0U
boonshen 0:a35c40f49345 150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 151 #endif
boonshen 0:a35c40f49345 152
boonshen 0:a35c40f49345 153 #ifndef __VTOR_PRESENT
boonshen 0:a35c40f49345 154 #define __VTOR_PRESENT 0U
boonshen 0:a35c40f49345 155 #warning "__VTOR_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 156 #endif
boonshen 0:a35c40f49345 157
boonshen 0:a35c40f49345 158 #ifndef __NVIC_PRIO_BITS
boonshen 0:a35c40f49345 159 #define __NVIC_PRIO_BITS 2U
boonshen 0:a35c40f49345 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
boonshen 0:a35c40f49345 161 #endif
boonshen 0:a35c40f49345 162
boonshen 0:a35c40f49345 163 #ifndef __Vendor_SysTickConfig
boonshen 0:a35c40f49345 164 #define __Vendor_SysTickConfig 0U
boonshen 0:a35c40f49345 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
boonshen 0:a35c40f49345 166 #endif
boonshen 0:a35c40f49345 167
boonshen 0:a35c40f49345 168 #ifndef __ETM_PRESENT
boonshen 0:a35c40f49345 169 #define __ETM_PRESENT 0U
boonshen 0:a35c40f49345 170 #warning "__ETM_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 171 #endif
boonshen 0:a35c40f49345 172
boonshen 0:a35c40f49345 173 #ifndef __MTB_PRESENT
boonshen 0:a35c40f49345 174 #define __MTB_PRESENT 0U
boonshen 0:a35c40f49345 175 #warning "__MTB_PRESENT not defined in device header file; using default!"
boonshen 0:a35c40f49345 176 #endif
boonshen 0:a35c40f49345 177
boonshen 0:a35c40f49345 178 #endif
boonshen 0:a35c40f49345 179
boonshen 0:a35c40f49345 180 /* IO definitions (access restrictions to peripheral registers) */
boonshen 0:a35c40f49345 181 /**
boonshen 0:a35c40f49345 182 \defgroup CMSIS_glob_defs CMSIS Global Defines
boonshen 0:a35c40f49345 183
boonshen 0:a35c40f49345 184 <strong>IO Type Qualifiers</strong> are used
boonshen 0:a35c40f49345 185 \li to specify the access to peripheral variables.
boonshen 0:a35c40f49345 186 \li for automatic generation of peripheral register debug information.
boonshen 0:a35c40f49345 187 */
boonshen 0:a35c40f49345 188 #ifdef __cplusplus
boonshen 0:a35c40f49345 189 #define __I volatile /*!< Defines 'read only' permissions */
boonshen 0:a35c40f49345 190 #else
boonshen 0:a35c40f49345 191 #define __I volatile const /*!< Defines 'read only' permissions */
boonshen 0:a35c40f49345 192 #endif
boonshen 0:a35c40f49345 193 #define __O volatile /*!< Defines 'write only' permissions */
boonshen 0:a35c40f49345 194 #define __IO volatile /*!< Defines 'read / write' permissions */
boonshen 0:a35c40f49345 195
boonshen 0:a35c40f49345 196 /* following defines should be used for structure members */
boonshen 0:a35c40f49345 197 #define __IM volatile const /*! Defines 'read only' structure member permissions */
boonshen 0:a35c40f49345 198 #define __OM volatile /*! Defines 'write only' structure member permissions */
boonshen 0:a35c40f49345 199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
boonshen 0:a35c40f49345 200
boonshen 0:a35c40f49345 201 /*@} end of group Cortex_M23 */
boonshen 0:a35c40f49345 202
boonshen 0:a35c40f49345 203
boonshen 0:a35c40f49345 204
boonshen 0:a35c40f49345 205 /*******************************************************************************
boonshen 0:a35c40f49345 206 * Register Abstraction
boonshen 0:a35c40f49345 207 Core Register contain:
boonshen 0:a35c40f49345 208 - Core Register
boonshen 0:a35c40f49345 209 - Core NVIC Register
boonshen 0:a35c40f49345 210 - Core SCB Register
boonshen 0:a35c40f49345 211 - Core SysTick Register
boonshen 0:a35c40f49345 212 - Core Debug Register
boonshen 0:a35c40f49345 213 - Core MPU Register
boonshen 0:a35c40f49345 214 - Core SAU Register
boonshen 0:a35c40f49345 215 ******************************************************************************/
boonshen 0:a35c40f49345 216 /**
boonshen 0:a35c40f49345 217 \defgroup CMSIS_core_register Defines and Type Definitions
boonshen 0:a35c40f49345 218 \brief Type definitions and defines for Cortex-M processor based devices.
boonshen 0:a35c40f49345 219 */
boonshen 0:a35c40f49345 220
boonshen 0:a35c40f49345 221 /**
boonshen 0:a35c40f49345 222 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 223 \defgroup CMSIS_CORE Status and Control Registers
boonshen 0:a35c40f49345 224 \brief Core Register type definitions.
boonshen 0:a35c40f49345 225 @{
boonshen 0:a35c40f49345 226 */
boonshen 0:a35c40f49345 227
boonshen 0:a35c40f49345 228 /**
boonshen 0:a35c40f49345 229 \brief Union type to access the Application Program Status Register (APSR).
boonshen 0:a35c40f49345 230 */
boonshen 0:a35c40f49345 231 typedef union
boonshen 0:a35c40f49345 232 {
boonshen 0:a35c40f49345 233 struct
boonshen 0:a35c40f49345 234 {
boonshen 0:a35c40f49345 235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
boonshen 0:a35c40f49345 236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
boonshen 0:a35c40f49345 237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
boonshen 0:a35c40f49345 238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
boonshen 0:a35c40f49345 239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
boonshen 0:a35c40f49345 240 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 241 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 242 } APSR_Type;
boonshen 0:a35c40f49345 243
boonshen 0:a35c40f49345 244 /* APSR Register Definitions */
boonshen 0:a35c40f49345 245 #define APSR_N_Pos 31U /*!< APSR: N Position */
boonshen 0:a35c40f49345 246 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
boonshen 0:a35c40f49345 247
boonshen 0:a35c40f49345 248 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
boonshen 0:a35c40f49345 249 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
boonshen 0:a35c40f49345 250
boonshen 0:a35c40f49345 251 #define APSR_C_Pos 29U /*!< APSR: C Position */
boonshen 0:a35c40f49345 252 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
boonshen 0:a35c40f49345 253
boonshen 0:a35c40f49345 254 #define APSR_V_Pos 28U /*!< APSR: V Position */
boonshen 0:a35c40f49345 255 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
boonshen 0:a35c40f49345 256
boonshen 0:a35c40f49345 257
boonshen 0:a35c40f49345 258 /**
boonshen 0:a35c40f49345 259 \brief Union type to access the Interrupt Program Status Register (IPSR).
boonshen 0:a35c40f49345 260 */
boonshen 0:a35c40f49345 261 typedef union
boonshen 0:a35c40f49345 262 {
boonshen 0:a35c40f49345 263 struct
boonshen 0:a35c40f49345 264 {
boonshen 0:a35c40f49345 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
boonshen 0:a35c40f49345 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
boonshen 0:a35c40f49345 267 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 268 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 269 } IPSR_Type;
boonshen 0:a35c40f49345 270
boonshen 0:a35c40f49345 271 /* IPSR Register Definitions */
boonshen 0:a35c40f49345 272 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
boonshen 0:a35c40f49345 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
boonshen 0:a35c40f49345 274
boonshen 0:a35c40f49345 275
boonshen 0:a35c40f49345 276 /**
boonshen 0:a35c40f49345 277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
boonshen 0:a35c40f49345 278 */
boonshen 0:a35c40f49345 279 typedef union
boonshen 0:a35c40f49345 280 {
boonshen 0:a35c40f49345 281 struct
boonshen 0:a35c40f49345 282 {
boonshen 0:a35c40f49345 283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
boonshen 0:a35c40f49345 284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
boonshen 0:a35c40f49345 285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
boonshen 0:a35c40f49345 286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
boonshen 0:a35c40f49345 287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
boonshen 0:a35c40f49345 288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
boonshen 0:a35c40f49345 289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
boonshen 0:a35c40f49345 290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
boonshen 0:a35c40f49345 291 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 292 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 293 } xPSR_Type;
boonshen 0:a35c40f49345 294
boonshen 0:a35c40f49345 295 /* xPSR Register Definitions */
boonshen 0:a35c40f49345 296 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
boonshen 0:a35c40f49345 297 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
boonshen 0:a35c40f49345 298
boonshen 0:a35c40f49345 299 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
boonshen 0:a35c40f49345 300 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
boonshen 0:a35c40f49345 301
boonshen 0:a35c40f49345 302 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
boonshen 0:a35c40f49345 303 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
boonshen 0:a35c40f49345 304
boonshen 0:a35c40f49345 305 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
boonshen 0:a35c40f49345 306 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
boonshen 0:a35c40f49345 307
boonshen 0:a35c40f49345 308 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
boonshen 0:a35c40f49345 309 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
boonshen 0:a35c40f49345 310
boonshen 0:a35c40f49345 311 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
boonshen 0:a35c40f49345 312 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
boonshen 0:a35c40f49345 313
boonshen 0:a35c40f49345 314
boonshen 0:a35c40f49345 315 /**
boonshen 0:a35c40f49345 316 \brief Union type to access the Control Registers (CONTROL).
boonshen 0:a35c40f49345 317 */
boonshen 0:a35c40f49345 318 typedef union
boonshen 0:a35c40f49345 319 {
boonshen 0:a35c40f49345 320 struct
boonshen 0:a35c40f49345 321 {
boonshen 0:a35c40f49345 322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
boonshen 0:a35c40f49345 323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
boonshen 0:a35c40f49345 324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
boonshen 0:a35c40f49345 325 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 326 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 327 } CONTROL_Type;
boonshen 0:a35c40f49345 328
boonshen 0:a35c40f49345 329 /* CONTROL Register Definitions */
boonshen 0:a35c40f49345 330 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
boonshen 0:a35c40f49345 331 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
boonshen 0:a35c40f49345 332
boonshen 0:a35c40f49345 333 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
boonshen 0:a35c40f49345 334 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
boonshen 0:a35c40f49345 335
boonshen 0:a35c40f49345 336 /*@} end of group CMSIS_CORE */
boonshen 0:a35c40f49345 337
boonshen 0:a35c40f49345 338
boonshen 0:a35c40f49345 339 /**
boonshen 0:a35c40f49345 340 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
boonshen 0:a35c40f49345 342 \brief Type definitions for the NVIC Registers
boonshen 0:a35c40f49345 343 @{
boonshen 0:a35c40f49345 344 */
boonshen 0:a35c40f49345 345
boonshen 0:a35c40f49345 346 /**
boonshen 0:a35c40f49345 347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
boonshen 0:a35c40f49345 348 */
boonshen 0:a35c40f49345 349 typedef struct
boonshen 0:a35c40f49345 350 {
boonshen 0:a35c40f49345 351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
boonshen 0:a35c40f49345 352 uint32_t RESERVED0[16U];
boonshen 0:a35c40f49345 353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
boonshen 0:a35c40f49345 354 uint32_t RSERVED1[16U];
boonshen 0:a35c40f49345 355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
boonshen 0:a35c40f49345 356 uint32_t RESERVED2[16U];
boonshen 0:a35c40f49345 357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
boonshen 0:a35c40f49345 358 uint32_t RESERVED3[16U];
boonshen 0:a35c40f49345 359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
boonshen 0:a35c40f49345 360 uint32_t RESERVED4[16U];
boonshen 0:a35c40f49345 361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
boonshen 0:a35c40f49345 362 uint32_t RESERVED5[16U];
boonshen 0:a35c40f49345 363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
boonshen 0:a35c40f49345 364 } NVIC_Type;
boonshen 0:a35c40f49345 365
boonshen 0:a35c40f49345 366 /*@} end of group CMSIS_NVIC */
boonshen 0:a35c40f49345 367
boonshen 0:a35c40f49345 368
boonshen 0:a35c40f49345 369 /**
boonshen 0:a35c40f49345 370 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 371 \defgroup CMSIS_SCB System Control Block (SCB)
boonshen 0:a35c40f49345 372 \brief Type definitions for the System Control Block Registers
boonshen 0:a35c40f49345 373 @{
boonshen 0:a35c40f49345 374 */
boonshen 0:a35c40f49345 375
boonshen 0:a35c40f49345 376 /**
boonshen 0:a35c40f49345 377 \brief Structure type to access the System Control Block (SCB).
boonshen 0:a35c40f49345 378 */
boonshen 0:a35c40f49345 379 typedef struct
boonshen 0:a35c40f49345 380 {
boonshen 0:a35c40f49345 381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
boonshen 0:a35c40f49345 382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
boonshen 0:a35c40f49345 383 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
boonshen 0:a35c40f49345 384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
boonshen 0:a35c40f49345 385 #else
boonshen 0:a35c40f49345 386 uint32_t RESERVED0;
boonshen 0:a35c40f49345 387 #endif
boonshen 0:a35c40f49345 388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
boonshen 0:a35c40f49345 389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
boonshen 0:a35c40f49345 390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
boonshen 0:a35c40f49345 391 uint32_t RESERVED1;
boonshen 0:a35c40f49345 392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
boonshen 0:a35c40f49345 393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
boonshen 0:a35c40f49345 394 } SCB_Type;
boonshen 0:a35c40f49345 395
boonshen 0:a35c40f49345 396 /* SCB CPUID Register Definitions */
boonshen 0:a35c40f49345 397 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
boonshen 0:a35c40f49345 398 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
boonshen 0:a35c40f49345 399
boonshen 0:a35c40f49345 400 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
boonshen 0:a35c40f49345 401 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
boonshen 0:a35c40f49345 402
boonshen 0:a35c40f49345 403 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
boonshen 0:a35c40f49345 404 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
boonshen 0:a35c40f49345 405
boonshen 0:a35c40f49345 406 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
boonshen 0:a35c40f49345 407 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
boonshen 0:a35c40f49345 408
boonshen 0:a35c40f49345 409 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
boonshen 0:a35c40f49345 410 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
boonshen 0:a35c40f49345 411
boonshen 0:a35c40f49345 412 /* SCB Interrupt Control State Register Definitions */
boonshen 0:a35c40f49345 413 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
boonshen 0:a35c40f49345 414 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
boonshen 0:a35c40f49345 415
boonshen 0:a35c40f49345 416 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
boonshen 0:a35c40f49345 417 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
boonshen 0:a35c40f49345 418
boonshen 0:a35c40f49345 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
boonshen 0:a35c40f49345 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
boonshen 0:a35c40f49345 421
boonshen 0:a35c40f49345 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
boonshen 0:a35c40f49345 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
boonshen 0:a35c40f49345 424
boonshen 0:a35c40f49345 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
boonshen 0:a35c40f49345 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
boonshen 0:a35c40f49345 427
boonshen 0:a35c40f49345 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
boonshen 0:a35c40f49345 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
boonshen 0:a35c40f49345 430
boonshen 0:a35c40f49345 431 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
boonshen 0:a35c40f49345 432 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
boonshen 0:a35c40f49345 433
boonshen 0:a35c40f49345 434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
boonshen 0:a35c40f49345 435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
boonshen 0:a35c40f49345 436
boonshen 0:a35c40f49345 437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
boonshen 0:a35c40f49345 438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
boonshen 0:a35c40f49345 439
boonshen 0:a35c40f49345 440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
boonshen 0:a35c40f49345 441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
boonshen 0:a35c40f49345 442
boonshen 0:a35c40f49345 443 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
boonshen 0:a35c40f49345 444 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
boonshen 0:a35c40f49345 445
boonshen 0:a35c40f49345 446 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
boonshen 0:a35c40f49345 447 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
boonshen 0:a35c40f49345 448
boonshen 0:a35c40f49345 449 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
boonshen 0:a35c40f49345 450 /* SCB Vector Table Offset Register Definitions */
boonshen 0:a35c40f49345 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
boonshen 0:a35c40f49345 452 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
boonshen 0:a35c40f49345 453 #endif
boonshen 0:a35c40f49345 454
boonshen 0:a35c40f49345 455 /* SCB Application Interrupt and Reset Control Register Definitions */
boonshen 0:a35c40f49345 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
boonshen 0:a35c40f49345 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
boonshen 0:a35c40f49345 458
boonshen 0:a35c40f49345 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
boonshen 0:a35c40f49345 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
boonshen 0:a35c40f49345 461
boonshen 0:a35c40f49345 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
boonshen 0:a35c40f49345 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
boonshen 0:a35c40f49345 464
boonshen 0:a35c40f49345 465 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
boonshen 0:a35c40f49345 466 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
boonshen 0:a35c40f49345 467
boonshen 0:a35c40f49345 468 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
boonshen 0:a35c40f49345 469 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
boonshen 0:a35c40f49345 470
boonshen 0:a35c40f49345 471 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
boonshen 0:a35c40f49345 472 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
boonshen 0:a35c40f49345 473
boonshen 0:a35c40f49345 474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
boonshen 0:a35c40f49345 475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
boonshen 0:a35c40f49345 476
boonshen 0:a35c40f49345 477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
boonshen 0:a35c40f49345 478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
boonshen 0:a35c40f49345 479
boonshen 0:a35c40f49345 480 /* SCB System Control Register Definitions */
boonshen 0:a35c40f49345 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
boonshen 0:a35c40f49345 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
boonshen 0:a35c40f49345 483
boonshen 0:a35c40f49345 484 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
boonshen 0:a35c40f49345 485 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
boonshen 0:a35c40f49345 486
boonshen 0:a35c40f49345 487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
boonshen 0:a35c40f49345 488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
boonshen 0:a35c40f49345 489
boonshen 0:a35c40f49345 490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
boonshen 0:a35c40f49345 491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
boonshen 0:a35c40f49345 492
boonshen 0:a35c40f49345 493 /* SCB Configuration Control Register Definitions */
boonshen 0:a35c40f49345 494 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
boonshen 0:a35c40f49345 495 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
boonshen 0:a35c40f49345 496
boonshen 0:a35c40f49345 497 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
boonshen 0:a35c40f49345 498 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
boonshen 0:a35c40f49345 499
boonshen 0:a35c40f49345 500 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
boonshen 0:a35c40f49345 501 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
boonshen 0:a35c40f49345 502
boonshen 0:a35c40f49345 503 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
boonshen 0:a35c40f49345 504 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
boonshen 0:a35c40f49345 505
boonshen 0:a35c40f49345 506 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
boonshen 0:a35c40f49345 507 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
boonshen 0:a35c40f49345 508
boonshen 0:a35c40f49345 509 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
boonshen 0:a35c40f49345 510 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
boonshen 0:a35c40f49345 511
boonshen 0:a35c40f49345 512 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
boonshen 0:a35c40f49345 513 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
boonshen 0:a35c40f49345 514
boonshen 0:a35c40f49345 515 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
boonshen 0:a35c40f49345 516 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
boonshen 0:a35c40f49345 517
boonshen 0:a35c40f49345 518 /* SCB System Handler Control and State Register Definitions */
boonshen 0:a35c40f49345 519 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
boonshen 0:a35c40f49345 520 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
boonshen 0:a35c40f49345 521
boonshen 0:a35c40f49345 522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
boonshen 0:a35c40f49345 523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
boonshen 0:a35c40f49345 524
boonshen 0:a35c40f49345 525 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
boonshen 0:a35c40f49345 526 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
boonshen 0:a35c40f49345 527
boonshen 0:a35c40f49345 528 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
boonshen 0:a35c40f49345 529 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
boonshen 0:a35c40f49345 530
boonshen 0:a35c40f49345 531 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
boonshen 0:a35c40f49345 532 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
boonshen 0:a35c40f49345 533
boonshen 0:a35c40f49345 534 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
boonshen 0:a35c40f49345 535 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
boonshen 0:a35c40f49345 536
boonshen 0:a35c40f49345 537 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
boonshen 0:a35c40f49345 538 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
boonshen 0:a35c40f49345 539
boonshen 0:a35c40f49345 540 /*@} end of group CMSIS_SCB */
boonshen 0:a35c40f49345 541
boonshen 0:a35c40f49345 542
boonshen 0:a35c40f49345 543 /**
boonshen 0:a35c40f49345 544 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 545 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
boonshen 0:a35c40f49345 546 \brief Type definitions for the System Timer Registers.
boonshen 0:a35c40f49345 547 @{
boonshen 0:a35c40f49345 548 */
boonshen 0:a35c40f49345 549
boonshen 0:a35c40f49345 550 /**
boonshen 0:a35c40f49345 551 \brief Structure type to access the System Timer (SysTick).
boonshen 0:a35c40f49345 552 */
boonshen 0:a35c40f49345 553 typedef struct
boonshen 0:a35c40f49345 554 {
boonshen 0:a35c40f49345 555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
boonshen 0:a35c40f49345 556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
boonshen 0:a35c40f49345 557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
boonshen 0:a35c40f49345 558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
boonshen 0:a35c40f49345 559 } SysTick_Type;
boonshen 0:a35c40f49345 560
boonshen 0:a35c40f49345 561 /* SysTick Control / Status Register Definitions */
boonshen 0:a35c40f49345 562 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
boonshen 0:a35c40f49345 563 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
boonshen 0:a35c40f49345 564
boonshen 0:a35c40f49345 565 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
boonshen 0:a35c40f49345 566 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
boonshen 0:a35c40f49345 567
boonshen 0:a35c40f49345 568 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
boonshen 0:a35c40f49345 569 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
boonshen 0:a35c40f49345 570
boonshen 0:a35c40f49345 571 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
boonshen 0:a35c40f49345 572 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
boonshen 0:a35c40f49345 573
boonshen 0:a35c40f49345 574 /* SysTick Reload Register Definitions */
boonshen 0:a35c40f49345 575 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
boonshen 0:a35c40f49345 576 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
boonshen 0:a35c40f49345 577
boonshen 0:a35c40f49345 578 /* SysTick Current Register Definitions */
boonshen 0:a35c40f49345 579 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
boonshen 0:a35c40f49345 580 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
boonshen 0:a35c40f49345 581
boonshen 0:a35c40f49345 582 /* SysTick Calibration Register Definitions */
boonshen 0:a35c40f49345 583 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
boonshen 0:a35c40f49345 584 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
boonshen 0:a35c40f49345 585
boonshen 0:a35c40f49345 586 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
boonshen 0:a35c40f49345 587 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
boonshen 0:a35c40f49345 588
boonshen 0:a35c40f49345 589 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
boonshen 0:a35c40f49345 590 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
boonshen 0:a35c40f49345 591
boonshen 0:a35c40f49345 592 /*@} end of group CMSIS_SysTick */
boonshen 0:a35c40f49345 593
boonshen 0:a35c40f49345 594
boonshen 0:a35c40f49345 595 /**
boonshen 0:a35c40f49345 596 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
boonshen 0:a35c40f49345 598 \brief Type definitions for the Data Watchpoint and Trace (DWT)
boonshen 0:a35c40f49345 599 @{
boonshen 0:a35c40f49345 600 */
boonshen 0:a35c40f49345 601
boonshen 0:a35c40f49345 602 /**
boonshen 0:a35c40f49345 603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
boonshen 0:a35c40f49345 604 */
boonshen 0:a35c40f49345 605 typedef struct
boonshen 0:a35c40f49345 606 {
boonshen 0:a35c40f49345 607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
boonshen 0:a35c40f49345 608 uint32_t RESERVED0[6U];
boonshen 0:a35c40f49345 609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
boonshen 0:a35c40f49345 610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
boonshen 0:a35c40f49345 611 uint32_t RESERVED1[1U];
boonshen 0:a35c40f49345 612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
boonshen 0:a35c40f49345 613 uint32_t RESERVED2[1U];
boonshen 0:a35c40f49345 614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
boonshen 0:a35c40f49345 615 uint32_t RESERVED3[1U];
boonshen 0:a35c40f49345 616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
boonshen 0:a35c40f49345 617 uint32_t RESERVED4[1U];
boonshen 0:a35c40f49345 618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
boonshen 0:a35c40f49345 619 uint32_t RESERVED5[1U];
boonshen 0:a35c40f49345 620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
boonshen 0:a35c40f49345 621 uint32_t RESERVED6[1U];
boonshen 0:a35c40f49345 622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
boonshen 0:a35c40f49345 623 uint32_t RESERVED7[1U];
boonshen 0:a35c40f49345 624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
boonshen 0:a35c40f49345 625 uint32_t RESERVED8[1U];
boonshen 0:a35c40f49345 626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
boonshen 0:a35c40f49345 627 uint32_t RESERVED9[1U];
boonshen 0:a35c40f49345 628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
boonshen 0:a35c40f49345 629 uint32_t RESERVED10[1U];
boonshen 0:a35c40f49345 630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
boonshen 0:a35c40f49345 631 uint32_t RESERVED11[1U];
boonshen 0:a35c40f49345 632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
boonshen 0:a35c40f49345 633 uint32_t RESERVED12[1U];
boonshen 0:a35c40f49345 634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
boonshen 0:a35c40f49345 635 uint32_t RESERVED13[1U];
boonshen 0:a35c40f49345 636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
boonshen 0:a35c40f49345 637 uint32_t RESERVED14[1U];
boonshen 0:a35c40f49345 638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
boonshen 0:a35c40f49345 639 uint32_t RESERVED15[1U];
boonshen 0:a35c40f49345 640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
boonshen 0:a35c40f49345 641 uint32_t RESERVED16[1U];
boonshen 0:a35c40f49345 642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
boonshen 0:a35c40f49345 643 uint32_t RESERVED17[1U];
boonshen 0:a35c40f49345 644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
boonshen 0:a35c40f49345 645 uint32_t RESERVED18[1U];
boonshen 0:a35c40f49345 646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
boonshen 0:a35c40f49345 647 uint32_t RESERVED19[1U];
boonshen 0:a35c40f49345 648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
boonshen 0:a35c40f49345 649 uint32_t RESERVED20[1U];
boonshen 0:a35c40f49345 650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
boonshen 0:a35c40f49345 651 uint32_t RESERVED21[1U];
boonshen 0:a35c40f49345 652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
boonshen 0:a35c40f49345 653 uint32_t RESERVED22[1U];
boonshen 0:a35c40f49345 654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
boonshen 0:a35c40f49345 655 uint32_t RESERVED23[1U];
boonshen 0:a35c40f49345 656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
boonshen 0:a35c40f49345 657 uint32_t RESERVED24[1U];
boonshen 0:a35c40f49345 658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
boonshen 0:a35c40f49345 659 uint32_t RESERVED25[1U];
boonshen 0:a35c40f49345 660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
boonshen 0:a35c40f49345 661 uint32_t RESERVED26[1U];
boonshen 0:a35c40f49345 662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
boonshen 0:a35c40f49345 663 uint32_t RESERVED27[1U];
boonshen 0:a35c40f49345 664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
boonshen 0:a35c40f49345 665 uint32_t RESERVED28[1U];
boonshen 0:a35c40f49345 666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
boonshen 0:a35c40f49345 667 uint32_t RESERVED29[1U];
boonshen 0:a35c40f49345 668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
boonshen 0:a35c40f49345 669 uint32_t RESERVED30[1U];
boonshen 0:a35c40f49345 670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
boonshen 0:a35c40f49345 671 uint32_t RESERVED31[1U];
boonshen 0:a35c40f49345 672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
boonshen 0:a35c40f49345 673 } DWT_Type;
boonshen 0:a35c40f49345 674
boonshen 0:a35c40f49345 675 /* DWT Control Register Definitions */
boonshen 0:a35c40f49345 676 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
boonshen 0:a35c40f49345 677 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
boonshen 0:a35c40f49345 678
boonshen 0:a35c40f49345 679 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
boonshen 0:a35c40f49345 680 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
boonshen 0:a35c40f49345 681
boonshen 0:a35c40f49345 682 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
boonshen 0:a35c40f49345 683 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
boonshen 0:a35c40f49345 684
boonshen 0:a35c40f49345 685 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
boonshen 0:a35c40f49345 686 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
boonshen 0:a35c40f49345 687
boonshen 0:a35c40f49345 688 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
boonshen 0:a35c40f49345 689 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
boonshen 0:a35c40f49345 690
boonshen 0:a35c40f49345 691 /* DWT Comparator Function Register Definitions */
boonshen 0:a35c40f49345 692 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
boonshen 0:a35c40f49345 693 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
boonshen 0:a35c40f49345 694
boonshen 0:a35c40f49345 695 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
boonshen 0:a35c40f49345 696 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
boonshen 0:a35c40f49345 697
boonshen 0:a35c40f49345 698 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
boonshen 0:a35c40f49345 699 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
boonshen 0:a35c40f49345 700
boonshen 0:a35c40f49345 701 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
boonshen 0:a35c40f49345 702 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
boonshen 0:a35c40f49345 703
boonshen 0:a35c40f49345 704 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
boonshen 0:a35c40f49345 705 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
boonshen 0:a35c40f49345 706
boonshen 0:a35c40f49345 707 /*@}*/ /* end of group CMSIS_DWT */
boonshen 0:a35c40f49345 708
boonshen 0:a35c40f49345 709
boonshen 0:a35c40f49345 710 /**
boonshen 0:a35c40f49345 711 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 712 \defgroup CMSIS_TPI Trace Port Interface (TPI)
boonshen 0:a35c40f49345 713 \brief Type definitions for the Trace Port Interface (TPI)
boonshen 0:a35c40f49345 714 @{
boonshen 0:a35c40f49345 715 */
boonshen 0:a35c40f49345 716
boonshen 0:a35c40f49345 717 /**
boonshen 0:a35c40f49345 718 \brief Structure type to access the Trace Port Interface Register (TPI).
boonshen 0:a35c40f49345 719 */
boonshen 0:a35c40f49345 720 typedef struct
boonshen 0:a35c40f49345 721 {
boonshen 0:a35c40f49345 722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
boonshen 0:a35c40f49345 723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
boonshen 0:a35c40f49345 724 uint32_t RESERVED0[2U];
boonshen 0:a35c40f49345 725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
boonshen 0:a35c40f49345 726 uint32_t RESERVED1[55U];
boonshen 0:a35c40f49345 727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
boonshen 0:a35c40f49345 728 uint32_t RESERVED2[131U];
boonshen 0:a35c40f49345 729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
boonshen 0:a35c40f49345 730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
boonshen 0:a35c40f49345 731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
boonshen 0:a35c40f49345 732 uint32_t RESERVED3[759U];
boonshen 0:a35c40f49345 733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
boonshen 0:a35c40f49345 734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
boonshen 0:a35c40f49345 735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
boonshen 0:a35c40f49345 736 uint32_t RESERVED4[1U];
boonshen 0:a35c40f49345 737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
boonshen 0:a35c40f49345 738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
boonshen 0:a35c40f49345 739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
boonshen 0:a35c40f49345 740 uint32_t RESERVED5[39U];
boonshen 0:a35c40f49345 741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
boonshen 0:a35c40f49345 742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
boonshen 0:a35c40f49345 743 uint32_t RESERVED7[8U];
boonshen 0:a35c40f49345 744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
boonshen 0:a35c40f49345 745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
boonshen 0:a35c40f49345 746 } TPI_Type;
boonshen 0:a35c40f49345 747
boonshen 0:a35c40f49345 748 /* TPI Asynchronous Clock Prescaler Register Definitions */
boonshen 0:a35c40f49345 749 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
boonshen 0:a35c40f49345 750 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
boonshen 0:a35c40f49345 751
boonshen 0:a35c40f49345 752 /* TPI Selected Pin Protocol Register Definitions */
boonshen 0:a35c40f49345 753 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
boonshen 0:a35c40f49345 754 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
boonshen 0:a35c40f49345 755
boonshen 0:a35c40f49345 756 /* TPI Formatter and Flush Status Register Definitions */
boonshen 0:a35c40f49345 757 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
boonshen 0:a35c40f49345 758 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
boonshen 0:a35c40f49345 759
boonshen 0:a35c40f49345 760 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
boonshen 0:a35c40f49345 761 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
boonshen 0:a35c40f49345 762
boonshen 0:a35c40f49345 763 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
boonshen 0:a35c40f49345 764 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
boonshen 0:a35c40f49345 765
boonshen 0:a35c40f49345 766 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
boonshen 0:a35c40f49345 767 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
boonshen 0:a35c40f49345 768
boonshen 0:a35c40f49345 769 /* TPI Formatter and Flush Control Register Definitions */
boonshen 0:a35c40f49345 770 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
boonshen 0:a35c40f49345 771 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
boonshen 0:a35c40f49345 772
boonshen 0:a35c40f49345 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
boonshen 0:a35c40f49345 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
boonshen 0:a35c40f49345 775
boonshen 0:a35c40f49345 776 /* TPI TRIGGER Register Definitions */
boonshen 0:a35c40f49345 777 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
boonshen 0:a35c40f49345 778 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
boonshen 0:a35c40f49345 779
boonshen 0:a35c40f49345 780 /* TPI Integration ETM Data Register Definitions (FIFO0) */
boonshen 0:a35c40f49345 781 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
boonshen 0:a35c40f49345 782 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
boonshen 0:a35c40f49345 783
boonshen 0:a35c40f49345 784 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
boonshen 0:a35c40f49345 785 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
boonshen 0:a35c40f49345 786
boonshen 0:a35c40f49345 787 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
boonshen 0:a35c40f49345 788 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
boonshen 0:a35c40f49345 789
boonshen 0:a35c40f49345 790 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
boonshen 0:a35c40f49345 791 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
boonshen 0:a35c40f49345 792
boonshen 0:a35c40f49345 793 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
boonshen 0:a35c40f49345 794 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
boonshen 0:a35c40f49345 795
boonshen 0:a35c40f49345 796 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
boonshen 0:a35c40f49345 797 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
boonshen 0:a35c40f49345 798
boonshen 0:a35c40f49345 799 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
boonshen 0:a35c40f49345 800 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
boonshen 0:a35c40f49345 801
boonshen 0:a35c40f49345 802 /* TPI ITATBCTR2 Register Definitions */
boonshen 0:a35c40f49345 803 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
boonshen 0:a35c40f49345 804 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
boonshen 0:a35c40f49345 805
boonshen 0:a35c40f49345 806 /* TPI Integration ITM Data Register Definitions (FIFO1) */
boonshen 0:a35c40f49345 807 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
boonshen 0:a35c40f49345 808 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
boonshen 0:a35c40f49345 809
boonshen 0:a35c40f49345 810 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
boonshen 0:a35c40f49345 811 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
boonshen 0:a35c40f49345 812
boonshen 0:a35c40f49345 813 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
boonshen 0:a35c40f49345 814 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
boonshen 0:a35c40f49345 815
boonshen 0:a35c40f49345 816 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
boonshen 0:a35c40f49345 817 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
boonshen 0:a35c40f49345 818
boonshen 0:a35c40f49345 819 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
boonshen 0:a35c40f49345 820 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
boonshen 0:a35c40f49345 821
boonshen 0:a35c40f49345 822 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
boonshen 0:a35c40f49345 823 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
boonshen 0:a35c40f49345 824
boonshen 0:a35c40f49345 825 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
boonshen 0:a35c40f49345 826 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
boonshen 0:a35c40f49345 827
boonshen 0:a35c40f49345 828 /* TPI ITATBCTR0 Register Definitions */
boonshen 0:a35c40f49345 829 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
boonshen 0:a35c40f49345 830 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
boonshen 0:a35c40f49345 831
boonshen 0:a35c40f49345 832 /* TPI Integration Mode Control Register Definitions */
boonshen 0:a35c40f49345 833 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
boonshen 0:a35c40f49345 834 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
boonshen 0:a35c40f49345 835
boonshen 0:a35c40f49345 836 /* TPI DEVID Register Definitions */
boonshen 0:a35c40f49345 837 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
boonshen 0:a35c40f49345 838 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
boonshen 0:a35c40f49345 839
boonshen 0:a35c40f49345 840 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
boonshen 0:a35c40f49345 841 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
boonshen 0:a35c40f49345 842
boonshen 0:a35c40f49345 843 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
boonshen 0:a35c40f49345 844 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
boonshen 0:a35c40f49345 845
boonshen 0:a35c40f49345 846 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
boonshen 0:a35c40f49345 847 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
boonshen 0:a35c40f49345 848
boonshen 0:a35c40f49345 849 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
boonshen 0:a35c40f49345 850 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
boonshen 0:a35c40f49345 851
boonshen 0:a35c40f49345 852 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
boonshen 0:a35c40f49345 853 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
boonshen 0:a35c40f49345 854
boonshen 0:a35c40f49345 855 /* TPI DEVTYPE Register Definitions */
boonshen 0:a35c40f49345 856 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
boonshen 0:a35c40f49345 857 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
boonshen 0:a35c40f49345 858
boonshen 0:a35c40f49345 859 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
boonshen 0:a35c40f49345 860 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
boonshen 0:a35c40f49345 861
boonshen 0:a35c40f49345 862 /*@}*/ /* end of group CMSIS_TPI */
boonshen 0:a35c40f49345 863
boonshen 0:a35c40f49345 864
boonshen 0:a35c40f49345 865 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen 0:a35c40f49345 866 /**
boonshen 0:a35c40f49345 867 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 868 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
boonshen 0:a35c40f49345 869 \brief Type definitions for the Memory Protection Unit (MPU)
boonshen 0:a35c40f49345 870 @{
boonshen 0:a35c40f49345 871 */
boonshen 0:a35c40f49345 872
boonshen 0:a35c40f49345 873 /**
boonshen 0:a35c40f49345 874 \brief Structure type to access the Memory Protection Unit (MPU).
boonshen 0:a35c40f49345 875 */
boonshen 0:a35c40f49345 876 typedef struct
boonshen 0:a35c40f49345 877 {
boonshen 0:a35c40f49345 878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
boonshen 0:a35c40f49345 879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
boonshen 0:a35c40f49345 880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
boonshen 0:a35c40f49345 881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
boonshen 0:a35c40f49345 882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
boonshen 0:a35c40f49345 883 uint32_t RESERVED0[7U];
boonshen 0:a35c40f49345 884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
boonshen 0:a35c40f49345 885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
boonshen 0:a35c40f49345 886 } MPU_Type;
boonshen 0:a35c40f49345 887
boonshen 0:a35c40f49345 888 /* MPU Type Register Definitions */
boonshen 0:a35c40f49345 889 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
boonshen 0:a35c40f49345 890 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
boonshen 0:a35c40f49345 891
boonshen 0:a35c40f49345 892 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
boonshen 0:a35c40f49345 893 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
boonshen 0:a35c40f49345 894
boonshen 0:a35c40f49345 895 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
boonshen 0:a35c40f49345 896 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
boonshen 0:a35c40f49345 897
boonshen 0:a35c40f49345 898 /* MPU Control Register Definitions */
boonshen 0:a35c40f49345 899 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
boonshen 0:a35c40f49345 900 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
boonshen 0:a35c40f49345 901
boonshen 0:a35c40f49345 902 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
boonshen 0:a35c40f49345 903 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
boonshen 0:a35c40f49345 904
boonshen 0:a35c40f49345 905 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
boonshen 0:a35c40f49345 906 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
boonshen 0:a35c40f49345 907
boonshen 0:a35c40f49345 908 /* MPU Region Number Register Definitions */
boonshen 0:a35c40f49345 909 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
boonshen 0:a35c40f49345 910 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
boonshen 0:a35c40f49345 911
boonshen 0:a35c40f49345 912 /* MPU Region Base Address Register Definitions */
boonshen 0:a35c40f49345 913 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
boonshen 0:a35c40f49345 914 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
boonshen 0:a35c40f49345 915
boonshen 0:a35c40f49345 916 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
boonshen 0:a35c40f49345 917 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
boonshen 0:a35c40f49345 918
boonshen 0:a35c40f49345 919 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
boonshen 0:a35c40f49345 920 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
boonshen 0:a35c40f49345 921
boonshen 0:a35c40f49345 922 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
boonshen 0:a35c40f49345 923 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
boonshen 0:a35c40f49345 924
boonshen 0:a35c40f49345 925 /* MPU Region Limit Address Register Definitions */
boonshen 0:a35c40f49345 926 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
boonshen 0:a35c40f49345 927 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
boonshen 0:a35c40f49345 928
boonshen 0:a35c40f49345 929 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
boonshen 0:a35c40f49345 930 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
boonshen 0:a35c40f49345 931
boonshen 0:a35c40f49345 932 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
boonshen 0:a35c40f49345 933 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
boonshen 0:a35c40f49345 934
boonshen 0:a35c40f49345 935 /* MPU Memory Attribute Indirection Register 0 Definitions */
boonshen 0:a35c40f49345 936 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
boonshen 0:a35c40f49345 937 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
boonshen 0:a35c40f49345 938
boonshen 0:a35c40f49345 939 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
boonshen 0:a35c40f49345 940 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
boonshen 0:a35c40f49345 941
boonshen 0:a35c40f49345 942 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
boonshen 0:a35c40f49345 943 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
boonshen 0:a35c40f49345 944
boonshen 0:a35c40f49345 945 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
boonshen 0:a35c40f49345 946 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
boonshen 0:a35c40f49345 947
boonshen 0:a35c40f49345 948 /* MPU Memory Attribute Indirection Register 1 Definitions */
boonshen 0:a35c40f49345 949 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
boonshen 0:a35c40f49345 950 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
boonshen 0:a35c40f49345 951
boonshen 0:a35c40f49345 952 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
boonshen 0:a35c40f49345 953 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
boonshen 0:a35c40f49345 954
boonshen 0:a35c40f49345 955 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
boonshen 0:a35c40f49345 956 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
boonshen 0:a35c40f49345 957
boonshen 0:a35c40f49345 958 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
boonshen 0:a35c40f49345 959 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
boonshen 0:a35c40f49345 960
boonshen 0:a35c40f49345 961 /*@} end of group CMSIS_MPU */
boonshen 0:a35c40f49345 962 #endif
boonshen 0:a35c40f49345 963
boonshen 0:a35c40f49345 964
boonshen 0:a35c40f49345 965 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen 0:a35c40f49345 966 /**
boonshen 0:a35c40f49345 967 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 968 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
boonshen 0:a35c40f49345 969 \brief Type definitions for the Security Attribution Unit (SAU)
boonshen 0:a35c40f49345 970 @{
boonshen 0:a35c40f49345 971 */
boonshen 0:a35c40f49345 972
boonshen 0:a35c40f49345 973 /**
boonshen 0:a35c40f49345 974 \brief Structure type to access the Security Attribution Unit (SAU).
boonshen 0:a35c40f49345 975 */
boonshen 0:a35c40f49345 976 typedef struct
boonshen 0:a35c40f49345 977 {
boonshen 0:a35c40f49345 978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
boonshen 0:a35c40f49345 979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
boonshen 0:a35c40f49345 980 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
boonshen 0:a35c40f49345 981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
boonshen 0:a35c40f49345 982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
boonshen 0:a35c40f49345 983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
boonshen 0:a35c40f49345 984 #endif
boonshen 0:a35c40f49345 985 } SAU_Type;
boonshen 0:a35c40f49345 986
boonshen 0:a35c40f49345 987 /* SAU Control Register Definitions */
boonshen 0:a35c40f49345 988 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
boonshen 0:a35c40f49345 989 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
boonshen 0:a35c40f49345 990
boonshen 0:a35c40f49345 991 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
boonshen 0:a35c40f49345 992 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
boonshen 0:a35c40f49345 993
boonshen 0:a35c40f49345 994 /* SAU Type Register Definitions */
boonshen 0:a35c40f49345 995 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
boonshen 0:a35c40f49345 996 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
boonshen 0:a35c40f49345 997
boonshen 0:a35c40f49345 998 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
boonshen 0:a35c40f49345 999 /* SAU Region Number Register Definitions */
boonshen 0:a35c40f49345 1000 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
boonshen 0:a35c40f49345 1001 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
boonshen 0:a35c40f49345 1002
boonshen 0:a35c40f49345 1003 /* SAU Region Base Address Register Definitions */
boonshen 0:a35c40f49345 1004 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
boonshen 0:a35c40f49345 1005 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
boonshen 0:a35c40f49345 1006
boonshen 0:a35c40f49345 1007 /* SAU Region Limit Address Register Definitions */
boonshen 0:a35c40f49345 1008 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
boonshen 0:a35c40f49345 1009 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
boonshen 0:a35c40f49345 1010
boonshen 0:a35c40f49345 1011 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
boonshen 0:a35c40f49345 1012 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
boonshen 0:a35c40f49345 1013
boonshen 0:a35c40f49345 1014 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
boonshen 0:a35c40f49345 1015 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
boonshen 0:a35c40f49345 1016
boonshen 0:a35c40f49345 1017 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
boonshen 0:a35c40f49345 1018
boonshen 0:a35c40f49345 1019 /*@} end of group CMSIS_SAU */
boonshen 0:a35c40f49345 1020 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen 0:a35c40f49345 1021
boonshen 0:a35c40f49345 1022
boonshen 0:a35c40f49345 1023 /**
boonshen 0:a35c40f49345 1024 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
boonshen 0:a35c40f49345 1026 \brief Type definitions for the Core Debug Registers
boonshen 0:a35c40f49345 1027 @{
boonshen 0:a35c40f49345 1028 */
boonshen 0:a35c40f49345 1029
boonshen 0:a35c40f49345 1030 /**
boonshen 0:a35c40f49345 1031 \brief Structure type to access the Core Debug Register (CoreDebug).
boonshen 0:a35c40f49345 1032 */
boonshen 0:a35c40f49345 1033 typedef struct
boonshen 0:a35c40f49345 1034 {
boonshen 0:a35c40f49345 1035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
boonshen 0:a35c40f49345 1036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
boonshen 0:a35c40f49345 1037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
boonshen 0:a35c40f49345 1038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
boonshen 0:a35c40f49345 1039 uint32_t RESERVED4[1U];
boonshen 0:a35c40f49345 1040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
boonshen 0:a35c40f49345 1041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
boonshen 0:a35c40f49345 1042 } CoreDebug_Type;
boonshen 0:a35c40f49345 1043
boonshen 0:a35c40f49345 1044 /* Debug Halting Control and Status Register Definitions */
boonshen 0:a35c40f49345 1045 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
boonshen 0:a35c40f49345 1046 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
boonshen 0:a35c40f49345 1047
boonshen 0:a35c40f49345 1048 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
boonshen 0:a35c40f49345 1049 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
boonshen 0:a35c40f49345 1050
boonshen 0:a35c40f49345 1051 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
boonshen 0:a35c40f49345 1052 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
boonshen 0:a35c40f49345 1053
boonshen 0:a35c40f49345 1054 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
boonshen 0:a35c40f49345 1055 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
boonshen 0:a35c40f49345 1056
boonshen 0:a35c40f49345 1057 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
boonshen 0:a35c40f49345 1058 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
boonshen 0:a35c40f49345 1059
boonshen 0:a35c40f49345 1060 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
boonshen 0:a35c40f49345 1061 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
boonshen 0:a35c40f49345 1062
boonshen 0:a35c40f49345 1063 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
boonshen 0:a35c40f49345 1064 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
boonshen 0:a35c40f49345 1065
boonshen 0:a35c40f49345 1066 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
boonshen 0:a35c40f49345 1067 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
boonshen 0:a35c40f49345 1068
boonshen 0:a35c40f49345 1069 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
boonshen 0:a35c40f49345 1070 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
boonshen 0:a35c40f49345 1071
boonshen 0:a35c40f49345 1072 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
boonshen 0:a35c40f49345 1073 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
boonshen 0:a35c40f49345 1074
boonshen 0:a35c40f49345 1075 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
boonshen 0:a35c40f49345 1076 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
boonshen 0:a35c40f49345 1077
boonshen 0:a35c40f49345 1078 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
boonshen 0:a35c40f49345 1079 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
boonshen 0:a35c40f49345 1080
boonshen 0:a35c40f49345 1081 /* Debug Core Register Selector Register Definitions */
boonshen 0:a35c40f49345 1082 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
boonshen 0:a35c40f49345 1083 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
boonshen 0:a35c40f49345 1084
boonshen 0:a35c40f49345 1085 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
boonshen 0:a35c40f49345 1086 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
boonshen 0:a35c40f49345 1087
boonshen 0:a35c40f49345 1088 /* Debug Exception and Monitor Control Register */
boonshen 0:a35c40f49345 1089 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
boonshen 0:a35c40f49345 1090 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
boonshen 0:a35c40f49345 1091
boonshen 0:a35c40f49345 1092 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
boonshen 0:a35c40f49345 1093 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
boonshen 0:a35c40f49345 1094
boonshen 0:a35c40f49345 1095 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
boonshen 0:a35c40f49345 1096 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
boonshen 0:a35c40f49345 1097
boonshen 0:a35c40f49345 1098 /* Debug Authentication Control Register Definitions */
boonshen 0:a35c40f49345 1099 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
boonshen 0:a35c40f49345 1100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
boonshen 0:a35c40f49345 1101
boonshen 0:a35c40f49345 1102 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
boonshen 0:a35c40f49345 1103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
boonshen 0:a35c40f49345 1104
boonshen 0:a35c40f49345 1105 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
boonshen 0:a35c40f49345 1106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
boonshen 0:a35c40f49345 1107
boonshen 0:a35c40f49345 1108 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
boonshen 0:a35c40f49345 1109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
boonshen 0:a35c40f49345 1110
boonshen 0:a35c40f49345 1111 /* Debug Security Control and Status Register Definitions */
boonshen 0:a35c40f49345 1112 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
boonshen 0:a35c40f49345 1113 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
boonshen 0:a35c40f49345 1114
boonshen 0:a35c40f49345 1115 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
boonshen 0:a35c40f49345 1116 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
boonshen 0:a35c40f49345 1117
boonshen 0:a35c40f49345 1118 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
boonshen 0:a35c40f49345 1119 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
boonshen 0:a35c40f49345 1120
boonshen 0:a35c40f49345 1121 /*@} end of group CMSIS_CoreDebug */
boonshen 0:a35c40f49345 1122
boonshen 0:a35c40f49345 1123
boonshen 0:a35c40f49345 1124 /**
boonshen 0:a35c40f49345 1125 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1126 \defgroup CMSIS_core_bitfield Core register bit field macros
boonshen 0:a35c40f49345 1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
boonshen 0:a35c40f49345 1128 @{
boonshen 0:a35c40f49345 1129 */
boonshen 0:a35c40f49345 1130
boonshen 0:a35c40f49345 1131 /**
boonshen 0:a35c40f49345 1132 \brief Mask and shift a bit field value for use in a register bit range.
boonshen 0:a35c40f49345 1133 \param[in] field Name of the register bit field.
boonshen 0:a35c40f49345 1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
boonshen 0:a35c40f49345 1135 \return Masked and shifted value.
boonshen 0:a35c40f49345 1136 */
boonshen 0:a35c40f49345 1137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
boonshen 0:a35c40f49345 1138
boonshen 0:a35c40f49345 1139 /**
boonshen 0:a35c40f49345 1140 \brief Mask and shift a register value to extract a bit filed value.
boonshen 0:a35c40f49345 1141 \param[in] field Name of the register bit field.
boonshen 0:a35c40f49345 1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
boonshen 0:a35c40f49345 1143 \return Masked and shifted bit field value.
boonshen 0:a35c40f49345 1144 */
boonshen 0:a35c40f49345 1145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
boonshen 0:a35c40f49345 1146
boonshen 0:a35c40f49345 1147 /*@} end of group CMSIS_core_bitfield */
boonshen 0:a35c40f49345 1148
boonshen 0:a35c40f49345 1149
boonshen 0:a35c40f49345 1150 /**
boonshen 0:a35c40f49345 1151 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 1152 \defgroup CMSIS_core_base Core Definitions
boonshen 0:a35c40f49345 1153 \brief Definitions for base addresses, unions, and structures.
boonshen 0:a35c40f49345 1154 @{
boonshen 0:a35c40f49345 1155 */
boonshen 0:a35c40f49345 1156
boonshen 0:a35c40f49345 1157 /* Memory mapping of Core Hardware */
boonshen 0:a35c40f49345 1158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
boonshen 0:a35c40f49345 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
boonshen 0:a35c40f49345 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
boonshen 0:a35c40f49345 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
boonshen 0:a35c40f49345 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
boonshen 0:a35c40f49345 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
boonshen 0:a35c40f49345 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
boonshen 0:a35c40f49345 1165
boonshen 0:a35c40f49345 1166
boonshen 0:a35c40f49345 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
boonshen 0:a35c40f49345 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
boonshen 0:a35c40f49345 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
boonshen 0:a35c40f49345 1170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
boonshen 0:a35c40f49345 1171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
boonshen 0:a35c40f49345 1172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
boonshen 0:a35c40f49345 1173
boonshen 0:a35c40f49345 1174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen 0:a35c40f49345 1175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
boonshen 0:a35c40f49345 1176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
boonshen 0:a35c40f49345 1177 #endif
boonshen 0:a35c40f49345 1178
boonshen 0:a35c40f49345 1179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen 0:a35c40f49345 1180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
boonshen 0:a35c40f49345 1181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
boonshen 0:a35c40f49345 1182 #endif
boonshen 0:a35c40f49345 1183
boonshen 0:a35c40f49345 1184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen 0:a35c40f49345 1185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
boonshen 0:a35c40f49345 1186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
boonshen 0:a35c40f49345 1187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
boonshen 0:a35c40f49345 1188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
boonshen 0:a35c40f49345 1189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
boonshen 0:a35c40f49345 1190
boonshen 0:a35c40f49345 1191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
boonshen 0:a35c40f49345 1192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
boonshen 0:a35c40f49345 1193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
boonshen 0:a35c40f49345 1194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
boonshen 0:a35c40f49345 1195
boonshen 0:a35c40f49345 1196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen 0:a35c40f49345 1197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
boonshen 0:a35c40f49345 1198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
boonshen 0:a35c40f49345 1199 #endif
boonshen 0:a35c40f49345 1200
boonshen 0:a35c40f49345 1201 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen 0:a35c40f49345 1202 /*@} */
boonshen 0:a35c40f49345 1203
boonshen 0:a35c40f49345 1204
boonshen 0:a35c40f49345 1205
boonshen 0:a35c40f49345 1206 /*******************************************************************************
boonshen 0:a35c40f49345 1207 * Hardware Abstraction Layer
boonshen 0:a35c40f49345 1208 Core Function Interface contains:
boonshen 0:a35c40f49345 1209 - Core NVIC Functions
boonshen 0:a35c40f49345 1210 - Core SysTick Functions
boonshen 0:a35c40f49345 1211 - Core Register Access Functions
boonshen 0:a35c40f49345 1212 ******************************************************************************/
boonshen 0:a35c40f49345 1213 /**
boonshen 0:a35c40f49345 1214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
boonshen 0:a35c40f49345 1215 */
boonshen 0:a35c40f49345 1216
boonshen 0:a35c40f49345 1217
boonshen 0:a35c40f49345 1218
boonshen 0:a35c40f49345 1219 /* ########################## NVIC functions #################################### */
boonshen 0:a35c40f49345 1220 /**
boonshen 0:a35c40f49345 1221 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 1222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
boonshen 0:a35c40f49345 1223 \brief Functions that manage interrupts and exceptions via the NVIC.
boonshen 0:a35c40f49345 1224 @{
boonshen 0:a35c40f49345 1225 */
boonshen 0:a35c40f49345 1226
boonshen 0:a35c40f49345 1227 #ifdef CMSIS_NVIC_VIRTUAL
boonshen 0:a35c40f49345 1228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
boonshen 0:a35c40f49345 1230 #endif
boonshen 0:a35c40f49345 1231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1232 #else
boonshen 0:a35c40f49345 1233 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
boonshen 0:a35c40f49345 1234 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
boonshen 0:a35c40f49345 1235 #define NVIC_EnableIRQ __NVIC_EnableIRQ
boonshen 0:a35c40f49345 1236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
boonshen 0:a35c40f49345 1237 #define NVIC_DisableIRQ __NVIC_DisableIRQ
boonshen 0:a35c40f49345 1238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
boonshen 0:a35c40f49345 1239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
boonshen 0:a35c40f49345 1240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
boonshen 0:a35c40f49345 1241 #define NVIC_GetActive __NVIC_GetActive
boonshen 0:a35c40f49345 1242 #define NVIC_SetPriority __NVIC_SetPriority
boonshen 0:a35c40f49345 1243 #define NVIC_GetPriority __NVIC_GetPriority
boonshen 0:a35c40f49345 1244 #define NVIC_SystemReset __NVIC_SystemReset
boonshen 0:a35c40f49345 1245 #endif /* CMSIS_NVIC_VIRTUAL */
boonshen 0:a35c40f49345 1246
boonshen 0:a35c40f49345 1247 #ifdef CMSIS_VECTAB_VIRTUAL
boonshen 0:a35c40f49345 1248 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1249 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
boonshen 0:a35c40f49345 1250 #endif
boonshen 0:a35c40f49345 1251 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 1252 #else
boonshen 0:a35c40f49345 1253 #define NVIC_SetVector __NVIC_SetVector
boonshen 0:a35c40f49345 1254 #define NVIC_GetVector __NVIC_GetVector
boonshen 0:a35c40f49345 1255 #endif /* (CMSIS_VECTAB_VIRTUAL) */
boonshen 0:a35c40f49345 1256
boonshen 0:a35c40f49345 1257 #define NVIC_USER_IRQ_OFFSET 16
boonshen 0:a35c40f49345 1258
boonshen 0:a35c40f49345 1259
boonshen 0:a35c40f49345 1260 /* Interrupt Priorities are WORD accessible only under ARMv6M */
boonshen 0:a35c40f49345 1261 /* The following MACROS handle generation of the register offset and byte masks */
boonshen 0:a35c40f49345 1262 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
boonshen 0:a35c40f49345 1263 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
boonshen 0:a35c40f49345 1264 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
boonshen 0:a35c40f49345 1265
boonshen 0:a35c40f49345 1266
boonshen 0:a35c40f49345 1267 /**
boonshen 0:a35c40f49345 1268 \brief Enable Interrupt
boonshen 0:a35c40f49345 1269 \details Enables a device specific interrupt in the NVIC interrupt controller.
boonshen 0:a35c40f49345 1270 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1271 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1272 */
boonshen 0:a35c40f49345 1273 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1274 {
boonshen 0:a35c40f49345 1275 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1276 {
boonshen 0:a35c40f49345 1277 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1278 }
boonshen 0:a35c40f49345 1279 }
boonshen 0:a35c40f49345 1280
boonshen 0:a35c40f49345 1281
boonshen 0:a35c40f49345 1282 /**
boonshen 0:a35c40f49345 1283 \brief Get Interrupt Enable status
boonshen 0:a35c40f49345 1284 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
boonshen 0:a35c40f49345 1285 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1286 \return 0 Interrupt is not enabled.
boonshen 0:a35c40f49345 1287 \return 1 Interrupt is enabled.
boonshen 0:a35c40f49345 1288 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1289 */
boonshen 0:a35c40f49345 1290 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1291 {
boonshen 0:a35c40f49345 1292 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1293 {
boonshen 0:a35c40f49345 1294 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1295 }
boonshen 0:a35c40f49345 1296 else
boonshen 0:a35c40f49345 1297 {
boonshen 0:a35c40f49345 1298 return(0U);
boonshen 0:a35c40f49345 1299 }
boonshen 0:a35c40f49345 1300 }
boonshen 0:a35c40f49345 1301
boonshen 0:a35c40f49345 1302
boonshen 0:a35c40f49345 1303 /**
boonshen 0:a35c40f49345 1304 \brief Disable Interrupt
boonshen 0:a35c40f49345 1305 \details Disables a device specific interrupt in the NVIC interrupt controller.
boonshen 0:a35c40f49345 1306 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1307 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1308 */
boonshen 0:a35c40f49345 1309 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1310 {
boonshen 0:a35c40f49345 1311 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1312 {
boonshen 0:a35c40f49345 1313 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1314 __DSB();
boonshen 0:a35c40f49345 1315 __ISB();
boonshen 0:a35c40f49345 1316 }
boonshen 0:a35c40f49345 1317 }
boonshen 0:a35c40f49345 1318
boonshen 0:a35c40f49345 1319
boonshen 0:a35c40f49345 1320 /**
boonshen 0:a35c40f49345 1321 \brief Get Pending Interrupt
boonshen 0:a35c40f49345 1322 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
boonshen 0:a35c40f49345 1323 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1324 \return 0 Interrupt status is not pending.
boonshen 0:a35c40f49345 1325 \return 1 Interrupt status is pending.
boonshen 0:a35c40f49345 1326 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1327 */
boonshen 0:a35c40f49345 1328 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1329 {
boonshen 0:a35c40f49345 1330 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1331 {
boonshen 0:a35c40f49345 1332 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1333 }
boonshen 0:a35c40f49345 1334 else
boonshen 0:a35c40f49345 1335 {
boonshen 0:a35c40f49345 1336 return(0U);
boonshen 0:a35c40f49345 1337 }
boonshen 0:a35c40f49345 1338 }
boonshen 0:a35c40f49345 1339
boonshen 0:a35c40f49345 1340
boonshen 0:a35c40f49345 1341 /**
boonshen 0:a35c40f49345 1342 \brief Set Pending Interrupt
boonshen 0:a35c40f49345 1343 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
boonshen 0:a35c40f49345 1344 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1345 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1346 */
boonshen 0:a35c40f49345 1347 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1348 {
boonshen 0:a35c40f49345 1349 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1350 {
boonshen 0:a35c40f49345 1351 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1352 }
boonshen 0:a35c40f49345 1353 }
boonshen 0:a35c40f49345 1354
boonshen 0:a35c40f49345 1355
boonshen 0:a35c40f49345 1356 /**
boonshen 0:a35c40f49345 1357 \brief Clear Pending Interrupt
boonshen 0:a35c40f49345 1358 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
boonshen 0:a35c40f49345 1359 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1360 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1361 */
boonshen 0:a35c40f49345 1362 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1363 {
boonshen 0:a35c40f49345 1364 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1365 {
boonshen 0:a35c40f49345 1366 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1367 }
boonshen 0:a35c40f49345 1368 }
boonshen 0:a35c40f49345 1369
boonshen 0:a35c40f49345 1370
boonshen 0:a35c40f49345 1371 /**
boonshen 0:a35c40f49345 1372 \brief Get Active Interrupt
boonshen 0:a35c40f49345 1373 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
boonshen 0:a35c40f49345 1374 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1375 \return 0 Interrupt status is not active.
boonshen 0:a35c40f49345 1376 \return 1 Interrupt status is active.
boonshen 0:a35c40f49345 1377 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1378 */
boonshen 0:a35c40f49345 1379 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1380 {
boonshen 0:a35c40f49345 1381 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1382 {
boonshen 0:a35c40f49345 1383 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1384 }
boonshen 0:a35c40f49345 1385 else
boonshen 0:a35c40f49345 1386 {
boonshen 0:a35c40f49345 1387 return(0U);
boonshen 0:a35c40f49345 1388 }
boonshen 0:a35c40f49345 1389 }
boonshen 0:a35c40f49345 1390
boonshen 0:a35c40f49345 1391
boonshen 0:a35c40f49345 1392 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen 0:a35c40f49345 1393 /**
boonshen 0:a35c40f49345 1394 \brief Get Interrupt Target State
boonshen 0:a35c40f49345 1395 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
boonshen 0:a35c40f49345 1396 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1397 \return 0 if interrupt is assigned to Secure
boonshen 0:a35c40f49345 1398 \return 1 if interrupt is assigned to Non Secure
boonshen 0:a35c40f49345 1399 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1400 */
boonshen 0:a35c40f49345 1401 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1402 {
boonshen 0:a35c40f49345 1403 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1404 {
boonshen 0:a35c40f49345 1405 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1406 }
boonshen 0:a35c40f49345 1407 else
boonshen 0:a35c40f49345 1408 {
boonshen 0:a35c40f49345 1409 return(0U);
boonshen 0:a35c40f49345 1410 }
boonshen 0:a35c40f49345 1411 }
boonshen 0:a35c40f49345 1412
boonshen 0:a35c40f49345 1413
boonshen 0:a35c40f49345 1414 /**
boonshen 0:a35c40f49345 1415 \brief Set Interrupt Target State
boonshen 0:a35c40f49345 1416 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
boonshen 0:a35c40f49345 1417 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1418 \return 0 if interrupt is assigned to Secure
boonshen 0:a35c40f49345 1419 1 if interrupt is assigned to Non Secure
boonshen 0:a35c40f49345 1420 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1421 */
boonshen 0:a35c40f49345 1422 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1423 {
boonshen 0:a35c40f49345 1424 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1425 {
boonshen 0:a35c40f49345 1426 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
boonshen 0:a35c40f49345 1427 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1428 }
boonshen 0:a35c40f49345 1429 else
boonshen 0:a35c40f49345 1430 {
boonshen 0:a35c40f49345 1431 return(0U);
boonshen 0:a35c40f49345 1432 }
boonshen 0:a35c40f49345 1433 }
boonshen 0:a35c40f49345 1434
boonshen 0:a35c40f49345 1435
boonshen 0:a35c40f49345 1436 /**
boonshen 0:a35c40f49345 1437 \brief Clear Interrupt Target State
boonshen 0:a35c40f49345 1438 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
boonshen 0:a35c40f49345 1439 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1440 \return 0 if interrupt is assigned to Secure
boonshen 0:a35c40f49345 1441 1 if interrupt is assigned to Non Secure
boonshen 0:a35c40f49345 1442 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1443 */
boonshen 0:a35c40f49345 1444 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1445 {
boonshen 0:a35c40f49345 1446 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1447 {
boonshen 0:a35c40f49345 1448 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
boonshen 0:a35c40f49345 1449 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1450 }
boonshen 0:a35c40f49345 1451 else
boonshen 0:a35c40f49345 1452 {
boonshen 0:a35c40f49345 1453 return(0U);
boonshen 0:a35c40f49345 1454 }
boonshen 0:a35c40f49345 1455 }
boonshen 0:a35c40f49345 1456 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen 0:a35c40f49345 1457
boonshen 0:a35c40f49345 1458
boonshen 0:a35c40f49345 1459 /**
boonshen 0:a35c40f49345 1460 \brief Set Interrupt Priority
boonshen 0:a35c40f49345 1461 \details Sets the priority of a device specific interrupt or a processor exception.
boonshen 0:a35c40f49345 1462 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1463 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1464 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1465 \param [in] priority Priority to set.
boonshen 0:a35c40f49345 1466 \note The priority cannot be set for every processor exception.
boonshen 0:a35c40f49345 1467 */
boonshen 0:a35c40f49345 1468 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
boonshen 0:a35c40f49345 1469 {
boonshen 0:a35c40f49345 1470 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1471 {
boonshen 0:a35c40f49345 1472 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
boonshen 0:a35c40f49345 1473 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
boonshen 0:a35c40f49345 1474 }
boonshen 0:a35c40f49345 1475 else
boonshen 0:a35c40f49345 1476 {
boonshen 0:a35c40f49345 1477 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
boonshen 0:a35c40f49345 1478 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
boonshen 0:a35c40f49345 1479 }
boonshen 0:a35c40f49345 1480 }
boonshen 0:a35c40f49345 1481
boonshen 0:a35c40f49345 1482
boonshen 0:a35c40f49345 1483 /**
boonshen 0:a35c40f49345 1484 \brief Get Interrupt Priority
boonshen 0:a35c40f49345 1485 \details Reads the priority of a device specific interrupt or a processor exception.
boonshen 0:a35c40f49345 1486 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1487 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1488 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1489 \return Interrupt Priority.
boonshen 0:a35c40f49345 1490 Value is aligned automatically to the implemented priority bits of the microcontroller.
boonshen 0:a35c40f49345 1491 */
boonshen 0:a35c40f49345 1492 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1493 {
boonshen 0:a35c40f49345 1494
boonshen 0:a35c40f49345 1495 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1496 {
boonshen 0:a35c40f49345 1497 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 1498 }
boonshen 0:a35c40f49345 1499 else
boonshen 0:a35c40f49345 1500 {
boonshen 0:a35c40f49345 1501 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 1502 }
boonshen 0:a35c40f49345 1503 }
boonshen 0:a35c40f49345 1504
boonshen 0:a35c40f49345 1505
boonshen 0:a35c40f49345 1506 /**
boonshen 0:a35c40f49345 1507 \brief Set Interrupt Vector
boonshen 0:a35c40f49345 1508 \details Sets an interrupt vector in SRAM based interrupt vector table.
boonshen 0:a35c40f49345 1509 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1510 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1511 VTOR must been relocated to SRAM before.
boonshen 0:a35c40f49345 1512 If VTOR is not present address 0 must be mapped to SRAM.
boonshen 0:a35c40f49345 1513 \param [in] IRQn Interrupt number
boonshen 0:a35c40f49345 1514 \param [in] vector Address of interrupt handler function
boonshen 0:a35c40f49345 1515 */
boonshen 0:a35c40f49345 1516 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
boonshen 0:a35c40f49345 1517 {
boonshen 0:a35c40f49345 1518 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
boonshen 0:a35c40f49345 1519 uint32_t *vectors = (uint32_t *)SCB->VTOR;
boonshen 0:a35c40f49345 1520 #else
boonshen 0:a35c40f49345 1521 uint32_t *vectors = (uint32_t *)0x0U;
boonshen 0:a35c40f49345 1522 #endif
boonshen 0:a35c40f49345 1523 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
boonshen 0:a35c40f49345 1524 }
boonshen 0:a35c40f49345 1525
boonshen 0:a35c40f49345 1526
boonshen 0:a35c40f49345 1527 /**
boonshen 0:a35c40f49345 1528 \brief Get Interrupt Vector
boonshen 0:a35c40f49345 1529 \details Reads an interrupt vector from interrupt vector table.
boonshen 0:a35c40f49345 1530 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1531 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1532 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1533 \return Address of interrupt handler function
boonshen 0:a35c40f49345 1534 */
boonshen 0:a35c40f49345 1535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1536 {
boonshen 0:a35c40f49345 1537 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
boonshen 0:a35c40f49345 1538 uint32_t *vectors = (uint32_t *)SCB->VTOR;
boonshen 0:a35c40f49345 1539 #else
boonshen 0:a35c40f49345 1540 uint32_t *vectors = (uint32_t *)0x0U;
boonshen 0:a35c40f49345 1541 #endif
boonshen 0:a35c40f49345 1542 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
boonshen 0:a35c40f49345 1543 }
boonshen 0:a35c40f49345 1544
boonshen 0:a35c40f49345 1545
boonshen 0:a35c40f49345 1546 /**
boonshen 0:a35c40f49345 1547 \brief System Reset
boonshen 0:a35c40f49345 1548 \details Initiates a system reset request to reset the MCU.
boonshen 0:a35c40f49345 1549 */
boonshen 0:a35c40f49345 1550 __STATIC_INLINE void __NVIC_SystemReset(void)
boonshen 0:a35c40f49345 1551 {
boonshen 0:a35c40f49345 1552 __DSB(); /* Ensure all outstanding memory accesses included
boonshen 0:a35c40f49345 1553 buffered write are completed before reset */
boonshen 0:a35c40f49345 1554 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
boonshen 0:a35c40f49345 1555 SCB_AIRCR_SYSRESETREQ_Msk);
boonshen 0:a35c40f49345 1556 __DSB(); /* Ensure completion of memory access */
boonshen 0:a35c40f49345 1557
boonshen 0:a35c40f49345 1558 for(;;) /* wait until reset */
boonshen 0:a35c40f49345 1559 {
boonshen 0:a35c40f49345 1560 __NOP();
boonshen 0:a35c40f49345 1561 }
boonshen 0:a35c40f49345 1562 }
boonshen 0:a35c40f49345 1563
boonshen 0:a35c40f49345 1564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen 0:a35c40f49345 1565 /**
boonshen 0:a35c40f49345 1566 \brief Enable Interrupt (non-secure)
boonshen 0:a35c40f49345 1567 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
boonshen 0:a35c40f49345 1568 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1569 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1570 */
boonshen 0:a35c40f49345 1571 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1572 {
boonshen 0:a35c40f49345 1573 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1574 {
boonshen 0:a35c40f49345 1575 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1576 }
boonshen 0:a35c40f49345 1577 }
boonshen 0:a35c40f49345 1578
boonshen 0:a35c40f49345 1579
boonshen 0:a35c40f49345 1580 /**
boonshen 0:a35c40f49345 1581 \brief Get Interrupt Enable status (non-secure)
boonshen 0:a35c40f49345 1582 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
boonshen 0:a35c40f49345 1583 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1584 \return 0 Interrupt is not enabled.
boonshen 0:a35c40f49345 1585 \return 1 Interrupt is enabled.
boonshen 0:a35c40f49345 1586 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1587 */
boonshen 0:a35c40f49345 1588 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1589 {
boonshen 0:a35c40f49345 1590 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1591 {
boonshen 0:a35c40f49345 1592 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1593 }
boonshen 0:a35c40f49345 1594 else
boonshen 0:a35c40f49345 1595 {
boonshen 0:a35c40f49345 1596 return(0U);
boonshen 0:a35c40f49345 1597 }
boonshen 0:a35c40f49345 1598 }
boonshen 0:a35c40f49345 1599
boonshen 0:a35c40f49345 1600
boonshen 0:a35c40f49345 1601 /**
boonshen 0:a35c40f49345 1602 \brief Disable Interrupt (non-secure)
boonshen 0:a35c40f49345 1603 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
boonshen 0:a35c40f49345 1604 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1605 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1606 */
boonshen 0:a35c40f49345 1607 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1608 {
boonshen 0:a35c40f49345 1609 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1610 {
boonshen 0:a35c40f49345 1611 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1612 }
boonshen 0:a35c40f49345 1613 }
boonshen 0:a35c40f49345 1614
boonshen 0:a35c40f49345 1615
boonshen 0:a35c40f49345 1616 /**
boonshen 0:a35c40f49345 1617 \brief Get Pending Interrupt (non-secure)
boonshen 0:a35c40f49345 1618 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
boonshen 0:a35c40f49345 1619 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1620 \return 0 Interrupt status is not pending.
boonshen 0:a35c40f49345 1621 \return 1 Interrupt status is pending.
boonshen 0:a35c40f49345 1622 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1623 */
boonshen 0:a35c40f49345 1624 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1625 {
boonshen 0:a35c40f49345 1626 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1627 {
boonshen 0:a35c40f49345 1628 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1629 }
boonshen 0:a35c40f49345 1630 }
boonshen 0:a35c40f49345 1631
boonshen 0:a35c40f49345 1632
boonshen 0:a35c40f49345 1633 /**
boonshen 0:a35c40f49345 1634 \brief Set Pending Interrupt (non-secure)
boonshen 0:a35c40f49345 1635 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
boonshen 0:a35c40f49345 1636 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1637 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1638 */
boonshen 0:a35c40f49345 1639 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1640 {
boonshen 0:a35c40f49345 1641 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1642 {
boonshen 0:a35c40f49345 1643 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1644 }
boonshen 0:a35c40f49345 1645 }
boonshen 0:a35c40f49345 1646
boonshen 0:a35c40f49345 1647
boonshen 0:a35c40f49345 1648 /**
boonshen 0:a35c40f49345 1649 \brief Clear Pending Interrupt (non-secure)
boonshen 0:a35c40f49345 1650 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
boonshen 0:a35c40f49345 1651 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1652 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1653 */
boonshen 0:a35c40f49345 1654 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1655 {
boonshen 0:a35c40f49345 1656 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1657 {
boonshen 0:a35c40f49345 1658 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 1659 }
boonshen 0:a35c40f49345 1660 }
boonshen 0:a35c40f49345 1661
boonshen 0:a35c40f49345 1662
boonshen 0:a35c40f49345 1663 /**
boonshen 0:a35c40f49345 1664 \brief Get Active Interrupt (non-secure)
boonshen 0:a35c40f49345 1665 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
boonshen 0:a35c40f49345 1666 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 1667 \return 0 Interrupt status is not active.
boonshen 0:a35c40f49345 1668 \return 1 Interrupt status is active.
boonshen 0:a35c40f49345 1669 \note IRQn must not be negative.
boonshen 0:a35c40f49345 1670 */
boonshen 0:a35c40f49345 1671 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1672 {
boonshen 0:a35c40f49345 1673 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1674 {
boonshen 0:a35c40f49345 1675 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 1676 }
boonshen 0:a35c40f49345 1677 else
boonshen 0:a35c40f49345 1678 {
boonshen 0:a35c40f49345 1679 return(0U);
boonshen 0:a35c40f49345 1680 }
boonshen 0:a35c40f49345 1681 }
boonshen 0:a35c40f49345 1682
boonshen 0:a35c40f49345 1683
boonshen 0:a35c40f49345 1684 /**
boonshen 0:a35c40f49345 1685 \brief Set Interrupt Priority (non-secure)
boonshen 0:a35c40f49345 1686 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
boonshen 0:a35c40f49345 1687 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1688 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1689 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1690 \param [in] priority Priority to set.
boonshen 0:a35c40f49345 1691 \note The priority cannot be set for every non-secure processor exception.
boonshen 0:a35c40f49345 1692 */
boonshen 0:a35c40f49345 1693 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
boonshen 0:a35c40f49345 1694 {
boonshen 0:a35c40f49345 1695 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1696 {
boonshen 0:a35c40f49345 1697 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
boonshen 0:a35c40f49345 1698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
boonshen 0:a35c40f49345 1699 }
boonshen 0:a35c40f49345 1700 else
boonshen 0:a35c40f49345 1701 {
boonshen 0:a35c40f49345 1702 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
boonshen 0:a35c40f49345 1703 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
boonshen 0:a35c40f49345 1704 }
boonshen 0:a35c40f49345 1705 }
boonshen 0:a35c40f49345 1706
boonshen 0:a35c40f49345 1707
boonshen 0:a35c40f49345 1708 /**
boonshen 0:a35c40f49345 1709 \brief Get Interrupt Priority (non-secure)
boonshen 0:a35c40f49345 1710 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
boonshen 0:a35c40f49345 1711 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 1712 or negative to specify a processor exception.
boonshen 0:a35c40f49345 1713 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 1714 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
boonshen 0:a35c40f49345 1715 */
boonshen 0:a35c40f49345 1716 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
boonshen 0:a35c40f49345 1717 {
boonshen 0:a35c40f49345 1718
boonshen 0:a35c40f49345 1719 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 1720 {
boonshen 0:a35c40f49345 1721 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 1722 }
boonshen 0:a35c40f49345 1723 else
boonshen 0:a35c40f49345 1724 {
boonshen 0:a35c40f49345 1725 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 1726 }
boonshen 0:a35c40f49345 1727 }
boonshen 0:a35c40f49345 1728 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
boonshen 0:a35c40f49345 1729
boonshen 0:a35c40f49345 1730 /*@} end of CMSIS_Core_NVICFunctions */
boonshen 0:a35c40f49345 1731
boonshen 0:a35c40f49345 1732
boonshen 0:a35c40f49345 1733 /* ########################## FPU functions #################################### */
boonshen 0:a35c40f49345 1734 /**
boonshen 0:a35c40f49345 1735 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 1736 \defgroup CMSIS_Core_FpuFunctions FPU Functions
boonshen 0:a35c40f49345 1737 \brief Function that provides FPU type.
boonshen 0:a35c40f49345 1738 @{
boonshen 0:a35c40f49345 1739 */
boonshen 0:a35c40f49345 1740
boonshen 0:a35c40f49345 1741 /**
boonshen 0:a35c40f49345 1742 \brief get FPU type
boonshen 0:a35c40f49345 1743 \details returns the FPU type
boonshen 0:a35c40f49345 1744 \returns
boonshen 0:a35c40f49345 1745 - \b 0: No FPU
boonshen 0:a35c40f49345 1746 - \b 1: Single precision FPU
boonshen 0:a35c40f49345 1747 - \b 2: Double + Single precision FPU
boonshen 0:a35c40f49345 1748 */
boonshen 0:a35c40f49345 1749 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
boonshen 0:a35c40f49345 1750 {
boonshen 0:a35c40f49345 1751 return 0U; /* No FPU */
boonshen 0:a35c40f49345 1752 }
boonshen 0:a35c40f49345 1753
boonshen 0:a35c40f49345 1754
boonshen 0:a35c40f49345 1755 /*@} end of CMSIS_Core_FpuFunctions */
boonshen 0:a35c40f49345 1756
boonshen 0:a35c40f49345 1757
boonshen 0:a35c40f49345 1758
boonshen 0:a35c40f49345 1759 /* ########################## SAU functions #################################### */
boonshen 0:a35c40f49345 1760 /**
boonshen 0:a35c40f49345 1761 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 1762 \defgroup CMSIS_Core_SAUFunctions SAU Functions
boonshen 0:a35c40f49345 1763 \brief Functions that configure the SAU.
boonshen 0:a35c40f49345 1764 @{
boonshen 0:a35c40f49345 1765 */
boonshen 0:a35c40f49345 1766
boonshen 0:a35c40f49345 1767 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen 0:a35c40f49345 1768
boonshen 0:a35c40f49345 1769 /**
boonshen 0:a35c40f49345 1770 \brief Enable SAU
boonshen 0:a35c40f49345 1771 \details Enables the Security Attribution Unit (SAU).
boonshen 0:a35c40f49345 1772 */
boonshen 0:a35c40f49345 1773 __STATIC_INLINE void TZ_SAU_Enable(void)
boonshen 0:a35c40f49345 1774 {
boonshen 0:a35c40f49345 1775 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
boonshen 0:a35c40f49345 1776 }
boonshen 0:a35c40f49345 1777
boonshen 0:a35c40f49345 1778
boonshen 0:a35c40f49345 1779
boonshen 0:a35c40f49345 1780 /**
boonshen 0:a35c40f49345 1781 \brief Disable SAU
boonshen 0:a35c40f49345 1782 \details Disables the Security Attribution Unit (SAU).
boonshen 0:a35c40f49345 1783 */
boonshen 0:a35c40f49345 1784 __STATIC_INLINE void TZ_SAU_Disable(void)
boonshen 0:a35c40f49345 1785 {
boonshen 0:a35c40f49345 1786 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
boonshen 0:a35c40f49345 1787 }
boonshen 0:a35c40f49345 1788
boonshen 0:a35c40f49345 1789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen 0:a35c40f49345 1790
boonshen 0:a35c40f49345 1791 /*@} end of CMSIS_Core_SAUFunctions */
boonshen 0:a35c40f49345 1792
boonshen 0:a35c40f49345 1793
boonshen 0:a35c40f49345 1794
boonshen 0:a35c40f49345 1795
boonshen 0:a35c40f49345 1796 /* ################################## SysTick function ############################################ */
boonshen 0:a35c40f49345 1797 /**
boonshen 0:a35c40f49345 1798 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 1799 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
boonshen 0:a35c40f49345 1800 \brief Functions that configure the System.
boonshen 0:a35c40f49345 1801 @{
boonshen 0:a35c40f49345 1802 */
boonshen 0:a35c40f49345 1803
boonshen 0:a35c40f49345 1804 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
boonshen 0:a35c40f49345 1805
boonshen 0:a35c40f49345 1806 /**
boonshen 0:a35c40f49345 1807 \brief System Tick Configuration
boonshen 0:a35c40f49345 1808 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
boonshen 0:a35c40f49345 1809 Counter is in free running mode to generate periodic interrupts.
boonshen 0:a35c40f49345 1810 \param [in] ticks Number of ticks between two interrupts.
boonshen 0:a35c40f49345 1811 \return 0 Function succeeded.
boonshen 0:a35c40f49345 1812 \return 1 Function failed.
boonshen 0:a35c40f49345 1813 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
boonshen 0:a35c40f49345 1814 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
boonshen 0:a35c40f49345 1815 must contain a vendor-specific implementation of this function.
boonshen 0:a35c40f49345 1816 */
boonshen 0:a35c40f49345 1817 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
boonshen 0:a35c40f49345 1818 {
boonshen 0:a35c40f49345 1819 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
boonshen 0:a35c40f49345 1820 {
boonshen 0:a35c40f49345 1821 return (1UL); /* Reload value impossible */
boonshen 0:a35c40f49345 1822 }
boonshen 0:a35c40f49345 1823
boonshen 0:a35c40f49345 1824 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
boonshen 0:a35c40f49345 1825 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
boonshen 0:a35c40f49345 1826 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
boonshen 0:a35c40f49345 1827 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
boonshen 0:a35c40f49345 1828 SysTick_CTRL_TICKINT_Msk |
boonshen 0:a35c40f49345 1829 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
boonshen 0:a35c40f49345 1830 return (0UL); /* Function successful */
boonshen 0:a35c40f49345 1831 }
boonshen 0:a35c40f49345 1832
boonshen 0:a35c40f49345 1833 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen 0:a35c40f49345 1834 /**
boonshen 0:a35c40f49345 1835 \brief System Tick Configuration (non-secure)
boonshen 0:a35c40f49345 1836 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
boonshen 0:a35c40f49345 1837 Counter is in free running mode to generate periodic interrupts.
boonshen 0:a35c40f49345 1838 \param [in] ticks Number of ticks between two interrupts.
boonshen 0:a35c40f49345 1839 \return 0 Function succeeded.
boonshen 0:a35c40f49345 1840 \return 1 Function failed.
boonshen 0:a35c40f49345 1841 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
boonshen 0:a35c40f49345 1842 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
boonshen 0:a35c40f49345 1843 must contain a vendor-specific implementation of this function.
boonshen 0:a35c40f49345 1844
boonshen 0:a35c40f49345 1845 */
boonshen 0:a35c40f49345 1846 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
boonshen 0:a35c40f49345 1847 {
boonshen 0:a35c40f49345 1848 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
boonshen 0:a35c40f49345 1849 {
boonshen 0:a35c40f49345 1850 return (1UL); /* Reload value impossible */
boonshen 0:a35c40f49345 1851 }
boonshen 0:a35c40f49345 1852
boonshen 0:a35c40f49345 1853 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
boonshen 0:a35c40f49345 1854 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
boonshen 0:a35c40f49345 1855 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
boonshen 0:a35c40f49345 1856 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
boonshen 0:a35c40f49345 1857 SysTick_CTRL_TICKINT_Msk |
boonshen 0:a35c40f49345 1858 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
boonshen 0:a35c40f49345 1859 return (0UL); /* Function successful */
boonshen 0:a35c40f49345 1860 }
boonshen 0:a35c40f49345 1861 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen 0:a35c40f49345 1862
boonshen 0:a35c40f49345 1863 #endif
boonshen 0:a35c40f49345 1864
boonshen 0:a35c40f49345 1865 /*@} end of CMSIS_Core_SysTickFunctions */
boonshen 0:a35c40f49345 1866
boonshen 0:a35c40f49345 1867
boonshen 0:a35c40f49345 1868
boonshen 0:a35c40f49345 1869
boonshen 0:a35c40f49345 1870 #ifdef __cplusplus
boonshen 0:a35c40f49345 1871 }
boonshen 0:a35c40f49345 1872 #endif
boonshen 0:a35c40f49345 1873
boonshen 0:a35c40f49345 1874 #endif /* __CORE_CM23_H_DEPENDANT */
boonshen 0:a35c40f49345 1875
boonshen 0:a35c40f49345 1876 #endif /* __CMSIS_GENERIC */