Lee Shen / FTHR_USB_serial_qSPI

max32630fthr quad spi , unexpected spi behavior

FTHR_USB_serial/mbed-os/cmsis/core_cm0.h@0:a35c40f49345, 2018-03-13 (annotated)

Committer:
boonshen
Date:
Tue Mar 13 21:12:00 2018 +0000
Revision:
0:a35c40f49345
MAX32630FTHR QuadSPI test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
boonshen 0:a35c40f49345 1 /**************************************************************************//**
boonshen 0:a35c40f49345 2 * @file core_cm0.h
boonshen 0:a35c40f49345 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
boonshen 0:a35c40f49345 4 * @version V5.0.2
boonshen 0:a35c40f49345 5 * @date 13. February 2017
boonshen 0:a35c40f49345 6 ******************************************************************************/
boonshen 0:a35c40f49345 7 /*
boonshen 0:a35c40f49345 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
boonshen 0:a35c40f49345 9 *
boonshen 0:a35c40f49345 10 * SPDX-License-Identifier: Apache-2.0
boonshen 0:a35c40f49345 11 *
boonshen 0:a35c40f49345 12 * Licensed under the Apache License, Version 2.0 (the License); you may
boonshen 0:a35c40f49345 13 * not use this file except in compliance with the License.
boonshen 0:a35c40f49345 14 * You may obtain a copy of the License at
boonshen 0:a35c40f49345 15 *
boonshen 0:a35c40f49345 16 * www.apache.org/licenses/LICENSE-2.0
boonshen 0:a35c40f49345 17 *
boonshen 0:a35c40f49345 18 * Unless required by applicable law or agreed to in writing, software
boonshen 0:a35c40f49345 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
boonshen 0:a35c40f49345 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
boonshen 0:a35c40f49345 21 * See the License for the specific language governing permissions and
boonshen 0:a35c40f49345 22 * limitations under the License.
boonshen 0:a35c40f49345 23 */
boonshen 0:a35c40f49345 24
boonshen 0:a35c40f49345 25 #if defined ( __ICCARM__ )
boonshen 0:a35c40f49345 26 #pragma system_include /* treat file as system include file for MISRA check */
boonshen 0:a35c40f49345 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen 0:a35c40f49345 28 #pragma clang system_header /* treat file as system include file */
boonshen 0:a35c40f49345 29 #endif
boonshen 0:a35c40f49345 30
boonshen 0:a35c40f49345 31 #ifndef __CORE_CM0_H_GENERIC
boonshen 0:a35c40f49345 32 #define __CORE_CM0_H_GENERIC
boonshen 0:a35c40f49345 33
boonshen 0:a35c40f49345 34 #include <stdint.h>
boonshen 0:a35c40f49345 35
boonshen 0:a35c40f49345 36 #ifdef __cplusplus
boonshen 0:a35c40f49345 37 extern "C" {
boonshen 0:a35c40f49345 38 #endif
boonshen 0:a35c40f49345 39
boonshen 0:a35c40f49345 40 /**
boonshen 0:a35c40f49345 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
boonshen 0:a35c40f49345 42 CMSIS violates the following MISRA-C:2004 rules:
boonshen 0:a35c40f49345 43
boonshen 0:a35c40f49345 44 \li Required Rule 8.5, object/function definition in header file.<br>
boonshen 0:a35c40f49345 45 Function definitions in header files are used to allow 'inlining'.
boonshen 0:a35c40f49345 46
boonshen 0:a35c40f49345 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
boonshen 0:a35c40f49345 48 Unions are used for effective representation of core registers.
boonshen 0:a35c40f49345 49
boonshen 0:a35c40f49345 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
boonshen 0:a35c40f49345 51 Function-like macros are used to allow more efficient code.
boonshen 0:a35c40f49345 52 */
boonshen 0:a35c40f49345 53
boonshen 0:a35c40f49345 54
boonshen 0:a35c40f49345 55 /*******************************************************************************
boonshen 0:a35c40f49345 56 * CMSIS definitions
boonshen 0:a35c40f49345 57 ******************************************************************************/
boonshen 0:a35c40f49345 58 /**
boonshen 0:a35c40f49345 59 \ingroup Cortex_M0
boonshen 0:a35c40f49345 60 @{
boonshen 0:a35c40f49345 61 */
boonshen 0:a35c40f49345 62
boonshen 0:a35c40f49345 63 /* CMSIS CM0 definitions */
boonshen 0:a35c40f49345 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
boonshen 0:a35c40f49345 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
boonshen 0:a35c40f49345 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
boonshen 0:a35c40f49345 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
boonshen 0:a35c40f49345 68
boonshen 0:a35c40f49345 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
boonshen 0:a35c40f49345 70
boonshen 0:a35c40f49345 71 /** __FPU_USED indicates whether an FPU is used or not.
boonshen 0:a35c40f49345 72 This core does not support an FPU at all
boonshen 0:a35c40f49345 73 */
boonshen 0:a35c40f49345 74 #define __FPU_USED 0U
boonshen 0:a35c40f49345 75
boonshen 0:a35c40f49345 76 #if defined ( __CC_ARM )
boonshen 0:a35c40f49345 77 #if defined __TARGET_FPU_VFP
boonshen 0:a35c40f49345 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 79 #endif
boonshen 0:a35c40f49345 80
boonshen 0:a35c40f49345 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen 0:a35c40f49345 82 #if defined __ARM_PCS_VFP
boonshen 0:a35c40f49345 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 84 #endif
boonshen 0:a35c40f49345 85
boonshen 0:a35c40f49345 86 #elif defined ( __GNUC__ )
boonshen 0:a35c40f49345 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
boonshen 0:a35c40f49345 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 89 #endif
boonshen 0:a35c40f49345 90
boonshen 0:a35c40f49345 91 #elif defined ( __ICCARM__ )
boonshen 0:a35c40f49345 92 #if defined __ARMVFP__
boonshen 0:a35c40f49345 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 94 #endif
boonshen 0:a35c40f49345 95
boonshen 0:a35c40f49345 96 #elif defined ( __TI_ARM__ )
boonshen 0:a35c40f49345 97 #if defined __TI_VFP_SUPPORT__
boonshen 0:a35c40f49345 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 99 #endif
boonshen 0:a35c40f49345 100
boonshen 0:a35c40f49345 101 #elif defined ( __TASKING__ )
boonshen 0:a35c40f49345 102 #if defined __FPU_VFP__
boonshen 0:a35c40f49345 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 104 #endif
boonshen 0:a35c40f49345 105
boonshen 0:a35c40f49345 106 #elif defined ( __CSMC__ )
boonshen 0:a35c40f49345 107 #if ( __CSMC__ & 0x400U)
boonshen 0:a35c40f49345 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen 0:a35c40f49345 109 #endif
boonshen 0:a35c40f49345 110
boonshen 0:a35c40f49345 111 #endif
boonshen 0:a35c40f49345 112
boonshen 0:a35c40f49345 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
boonshen 0:a35c40f49345 114
boonshen 0:a35c40f49345 115
boonshen 0:a35c40f49345 116 #ifdef __cplusplus
boonshen 0:a35c40f49345 117 }
boonshen 0:a35c40f49345 118 #endif
boonshen 0:a35c40f49345 119
boonshen 0:a35c40f49345 120 #endif /* __CORE_CM0_H_GENERIC */
boonshen 0:a35c40f49345 121
boonshen 0:a35c40f49345 122 #ifndef __CMSIS_GENERIC
boonshen 0:a35c40f49345 123
boonshen 0:a35c40f49345 124 #ifndef __CORE_CM0_H_DEPENDANT
boonshen 0:a35c40f49345 125 #define __CORE_CM0_H_DEPENDANT
boonshen 0:a35c40f49345 126
boonshen 0:a35c40f49345 127 #ifdef __cplusplus
boonshen 0:a35c40f49345 128 extern "C" {
boonshen 0:a35c40f49345 129 #endif
boonshen 0:a35c40f49345 130
boonshen 0:a35c40f49345 131 /* check device defines and use defaults */
boonshen 0:a35c40f49345 132 #if defined __CHECK_DEVICE_DEFINES
boonshen 0:a35c40f49345 133 #ifndef __CM0_REV
boonshen 0:a35c40f49345 134 #define __CM0_REV 0x0000U
boonshen 0:a35c40f49345 135 #warning "__CM0_REV not defined in device header file; using default!"
boonshen 0:a35c40f49345 136 #endif
boonshen 0:a35c40f49345 137
boonshen 0:a35c40f49345 138 #ifndef __NVIC_PRIO_BITS
boonshen 0:a35c40f49345 139 #define __NVIC_PRIO_BITS 2U
boonshen 0:a35c40f49345 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
boonshen 0:a35c40f49345 141 #endif
boonshen 0:a35c40f49345 142
boonshen 0:a35c40f49345 143 #ifndef __Vendor_SysTickConfig
boonshen 0:a35c40f49345 144 #define __Vendor_SysTickConfig 0U
boonshen 0:a35c40f49345 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
boonshen 0:a35c40f49345 146 #endif
boonshen 0:a35c40f49345 147 #endif
boonshen 0:a35c40f49345 148
boonshen 0:a35c40f49345 149 /* IO definitions (access restrictions to peripheral registers) */
boonshen 0:a35c40f49345 150 /**
boonshen 0:a35c40f49345 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
boonshen 0:a35c40f49345 152
boonshen 0:a35c40f49345 153 <strong>IO Type Qualifiers</strong> are used
boonshen 0:a35c40f49345 154 \li to specify the access to peripheral variables.
boonshen 0:a35c40f49345 155 \li for automatic generation of peripheral register debug information.
boonshen 0:a35c40f49345 156 */
boonshen 0:a35c40f49345 157 #ifdef __cplusplus
boonshen 0:a35c40f49345 158 #define __I volatile /*!< Defines 'read only' permissions */
boonshen 0:a35c40f49345 159 #else
boonshen 0:a35c40f49345 160 #define __I volatile const /*!< Defines 'read only' permissions */
boonshen 0:a35c40f49345 161 #endif
boonshen 0:a35c40f49345 162 #define __O volatile /*!< Defines 'write only' permissions */
boonshen 0:a35c40f49345 163 #define __IO volatile /*!< Defines 'read / write' permissions */
boonshen 0:a35c40f49345 164
boonshen 0:a35c40f49345 165 /* following defines should be used for structure members */
boonshen 0:a35c40f49345 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
boonshen 0:a35c40f49345 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
boonshen 0:a35c40f49345 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
boonshen 0:a35c40f49345 169
boonshen 0:a35c40f49345 170 /*@} end of group Cortex_M0 */
boonshen 0:a35c40f49345 171
boonshen 0:a35c40f49345 172
boonshen 0:a35c40f49345 173
boonshen 0:a35c40f49345 174 /*******************************************************************************
boonshen 0:a35c40f49345 175 * Register Abstraction
boonshen 0:a35c40f49345 176 Core Register contain:
boonshen 0:a35c40f49345 177 - Core Register
boonshen 0:a35c40f49345 178 - Core NVIC Register
boonshen 0:a35c40f49345 179 - Core SCB Register
boonshen 0:a35c40f49345 180 - Core SysTick Register
boonshen 0:a35c40f49345 181 ******************************************************************************/
boonshen 0:a35c40f49345 182 /**
boonshen 0:a35c40f49345 183 \defgroup CMSIS_core_register Defines and Type Definitions
boonshen 0:a35c40f49345 184 \brief Type definitions and defines for Cortex-M processor based devices.
boonshen 0:a35c40f49345 185 */
boonshen 0:a35c40f49345 186
boonshen 0:a35c40f49345 187 /**
boonshen 0:a35c40f49345 188 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 189 \defgroup CMSIS_CORE Status and Control Registers
boonshen 0:a35c40f49345 190 \brief Core Register type definitions.
boonshen 0:a35c40f49345 191 @{
boonshen 0:a35c40f49345 192 */
boonshen 0:a35c40f49345 193
boonshen 0:a35c40f49345 194 /**
boonshen 0:a35c40f49345 195 \brief Union type to access the Application Program Status Register (APSR).
boonshen 0:a35c40f49345 196 */
boonshen 0:a35c40f49345 197 typedef union
boonshen 0:a35c40f49345 198 {
boonshen 0:a35c40f49345 199 struct
boonshen 0:a35c40f49345 200 {
boonshen 0:a35c40f49345 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
boonshen 0:a35c40f49345 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
boonshen 0:a35c40f49345 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
boonshen 0:a35c40f49345 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
boonshen 0:a35c40f49345 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
boonshen 0:a35c40f49345 206 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 207 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 208 } APSR_Type;
boonshen 0:a35c40f49345 209
boonshen 0:a35c40f49345 210 /* APSR Register Definitions */
boonshen 0:a35c40f49345 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
boonshen 0:a35c40f49345 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
boonshen 0:a35c40f49345 213
boonshen 0:a35c40f49345 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
boonshen 0:a35c40f49345 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
boonshen 0:a35c40f49345 216
boonshen 0:a35c40f49345 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
boonshen 0:a35c40f49345 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
boonshen 0:a35c40f49345 219
boonshen 0:a35c40f49345 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
boonshen 0:a35c40f49345 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
boonshen 0:a35c40f49345 222
boonshen 0:a35c40f49345 223
boonshen 0:a35c40f49345 224 /**
boonshen 0:a35c40f49345 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
boonshen 0:a35c40f49345 226 */
boonshen 0:a35c40f49345 227 typedef union
boonshen 0:a35c40f49345 228 {
boonshen 0:a35c40f49345 229 struct
boonshen 0:a35c40f49345 230 {
boonshen 0:a35c40f49345 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
boonshen 0:a35c40f49345 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
boonshen 0:a35c40f49345 233 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 234 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 235 } IPSR_Type;
boonshen 0:a35c40f49345 236
boonshen 0:a35c40f49345 237 /* IPSR Register Definitions */
boonshen 0:a35c40f49345 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
boonshen 0:a35c40f49345 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
boonshen 0:a35c40f49345 240
boonshen 0:a35c40f49345 241
boonshen 0:a35c40f49345 242 /**
boonshen 0:a35c40f49345 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
boonshen 0:a35c40f49345 244 */
boonshen 0:a35c40f49345 245 typedef union
boonshen 0:a35c40f49345 246 {
boonshen 0:a35c40f49345 247 struct
boonshen 0:a35c40f49345 248 {
boonshen 0:a35c40f49345 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
boonshen 0:a35c40f49345 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
boonshen 0:a35c40f49345 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
boonshen 0:a35c40f49345 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
boonshen 0:a35c40f49345 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
boonshen 0:a35c40f49345 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
boonshen 0:a35c40f49345 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
boonshen 0:a35c40f49345 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
boonshen 0:a35c40f49345 257 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 258 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 259 } xPSR_Type;
boonshen 0:a35c40f49345 260
boonshen 0:a35c40f49345 261 /* xPSR Register Definitions */
boonshen 0:a35c40f49345 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
boonshen 0:a35c40f49345 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
boonshen 0:a35c40f49345 264
boonshen 0:a35c40f49345 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
boonshen 0:a35c40f49345 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
boonshen 0:a35c40f49345 267
boonshen 0:a35c40f49345 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
boonshen 0:a35c40f49345 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
boonshen 0:a35c40f49345 270
boonshen 0:a35c40f49345 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
boonshen 0:a35c40f49345 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
boonshen 0:a35c40f49345 273
boonshen 0:a35c40f49345 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
boonshen 0:a35c40f49345 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
boonshen 0:a35c40f49345 276
boonshen 0:a35c40f49345 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
boonshen 0:a35c40f49345 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
boonshen 0:a35c40f49345 279
boonshen 0:a35c40f49345 280
boonshen 0:a35c40f49345 281 /**
boonshen 0:a35c40f49345 282 \brief Union type to access the Control Registers (CONTROL).
boonshen 0:a35c40f49345 283 */
boonshen 0:a35c40f49345 284 typedef union
boonshen 0:a35c40f49345 285 {
boonshen 0:a35c40f49345 286 struct
boonshen 0:a35c40f49345 287 {
boonshen 0:a35c40f49345 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
boonshen 0:a35c40f49345 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
boonshen 0:a35c40f49345 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
boonshen 0:a35c40f49345 291 } b; /*!< Structure used for bit access */
boonshen 0:a35c40f49345 292 uint32_t w; /*!< Type used for word access */
boonshen 0:a35c40f49345 293 } CONTROL_Type;
boonshen 0:a35c40f49345 294
boonshen 0:a35c40f49345 295 /* CONTROL Register Definitions */
boonshen 0:a35c40f49345 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
boonshen 0:a35c40f49345 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
boonshen 0:a35c40f49345 298
boonshen 0:a35c40f49345 299 /*@} end of group CMSIS_CORE */
boonshen 0:a35c40f49345 300
boonshen 0:a35c40f49345 301
boonshen 0:a35c40f49345 302 /**
boonshen 0:a35c40f49345 303 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
boonshen 0:a35c40f49345 305 \brief Type definitions for the NVIC Registers
boonshen 0:a35c40f49345 306 @{
boonshen 0:a35c40f49345 307 */
boonshen 0:a35c40f49345 308
boonshen 0:a35c40f49345 309 /**
boonshen 0:a35c40f49345 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
boonshen 0:a35c40f49345 311 */
boonshen 0:a35c40f49345 312 typedef struct
boonshen 0:a35c40f49345 313 {
boonshen 0:a35c40f49345 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
boonshen 0:a35c40f49345 315 uint32_t RESERVED0[31U];
boonshen 0:a35c40f49345 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
boonshen 0:a35c40f49345 317 uint32_t RSERVED1[31U];
boonshen 0:a35c40f49345 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
boonshen 0:a35c40f49345 319 uint32_t RESERVED2[31U];
boonshen 0:a35c40f49345 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
boonshen 0:a35c40f49345 321 uint32_t RESERVED3[31U];
boonshen 0:a35c40f49345 322 uint32_t RESERVED4[64U];
boonshen 0:a35c40f49345 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
boonshen 0:a35c40f49345 324 } NVIC_Type;
boonshen 0:a35c40f49345 325
boonshen 0:a35c40f49345 326 /*@} end of group CMSIS_NVIC */
boonshen 0:a35c40f49345 327
boonshen 0:a35c40f49345 328
boonshen 0:a35c40f49345 329 /**
boonshen 0:a35c40f49345 330 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 331 \defgroup CMSIS_SCB System Control Block (SCB)
boonshen 0:a35c40f49345 332 \brief Type definitions for the System Control Block Registers
boonshen 0:a35c40f49345 333 @{
boonshen 0:a35c40f49345 334 */
boonshen 0:a35c40f49345 335
boonshen 0:a35c40f49345 336 /**
boonshen 0:a35c40f49345 337 \brief Structure type to access the System Control Block (SCB).
boonshen 0:a35c40f49345 338 */
boonshen 0:a35c40f49345 339 typedef struct
boonshen 0:a35c40f49345 340 {
boonshen 0:a35c40f49345 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
boonshen 0:a35c40f49345 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
boonshen 0:a35c40f49345 343 uint32_t RESERVED0;
boonshen 0:a35c40f49345 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
boonshen 0:a35c40f49345 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
boonshen 0:a35c40f49345 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
boonshen 0:a35c40f49345 347 uint32_t RESERVED1;
boonshen 0:a35c40f49345 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
boonshen 0:a35c40f49345 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
boonshen 0:a35c40f49345 350 } SCB_Type;
boonshen 0:a35c40f49345 351
boonshen 0:a35c40f49345 352 /* SCB CPUID Register Definitions */
boonshen 0:a35c40f49345 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
boonshen 0:a35c40f49345 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
boonshen 0:a35c40f49345 355
boonshen 0:a35c40f49345 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
boonshen 0:a35c40f49345 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
boonshen 0:a35c40f49345 358
boonshen 0:a35c40f49345 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
boonshen 0:a35c40f49345 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
boonshen 0:a35c40f49345 361
boonshen 0:a35c40f49345 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
boonshen 0:a35c40f49345 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
boonshen 0:a35c40f49345 364
boonshen 0:a35c40f49345 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
boonshen 0:a35c40f49345 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
boonshen 0:a35c40f49345 367
boonshen 0:a35c40f49345 368 /* SCB Interrupt Control State Register Definitions */
boonshen 0:a35c40f49345 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
boonshen 0:a35c40f49345 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
boonshen 0:a35c40f49345 371
boonshen 0:a35c40f49345 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
boonshen 0:a35c40f49345 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
boonshen 0:a35c40f49345 374
boonshen 0:a35c40f49345 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
boonshen 0:a35c40f49345 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
boonshen 0:a35c40f49345 377
boonshen 0:a35c40f49345 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
boonshen 0:a35c40f49345 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
boonshen 0:a35c40f49345 380
boonshen 0:a35c40f49345 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
boonshen 0:a35c40f49345 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
boonshen 0:a35c40f49345 383
boonshen 0:a35c40f49345 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
boonshen 0:a35c40f49345 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
boonshen 0:a35c40f49345 386
boonshen 0:a35c40f49345 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
boonshen 0:a35c40f49345 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
boonshen 0:a35c40f49345 389
boonshen 0:a35c40f49345 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
boonshen 0:a35c40f49345 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
boonshen 0:a35c40f49345 392
boonshen 0:a35c40f49345 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
boonshen 0:a35c40f49345 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
boonshen 0:a35c40f49345 395
boonshen 0:a35c40f49345 396 /* SCB Application Interrupt and Reset Control Register Definitions */
boonshen 0:a35c40f49345 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
boonshen 0:a35c40f49345 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
boonshen 0:a35c40f49345 399
boonshen 0:a35c40f49345 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
boonshen 0:a35c40f49345 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
boonshen 0:a35c40f49345 402
boonshen 0:a35c40f49345 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
boonshen 0:a35c40f49345 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
boonshen 0:a35c40f49345 405
boonshen 0:a35c40f49345 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
boonshen 0:a35c40f49345 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
boonshen 0:a35c40f49345 408
boonshen 0:a35c40f49345 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
boonshen 0:a35c40f49345 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
boonshen 0:a35c40f49345 411
boonshen 0:a35c40f49345 412 /* SCB System Control Register Definitions */
boonshen 0:a35c40f49345 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
boonshen 0:a35c40f49345 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
boonshen 0:a35c40f49345 415
boonshen 0:a35c40f49345 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
boonshen 0:a35c40f49345 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
boonshen 0:a35c40f49345 418
boonshen 0:a35c40f49345 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
boonshen 0:a35c40f49345 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
boonshen 0:a35c40f49345 421
boonshen 0:a35c40f49345 422 /* SCB Configuration Control Register Definitions */
boonshen 0:a35c40f49345 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
boonshen 0:a35c40f49345 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
boonshen 0:a35c40f49345 425
boonshen 0:a35c40f49345 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
boonshen 0:a35c40f49345 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
boonshen 0:a35c40f49345 428
boonshen 0:a35c40f49345 429 /* SCB System Handler Control and State Register Definitions */
boonshen 0:a35c40f49345 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
boonshen 0:a35c40f49345 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
boonshen 0:a35c40f49345 432
boonshen 0:a35c40f49345 433 /*@} end of group CMSIS_SCB */
boonshen 0:a35c40f49345 434
boonshen 0:a35c40f49345 435
boonshen 0:a35c40f49345 436 /**
boonshen 0:a35c40f49345 437 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
boonshen 0:a35c40f49345 439 \brief Type definitions for the System Timer Registers.
boonshen 0:a35c40f49345 440 @{
boonshen 0:a35c40f49345 441 */
boonshen 0:a35c40f49345 442
boonshen 0:a35c40f49345 443 /**
boonshen 0:a35c40f49345 444 \brief Structure type to access the System Timer (SysTick).
boonshen 0:a35c40f49345 445 */
boonshen 0:a35c40f49345 446 typedef struct
boonshen 0:a35c40f49345 447 {
boonshen 0:a35c40f49345 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
boonshen 0:a35c40f49345 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
boonshen 0:a35c40f49345 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
boonshen 0:a35c40f49345 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
boonshen 0:a35c40f49345 452 } SysTick_Type;
boonshen 0:a35c40f49345 453
boonshen 0:a35c40f49345 454 /* SysTick Control / Status Register Definitions */
boonshen 0:a35c40f49345 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
boonshen 0:a35c40f49345 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
boonshen 0:a35c40f49345 457
boonshen 0:a35c40f49345 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
boonshen 0:a35c40f49345 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
boonshen 0:a35c40f49345 460
boonshen 0:a35c40f49345 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
boonshen 0:a35c40f49345 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
boonshen 0:a35c40f49345 463
boonshen 0:a35c40f49345 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
boonshen 0:a35c40f49345 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
boonshen 0:a35c40f49345 466
boonshen 0:a35c40f49345 467 /* SysTick Reload Register Definitions */
boonshen 0:a35c40f49345 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
boonshen 0:a35c40f49345 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
boonshen 0:a35c40f49345 470
boonshen 0:a35c40f49345 471 /* SysTick Current Register Definitions */
boonshen 0:a35c40f49345 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
boonshen 0:a35c40f49345 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
boonshen 0:a35c40f49345 474
boonshen 0:a35c40f49345 475 /* SysTick Calibration Register Definitions */
boonshen 0:a35c40f49345 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
boonshen 0:a35c40f49345 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
boonshen 0:a35c40f49345 478
boonshen 0:a35c40f49345 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
boonshen 0:a35c40f49345 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
boonshen 0:a35c40f49345 481
boonshen 0:a35c40f49345 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
boonshen 0:a35c40f49345 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
boonshen 0:a35c40f49345 484
boonshen 0:a35c40f49345 485 /*@} end of group CMSIS_SysTick */
boonshen 0:a35c40f49345 486
boonshen 0:a35c40f49345 487
boonshen 0:a35c40f49345 488 /**
boonshen 0:a35c40f49345 489 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
boonshen 0:a35c40f49345 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
boonshen 0:a35c40f49345 492 Therefore they are not covered by the Cortex-M0 header file.
boonshen 0:a35c40f49345 493 @{
boonshen 0:a35c40f49345 494 */
boonshen 0:a35c40f49345 495 /*@} end of group CMSIS_CoreDebug */
boonshen 0:a35c40f49345 496
boonshen 0:a35c40f49345 497
boonshen 0:a35c40f49345 498 /**
boonshen 0:a35c40f49345 499 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 500 \defgroup CMSIS_core_bitfield Core register bit field macros
boonshen 0:a35c40f49345 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
boonshen 0:a35c40f49345 502 @{
boonshen 0:a35c40f49345 503 */
boonshen 0:a35c40f49345 504
boonshen 0:a35c40f49345 505 /**
boonshen 0:a35c40f49345 506 \brief Mask and shift a bit field value for use in a register bit range.
boonshen 0:a35c40f49345 507 \param[in] field Name of the register bit field.
boonshen 0:a35c40f49345 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
boonshen 0:a35c40f49345 509 \return Masked and shifted value.
boonshen 0:a35c40f49345 510 */
boonshen 0:a35c40f49345 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
boonshen 0:a35c40f49345 512
boonshen 0:a35c40f49345 513 /**
boonshen 0:a35c40f49345 514 \brief Mask and shift a register value to extract a bit filed value.
boonshen 0:a35c40f49345 515 \param[in] field Name of the register bit field.
boonshen 0:a35c40f49345 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
boonshen 0:a35c40f49345 517 \return Masked and shifted bit field value.
boonshen 0:a35c40f49345 518 */
boonshen 0:a35c40f49345 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
boonshen 0:a35c40f49345 520
boonshen 0:a35c40f49345 521 /*@} end of group CMSIS_core_bitfield */
boonshen 0:a35c40f49345 522
boonshen 0:a35c40f49345 523
boonshen 0:a35c40f49345 524 /**
boonshen 0:a35c40f49345 525 \ingroup CMSIS_core_register
boonshen 0:a35c40f49345 526 \defgroup CMSIS_core_base Core Definitions
boonshen 0:a35c40f49345 527 \brief Definitions for base addresses, unions, and structures.
boonshen 0:a35c40f49345 528 @{
boonshen 0:a35c40f49345 529 */
boonshen 0:a35c40f49345 530
boonshen 0:a35c40f49345 531 /* Memory mapping of Core Hardware */
boonshen 0:a35c40f49345 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
boonshen 0:a35c40f49345 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
boonshen 0:a35c40f49345 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
boonshen 0:a35c40f49345 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
boonshen 0:a35c40f49345 536
boonshen 0:a35c40f49345 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
boonshen 0:a35c40f49345 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
boonshen 0:a35c40f49345 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
boonshen 0:a35c40f49345 540
boonshen 0:a35c40f49345 541
boonshen 0:a35c40f49345 542 /*@} */
boonshen 0:a35c40f49345 543
boonshen 0:a35c40f49345 544
boonshen 0:a35c40f49345 545
boonshen 0:a35c40f49345 546 /*******************************************************************************
boonshen 0:a35c40f49345 547 * Hardware Abstraction Layer
boonshen 0:a35c40f49345 548 Core Function Interface contains:
boonshen 0:a35c40f49345 549 - Core NVIC Functions
boonshen 0:a35c40f49345 550 - Core SysTick Functions
boonshen 0:a35c40f49345 551 - Core Register Access Functions
boonshen 0:a35c40f49345 552 ******************************************************************************/
boonshen 0:a35c40f49345 553 /**
boonshen 0:a35c40f49345 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
boonshen 0:a35c40f49345 555 */
boonshen 0:a35c40f49345 556
boonshen 0:a35c40f49345 557
boonshen 0:a35c40f49345 558
boonshen 0:a35c40f49345 559 /* ########################## NVIC functions #################################### */
boonshen 0:a35c40f49345 560 /**
boonshen 0:a35c40f49345 561 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
boonshen 0:a35c40f49345 563 \brief Functions that manage interrupts and exceptions via the NVIC.
boonshen 0:a35c40f49345 564 @{
boonshen 0:a35c40f49345 565 */
boonshen 0:a35c40f49345 566
boonshen 0:a35c40f49345 567 #ifdef CMSIS_NVIC_VIRTUAL
boonshen 0:a35c40f49345 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
boonshen 0:a35c40f49345 570 #endif
boonshen 0:a35c40f49345 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 572 #else
boonshen 0:a35c40f49345 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
boonshen 0:a35c40f49345 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
boonshen 0:a35c40f49345 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
boonshen 0:a35c40f49345 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
boonshen 0:a35c40f49345 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
boonshen 0:a35c40f49345 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
boonshen 0:a35c40f49345 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
boonshen 0:a35c40f49345 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
boonshen 0:a35c40f49345 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
boonshen 0:a35c40f49345 582 #define NVIC_SetPriority __NVIC_SetPriority
boonshen 0:a35c40f49345 583 #define NVIC_GetPriority __NVIC_GetPriority
boonshen 0:a35c40f49345 584 #define NVIC_SystemReset __NVIC_SystemReset
boonshen 0:a35c40f49345 585 #endif /* CMSIS_NVIC_VIRTUAL */
boonshen 0:a35c40f49345 586
boonshen 0:a35c40f49345 587 #ifdef CMSIS_VECTAB_VIRTUAL
boonshen 0:a35c40f49345 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
boonshen 0:a35c40f49345 590 #endif
boonshen 0:a35c40f49345 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen 0:a35c40f49345 592 #else
boonshen 0:a35c40f49345 593 #define NVIC_SetVector __NVIC_SetVector
boonshen 0:a35c40f49345 594 #define NVIC_GetVector __NVIC_GetVector
boonshen 0:a35c40f49345 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
boonshen 0:a35c40f49345 596
boonshen 0:a35c40f49345 597 #define NVIC_USER_IRQ_OFFSET 16
boonshen 0:a35c40f49345 598
boonshen 0:a35c40f49345 599
boonshen 0:a35c40f49345 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
boonshen 0:a35c40f49345 601 /* The following MACROS handle generation of the register offset and byte masks */
boonshen 0:a35c40f49345 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
boonshen 0:a35c40f49345 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
boonshen 0:a35c40f49345 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
boonshen 0:a35c40f49345 605
boonshen 0:a35c40f49345 606
boonshen 0:a35c40f49345 607 /**
boonshen 0:a35c40f49345 608 \brief Enable Interrupt
boonshen 0:a35c40f49345 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
boonshen 0:a35c40f49345 610 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 611 \note IRQn must not be negative.
boonshen 0:a35c40f49345 612 */
boonshen 0:a35c40f49345 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 614 {
boonshen 0:a35c40f49345 615 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 616 {
boonshen 0:a35c40f49345 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 618 }
boonshen 0:a35c40f49345 619 }
boonshen 0:a35c40f49345 620
boonshen 0:a35c40f49345 621
boonshen 0:a35c40f49345 622 /**
boonshen 0:a35c40f49345 623 \brief Get Interrupt Enable status
boonshen 0:a35c40f49345 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
boonshen 0:a35c40f49345 625 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 626 \return 0 Interrupt is not enabled.
boonshen 0:a35c40f49345 627 \return 1 Interrupt is enabled.
boonshen 0:a35c40f49345 628 \note IRQn must not be negative.
boonshen 0:a35c40f49345 629 */
boonshen 0:a35c40f49345 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 631 {
boonshen 0:a35c40f49345 632 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 633 {
boonshen 0:a35c40f49345 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 635 }
boonshen 0:a35c40f49345 636 else
boonshen 0:a35c40f49345 637 {
boonshen 0:a35c40f49345 638 return(0U);
boonshen 0:a35c40f49345 639 }
boonshen 0:a35c40f49345 640 }
boonshen 0:a35c40f49345 641
boonshen 0:a35c40f49345 642
boonshen 0:a35c40f49345 643 /**
boonshen 0:a35c40f49345 644 \brief Disable Interrupt
boonshen 0:a35c40f49345 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
boonshen 0:a35c40f49345 646 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 647 \note IRQn must not be negative.
boonshen 0:a35c40f49345 648 */
boonshen 0:a35c40f49345 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 650 {
boonshen 0:a35c40f49345 651 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 652 {
boonshen 0:a35c40f49345 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 654 __DSB();
boonshen 0:a35c40f49345 655 __ISB();
boonshen 0:a35c40f49345 656 }
boonshen 0:a35c40f49345 657 }
boonshen 0:a35c40f49345 658
boonshen 0:a35c40f49345 659
boonshen 0:a35c40f49345 660 /**
boonshen 0:a35c40f49345 661 \brief Get Pending Interrupt
boonshen 0:a35c40f49345 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
boonshen 0:a35c40f49345 663 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 664 \return 0 Interrupt status is not pending.
boonshen 0:a35c40f49345 665 \return 1 Interrupt status is pending.
boonshen 0:a35c40f49345 666 \note IRQn must not be negative.
boonshen 0:a35c40f49345 667 */
boonshen 0:a35c40f49345 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 669 {
boonshen 0:a35c40f49345 670 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 671 {
boonshen 0:a35c40f49345 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen 0:a35c40f49345 673 }
boonshen 0:a35c40f49345 674 else
boonshen 0:a35c40f49345 675 {
boonshen 0:a35c40f49345 676 return(0U);
boonshen 0:a35c40f49345 677 }
boonshen 0:a35c40f49345 678 }
boonshen 0:a35c40f49345 679
boonshen 0:a35c40f49345 680
boonshen 0:a35c40f49345 681 /**
boonshen 0:a35c40f49345 682 \brief Set Pending Interrupt
boonshen 0:a35c40f49345 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
boonshen 0:a35c40f49345 684 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 685 \note IRQn must not be negative.
boonshen 0:a35c40f49345 686 */
boonshen 0:a35c40f49345 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 688 {
boonshen 0:a35c40f49345 689 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 690 {
boonshen 0:a35c40f49345 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 692 }
boonshen 0:a35c40f49345 693 }
boonshen 0:a35c40f49345 694
boonshen 0:a35c40f49345 695
boonshen 0:a35c40f49345 696 /**
boonshen 0:a35c40f49345 697 \brief Clear Pending Interrupt
boonshen 0:a35c40f49345 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
boonshen 0:a35c40f49345 699 \param [in] IRQn Device specific interrupt number.
boonshen 0:a35c40f49345 700 \note IRQn must not be negative.
boonshen 0:a35c40f49345 701 */
boonshen 0:a35c40f49345 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
boonshen 0:a35c40f49345 703 {
boonshen 0:a35c40f49345 704 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 705 {
boonshen 0:a35c40f49345 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen 0:a35c40f49345 707 }
boonshen 0:a35c40f49345 708 }
boonshen 0:a35c40f49345 709
boonshen 0:a35c40f49345 710
boonshen 0:a35c40f49345 711 /**
boonshen 0:a35c40f49345 712 \brief Set Interrupt Priority
boonshen 0:a35c40f49345 713 \details Sets the priority of a device specific interrupt or a processor exception.
boonshen 0:a35c40f49345 714 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 715 or negative to specify a processor exception.
boonshen 0:a35c40f49345 716 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 717 \param [in] priority Priority to set.
boonshen 0:a35c40f49345 718 \note The priority cannot be set for every processor exception.
boonshen 0:a35c40f49345 719 */
boonshen 0:a35c40f49345 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
boonshen 0:a35c40f49345 721 {
boonshen 0:a35c40f49345 722 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 723 {
boonshen 0:a35c40f49345 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
boonshen 0:a35c40f49345 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
boonshen 0:a35c40f49345 726 }
boonshen 0:a35c40f49345 727 else
boonshen 0:a35c40f49345 728 {
boonshen 0:a35c40f49345 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
boonshen 0:a35c40f49345 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
boonshen 0:a35c40f49345 731 }
boonshen 0:a35c40f49345 732 }
boonshen 0:a35c40f49345 733
boonshen 0:a35c40f49345 734
boonshen 0:a35c40f49345 735 /**
boonshen 0:a35c40f49345 736 \brief Get Interrupt Priority
boonshen 0:a35c40f49345 737 \details Reads the priority of a device specific interrupt or a processor exception.
boonshen 0:a35c40f49345 738 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 739 or negative to specify a processor exception.
boonshen 0:a35c40f49345 740 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 741 \return Interrupt Priority.
boonshen 0:a35c40f49345 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
boonshen 0:a35c40f49345 743 */
boonshen 0:a35c40f49345 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
boonshen 0:a35c40f49345 745 {
boonshen 0:a35c40f49345 746
boonshen 0:a35c40f49345 747 if ((int32_t)(IRQn) >= 0)
boonshen 0:a35c40f49345 748 {
boonshen 0:a35c40f49345 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 750 }
boonshen 0:a35c40f49345 751 else
boonshen 0:a35c40f49345 752 {
boonshen 0:a35c40f49345 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
boonshen 0:a35c40f49345 754 }
boonshen 0:a35c40f49345 755 }
boonshen 0:a35c40f49345 756
boonshen 0:a35c40f49345 757
boonshen 0:a35c40f49345 758 /**
boonshen 0:a35c40f49345 759 \brief Set Interrupt Vector
boonshen 0:a35c40f49345 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
boonshen 0:a35c40f49345 761 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 762 or negative to specify a processor exception.
boonshen 0:a35c40f49345 763 Address 0 must be mapped to SRAM.
boonshen 0:a35c40f49345 764 \param [in] IRQn Interrupt number
boonshen 0:a35c40f49345 765 \param [in] vector Address of interrupt handler function
boonshen 0:a35c40f49345 766 */
boonshen 0:a35c40f49345 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
boonshen 0:a35c40f49345 768 {
boonshen 0:a35c40f49345 769 uint32_t *vectors = (uint32_t *)0x0U;
boonshen 0:a35c40f49345 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
boonshen 0:a35c40f49345 771 }
boonshen 0:a35c40f49345 772
boonshen 0:a35c40f49345 773
boonshen 0:a35c40f49345 774 /**
boonshen 0:a35c40f49345 775 \brief Get Interrupt Vector
boonshen 0:a35c40f49345 776 \details Reads an interrupt vector from interrupt vector table.
boonshen 0:a35c40f49345 777 The interrupt number can be positive to specify a device specific interrupt,
boonshen 0:a35c40f49345 778 or negative to specify a processor exception.
boonshen 0:a35c40f49345 779 \param [in] IRQn Interrupt number.
boonshen 0:a35c40f49345 780 \return Address of interrupt handler function
boonshen 0:a35c40f49345 781 */
boonshen 0:a35c40f49345 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
boonshen 0:a35c40f49345 783 {
boonshen 0:a35c40f49345 784 uint32_t *vectors = (uint32_t *)0x0U;
boonshen 0:a35c40f49345 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
boonshen 0:a35c40f49345 786 }
boonshen 0:a35c40f49345 787
boonshen 0:a35c40f49345 788
boonshen 0:a35c40f49345 789 /**
boonshen 0:a35c40f49345 790 \brief System Reset
boonshen 0:a35c40f49345 791 \details Initiates a system reset request to reset the MCU.
boonshen 0:a35c40f49345 792 */
boonshen 0:a35c40f49345 793 __STATIC_INLINE void __NVIC_SystemReset(void)
boonshen 0:a35c40f49345 794 {
boonshen 0:a35c40f49345 795 __DSB(); /* Ensure all outstanding memory accesses included
boonshen 0:a35c40f49345 796 buffered write are completed before reset */
boonshen 0:a35c40f49345 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
boonshen 0:a35c40f49345 798 SCB_AIRCR_SYSRESETREQ_Msk);
boonshen 0:a35c40f49345 799 __DSB(); /* Ensure completion of memory access */
boonshen 0:a35c40f49345 800
boonshen 0:a35c40f49345 801 for(;;) /* wait until reset */
boonshen 0:a35c40f49345 802 {
boonshen 0:a35c40f49345 803 __NOP();
boonshen 0:a35c40f49345 804 }
boonshen 0:a35c40f49345 805 }
boonshen 0:a35c40f49345 806
boonshen 0:a35c40f49345 807 /*@} end of CMSIS_Core_NVICFunctions */
boonshen 0:a35c40f49345 808
boonshen 0:a35c40f49345 809
boonshen 0:a35c40f49345 810 /* ########################## FPU functions #################################### */
boonshen 0:a35c40f49345 811 /**
boonshen 0:a35c40f49345 812 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
boonshen 0:a35c40f49345 814 \brief Function that provides FPU type.
boonshen 0:a35c40f49345 815 @{
boonshen 0:a35c40f49345 816 */
boonshen 0:a35c40f49345 817
boonshen 0:a35c40f49345 818 /**
boonshen 0:a35c40f49345 819 \brief get FPU type
boonshen 0:a35c40f49345 820 \details returns the FPU type
boonshen 0:a35c40f49345 821 \returns
boonshen 0:a35c40f49345 822 - \b 0: No FPU
boonshen 0:a35c40f49345 823 - \b 1: Single precision FPU
boonshen 0:a35c40f49345 824 - \b 2: Double + Single precision FPU
boonshen 0:a35c40f49345 825 */
boonshen 0:a35c40f49345 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
boonshen 0:a35c40f49345 827 {
boonshen 0:a35c40f49345 828 return 0U; /* No FPU */
boonshen 0:a35c40f49345 829 }
boonshen 0:a35c40f49345 830
boonshen 0:a35c40f49345 831
boonshen 0:a35c40f49345 832 /*@} end of CMSIS_Core_FpuFunctions */
boonshen 0:a35c40f49345 833
boonshen 0:a35c40f49345 834
boonshen 0:a35c40f49345 835
boonshen 0:a35c40f49345 836 /* ################################## SysTick function ############################################ */
boonshen 0:a35c40f49345 837 /**
boonshen 0:a35c40f49345 838 \ingroup CMSIS_Core_FunctionInterface
boonshen 0:a35c40f49345 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
boonshen 0:a35c40f49345 840 \brief Functions that configure the System.
boonshen 0:a35c40f49345 841 @{
boonshen 0:a35c40f49345 842 */
boonshen 0:a35c40f49345 843
boonshen 0:a35c40f49345 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
boonshen 0:a35c40f49345 845
boonshen 0:a35c40f49345 846 /**
boonshen 0:a35c40f49345 847 \brief System Tick Configuration
boonshen 0:a35c40f49345 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
boonshen 0:a35c40f49345 849 Counter is in free running mode to generate periodic interrupts.
boonshen 0:a35c40f49345 850 \param [in] ticks Number of ticks between two interrupts.
boonshen 0:a35c40f49345 851 \return 0 Function succeeded.
boonshen 0:a35c40f49345 852 \return 1 Function failed.
boonshen 0:a35c40f49345 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
boonshen 0:a35c40f49345 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
boonshen 0:a35c40f49345 855 must contain a vendor-specific implementation of this function.
boonshen 0:a35c40f49345 856 */
boonshen 0:a35c40f49345 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
boonshen 0:a35c40f49345 858 {
boonshen 0:a35c40f49345 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
boonshen 0:a35c40f49345 860 {
boonshen 0:a35c40f49345 861 return (1UL); /* Reload value impossible */
boonshen 0:a35c40f49345 862 }
boonshen 0:a35c40f49345 863
boonshen 0:a35c40f49345 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
boonshen 0:a35c40f49345 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
boonshen 0:a35c40f49345 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
boonshen 0:a35c40f49345 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
boonshen 0:a35c40f49345 868 SysTick_CTRL_TICKINT_Msk |
boonshen 0:a35c40f49345 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
boonshen 0:a35c40f49345 870 return (0UL); /* Function successful */
boonshen 0:a35c40f49345 871 }
boonshen 0:a35c40f49345 872
boonshen 0:a35c40f49345 873 #endif
boonshen 0:a35c40f49345 874
boonshen 0:a35c40f49345 875 /*@} end of CMSIS_Core_SysTickFunctions */
boonshen 0:a35c40f49345 876
boonshen 0:a35c40f49345 877
boonshen 0:a35c40f49345 878
boonshen 0:a35c40f49345 879
boonshen 0:a35c40f49345 880 #ifdef __cplusplus
boonshen 0:a35c40f49345 881 }
boonshen 0:a35c40f49345 882 #endif
boonshen 0:a35c40f49345 883
boonshen 0:a35c40f49345 884 #endif /* __CORE_CM0_H_DEPENDANT */
boonshen 0:a35c40f49345 885
boonshen 0:a35c40f49345 886 #endif /* __CMSIS_GENERIC */