FTHR_USB_serial_qSPI - max32630fthr quad spi , unexpected spi behavior

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max32630fthr quad spi , unexpected spi behavior

FTHR_USB_serial/mbed-os/cmsis/core_armv8mml.h@0:a35c40f49345, 2018-03-13 (annotated)

Committer:: boonshen
Date:: Tue Mar 13 21:12:00 2018 +0000
Revision:: 0:a35c40f49345

MAX32630FTHR QuadSPI test

Who changed what in which revision?

User	Revision	Line number	New contents of line
boonshen	0:a35c40f49345	1	/************************************************************************//
boonshen	0:a35c40f49345	2	* @file core_armv8mml.h
boonshen	0:a35c40f49345	3	* @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
boonshen	0:a35c40f49345	4	* @version V5.0.2
boonshen	0:a35c40f49345	5	* @date 13. February 2017
boonshen	0:a35c40f49345	6	******************************************************************************/
boonshen	0:a35c40f49345	7	/*
boonshen	0:a35c40f49345	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
boonshen	0:a35c40f49345	9	*
boonshen	0:a35c40f49345	10	* SPDX-License-Identifier: Apache-2.0
boonshen	0:a35c40f49345	11	*
boonshen	0:a35c40f49345	12	* Licensed under the Apache License, Version 2.0 (the License); you may
boonshen	0:a35c40f49345	13	* not use this file except in compliance with the License.
boonshen	0:a35c40f49345	14	* You may obtain a copy of the License at
boonshen	0:a35c40f49345	15	*
boonshen	0:a35c40f49345	16	* www.apache.org/licenses/LICENSE-2.0
boonshen	0:a35c40f49345	17	*
boonshen	0:a35c40f49345	18	* Unless required by applicable law or agreed to in writing, software
boonshen	0:a35c40f49345	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
boonshen	0:a35c40f49345	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
boonshen	0:a35c40f49345	21	* See the License for the specific language governing permissions and
boonshen	0:a35c40f49345	22	* limitations under the License.
boonshen	0:a35c40f49345	23	*/
boonshen	0:a35c40f49345	24
boonshen	0:a35c40f49345	25	#if defined ( __ICCARM__ )
boonshen	0:a35c40f49345	26	#pragma system_include /* treat file as system include file for MISRA check */
boonshen	0:a35c40f49345	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen	0:a35c40f49345	28	#pragma clang system_header /* treat file as system include file */
boonshen	0:a35c40f49345	29	#endif
boonshen	0:a35c40f49345	30
boonshen	0:a35c40f49345	31	#ifndef __CORE_ARMV8MML_H_GENERIC
boonshen	0:a35c40f49345	32	#define __CORE_ARMV8MML_H_GENERIC
boonshen	0:a35c40f49345	33
boonshen	0:a35c40f49345	34	#include <stdint.h>
boonshen	0:a35c40f49345	35
boonshen	0:a35c40f49345	36	#ifdef __cplusplus
boonshen	0:a35c40f49345	37	extern "C" {
boonshen	0:a35c40f49345	38	#endif
boonshen	0:a35c40f49345	39
boonshen	0:a35c40f49345	40	/**
boonshen	0:a35c40f49345	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
boonshen	0:a35c40f49345	42	CMSIS violates the following MISRA-C:2004 rules:
boonshen	0:a35c40f49345	43
boonshen	0:a35c40f49345	44	\li Required Rule 8.5, object/function definition in header file.<br>
boonshen	0:a35c40f49345	45	Function definitions in header files are used to allow 'inlining'.
boonshen	0:a35c40f49345	46
boonshen	0:a35c40f49345	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
boonshen	0:a35c40f49345	48	Unions are used for effective representation of core registers.
boonshen	0:a35c40f49345	49
boonshen	0:a35c40f49345	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
boonshen	0:a35c40f49345	51	Function-like macros are used to allow more efficient code.
boonshen	0:a35c40f49345	52	*/
boonshen	0:a35c40f49345	53
boonshen	0:a35c40f49345	54
boonshen	0:a35c40f49345	55	/*******************************************************************************
boonshen	0:a35c40f49345	56	* CMSIS definitions
boonshen	0:a35c40f49345	57	******************************************************************************/
boonshen	0:a35c40f49345	58	/**
boonshen	0:a35c40f49345	59	\ingroup Cortex_ARMv8MML
boonshen	0:a35c40f49345	60	@{
boonshen	0:a35c40f49345	61	*/
boonshen	0:a35c40f49345	62
boonshen	0:a35c40f49345	63	/* CMSIS ARMv8MML definitions */
boonshen	0:a35c40f49345	64	#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
boonshen	0:a35c40f49345	65	#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
boonshen	0:a35c40f49345	66	#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) \| \
boonshen	0:a35c40f49345	67	__ARMv8MML_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
boonshen	0:a35c40f49345	68
boonshen	0:a35c40f49345	69	#define __CORTEX_M (81U) /!< Cortex-M Core /
boonshen	0:a35c40f49345	70
boonshen	0:a35c40f49345	71	/** __FPU_USED indicates whether an FPU is used or not.
boonshen	0:a35c40f49345	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
boonshen	0:a35c40f49345	73	*/
boonshen	0:a35c40f49345	74	#if defined ( __CC_ARM )
boonshen	0:a35c40f49345	75	#if defined __TARGET_FPU_VFP
boonshen	0:a35c40f49345	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen	0:a35c40f49345	77	#define __FPU_USED 1U
boonshen	0:a35c40f49345	78	#else
boonshen	0:a35c40f49345	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen	0:a35c40f49345	80	#define __FPU_USED 0U
boonshen	0:a35c40f49345	81	#endif
boonshen	0:a35c40f49345	82	#else
boonshen	0:a35c40f49345	83	#define __FPU_USED 0U
boonshen	0:a35c40f49345	84	#endif
boonshen	0:a35c40f49345	85
boonshen	0:a35c40f49345	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
boonshen	0:a35c40f49345	87	#if defined __ARM_PCS_VFP
boonshen	0:a35c40f49345	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen	0:a35c40f49345	89	#define __FPU_USED 1U
boonshen	0:a35c40f49345	90	#else
boonshen	0:a35c40f49345	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen	0:a35c40f49345	92	#define __FPU_USED 0U
boonshen	0:a35c40f49345	93	#endif
boonshen	0:a35c40f49345	94	#else
boonshen	0:a35c40f49345	95	#define __FPU_USED 0U
boonshen	0:a35c40f49345	96	#endif
boonshen	0:a35c40f49345	97
boonshen	0:a35c40f49345	98	#elif defined ( __GNUC__ )
boonshen	0:a35c40f49345	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
boonshen	0:a35c40f49345	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen	0:a35c40f49345	101	#define __FPU_USED 1U
boonshen	0:a35c40f49345	102	#else
boonshen	0:a35c40f49345	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen	0:a35c40f49345	104	#define __FPU_USED 0U
boonshen	0:a35c40f49345	105	#endif
boonshen	0:a35c40f49345	106	#else
boonshen	0:a35c40f49345	107	#define __FPU_USED 0U
boonshen	0:a35c40f49345	108	#endif
boonshen	0:a35c40f49345	109
boonshen	0:a35c40f49345	110	#elif defined ( __ICCARM__ )
boonshen	0:a35c40f49345	111	#if defined __ARMVFP__
boonshen	0:a35c40f49345	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen	0:a35c40f49345	113	#define __FPU_USED 1U
boonshen	0:a35c40f49345	114	#else
boonshen	0:a35c40f49345	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen	0:a35c40f49345	116	#define __FPU_USED 0U
boonshen	0:a35c40f49345	117	#endif
boonshen	0:a35c40f49345	118	#else
boonshen	0:a35c40f49345	119	#define __FPU_USED 0U
boonshen	0:a35c40f49345	120	#endif
boonshen	0:a35c40f49345	121
boonshen	0:a35c40f49345	122	#elif defined ( __TI_ARM__ )
boonshen	0:a35c40f49345	123	#if defined __TI_VFP_SUPPORT__
boonshen	0:a35c40f49345	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen	0:a35c40f49345	125	#define __FPU_USED 1U
boonshen	0:a35c40f49345	126	#else
boonshen	0:a35c40f49345	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen	0:a35c40f49345	128	#define __FPU_USED 0U
boonshen	0:a35c40f49345	129	#endif
boonshen	0:a35c40f49345	130	#else
boonshen	0:a35c40f49345	131	#define __FPU_USED 0U
boonshen	0:a35c40f49345	132	#endif
boonshen	0:a35c40f49345	133
boonshen	0:a35c40f49345	134	#elif defined ( __TASKING__ )
boonshen	0:a35c40f49345	135	#if defined __FPU_VFP__
boonshen	0:a35c40f49345	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen	0:a35c40f49345	137	#define __FPU_USED 1U
boonshen	0:a35c40f49345	138	#else
boonshen	0:a35c40f49345	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen	0:a35c40f49345	140	#define __FPU_USED 0U
boonshen	0:a35c40f49345	141	#endif
boonshen	0:a35c40f49345	142	#else
boonshen	0:a35c40f49345	143	#define __FPU_USED 0U
boonshen	0:a35c40f49345	144	#endif
boonshen	0:a35c40f49345	145
boonshen	0:a35c40f49345	146	#elif defined ( __CSMC__ )
boonshen	0:a35c40f49345	147	#if ( __CSMC__ & 0x400U)
boonshen	0:a35c40f49345	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
boonshen	0:a35c40f49345	149	#define __FPU_USED 1U
boonshen	0:a35c40f49345	150	#else
boonshen	0:a35c40f49345	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
boonshen	0:a35c40f49345	152	#define __FPU_USED 0U
boonshen	0:a35c40f49345	153	#endif
boonshen	0:a35c40f49345	154	#else
boonshen	0:a35c40f49345	155	#define __FPU_USED 0U
boonshen	0:a35c40f49345	156	#endif
boonshen	0:a35c40f49345	157
boonshen	0:a35c40f49345	158	#endif
boonshen	0:a35c40f49345	159
boonshen	0:a35c40f49345	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
boonshen	0:a35c40f49345	161
boonshen	0:a35c40f49345	162
boonshen	0:a35c40f49345	163	#ifdef __cplusplus
boonshen	0:a35c40f49345	164	}
boonshen	0:a35c40f49345	165	#endif
boonshen	0:a35c40f49345	166
boonshen	0:a35c40f49345	167	#endif /* __CORE_ARMV8MML_H_GENERIC */
boonshen	0:a35c40f49345	168
boonshen	0:a35c40f49345	169	#ifndef __CMSIS_GENERIC
boonshen	0:a35c40f49345	170
boonshen	0:a35c40f49345	171	#ifndef __CORE_ARMV8MML_H_DEPENDANT
boonshen	0:a35c40f49345	172	#define __CORE_ARMV8MML_H_DEPENDANT
boonshen	0:a35c40f49345	173
boonshen	0:a35c40f49345	174	#ifdef __cplusplus
boonshen	0:a35c40f49345	175	extern "C" {
boonshen	0:a35c40f49345	176	#endif
boonshen	0:a35c40f49345	177
boonshen	0:a35c40f49345	178	/* check device defines and use defaults */
boonshen	0:a35c40f49345	179	#if defined __CHECK_DEVICE_DEFINES
boonshen	0:a35c40f49345	180	#ifndef __ARMv8MML_REV
boonshen	0:a35c40f49345	181	#define __ARMv8MML_REV 0x0000U
boonshen	0:a35c40f49345	182	#warning "__ARMv8MML_REV not defined in device header file; using default!"
boonshen	0:a35c40f49345	183	#endif
boonshen	0:a35c40f49345	184
boonshen	0:a35c40f49345	185	#ifndef __FPU_PRESENT
boonshen	0:a35c40f49345	186	#define __FPU_PRESENT 0U
boonshen	0:a35c40f49345	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
boonshen	0:a35c40f49345	188	#endif
boonshen	0:a35c40f49345	189
boonshen	0:a35c40f49345	190	#ifndef __MPU_PRESENT
boonshen	0:a35c40f49345	191	#define __MPU_PRESENT 0U
boonshen	0:a35c40f49345	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
boonshen	0:a35c40f49345	193	#endif
boonshen	0:a35c40f49345	194
boonshen	0:a35c40f49345	195	#ifndef __SAUREGION_PRESENT
boonshen	0:a35c40f49345	196	#define __SAUREGION_PRESENT 0U
boonshen	0:a35c40f49345	197	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
boonshen	0:a35c40f49345	198	#endif
boonshen	0:a35c40f49345	199
boonshen	0:a35c40f49345	200	#ifndef __DSP_PRESENT
boonshen	0:a35c40f49345	201	#define __DSP_PRESENT 0U
boonshen	0:a35c40f49345	202	#warning "__DSP_PRESENT not defined in device header file; using default!"
boonshen	0:a35c40f49345	203	#endif
boonshen	0:a35c40f49345	204
boonshen	0:a35c40f49345	205	#ifndef __NVIC_PRIO_BITS
boonshen	0:a35c40f49345	206	#define __NVIC_PRIO_BITS 3U
boonshen	0:a35c40f49345	207	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
boonshen	0:a35c40f49345	208	#endif
boonshen	0:a35c40f49345	209
boonshen	0:a35c40f49345	210	#ifndef __Vendor_SysTickConfig
boonshen	0:a35c40f49345	211	#define __Vendor_SysTickConfig 0U
boonshen	0:a35c40f49345	212	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
boonshen	0:a35c40f49345	213	#endif
boonshen	0:a35c40f49345	214	#endif
boonshen	0:a35c40f49345	215
boonshen	0:a35c40f49345	216	/* IO definitions (access restrictions to peripheral registers) */
boonshen	0:a35c40f49345	217	/**
boonshen	0:a35c40f49345	218	\defgroup CMSIS_glob_defs CMSIS Global Defines
boonshen	0:a35c40f49345	219
boonshen	0:a35c40f49345	220	<strong>IO Type Qualifiers</strong> are used
boonshen	0:a35c40f49345	221	\li to specify the access to peripheral variables.
boonshen	0:a35c40f49345	222	\li for automatic generation of peripheral register debug information.
boonshen	0:a35c40f49345	223	*/
boonshen	0:a35c40f49345	224	#ifdef __cplusplus
boonshen	0:a35c40f49345	225	#define __I volatile /!< Defines 'read only' permissions /
boonshen	0:a35c40f49345	226	#else
boonshen	0:a35c40f49345	227	#define __I volatile const /!< Defines 'read only' permissions /
boonshen	0:a35c40f49345	228	#endif
boonshen	0:a35c40f49345	229	#define __O volatile /!< Defines 'write only' permissions /
boonshen	0:a35c40f49345	230	#define __IO volatile /!< Defines 'read / write' permissions /
boonshen	0:a35c40f49345	231
boonshen	0:a35c40f49345	232	/* following defines should be used for structure members */
boonshen	0:a35c40f49345	233	#define __IM volatile const /! Defines 'read only' structure member permissions /
boonshen	0:a35c40f49345	234	#define __OM volatile /! Defines 'write only' structure member permissions /
boonshen	0:a35c40f49345	235	#define __IOM volatile /! Defines 'read / write' structure member permissions /
boonshen	0:a35c40f49345	236
boonshen	0:a35c40f49345	237	/@} end of group ARMv8MML /
boonshen	0:a35c40f49345	238
boonshen	0:a35c40f49345	239
boonshen	0:a35c40f49345	240
boonshen	0:a35c40f49345	241	/*******************************************************************************
boonshen	0:a35c40f49345	242	* Register Abstraction
boonshen	0:a35c40f49345	243	Core Register contain:
boonshen	0:a35c40f49345	244	- Core Register
boonshen	0:a35c40f49345	245	- Core NVIC Register
boonshen	0:a35c40f49345	246	- Core SCB Register
boonshen	0:a35c40f49345	247	- Core SysTick Register
boonshen	0:a35c40f49345	248	- Core Debug Register
boonshen	0:a35c40f49345	249	- Core MPU Register
boonshen	0:a35c40f49345	250	- Core SAU Register
boonshen	0:a35c40f49345	251	- Core FPU Register
boonshen	0:a35c40f49345	252	******************************************************************************/
boonshen	0:a35c40f49345	253	/**
boonshen	0:a35c40f49345	254	\defgroup CMSIS_core_register Defines and Type Definitions
boonshen	0:a35c40f49345	255	\brief Type definitions and defines for Cortex-M processor based devices.
boonshen	0:a35c40f49345	256	*/
boonshen	0:a35c40f49345	257
boonshen	0:a35c40f49345	258	/**
boonshen	0:a35c40f49345	259	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	260	\defgroup CMSIS_CORE Status and Control Registers
boonshen	0:a35c40f49345	261	\brief Core Register type definitions.
boonshen	0:a35c40f49345	262	@{
boonshen	0:a35c40f49345	263	*/
boonshen	0:a35c40f49345	264
boonshen	0:a35c40f49345	265	/**
boonshen	0:a35c40f49345	266	\brief Union type to access the Application Program Status Register (APSR).
boonshen	0:a35c40f49345	267	*/
boonshen	0:a35c40f49345	268	typedef union
boonshen	0:a35c40f49345	269	{
boonshen	0:a35c40f49345	270	struct
boonshen	0:a35c40f49345	271	{
boonshen	0:a35c40f49345	272	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
boonshen	0:a35c40f49345	273	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
boonshen	0:a35c40f49345	274	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
boonshen	0:a35c40f49345	275	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
boonshen	0:a35c40f49345	276	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
boonshen	0:a35c40f49345	277	uint32_t C:1; /!< bit: 29 Carry condition code flag /
boonshen	0:a35c40f49345	278	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
boonshen	0:a35c40f49345	279	uint32_t N:1; /!< bit: 31 Negative condition code flag /
boonshen	0:a35c40f49345	280	} b; /!< Structure used for bit access /
boonshen	0:a35c40f49345	281	uint32_t w; /!< Type used for word access /
boonshen	0:a35c40f49345	282	} APSR_Type;
boonshen	0:a35c40f49345	283
boonshen	0:a35c40f49345	284	/* APSR Register Definitions */
boonshen	0:a35c40f49345	285	#define APSR_N_Pos 31U /!< APSR: N Position /
boonshen	0:a35c40f49345	286	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
boonshen	0:a35c40f49345	287
boonshen	0:a35c40f49345	288	#define APSR_Z_Pos 30U /!< APSR: Z Position /
boonshen	0:a35c40f49345	289	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
boonshen	0:a35c40f49345	290
boonshen	0:a35c40f49345	291	#define APSR_C_Pos 29U /!< APSR: C Position /
boonshen	0:a35c40f49345	292	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
boonshen	0:a35c40f49345	293
boonshen	0:a35c40f49345	294	#define APSR_V_Pos 28U /!< APSR: V Position /
boonshen	0:a35c40f49345	295	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
boonshen	0:a35c40f49345	296
boonshen	0:a35c40f49345	297	#define APSR_Q_Pos 27U /!< APSR: Q Position /
boonshen	0:a35c40f49345	298	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
boonshen	0:a35c40f49345	299
boonshen	0:a35c40f49345	300	#define APSR_GE_Pos 16U /!< APSR: GE Position /
boonshen	0:a35c40f49345	301	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
boonshen	0:a35c40f49345	302
boonshen	0:a35c40f49345	303
boonshen	0:a35c40f49345	304	/**
boonshen	0:a35c40f49345	305	\brief Union type to access the Interrupt Program Status Register (IPSR).
boonshen	0:a35c40f49345	306	*/
boonshen	0:a35c40f49345	307	typedef union
boonshen	0:a35c40f49345	308	{
boonshen	0:a35c40f49345	309	struct
boonshen	0:a35c40f49345	310	{
boonshen	0:a35c40f49345	311	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
boonshen	0:a35c40f49345	312	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
boonshen	0:a35c40f49345	313	} b; /!< Structure used for bit access /
boonshen	0:a35c40f49345	314	uint32_t w; /!< Type used for word access /
boonshen	0:a35c40f49345	315	} IPSR_Type;
boonshen	0:a35c40f49345	316
boonshen	0:a35c40f49345	317	/* IPSR Register Definitions */
boonshen	0:a35c40f49345	318	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
boonshen	0:a35c40f49345	319	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
boonshen	0:a35c40f49345	320
boonshen	0:a35c40f49345	321
boonshen	0:a35c40f49345	322	/**
boonshen	0:a35c40f49345	323	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
boonshen	0:a35c40f49345	324	*/
boonshen	0:a35c40f49345	325	typedef union
boonshen	0:a35c40f49345	326	{
boonshen	0:a35c40f49345	327	struct
boonshen	0:a35c40f49345	328	{
boonshen	0:a35c40f49345	329	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
boonshen	0:a35c40f49345	330	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
boonshen	0:a35c40f49345	331	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
boonshen	0:a35c40f49345	332	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
boonshen	0:a35c40f49345	333	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
boonshen	0:a35c40f49345	334	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
boonshen	0:a35c40f49345	335	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
boonshen	0:a35c40f49345	336	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
boonshen	0:a35c40f49345	337	uint32_t C:1; /!< bit: 29 Carry condition code flag /
boonshen	0:a35c40f49345	338	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
boonshen	0:a35c40f49345	339	uint32_t N:1; /!< bit: 31 Negative condition code flag /
boonshen	0:a35c40f49345	340	} b; /!< Structure used for bit access /
boonshen	0:a35c40f49345	341	uint32_t w; /!< Type used for word access /
boonshen	0:a35c40f49345	342	} xPSR_Type;
boonshen	0:a35c40f49345	343
boonshen	0:a35c40f49345	344	/* xPSR Register Definitions */
boonshen	0:a35c40f49345	345	#define xPSR_N_Pos 31U /!< xPSR: N Position /
boonshen	0:a35c40f49345	346	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
boonshen	0:a35c40f49345	347
boonshen	0:a35c40f49345	348	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
boonshen	0:a35c40f49345	349	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
boonshen	0:a35c40f49345	350
boonshen	0:a35c40f49345	351	#define xPSR_C_Pos 29U /!< xPSR: C Position /
boonshen	0:a35c40f49345	352	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
boonshen	0:a35c40f49345	353
boonshen	0:a35c40f49345	354	#define xPSR_V_Pos 28U /!< xPSR: V Position /
boonshen	0:a35c40f49345	355	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
boonshen	0:a35c40f49345	356
boonshen	0:a35c40f49345	357	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
boonshen	0:a35c40f49345	358	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
boonshen	0:a35c40f49345	359
boonshen	0:a35c40f49345	360	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
boonshen	0:a35c40f49345	361	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
boonshen	0:a35c40f49345	362
boonshen	0:a35c40f49345	363	#define xPSR_T_Pos 24U /!< xPSR: T Position /
boonshen	0:a35c40f49345	364	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
boonshen	0:a35c40f49345	365
boonshen	0:a35c40f49345	366	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
boonshen	0:a35c40f49345	367	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
boonshen	0:a35c40f49345	368
boonshen	0:a35c40f49345	369	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
boonshen	0:a35c40f49345	370	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
boonshen	0:a35c40f49345	371
boonshen	0:a35c40f49345	372
boonshen	0:a35c40f49345	373	/**
boonshen	0:a35c40f49345	374	\brief Union type to access the Control Registers (CONTROL).
boonshen	0:a35c40f49345	375	*/
boonshen	0:a35c40f49345	376	typedef union
boonshen	0:a35c40f49345	377	{
boonshen	0:a35c40f49345	378	struct
boonshen	0:a35c40f49345	379	{
boonshen	0:a35c40f49345	380	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
boonshen	0:a35c40f49345	381	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
boonshen	0:a35c40f49345	382	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
boonshen	0:a35c40f49345	383	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
boonshen	0:a35c40f49345	384	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
boonshen	0:a35c40f49345	385	} b; /!< Structure used for bit access /
boonshen	0:a35c40f49345	386	uint32_t w; /!< Type used for word access /
boonshen	0:a35c40f49345	387	} CONTROL_Type;
boonshen	0:a35c40f49345	388
boonshen	0:a35c40f49345	389	/* CONTROL Register Definitions */
boonshen	0:a35c40f49345	390	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
boonshen	0:a35c40f49345	391	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
boonshen	0:a35c40f49345	392
boonshen	0:a35c40f49345	393	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
boonshen	0:a35c40f49345	394	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
boonshen	0:a35c40f49345	395
boonshen	0:a35c40f49345	396	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
boonshen	0:a35c40f49345	397	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
boonshen	0:a35c40f49345	398
boonshen	0:a35c40f49345	399	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
boonshen	0:a35c40f49345	400	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
boonshen	0:a35c40f49345	401
boonshen	0:a35c40f49345	402	/@} end of group CMSIS_CORE /
boonshen	0:a35c40f49345	403
boonshen	0:a35c40f49345	404
boonshen	0:a35c40f49345	405	/**
boonshen	0:a35c40f49345	406	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	407	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
boonshen	0:a35c40f49345	408	\brief Type definitions for the NVIC Registers
boonshen	0:a35c40f49345	409	@{
boonshen	0:a35c40f49345	410	*/
boonshen	0:a35c40f49345	411
boonshen	0:a35c40f49345	412	/**
boonshen	0:a35c40f49345	413	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
boonshen	0:a35c40f49345	414	*/
boonshen	0:a35c40f49345	415	typedef struct
boonshen	0:a35c40f49345	416	{
boonshen	0:a35c40f49345	417	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
boonshen	0:a35c40f49345	418	uint32_t RESERVED0[16U];
boonshen	0:a35c40f49345	419	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
boonshen	0:a35c40f49345	420	uint32_t RSERVED1[16U];
boonshen	0:a35c40f49345	421	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
boonshen	0:a35c40f49345	422	uint32_t RESERVED2[16U];
boonshen	0:a35c40f49345	423	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
boonshen	0:a35c40f49345	424	uint32_t RESERVED3[16U];
boonshen	0:a35c40f49345	425	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
boonshen	0:a35c40f49345	426	uint32_t RESERVED4[16U];
boonshen	0:a35c40f49345	427	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
boonshen	0:a35c40f49345	428	uint32_t RESERVED5[16U];
boonshen	0:a35c40f49345	429	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
boonshen	0:a35c40f49345	430	uint32_t RESERVED6[580U];
boonshen	0:a35c40f49345	431	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
boonshen	0:a35c40f49345	432	} NVIC_Type;
boonshen	0:a35c40f49345	433
boonshen	0:a35c40f49345	434	/* Software Triggered Interrupt Register Definitions */
boonshen	0:a35c40f49345	435	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
boonshen	0:a35c40f49345	436	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
boonshen	0:a35c40f49345	437
boonshen	0:a35c40f49345	438	/@} end of group CMSIS_NVIC /
boonshen	0:a35c40f49345	439
boonshen	0:a35c40f49345	440
boonshen	0:a35c40f49345	441	/**
boonshen	0:a35c40f49345	442	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	443	\defgroup CMSIS_SCB System Control Block (SCB)
boonshen	0:a35c40f49345	444	\brief Type definitions for the System Control Block Registers
boonshen	0:a35c40f49345	445	@{
boonshen	0:a35c40f49345	446	*/
boonshen	0:a35c40f49345	447
boonshen	0:a35c40f49345	448	/**
boonshen	0:a35c40f49345	449	\brief Structure type to access the System Control Block (SCB).
boonshen	0:a35c40f49345	450	*/
boonshen	0:a35c40f49345	451	typedef struct
boonshen	0:a35c40f49345	452	{
boonshen	0:a35c40f49345	453	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
boonshen	0:a35c40f49345	454	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
boonshen	0:a35c40f49345	455	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
boonshen	0:a35c40f49345	456	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
boonshen	0:a35c40f49345	457	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
boonshen	0:a35c40f49345	458	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
boonshen	0:a35c40f49345	459	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
boonshen	0:a35c40f49345	460	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
boonshen	0:a35c40f49345	461	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
boonshen	0:a35c40f49345	462	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
boonshen	0:a35c40f49345	463	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
boonshen	0:a35c40f49345	464	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
boonshen	0:a35c40f49345	465	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
boonshen	0:a35c40f49345	466	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
boonshen	0:a35c40f49345	467	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
boonshen	0:a35c40f49345	468	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
boonshen	0:a35c40f49345	469	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
boonshen	0:a35c40f49345	470	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
boonshen	0:a35c40f49345	471	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
boonshen	0:a35c40f49345	472	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
boonshen	0:a35c40f49345	473	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
boonshen	0:a35c40f49345	474	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
boonshen	0:a35c40f49345	475	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
boonshen	0:a35c40f49345	476	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
boonshen	0:a35c40f49345	477	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
boonshen	0:a35c40f49345	478	uint32_t RESERVED3[92U];
boonshen	0:a35c40f49345	479	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
boonshen	0:a35c40f49345	480	uint32_t RESERVED4[15U];
boonshen	0:a35c40f49345	481	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
boonshen	0:a35c40f49345	482	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
boonshen	0:a35c40f49345	483	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
boonshen	0:a35c40f49345	484	uint32_t RESERVED5[1U];
boonshen	0:a35c40f49345	485	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
boonshen	0:a35c40f49345	486	uint32_t RESERVED6[1U];
boonshen	0:a35c40f49345	487	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
boonshen	0:a35c40f49345	488	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
boonshen	0:a35c40f49345	489	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
boonshen	0:a35c40f49345	490	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
boonshen	0:a35c40f49345	491	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
boonshen	0:a35c40f49345	492	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
boonshen	0:a35c40f49345	493	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
boonshen	0:a35c40f49345	494	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
boonshen	0:a35c40f49345	495	uint32_t RESERVED7[6U];
boonshen	0:a35c40f49345	496	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
boonshen	0:a35c40f49345	497	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
boonshen	0:a35c40f49345	498	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
boonshen	0:a35c40f49345	499	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
boonshen	0:a35c40f49345	500	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
boonshen	0:a35c40f49345	501	uint32_t RESERVED8[1U];
boonshen	0:a35c40f49345	502	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
boonshen	0:a35c40f49345	503	} SCB_Type;
boonshen	0:a35c40f49345	504
boonshen	0:a35c40f49345	505	/* SCB CPUID Register Definitions */
boonshen	0:a35c40f49345	506	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
boonshen	0:a35c40f49345	507	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
boonshen	0:a35c40f49345	508
boonshen	0:a35c40f49345	509	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
boonshen	0:a35c40f49345	510	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
boonshen	0:a35c40f49345	511
boonshen	0:a35c40f49345	512	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
boonshen	0:a35c40f49345	513	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
boonshen	0:a35c40f49345	514
boonshen	0:a35c40f49345	515	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
boonshen	0:a35c40f49345	516	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
boonshen	0:a35c40f49345	517
boonshen	0:a35c40f49345	518	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
boonshen	0:a35c40f49345	519	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
boonshen	0:a35c40f49345	520
boonshen	0:a35c40f49345	521	/* SCB Interrupt Control State Register Definitions */
boonshen	0:a35c40f49345	522	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
boonshen	0:a35c40f49345	523	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
boonshen	0:a35c40f49345	524
boonshen	0:a35c40f49345	525	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
boonshen	0:a35c40f49345	526	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
boonshen	0:a35c40f49345	527
boonshen	0:a35c40f49345	528	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
boonshen	0:a35c40f49345	529	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
boonshen	0:a35c40f49345	530
boonshen	0:a35c40f49345	531	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
boonshen	0:a35c40f49345	532	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
boonshen	0:a35c40f49345	533
boonshen	0:a35c40f49345	534	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
boonshen	0:a35c40f49345	535	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
boonshen	0:a35c40f49345	536
boonshen	0:a35c40f49345	537	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
boonshen	0:a35c40f49345	538	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
boonshen	0:a35c40f49345	539
boonshen	0:a35c40f49345	540	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
boonshen	0:a35c40f49345	541	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
boonshen	0:a35c40f49345	542
boonshen	0:a35c40f49345	543	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
boonshen	0:a35c40f49345	544	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
boonshen	0:a35c40f49345	545
boonshen	0:a35c40f49345	546	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
boonshen	0:a35c40f49345	547	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
boonshen	0:a35c40f49345	548
boonshen	0:a35c40f49345	549	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
boonshen	0:a35c40f49345	550	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
boonshen	0:a35c40f49345	551
boonshen	0:a35c40f49345	552	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
boonshen	0:a35c40f49345	553	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
boonshen	0:a35c40f49345	554
boonshen	0:a35c40f49345	555	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
boonshen	0:a35c40f49345	556	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
boonshen	0:a35c40f49345	557
boonshen	0:a35c40f49345	558	/* SCB Vector Table Offset Register Definitions */
boonshen	0:a35c40f49345	559	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
boonshen	0:a35c40f49345	560	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
boonshen	0:a35c40f49345	561
boonshen	0:a35c40f49345	562	/* SCB Application Interrupt and Reset Control Register Definitions */
boonshen	0:a35c40f49345	563	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
boonshen	0:a35c40f49345	564	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
boonshen	0:a35c40f49345	565
boonshen	0:a35c40f49345	566	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
boonshen	0:a35c40f49345	567	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
boonshen	0:a35c40f49345	568
boonshen	0:a35c40f49345	569	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
boonshen	0:a35c40f49345	570	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
boonshen	0:a35c40f49345	571
boonshen	0:a35c40f49345	572	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
boonshen	0:a35c40f49345	573	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
boonshen	0:a35c40f49345	574
boonshen	0:a35c40f49345	575	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
boonshen	0:a35c40f49345	576	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
boonshen	0:a35c40f49345	577
boonshen	0:a35c40f49345	578	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
boonshen	0:a35c40f49345	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
boonshen	0:a35c40f49345	580
boonshen	0:a35c40f49345	581	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
boonshen	0:a35c40f49345	582	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
boonshen	0:a35c40f49345	583
boonshen	0:a35c40f49345	584	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
boonshen	0:a35c40f49345	585	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
boonshen	0:a35c40f49345	586
boonshen	0:a35c40f49345	587	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
boonshen	0:a35c40f49345	588	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
boonshen	0:a35c40f49345	589
boonshen	0:a35c40f49345	590	/* SCB System Control Register Definitions */
boonshen	0:a35c40f49345	591	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
boonshen	0:a35c40f49345	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
boonshen	0:a35c40f49345	593
boonshen	0:a35c40f49345	594	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
boonshen	0:a35c40f49345	595	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
boonshen	0:a35c40f49345	596
boonshen	0:a35c40f49345	597	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
boonshen	0:a35c40f49345	598	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
boonshen	0:a35c40f49345	599
boonshen	0:a35c40f49345	600	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
boonshen	0:a35c40f49345	601	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
boonshen	0:a35c40f49345	602
boonshen	0:a35c40f49345	603	/* SCB Configuration Control Register Definitions */
boonshen	0:a35c40f49345	604	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
boonshen	0:a35c40f49345	605	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
boonshen	0:a35c40f49345	606
boonshen	0:a35c40f49345	607	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
boonshen	0:a35c40f49345	608	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
boonshen	0:a35c40f49345	609
boonshen	0:a35c40f49345	610	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
boonshen	0:a35c40f49345	611	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
boonshen	0:a35c40f49345	612
boonshen	0:a35c40f49345	613	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
boonshen	0:a35c40f49345	614	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
boonshen	0:a35c40f49345	615
boonshen	0:a35c40f49345	616	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
boonshen	0:a35c40f49345	617	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
boonshen	0:a35c40f49345	618
boonshen	0:a35c40f49345	619	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
boonshen	0:a35c40f49345	620	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
boonshen	0:a35c40f49345	621
boonshen	0:a35c40f49345	622	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
boonshen	0:a35c40f49345	623	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
boonshen	0:a35c40f49345	624
boonshen	0:a35c40f49345	625	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
boonshen	0:a35c40f49345	626	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
boonshen	0:a35c40f49345	627
boonshen	0:a35c40f49345	628	/* SCB System Handler Control and State Register Definitions */
boonshen	0:a35c40f49345	629	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
boonshen	0:a35c40f49345	630	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
boonshen	0:a35c40f49345	631
boonshen	0:a35c40f49345	632	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
boonshen	0:a35c40f49345	633	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
boonshen	0:a35c40f49345	634
boonshen	0:a35c40f49345	635	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
boonshen	0:a35c40f49345	636	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
boonshen	0:a35c40f49345	637
boonshen	0:a35c40f49345	638	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
boonshen	0:a35c40f49345	639	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
boonshen	0:a35c40f49345	640
boonshen	0:a35c40f49345	641	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
boonshen	0:a35c40f49345	642	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
boonshen	0:a35c40f49345	643
boonshen	0:a35c40f49345	644	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
boonshen	0:a35c40f49345	645	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
boonshen	0:a35c40f49345	646
boonshen	0:a35c40f49345	647	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
boonshen	0:a35c40f49345	648	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
boonshen	0:a35c40f49345	649
boonshen	0:a35c40f49345	650	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
boonshen	0:a35c40f49345	651	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
boonshen	0:a35c40f49345	652
boonshen	0:a35c40f49345	653	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
boonshen	0:a35c40f49345	654	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
boonshen	0:a35c40f49345	655
boonshen	0:a35c40f49345	656	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
boonshen	0:a35c40f49345	657	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
boonshen	0:a35c40f49345	658
boonshen	0:a35c40f49345	659	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
boonshen	0:a35c40f49345	660	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
boonshen	0:a35c40f49345	661
boonshen	0:a35c40f49345	662	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
boonshen	0:a35c40f49345	663	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
boonshen	0:a35c40f49345	664
boonshen	0:a35c40f49345	665	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
boonshen	0:a35c40f49345	666	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
boonshen	0:a35c40f49345	667
boonshen	0:a35c40f49345	668	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
boonshen	0:a35c40f49345	669	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
boonshen	0:a35c40f49345	670
boonshen	0:a35c40f49345	671	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
boonshen	0:a35c40f49345	672	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
boonshen	0:a35c40f49345	673
boonshen	0:a35c40f49345	674	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
boonshen	0:a35c40f49345	675	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
boonshen	0:a35c40f49345	676
boonshen	0:a35c40f49345	677	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
boonshen	0:a35c40f49345	678	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
boonshen	0:a35c40f49345	679
boonshen	0:a35c40f49345	680	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
boonshen	0:a35c40f49345	681	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
boonshen	0:a35c40f49345	682
boonshen	0:a35c40f49345	683	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
boonshen	0:a35c40f49345	684	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
boonshen	0:a35c40f49345	685
boonshen	0:a35c40f49345	686	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
boonshen	0:a35c40f49345	687	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
boonshen	0:a35c40f49345	688
boonshen	0:a35c40f49345	689	/* SCB Configurable Fault Status Register Definitions */
boonshen	0:a35c40f49345	690	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
boonshen	0:a35c40f49345	691	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
boonshen	0:a35c40f49345	692
boonshen	0:a35c40f49345	693	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
boonshen	0:a35c40f49345	694	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
boonshen	0:a35c40f49345	695
boonshen	0:a35c40f49345	696	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
boonshen	0:a35c40f49345	697	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
boonshen	0:a35c40f49345	698
boonshen	0:a35c40f49345	699	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
boonshen	0:a35c40f49345	700	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
boonshen	0:a35c40f49345	701	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
boonshen	0:a35c40f49345	702
boonshen	0:a35c40f49345	703	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
boonshen	0:a35c40f49345	704	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
boonshen	0:a35c40f49345	705
boonshen	0:a35c40f49345	706	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
boonshen	0:a35c40f49345	707	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
boonshen	0:a35c40f49345	708
boonshen	0:a35c40f49345	709	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
boonshen	0:a35c40f49345	710	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
boonshen	0:a35c40f49345	711
boonshen	0:a35c40f49345	712	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
boonshen	0:a35c40f49345	713	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
boonshen	0:a35c40f49345	714
boonshen	0:a35c40f49345	715	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
boonshen	0:a35c40f49345	716	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
boonshen	0:a35c40f49345	717
boonshen	0:a35c40f49345	718	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
boonshen	0:a35c40f49345	719	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
boonshen	0:a35c40f49345	720	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
boonshen	0:a35c40f49345	721
boonshen	0:a35c40f49345	722	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
boonshen	0:a35c40f49345	723	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
boonshen	0:a35c40f49345	724
boonshen	0:a35c40f49345	725	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
boonshen	0:a35c40f49345	726	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
boonshen	0:a35c40f49345	727
boonshen	0:a35c40f49345	728	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
boonshen	0:a35c40f49345	729	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
boonshen	0:a35c40f49345	730
boonshen	0:a35c40f49345	731	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
boonshen	0:a35c40f49345	732	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
boonshen	0:a35c40f49345	733
boonshen	0:a35c40f49345	734	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
boonshen	0:a35c40f49345	735	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
boonshen	0:a35c40f49345	736
boonshen	0:a35c40f49345	737	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
boonshen	0:a35c40f49345	738	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
boonshen	0:a35c40f49345	739
boonshen	0:a35c40f49345	740	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
boonshen	0:a35c40f49345	741	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
boonshen	0:a35c40f49345	742	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
boonshen	0:a35c40f49345	743
boonshen	0:a35c40f49345	744	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
boonshen	0:a35c40f49345	745	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
boonshen	0:a35c40f49345	746
boonshen	0:a35c40f49345	747	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
boonshen	0:a35c40f49345	748	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
boonshen	0:a35c40f49345	749
boonshen	0:a35c40f49345	750	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
boonshen	0:a35c40f49345	751	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
boonshen	0:a35c40f49345	752
boonshen	0:a35c40f49345	753	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
boonshen	0:a35c40f49345	754	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
boonshen	0:a35c40f49345	755
boonshen	0:a35c40f49345	756	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
boonshen	0:a35c40f49345	757	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
boonshen	0:a35c40f49345	758
boonshen	0:a35c40f49345	759	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
boonshen	0:a35c40f49345	760	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
boonshen	0:a35c40f49345	761
boonshen	0:a35c40f49345	762	/* SCB Hard Fault Status Register Definitions */
boonshen	0:a35c40f49345	763	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
boonshen	0:a35c40f49345	764	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
boonshen	0:a35c40f49345	765
boonshen	0:a35c40f49345	766	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
boonshen	0:a35c40f49345	767	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
boonshen	0:a35c40f49345	768
boonshen	0:a35c40f49345	769	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
boonshen	0:a35c40f49345	770	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
boonshen	0:a35c40f49345	771
boonshen	0:a35c40f49345	772	/* SCB Debug Fault Status Register Definitions */
boonshen	0:a35c40f49345	773	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
boonshen	0:a35c40f49345	774	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
boonshen	0:a35c40f49345	775
boonshen	0:a35c40f49345	776	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
boonshen	0:a35c40f49345	777	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
boonshen	0:a35c40f49345	778
boonshen	0:a35c40f49345	779	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
boonshen	0:a35c40f49345	780	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
boonshen	0:a35c40f49345	781
boonshen	0:a35c40f49345	782	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
boonshen	0:a35c40f49345	783	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
boonshen	0:a35c40f49345	784
boonshen	0:a35c40f49345	785	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
boonshen	0:a35c40f49345	786	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
boonshen	0:a35c40f49345	787
boonshen	0:a35c40f49345	788	/* SCB Non-Secure Access Control Register Definitions */
boonshen	0:a35c40f49345	789	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
boonshen	0:a35c40f49345	790	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
boonshen	0:a35c40f49345	791
boonshen	0:a35c40f49345	792	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
boonshen	0:a35c40f49345	793	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
boonshen	0:a35c40f49345	794
boonshen	0:a35c40f49345	795	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
boonshen	0:a35c40f49345	796	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
boonshen	0:a35c40f49345	797
boonshen	0:a35c40f49345	798	/* SCB Cache Level ID Register Definitions */
boonshen	0:a35c40f49345	799	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
boonshen	0:a35c40f49345	800	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
boonshen	0:a35c40f49345	801
boonshen	0:a35c40f49345	802	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
boonshen	0:a35c40f49345	803	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
boonshen	0:a35c40f49345	804
boonshen	0:a35c40f49345	805	/* SCB Cache Type Register Definitions */
boonshen	0:a35c40f49345	806	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
boonshen	0:a35c40f49345	807	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
boonshen	0:a35c40f49345	808
boonshen	0:a35c40f49345	809	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
boonshen	0:a35c40f49345	810	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
boonshen	0:a35c40f49345	811
boonshen	0:a35c40f49345	812	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
boonshen	0:a35c40f49345	813	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
boonshen	0:a35c40f49345	814
boonshen	0:a35c40f49345	815	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
boonshen	0:a35c40f49345	816	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
boonshen	0:a35c40f49345	817
boonshen	0:a35c40f49345	818	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
boonshen	0:a35c40f49345	819	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
boonshen	0:a35c40f49345	820
boonshen	0:a35c40f49345	821	/* SCB Cache Size ID Register Definitions */
boonshen	0:a35c40f49345	822	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
boonshen	0:a35c40f49345	823	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
boonshen	0:a35c40f49345	824
boonshen	0:a35c40f49345	825	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
boonshen	0:a35c40f49345	826	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
boonshen	0:a35c40f49345	827
boonshen	0:a35c40f49345	828	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
boonshen	0:a35c40f49345	829	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
boonshen	0:a35c40f49345	830
boonshen	0:a35c40f49345	831	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
boonshen	0:a35c40f49345	832	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
boonshen	0:a35c40f49345	833
boonshen	0:a35c40f49345	834	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
boonshen	0:a35c40f49345	835	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
boonshen	0:a35c40f49345	836
boonshen	0:a35c40f49345	837	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
boonshen	0:a35c40f49345	838	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
boonshen	0:a35c40f49345	839
boonshen	0:a35c40f49345	840	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
boonshen	0:a35c40f49345	841	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
boonshen	0:a35c40f49345	842
boonshen	0:a35c40f49345	843	/* SCB Cache Size Selection Register Definitions */
boonshen	0:a35c40f49345	844	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
boonshen	0:a35c40f49345	845	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
boonshen	0:a35c40f49345	846
boonshen	0:a35c40f49345	847	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
boonshen	0:a35c40f49345	848	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
boonshen	0:a35c40f49345	849
boonshen	0:a35c40f49345	850	/* SCB Software Triggered Interrupt Register Definitions */
boonshen	0:a35c40f49345	851	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
boonshen	0:a35c40f49345	852	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
boonshen	0:a35c40f49345	853
boonshen	0:a35c40f49345	854	/* SCB D-Cache Invalidate by Set-way Register Definitions */
boonshen	0:a35c40f49345	855	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
boonshen	0:a35c40f49345	856	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
boonshen	0:a35c40f49345	857
boonshen	0:a35c40f49345	858	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
boonshen	0:a35c40f49345	859	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
boonshen	0:a35c40f49345	860
boonshen	0:a35c40f49345	861	/* SCB D-Cache Clean by Set-way Register Definitions */
boonshen	0:a35c40f49345	862	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
boonshen	0:a35c40f49345	863	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
boonshen	0:a35c40f49345	864
boonshen	0:a35c40f49345	865	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
boonshen	0:a35c40f49345	866	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
boonshen	0:a35c40f49345	867
boonshen	0:a35c40f49345	868	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
boonshen	0:a35c40f49345	869	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
boonshen	0:a35c40f49345	870	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
boonshen	0:a35c40f49345	871
boonshen	0:a35c40f49345	872	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
boonshen	0:a35c40f49345	873	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
boonshen	0:a35c40f49345	874
boonshen	0:a35c40f49345	875	/* Instruction Tightly-Coupled Memory Control Register Definitions */
boonshen	0:a35c40f49345	876	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
boonshen	0:a35c40f49345	877	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
boonshen	0:a35c40f49345	878
boonshen	0:a35c40f49345	879	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
boonshen	0:a35c40f49345	880	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
boonshen	0:a35c40f49345	881
boonshen	0:a35c40f49345	882	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
boonshen	0:a35c40f49345	883	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
boonshen	0:a35c40f49345	884
boonshen	0:a35c40f49345	885	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
boonshen	0:a35c40f49345	886	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
boonshen	0:a35c40f49345	887
boonshen	0:a35c40f49345	888	/* Data Tightly-Coupled Memory Control Register Definitions */
boonshen	0:a35c40f49345	889	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
boonshen	0:a35c40f49345	890	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
boonshen	0:a35c40f49345	891
boonshen	0:a35c40f49345	892	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
boonshen	0:a35c40f49345	893	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
boonshen	0:a35c40f49345	894
boonshen	0:a35c40f49345	895	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
boonshen	0:a35c40f49345	896	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
boonshen	0:a35c40f49345	897
boonshen	0:a35c40f49345	898	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
boonshen	0:a35c40f49345	899	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
boonshen	0:a35c40f49345	900
boonshen	0:a35c40f49345	901	/* AHBP Control Register Definitions */
boonshen	0:a35c40f49345	902	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
boonshen	0:a35c40f49345	903	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
boonshen	0:a35c40f49345	904
boonshen	0:a35c40f49345	905	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
boonshen	0:a35c40f49345	906	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
boonshen	0:a35c40f49345	907
boonshen	0:a35c40f49345	908	/* L1 Cache Control Register Definitions */
boonshen	0:a35c40f49345	909	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
boonshen	0:a35c40f49345	910	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
boonshen	0:a35c40f49345	911
boonshen	0:a35c40f49345	912	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
boonshen	0:a35c40f49345	913	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
boonshen	0:a35c40f49345	914
boonshen	0:a35c40f49345	915	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
boonshen	0:a35c40f49345	916	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
boonshen	0:a35c40f49345	917
boonshen	0:a35c40f49345	918	/* AHBS Control Register Definitions */
boonshen	0:a35c40f49345	919	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
boonshen	0:a35c40f49345	920	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
boonshen	0:a35c40f49345	921
boonshen	0:a35c40f49345	922	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
boonshen	0:a35c40f49345	923	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
boonshen	0:a35c40f49345	924
boonshen	0:a35c40f49345	925	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
boonshen	0:a35c40f49345	926	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
boonshen	0:a35c40f49345	927
boonshen	0:a35c40f49345	928	/* Auxiliary Bus Fault Status Register Definitions */
boonshen	0:a35c40f49345	929	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
boonshen	0:a35c40f49345	930	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
boonshen	0:a35c40f49345	931
boonshen	0:a35c40f49345	932	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
boonshen	0:a35c40f49345	933	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
boonshen	0:a35c40f49345	934
boonshen	0:a35c40f49345	935	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
boonshen	0:a35c40f49345	936	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
boonshen	0:a35c40f49345	937
boonshen	0:a35c40f49345	938	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
boonshen	0:a35c40f49345	939	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
boonshen	0:a35c40f49345	940
boonshen	0:a35c40f49345	941	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
boonshen	0:a35c40f49345	942	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
boonshen	0:a35c40f49345	943
boonshen	0:a35c40f49345	944	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
boonshen	0:a35c40f49345	945	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
boonshen	0:a35c40f49345	946
boonshen	0:a35c40f49345	947	/@} end of group CMSIS_SCB /
boonshen	0:a35c40f49345	948
boonshen	0:a35c40f49345	949
boonshen	0:a35c40f49345	950	/**
boonshen	0:a35c40f49345	951	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	952	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
boonshen	0:a35c40f49345	953	\brief Type definitions for the System Control and ID Register not in the SCB
boonshen	0:a35c40f49345	954	@{
boonshen	0:a35c40f49345	955	*/
boonshen	0:a35c40f49345	956
boonshen	0:a35c40f49345	957	/**
boonshen	0:a35c40f49345	958	\brief Structure type to access the System Control and ID Register not in the SCB.
boonshen	0:a35c40f49345	959	*/
boonshen	0:a35c40f49345	960	typedef struct
boonshen	0:a35c40f49345	961	{
boonshen	0:a35c40f49345	962	uint32_t RESERVED0[1U];
boonshen	0:a35c40f49345	963	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
boonshen	0:a35c40f49345	964	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
boonshen	0:a35c40f49345	965	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
boonshen	0:a35c40f49345	966	} SCnSCB_Type;
boonshen	0:a35c40f49345	967
boonshen	0:a35c40f49345	968	/* Interrupt Controller Type Register Definitions */
boonshen	0:a35c40f49345	969	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
boonshen	0:a35c40f49345	970	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
boonshen	0:a35c40f49345	971
boonshen	0:a35c40f49345	972	/@} end of group CMSIS_SCnotSCB /
boonshen	0:a35c40f49345	973
boonshen	0:a35c40f49345	974
boonshen	0:a35c40f49345	975	/**
boonshen	0:a35c40f49345	976	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	977	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
boonshen	0:a35c40f49345	978	\brief Type definitions for the System Timer Registers.
boonshen	0:a35c40f49345	979	@{
boonshen	0:a35c40f49345	980	*/
boonshen	0:a35c40f49345	981
boonshen	0:a35c40f49345	982	/**
boonshen	0:a35c40f49345	983	\brief Structure type to access the System Timer (SysTick).
boonshen	0:a35c40f49345	984	*/
boonshen	0:a35c40f49345	985	typedef struct
boonshen	0:a35c40f49345	986	{
boonshen	0:a35c40f49345	987	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
boonshen	0:a35c40f49345	988	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
boonshen	0:a35c40f49345	989	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
boonshen	0:a35c40f49345	990	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
boonshen	0:a35c40f49345	991	} SysTick_Type;
boonshen	0:a35c40f49345	992
boonshen	0:a35c40f49345	993	/* SysTick Control / Status Register Definitions */
boonshen	0:a35c40f49345	994	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
boonshen	0:a35c40f49345	995	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
boonshen	0:a35c40f49345	996
boonshen	0:a35c40f49345	997	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
boonshen	0:a35c40f49345	998	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
boonshen	0:a35c40f49345	999
boonshen	0:a35c40f49345	1000	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
boonshen	0:a35c40f49345	1001	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
boonshen	0:a35c40f49345	1002
boonshen	0:a35c40f49345	1003	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
boonshen	0:a35c40f49345	1004	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
boonshen	0:a35c40f49345	1005
boonshen	0:a35c40f49345	1006	/* SysTick Reload Register Definitions */
boonshen	0:a35c40f49345	1007	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
boonshen	0:a35c40f49345	1008	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
boonshen	0:a35c40f49345	1009
boonshen	0:a35c40f49345	1010	/* SysTick Current Register Definitions */
boonshen	0:a35c40f49345	1011	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
boonshen	0:a35c40f49345	1012	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
boonshen	0:a35c40f49345	1013
boonshen	0:a35c40f49345	1014	/* SysTick Calibration Register Definitions */
boonshen	0:a35c40f49345	1015	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
boonshen	0:a35c40f49345	1016	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
boonshen	0:a35c40f49345	1017
boonshen	0:a35c40f49345	1018	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
boonshen	0:a35c40f49345	1019	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
boonshen	0:a35c40f49345	1020
boonshen	0:a35c40f49345	1021	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
boonshen	0:a35c40f49345	1022	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
boonshen	0:a35c40f49345	1023
boonshen	0:a35c40f49345	1024	/@} end of group CMSIS_SysTick /
boonshen	0:a35c40f49345	1025
boonshen	0:a35c40f49345	1026
boonshen	0:a35c40f49345	1027	/**
boonshen	0:a35c40f49345	1028	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1029	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
boonshen	0:a35c40f49345	1030	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
boonshen	0:a35c40f49345	1031	@{
boonshen	0:a35c40f49345	1032	*/
boonshen	0:a35c40f49345	1033
boonshen	0:a35c40f49345	1034	/**
boonshen	0:a35c40f49345	1035	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
boonshen	0:a35c40f49345	1036	*/
boonshen	0:a35c40f49345	1037	typedef struct
boonshen	0:a35c40f49345	1038	{
boonshen	0:a35c40f49345	1039	__OM union
boonshen	0:a35c40f49345	1040	{
boonshen	0:a35c40f49345	1041	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
boonshen	0:a35c40f49345	1042	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
boonshen	0:a35c40f49345	1043	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
boonshen	0:a35c40f49345	1044	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
boonshen	0:a35c40f49345	1045	uint32_t RESERVED0[864U];
boonshen	0:a35c40f49345	1046	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
boonshen	0:a35c40f49345	1047	uint32_t RESERVED1[15U];
boonshen	0:a35c40f49345	1048	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
boonshen	0:a35c40f49345	1049	uint32_t RESERVED2[15U];
boonshen	0:a35c40f49345	1050	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
boonshen	0:a35c40f49345	1051	uint32_t RESERVED3[29U];
boonshen	0:a35c40f49345	1052	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
boonshen	0:a35c40f49345	1053	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
boonshen	0:a35c40f49345	1054	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
boonshen	0:a35c40f49345	1055	uint32_t RESERVED4[43U];
boonshen	0:a35c40f49345	1056	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
boonshen	0:a35c40f49345	1057	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
boonshen	0:a35c40f49345	1058	uint32_t RESERVED5[1U];
boonshen	0:a35c40f49345	1059	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
boonshen	0:a35c40f49345	1060	uint32_t RESERVED6[4U];
boonshen	0:a35c40f49345	1061	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
boonshen	0:a35c40f49345	1062	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
boonshen	0:a35c40f49345	1063	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
boonshen	0:a35c40f49345	1064	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
boonshen	0:a35c40f49345	1065	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
boonshen	0:a35c40f49345	1066	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
boonshen	0:a35c40f49345	1067	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
boonshen	0:a35c40f49345	1068	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
boonshen	0:a35c40f49345	1069	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
boonshen	0:a35c40f49345	1070	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
boonshen	0:a35c40f49345	1071	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
boonshen	0:a35c40f49345	1072	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
boonshen	0:a35c40f49345	1073	} ITM_Type;
boonshen	0:a35c40f49345	1074
boonshen	0:a35c40f49345	1075	/* ITM Stimulus Port Register Definitions */
boonshen	0:a35c40f49345	1076	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
boonshen	0:a35c40f49345	1077	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
boonshen	0:a35c40f49345	1078
boonshen	0:a35c40f49345	1079	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
boonshen	0:a35c40f49345	1080	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
boonshen	0:a35c40f49345	1081
boonshen	0:a35c40f49345	1082	/* ITM Trace Privilege Register Definitions */
boonshen	0:a35c40f49345	1083	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
boonshen	0:a35c40f49345	1084	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
boonshen	0:a35c40f49345	1085
boonshen	0:a35c40f49345	1086	/* ITM Trace Control Register Definitions */
boonshen	0:a35c40f49345	1087	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
boonshen	0:a35c40f49345	1088	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
boonshen	0:a35c40f49345	1089
boonshen	0:a35c40f49345	1090	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
boonshen	0:a35c40f49345	1091	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
boonshen	0:a35c40f49345	1092
boonshen	0:a35c40f49345	1093	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
boonshen	0:a35c40f49345	1094	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
boonshen	0:a35c40f49345	1095
boonshen	0:a35c40f49345	1096	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
boonshen	0:a35c40f49345	1097	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
boonshen	0:a35c40f49345	1098
boonshen	0:a35c40f49345	1099	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
boonshen	0:a35c40f49345	1100	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
boonshen	0:a35c40f49345	1101
boonshen	0:a35c40f49345	1102	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
boonshen	0:a35c40f49345	1103	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
boonshen	0:a35c40f49345	1104
boonshen	0:a35c40f49345	1105	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
boonshen	0:a35c40f49345	1106	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
boonshen	0:a35c40f49345	1107
boonshen	0:a35c40f49345	1108	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
boonshen	0:a35c40f49345	1109	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
boonshen	0:a35c40f49345	1110
boonshen	0:a35c40f49345	1111	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
boonshen	0:a35c40f49345	1112	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
boonshen	0:a35c40f49345	1113
boonshen	0:a35c40f49345	1114	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
boonshen	0:a35c40f49345	1115	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
boonshen	0:a35c40f49345	1116
boonshen	0:a35c40f49345	1117	/* ITM Integration Write Register Definitions */
boonshen	0:a35c40f49345	1118	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
boonshen	0:a35c40f49345	1119	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
boonshen	0:a35c40f49345	1120
boonshen	0:a35c40f49345	1121	/* ITM Integration Read Register Definitions */
boonshen	0:a35c40f49345	1122	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
boonshen	0:a35c40f49345	1123	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
boonshen	0:a35c40f49345	1124
boonshen	0:a35c40f49345	1125	/* ITM Integration Mode Control Register Definitions */
boonshen	0:a35c40f49345	1126	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
boonshen	0:a35c40f49345	1127	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
boonshen	0:a35c40f49345	1128
boonshen	0:a35c40f49345	1129	/* ITM Lock Status Register Definitions */
boonshen	0:a35c40f49345	1130	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
boonshen	0:a35c40f49345	1131	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
boonshen	0:a35c40f49345	1132
boonshen	0:a35c40f49345	1133	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
boonshen	0:a35c40f49345	1134	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
boonshen	0:a35c40f49345	1135
boonshen	0:a35c40f49345	1136	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
boonshen	0:a35c40f49345	1137	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
boonshen	0:a35c40f49345	1138
boonshen	0:a35c40f49345	1139	/@}/ /* end of group CMSIS_ITM */
boonshen	0:a35c40f49345	1140
boonshen	0:a35c40f49345	1141
boonshen	0:a35c40f49345	1142	/**
boonshen	0:a35c40f49345	1143	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1144	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
boonshen	0:a35c40f49345	1145	\brief Type definitions for the Data Watchpoint and Trace (DWT)
boonshen	0:a35c40f49345	1146	@{
boonshen	0:a35c40f49345	1147	*/
boonshen	0:a35c40f49345	1148
boonshen	0:a35c40f49345	1149	/**
boonshen	0:a35c40f49345	1150	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
boonshen	0:a35c40f49345	1151	*/
boonshen	0:a35c40f49345	1152	typedef struct
boonshen	0:a35c40f49345	1153	{
boonshen	0:a35c40f49345	1154	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
boonshen	0:a35c40f49345	1155	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
boonshen	0:a35c40f49345	1156	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
boonshen	0:a35c40f49345	1157	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
boonshen	0:a35c40f49345	1158	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
boonshen	0:a35c40f49345	1159	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
boonshen	0:a35c40f49345	1160	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
boonshen	0:a35c40f49345	1161	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
boonshen	0:a35c40f49345	1162	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
boonshen	0:a35c40f49345	1163	uint32_t RESERVED1[1U];
boonshen	0:a35c40f49345	1164	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
boonshen	0:a35c40f49345	1165	uint32_t RESERVED2[1U];
boonshen	0:a35c40f49345	1166	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
boonshen	0:a35c40f49345	1167	uint32_t RESERVED3[1U];
boonshen	0:a35c40f49345	1168	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
boonshen	0:a35c40f49345	1169	uint32_t RESERVED4[1U];
boonshen	0:a35c40f49345	1170	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
boonshen	0:a35c40f49345	1171	uint32_t RESERVED5[1U];
boonshen	0:a35c40f49345	1172	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
boonshen	0:a35c40f49345	1173	uint32_t RESERVED6[1U];
boonshen	0:a35c40f49345	1174	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
boonshen	0:a35c40f49345	1175	uint32_t RESERVED7[1U];
boonshen	0:a35c40f49345	1176	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
boonshen	0:a35c40f49345	1177	uint32_t RESERVED8[1U];
boonshen	0:a35c40f49345	1178	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
boonshen	0:a35c40f49345	1179	uint32_t RESERVED9[1U];
boonshen	0:a35c40f49345	1180	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
boonshen	0:a35c40f49345	1181	uint32_t RESERVED10[1U];
boonshen	0:a35c40f49345	1182	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
boonshen	0:a35c40f49345	1183	uint32_t RESERVED11[1U];
boonshen	0:a35c40f49345	1184	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
boonshen	0:a35c40f49345	1185	uint32_t RESERVED12[1U];
boonshen	0:a35c40f49345	1186	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
boonshen	0:a35c40f49345	1187	uint32_t RESERVED13[1U];
boonshen	0:a35c40f49345	1188	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
boonshen	0:a35c40f49345	1189	uint32_t RESERVED14[1U];
boonshen	0:a35c40f49345	1190	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
boonshen	0:a35c40f49345	1191	uint32_t RESERVED15[1U];
boonshen	0:a35c40f49345	1192	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
boonshen	0:a35c40f49345	1193	uint32_t RESERVED16[1U];
boonshen	0:a35c40f49345	1194	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
boonshen	0:a35c40f49345	1195	uint32_t RESERVED17[1U];
boonshen	0:a35c40f49345	1196	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
boonshen	0:a35c40f49345	1197	uint32_t RESERVED18[1U];
boonshen	0:a35c40f49345	1198	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
boonshen	0:a35c40f49345	1199	uint32_t RESERVED19[1U];
boonshen	0:a35c40f49345	1200	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
boonshen	0:a35c40f49345	1201	uint32_t RESERVED20[1U];
boonshen	0:a35c40f49345	1202	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
boonshen	0:a35c40f49345	1203	uint32_t RESERVED21[1U];
boonshen	0:a35c40f49345	1204	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
boonshen	0:a35c40f49345	1205	uint32_t RESERVED22[1U];
boonshen	0:a35c40f49345	1206	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
boonshen	0:a35c40f49345	1207	uint32_t RESERVED23[1U];
boonshen	0:a35c40f49345	1208	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
boonshen	0:a35c40f49345	1209	uint32_t RESERVED24[1U];
boonshen	0:a35c40f49345	1210	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
boonshen	0:a35c40f49345	1211	uint32_t RESERVED25[1U];
boonshen	0:a35c40f49345	1212	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
boonshen	0:a35c40f49345	1213	uint32_t RESERVED26[1U];
boonshen	0:a35c40f49345	1214	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
boonshen	0:a35c40f49345	1215	uint32_t RESERVED27[1U];
boonshen	0:a35c40f49345	1216	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
boonshen	0:a35c40f49345	1217	uint32_t RESERVED28[1U];
boonshen	0:a35c40f49345	1218	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
boonshen	0:a35c40f49345	1219	uint32_t RESERVED29[1U];
boonshen	0:a35c40f49345	1220	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
boonshen	0:a35c40f49345	1221	uint32_t RESERVED30[1U];
boonshen	0:a35c40f49345	1222	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
boonshen	0:a35c40f49345	1223	uint32_t RESERVED31[1U];
boonshen	0:a35c40f49345	1224	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
boonshen	0:a35c40f49345	1225	uint32_t RESERVED32[934U];
boonshen	0:a35c40f49345	1226	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
boonshen	0:a35c40f49345	1227	uint32_t RESERVED33[1U];
boonshen	0:a35c40f49345	1228	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
boonshen	0:a35c40f49345	1229	} DWT_Type;
boonshen	0:a35c40f49345	1230
boonshen	0:a35c40f49345	1231	/* DWT Control Register Definitions */
boonshen	0:a35c40f49345	1232	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
boonshen	0:a35c40f49345	1233	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
boonshen	0:a35c40f49345	1234
boonshen	0:a35c40f49345	1235	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
boonshen	0:a35c40f49345	1236	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
boonshen	0:a35c40f49345	1237
boonshen	0:a35c40f49345	1238	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
boonshen	0:a35c40f49345	1239	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
boonshen	0:a35c40f49345	1240
boonshen	0:a35c40f49345	1241	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
boonshen	0:a35c40f49345	1242	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
boonshen	0:a35c40f49345	1243
boonshen	0:a35c40f49345	1244	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
boonshen	0:a35c40f49345	1245	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
boonshen	0:a35c40f49345	1246
boonshen	0:a35c40f49345	1247	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
boonshen	0:a35c40f49345	1248	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
boonshen	0:a35c40f49345	1249
boonshen	0:a35c40f49345	1250	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
boonshen	0:a35c40f49345	1251	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
boonshen	0:a35c40f49345	1252
boonshen	0:a35c40f49345	1253	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
boonshen	0:a35c40f49345	1254	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
boonshen	0:a35c40f49345	1255
boonshen	0:a35c40f49345	1256	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
boonshen	0:a35c40f49345	1257	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
boonshen	0:a35c40f49345	1258
boonshen	0:a35c40f49345	1259	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
boonshen	0:a35c40f49345	1260	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
boonshen	0:a35c40f49345	1261
boonshen	0:a35c40f49345	1262	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
boonshen	0:a35c40f49345	1263	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
boonshen	0:a35c40f49345	1264
boonshen	0:a35c40f49345	1265	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
boonshen	0:a35c40f49345	1266	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
boonshen	0:a35c40f49345	1267
boonshen	0:a35c40f49345	1268	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
boonshen	0:a35c40f49345	1269	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
boonshen	0:a35c40f49345	1270
boonshen	0:a35c40f49345	1271	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
boonshen	0:a35c40f49345	1272	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
boonshen	0:a35c40f49345	1273
boonshen	0:a35c40f49345	1274	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
boonshen	0:a35c40f49345	1275	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
boonshen	0:a35c40f49345	1276
boonshen	0:a35c40f49345	1277	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
boonshen	0:a35c40f49345	1278	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
boonshen	0:a35c40f49345	1279
boonshen	0:a35c40f49345	1280	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
boonshen	0:a35c40f49345	1281	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
boonshen	0:a35c40f49345	1282
boonshen	0:a35c40f49345	1283	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
boonshen	0:a35c40f49345	1284	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
boonshen	0:a35c40f49345	1285
boonshen	0:a35c40f49345	1286	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
boonshen	0:a35c40f49345	1287	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
boonshen	0:a35c40f49345	1288
boonshen	0:a35c40f49345	1289	/* DWT CPI Count Register Definitions */
boonshen	0:a35c40f49345	1290	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
boonshen	0:a35c40f49345	1291	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
boonshen	0:a35c40f49345	1292
boonshen	0:a35c40f49345	1293	/* DWT Exception Overhead Count Register Definitions */
boonshen	0:a35c40f49345	1294	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
boonshen	0:a35c40f49345	1295	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
boonshen	0:a35c40f49345	1296
boonshen	0:a35c40f49345	1297	/* DWT Sleep Count Register Definitions */
boonshen	0:a35c40f49345	1298	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
boonshen	0:a35c40f49345	1299	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
boonshen	0:a35c40f49345	1300
boonshen	0:a35c40f49345	1301	/* DWT LSU Count Register Definitions */
boonshen	0:a35c40f49345	1302	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
boonshen	0:a35c40f49345	1303	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
boonshen	0:a35c40f49345	1304
boonshen	0:a35c40f49345	1305	/* DWT Folded-instruction Count Register Definitions */
boonshen	0:a35c40f49345	1306	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
boonshen	0:a35c40f49345	1307	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
boonshen	0:a35c40f49345	1308
boonshen	0:a35c40f49345	1309	/* DWT Comparator Function Register Definitions */
boonshen	0:a35c40f49345	1310	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
boonshen	0:a35c40f49345	1311	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
boonshen	0:a35c40f49345	1312
boonshen	0:a35c40f49345	1313	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
boonshen	0:a35c40f49345	1314	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
boonshen	0:a35c40f49345	1315
boonshen	0:a35c40f49345	1316	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
boonshen	0:a35c40f49345	1317	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
boonshen	0:a35c40f49345	1318
boonshen	0:a35c40f49345	1319	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
boonshen	0:a35c40f49345	1320	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
boonshen	0:a35c40f49345	1321
boonshen	0:a35c40f49345	1322	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
boonshen	0:a35c40f49345	1323	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
boonshen	0:a35c40f49345	1324
boonshen	0:a35c40f49345	1325	/@}/ /* end of group CMSIS_DWT */
boonshen	0:a35c40f49345	1326
boonshen	0:a35c40f49345	1327
boonshen	0:a35c40f49345	1328	/**
boonshen	0:a35c40f49345	1329	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1330	\defgroup CMSIS_TPI Trace Port Interface (TPI)
boonshen	0:a35c40f49345	1331	\brief Type definitions for the Trace Port Interface (TPI)
boonshen	0:a35c40f49345	1332	@{
boonshen	0:a35c40f49345	1333	*/
boonshen	0:a35c40f49345	1334
boonshen	0:a35c40f49345	1335	/**
boonshen	0:a35c40f49345	1336	\brief Structure type to access the Trace Port Interface Register (TPI).
boonshen	0:a35c40f49345	1337	*/
boonshen	0:a35c40f49345	1338	typedef struct
boonshen	0:a35c40f49345	1339	{
boonshen	0:a35c40f49345	1340	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
boonshen	0:a35c40f49345	1341	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
boonshen	0:a35c40f49345	1342	uint32_t RESERVED0[2U];
boonshen	0:a35c40f49345	1343	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
boonshen	0:a35c40f49345	1344	uint32_t RESERVED1[55U];
boonshen	0:a35c40f49345	1345	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
boonshen	0:a35c40f49345	1346	uint32_t RESERVED2[131U];
boonshen	0:a35c40f49345	1347	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
boonshen	0:a35c40f49345	1348	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
boonshen	0:a35c40f49345	1349	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
boonshen	0:a35c40f49345	1350	uint32_t RESERVED3[759U];
boonshen	0:a35c40f49345	1351	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
boonshen	0:a35c40f49345	1352	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
boonshen	0:a35c40f49345	1353	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
boonshen	0:a35c40f49345	1354	uint32_t RESERVED4[1U];
boonshen	0:a35c40f49345	1355	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
boonshen	0:a35c40f49345	1356	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
boonshen	0:a35c40f49345	1357	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
boonshen	0:a35c40f49345	1358	uint32_t RESERVED5[39U];
boonshen	0:a35c40f49345	1359	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
boonshen	0:a35c40f49345	1360	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
boonshen	0:a35c40f49345	1361	uint32_t RESERVED7[8U];
boonshen	0:a35c40f49345	1362	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
boonshen	0:a35c40f49345	1363	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
boonshen	0:a35c40f49345	1364	} TPI_Type;
boonshen	0:a35c40f49345	1365
boonshen	0:a35c40f49345	1366	/* TPI Asynchronous Clock Prescaler Register Definitions */
boonshen	0:a35c40f49345	1367	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
boonshen	0:a35c40f49345	1368	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
boonshen	0:a35c40f49345	1369
boonshen	0:a35c40f49345	1370	/* TPI Selected Pin Protocol Register Definitions */
boonshen	0:a35c40f49345	1371	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
boonshen	0:a35c40f49345	1372	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
boonshen	0:a35c40f49345	1373
boonshen	0:a35c40f49345	1374	/* TPI Formatter and Flush Status Register Definitions */
boonshen	0:a35c40f49345	1375	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
boonshen	0:a35c40f49345	1376	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
boonshen	0:a35c40f49345	1377
boonshen	0:a35c40f49345	1378	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
boonshen	0:a35c40f49345	1379	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
boonshen	0:a35c40f49345	1380
boonshen	0:a35c40f49345	1381	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
boonshen	0:a35c40f49345	1382	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
boonshen	0:a35c40f49345	1383
boonshen	0:a35c40f49345	1384	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
boonshen	0:a35c40f49345	1385	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
boonshen	0:a35c40f49345	1386
boonshen	0:a35c40f49345	1387	/* TPI Formatter and Flush Control Register Definitions */
boonshen	0:a35c40f49345	1388	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
boonshen	0:a35c40f49345	1389	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
boonshen	0:a35c40f49345	1390
boonshen	0:a35c40f49345	1391	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
boonshen	0:a35c40f49345	1392	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
boonshen	0:a35c40f49345	1393
boonshen	0:a35c40f49345	1394	/* TPI TRIGGER Register Definitions */
boonshen	0:a35c40f49345	1395	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
boonshen	0:a35c40f49345	1396	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
boonshen	0:a35c40f49345	1397
boonshen	0:a35c40f49345	1398	/* TPI Integration ETM Data Register Definitions (FIFO0) */
boonshen	0:a35c40f49345	1399	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
boonshen	0:a35c40f49345	1400	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
boonshen	0:a35c40f49345	1401
boonshen	0:a35c40f49345	1402	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
boonshen	0:a35c40f49345	1403	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
boonshen	0:a35c40f49345	1404
boonshen	0:a35c40f49345	1405	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
boonshen	0:a35c40f49345	1406	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
boonshen	0:a35c40f49345	1407
boonshen	0:a35c40f49345	1408	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
boonshen	0:a35c40f49345	1409	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
boonshen	0:a35c40f49345	1410
boonshen	0:a35c40f49345	1411	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
boonshen	0:a35c40f49345	1412	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
boonshen	0:a35c40f49345	1413
boonshen	0:a35c40f49345	1414	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
boonshen	0:a35c40f49345	1415	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
boonshen	0:a35c40f49345	1416
boonshen	0:a35c40f49345	1417	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
boonshen	0:a35c40f49345	1418	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
boonshen	0:a35c40f49345	1419
boonshen	0:a35c40f49345	1420	/* TPI ITATBCTR2 Register Definitions */
boonshen	0:a35c40f49345	1421	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
boonshen	0:a35c40f49345	1422	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
boonshen	0:a35c40f49345	1423
boonshen	0:a35c40f49345	1424	/* TPI Integration ITM Data Register Definitions (FIFO1) */
boonshen	0:a35c40f49345	1425	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
boonshen	0:a35c40f49345	1426	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
boonshen	0:a35c40f49345	1427
boonshen	0:a35c40f49345	1428	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
boonshen	0:a35c40f49345	1429	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
boonshen	0:a35c40f49345	1430
boonshen	0:a35c40f49345	1431	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
boonshen	0:a35c40f49345	1432	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
boonshen	0:a35c40f49345	1433
boonshen	0:a35c40f49345	1434	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
boonshen	0:a35c40f49345	1435	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
boonshen	0:a35c40f49345	1436
boonshen	0:a35c40f49345	1437	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
boonshen	0:a35c40f49345	1438	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
boonshen	0:a35c40f49345	1439
boonshen	0:a35c40f49345	1440	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
boonshen	0:a35c40f49345	1441	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
boonshen	0:a35c40f49345	1442
boonshen	0:a35c40f49345	1443	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
boonshen	0:a35c40f49345	1444	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
boonshen	0:a35c40f49345	1445
boonshen	0:a35c40f49345	1446	/* TPI ITATBCTR0 Register Definitions */
boonshen	0:a35c40f49345	1447	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
boonshen	0:a35c40f49345	1448	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
boonshen	0:a35c40f49345	1449
boonshen	0:a35c40f49345	1450	/* TPI Integration Mode Control Register Definitions */
boonshen	0:a35c40f49345	1451	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
boonshen	0:a35c40f49345	1452	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
boonshen	0:a35c40f49345	1453
boonshen	0:a35c40f49345	1454	/* TPI DEVID Register Definitions */
boonshen	0:a35c40f49345	1455	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
boonshen	0:a35c40f49345	1456	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
boonshen	0:a35c40f49345	1457
boonshen	0:a35c40f49345	1458	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
boonshen	0:a35c40f49345	1459	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
boonshen	0:a35c40f49345	1460
boonshen	0:a35c40f49345	1461	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
boonshen	0:a35c40f49345	1462	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
boonshen	0:a35c40f49345	1463
boonshen	0:a35c40f49345	1464	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
boonshen	0:a35c40f49345	1465	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
boonshen	0:a35c40f49345	1466
boonshen	0:a35c40f49345	1467	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
boonshen	0:a35c40f49345	1468	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
boonshen	0:a35c40f49345	1469
boonshen	0:a35c40f49345	1470	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
boonshen	0:a35c40f49345	1471	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
boonshen	0:a35c40f49345	1472
boonshen	0:a35c40f49345	1473	/* TPI DEVTYPE Register Definitions */
boonshen	0:a35c40f49345	1474	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
boonshen	0:a35c40f49345	1475	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
boonshen	0:a35c40f49345	1476
boonshen	0:a35c40f49345	1477	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
boonshen	0:a35c40f49345	1478	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
boonshen	0:a35c40f49345	1479
boonshen	0:a35c40f49345	1480	/@}/ /* end of group CMSIS_TPI */
boonshen	0:a35c40f49345	1481
boonshen	0:a35c40f49345	1482
boonshen	0:a35c40f49345	1483	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen	0:a35c40f49345	1484	/**
boonshen	0:a35c40f49345	1485	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1486	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
boonshen	0:a35c40f49345	1487	\brief Type definitions for the Memory Protection Unit (MPU)
boonshen	0:a35c40f49345	1488	@{
boonshen	0:a35c40f49345	1489	*/
boonshen	0:a35c40f49345	1490
boonshen	0:a35c40f49345	1491	/**
boonshen	0:a35c40f49345	1492	\brief Structure type to access the Memory Protection Unit (MPU).
boonshen	0:a35c40f49345	1493	*/
boonshen	0:a35c40f49345	1494	typedef struct
boonshen	0:a35c40f49345	1495	{
boonshen	0:a35c40f49345	1496	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
boonshen	0:a35c40f49345	1497	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
boonshen	0:a35c40f49345	1498	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
boonshen	0:a35c40f49345	1499	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
boonshen	0:a35c40f49345	1500	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
boonshen	0:a35c40f49345	1501	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
boonshen	0:a35c40f49345	1502	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
boonshen	0:a35c40f49345	1503	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
boonshen	0:a35c40f49345	1504	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
boonshen	0:a35c40f49345	1505	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
boonshen	0:a35c40f49345	1506	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
boonshen	0:a35c40f49345	1507	uint32_t RESERVED0[1];
boonshen	0:a35c40f49345	1508	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
boonshen	0:a35c40f49345	1509	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
boonshen	0:a35c40f49345	1510	} MPU_Type;
boonshen	0:a35c40f49345	1511
boonshen	0:a35c40f49345	1512	/* MPU Type Register Definitions */
boonshen	0:a35c40f49345	1513	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
boonshen	0:a35c40f49345	1514	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
boonshen	0:a35c40f49345	1515
boonshen	0:a35c40f49345	1516	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
boonshen	0:a35c40f49345	1517	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
boonshen	0:a35c40f49345	1518
boonshen	0:a35c40f49345	1519	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
boonshen	0:a35c40f49345	1520	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
boonshen	0:a35c40f49345	1521
boonshen	0:a35c40f49345	1522	/* MPU Control Register Definitions */
boonshen	0:a35c40f49345	1523	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
boonshen	0:a35c40f49345	1524	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
boonshen	0:a35c40f49345	1525
boonshen	0:a35c40f49345	1526	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
boonshen	0:a35c40f49345	1527	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
boonshen	0:a35c40f49345	1528
boonshen	0:a35c40f49345	1529	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
boonshen	0:a35c40f49345	1530	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
boonshen	0:a35c40f49345	1531
boonshen	0:a35c40f49345	1532	/* MPU Region Number Register Definitions */
boonshen	0:a35c40f49345	1533	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
boonshen	0:a35c40f49345	1534	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
boonshen	0:a35c40f49345	1535
boonshen	0:a35c40f49345	1536	/* MPU Region Base Address Register Definitions */
boonshen	0:a35c40f49345	1537	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
boonshen	0:a35c40f49345	1538	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
boonshen	0:a35c40f49345	1539
boonshen	0:a35c40f49345	1540	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
boonshen	0:a35c40f49345	1541	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
boonshen	0:a35c40f49345	1542
boonshen	0:a35c40f49345	1543	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
boonshen	0:a35c40f49345	1544	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
boonshen	0:a35c40f49345	1545
boonshen	0:a35c40f49345	1546	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
boonshen	0:a35c40f49345	1547	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
boonshen	0:a35c40f49345	1548
boonshen	0:a35c40f49345	1549	/* MPU Region Limit Address Register Definitions */
boonshen	0:a35c40f49345	1550	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
boonshen	0:a35c40f49345	1551	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
boonshen	0:a35c40f49345	1552
boonshen	0:a35c40f49345	1553	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
boonshen	0:a35c40f49345	1554	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
boonshen	0:a35c40f49345	1555
boonshen	0:a35c40f49345	1556	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
boonshen	0:a35c40f49345	1557	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
boonshen	0:a35c40f49345	1558
boonshen	0:a35c40f49345	1559	/* MPU Memory Attribute Indirection Register 0 Definitions */
boonshen	0:a35c40f49345	1560	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
boonshen	0:a35c40f49345	1561	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
boonshen	0:a35c40f49345	1562
boonshen	0:a35c40f49345	1563	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
boonshen	0:a35c40f49345	1564	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
boonshen	0:a35c40f49345	1565
boonshen	0:a35c40f49345	1566	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
boonshen	0:a35c40f49345	1567	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
boonshen	0:a35c40f49345	1568
boonshen	0:a35c40f49345	1569	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
boonshen	0:a35c40f49345	1570	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
boonshen	0:a35c40f49345	1571
boonshen	0:a35c40f49345	1572	/* MPU Memory Attribute Indirection Register 1 Definitions */
boonshen	0:a35c40f49345	1573	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
boonshen	0:a35c40f49345	1574	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
boonshen	0:a35c40f49345	1575
boonshen	0:a35c40f49345	1576	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
boonshen	0:a35c40f49345	1577	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
boonshen	0:a35c40f49345	1578
boonshen	0:a35c40f49345	1579	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
boonshen	0:a35c40f49345	1580	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
boonshen	0:a35c40f49345	1581
boonshen	0:a35c40f49345	1582	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
boonshen	0:a35c40f49345	1583	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
boonshen	0:a35c40f49345	1584
boonshen	0:a35c40f49345	1585	/@} end of group CMSIS_MPU /
boonshen	0:a35c40f49345	1586	#endif
boonshen	0:a35c40f49345	1587
boonshen	0:a35c40f49345	1588
boonshen	0:a35c40f49345	1589	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen	0:a35c40f49345	1590	/**
boonshen	0:a35c40f49345	1591	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1592	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
boonshen	0:a35c40f49345	1593	\brief Type definitions for the Security Attribution Unit (SAU)
boonshen	0:a35c40f49345	1594	@{
boonshen	0:a35c40f49345	1595	*/
boonshen	0:a35c40f49345	1596
boonshen	0:a35c40f49345	1597	/**
boonshen	0:a35c40f49345	1598	\brief Structure type to access the Security Attribution Unit (SAU).
boonshen	0:a35c40f49345	1599	*/
boonshen	0:a35c40f49345	1600	typedef struct
boonshen	0:a35c40f49345	1601	{
boonshen	0:a35c40f49345	1602	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
boonshen	0:a35c40f49345	1603	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
boonshen	0:a35c40f49345	1604	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
boonshen	0:a35c40f49345	1605	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
boonshen	0:a35c40f49345	1606	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
boonshen	0:a35c40f49345	1607	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
boonshen	0:a35c40f49345	1608	#else
boonshen	0:a35c40f49345	1609	uint32_t RESERVED0[3];
boonshen	0:a35c40f49345	1610	#endif
boonshen	0:a35c40f49345	1611	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
boonshen	0:a35c40f49345	1612	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
boonshen	0:a35c40f49345	1613	} SAU_Type;
boonshen	0:a35c40f49345	1614
boonshen	0:a35c40f49345	1615	/* SAU Control Register Definitions */
boonshen	0:a35c40f49345	1616	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
boonshen	0:a35c40f49345	1617	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
boonshen	0:a35c40f49345	1618
boonshen	0:a35c40f49345	1619	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
boonshen	0:a35c40f49345	1620	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
boonshen	0:a35c40f49345	1621
boonshen	0:a35c40f49345	1622	/* SAU Type Register Definitions */
boonshen	0:a35c40f49345	1623	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
boonshen	0:a35c40f49345	1624	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
boonshen	0:a35c40f49345	1625
boonshen	0:a35c40f49345	1626	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
boonshen	0:a35c40f49345	1627	/* SAU Region Number Register Definitions */
boonshen	0:a35c40f49345	1628	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
boonshen	0:a35c40f49345	1629	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
boonshen	0:a35c40f49345	1630
boonshen	0:a35c40f49345	1631	/* SAU Region Base Address Register Definitions */
boonshen	0:a35c40f49345	1632	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
boonshen	0:a35c40f49345	1633	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
boonshen	0:a35c40f49345	1634
boonshen	0:a35c40f49345	1635	/* SAU Region Limit Address Register Definitions */
boonshen	0:a35c40f49345	1636	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
boonshen	0:a35c40f49345	1637	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
boonshen	0:a35c40f49345	1638
boonshen	0:a35c40f49345	1639	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
boonshen	0:a35c40f49345	1640	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
boonshen	0:a35c40f49345	1641
boonshen	0:a35c40f49345	1642	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
boonshen	0:a35c40f49345	1643	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
boonshen	0:a35c40f49345	1644
boonshen	0:a35c40f49345	1645	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
boonshen	0:a35c40f49345	1646
boonshen	0:a35c40f49345	1647	/* Secure Fault Status Register Definitions */
boonshen	0:a35c40f49345	1648	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
boonshen	0:a35c40f49345	1649	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
boonshen	0:a35c40f49345	1650
boonshen	0:a35c40f49345	1651	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
boonshen	0:a35c40f49345	1652	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
boonshen	0:a35c40f49345	1653
boonshen	0:a35c40f49345	1654	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
boonshen	0:a35c40f49345	1655	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
boonshen	0:a35c40f49345	1656
boonshen	0:a35c40f49345	1657	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
boonshen	0:a35c40f49345	1658	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
boonshen	0:a35c40f49345	1659
boonshen	0:a35c40f49345	1660	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
boonshen	0:a35c40f49345	1661	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
boonshen	0:a35c40f49345	1662
boonshen	0:a35c40f49345	1663	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
boonshen	0:a35c40f49345	1664	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
boonshen	0:a35c40f49345	1665
boonshen	0:a35c40f49345	1666	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
boonshen	0:a35c40f49345	1667	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
boonshen	0:a35c40f49345	1668
boonshen	0:a35c40f49345	1669	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
boonshen	0:a35c40f49345	1670	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
boonshen	0:a35c40f49345	1671
boonshen	0:a35c40f49345	1672	/@} end of group CMSIS_SAU /
boonshen	0:a35c40f49345	1673	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen	0:a35c40f49345	1674
boonshen	0:a35c40f49345	1675
boonshen	0:a35c40f49345	1676	/**
boonshen	0:a35c40f49345	1677	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1678	\defgroup CMSIS_FPU Floating Point Unit (FPU)
boonshen	0:a35c40f49345	1679	\brief Type definitions for the Floating Point Unit (FPU)
boonshen	0:a35c40f49345	1680	@{
boonshen	0:a35c40f49345	1681	*/
boonshen	0:a35c40f49345	1682
boonshen	0:a35c40f49345	1683	/**
boonshen	0:a35c40f49345	1684	\brief Structure type to access the Floating Point Unit (FPU).
boonshen	0:a35c40f49345	1685	*/
boonshen	0:a35c40f49345	1686	typedef struct
boonshen	0:a35c40f49345	1687	{
boonshen	0:a35c40f49345	1688	uint32_t RESERVED0[1U];
boonshen	0:a35c40f49345	1689	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
boonshen	0:a35c40f49345	1690	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
boonshen	0:a35c40f49345	1691	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
boonshen	0:a35c40f49345	1692	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
boonshen	0:a35c40f49345	1693	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
boonshen	0:a35c40f49345	1694	} FPU_Type;
boonshen	0:a35c40f49345	1695
boonshen	0:a35c40f49345	1696	/* Floating-Point Context Control Register Definitions */
boonshen	0:a35c40f49345	1697	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
boonshen	0:a35c40f49345	1698	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
boonshen	0:a35c40f49345	1699
boonshen	0:a35c40f49345	1700	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
boonshen	0:a35c40f49345	1701	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
boonshen	0:a35c40f49345	1702
boonshen	0:a35c40f49345	1703	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
boonshen	0:a35c40f49345	1704	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
boonshen	0:a35c40f49345	1705
boonshen	0:a35c40f49345	1706	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
boonshen	0:a35c40f49345	1707	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
boonshen	0:a35c40f49345	1708
boonshen	0:a35c40f49345	1709	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
boonshen	0:a35c40f49345	1710	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
boonshen	0:a35c40f49345	1711
boonshen	0:a35c40f49345	1712	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
boonshen	0:a35c40f49345	1713	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
boonshen	0:a35c40f49345	1714
boonshen	0:a35c40f49345	1715	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
boonshen	0:a35c40f49345	1716	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
boonshen	0:a35c40f49345	1717
boonshen	0:a35c40f49345	1718	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
boonshen	0:a35c40f49345	1719	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
boonshen	0:a35c40f49345	1720
boonshen	0:a35c40f49345	1721	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
boonshen	0:a35c40f49345	1722	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
boonshen	0:a35c40f49345	1723
boonshen	0:a35c40f49345	1724	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
boonshen	0:a35c40f49345	1725	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
boonshen	0:a35c40f49345	1726
boonshen	0:a35c40f49345	1727	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
boonshen	0:a35c40f49345	1728	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
boonshen	0:a35c40f49345	1729
boonshen	0:a35c40f49345	1730	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
boonshen	0:a35c40f49345	1731	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
boonshen	0:a35c40f49345	1732
boonshen	0:a35c40f49345	1733	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
boonshen	0:a35c40f49345	1734	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
boonshen	0:a35c40f49345	1735
boonshen	0:a35c40f49345	1736	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
boonshen	0:a35c40f49345	1737	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
boonshen	0:a35c40f49345	1738
boonshen	0:a35c40f49345	1739	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
boonshen	0:a35c40f49345	1740	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
boonshen	0:a35c40f49345	1741
boonshen	0:a35c40f49345	1742	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
boonshen	0:a35c40f49345	1743	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
boonshen	0:a35c40f49345	1744
boonshen	0:a35c40f49345	1745	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
boonshen	0:a35c40f49345	1746	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
boonshen	0:a35c40f49345	1747
boonshen	0:a35c40f49345	1748	/* Floating-Point Context Address Register Definitions */
boonshen	0:a35c40f49345	1749	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
boonshen	0:a35c40f49345	1750	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
boonshen	0:a35c40f49345	1751
boonshen	0:a35c40f49345	1752	/* Floating-Point Default Status Control Register Definitions */
boonshen	0:a35c40f49345	1753	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
boonshen	0:a35c40f49345	1754	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
boonshen	0:a35c40f49345	1755
boonshen	0:a35c40f49345	1756	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
boonshen	0:a35c40f49345	1757	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
boonshen	0:a35c40f49345	1758
boonshen	0:a35c40f49345	1759	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
boonshen	0:a35c40f49345	1760	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
boonshen	0:a35c40f49345	1761
boonshen	0:a35c40f49345	1762	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
boonshen	0:a35c40f49345	1763	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
boonshen	0:a35c40f49345	1764
boonshen	0:a35c40f49345	1765	/* Media and FP Feature Register 0 Definitions */
boonshen	0:a35c40f49345	1766	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
boonshen	0:a35c40f49345	1767	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
boonshen	0:a35c40f49345	1768
boonshen	0:a35c40f49345	1769	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
boonshen	0:a35c40f49345	1770	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
boonshen	0:a35c40f49345	1771
boonshen	0:a35c40f49345	1772	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
boonshen	0:a35c40f49345	1773	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
boonshen	0:a35c40f49345	1774
boonshen	0:a35c40f49345	1775	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
boonshen	0:a35c40f49345	1776	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
boonshen	0:a35c40f49345	1777
boonshen	0:a35c40f49345	1778	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
boonshen	0:a35c40f49345	1779	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
boonshen	0:a35c40f49345	1780
boonshen	0:a35c40f49345	1781	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
boonshen	0:a35c40f49345	1782	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
boonshen	0:a35c40f49345	1783
boonshen	0:a35c40f49345	1784	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
boonshen	0:a35c40f49345	1785	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
boonshen	0:a35c40f49345	1786
boonshen	0:a35c40f49345	1787	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
boonshen	0:a35c40f49345	1788	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
boonshen	0:a35c40f49345	1789
boonshen	0:a35c40f49345	1790	/* Media and FP Feature Register 1 Definitions */
boonshen	0:a35c40f49345	1791	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
boonshen	0:a35c40f49345	1792	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
boonshen	0:a35c40f49345	1793
boonshen	0:a35c40f49345	1794	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
boonshen	0:a35c40f49345	1795	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
boonshen	0:a35c40f49345	1796
boonshen	0:a35c40f49345	1797	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
boonshen	0:a35c40f49345	1798	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
boonshen	0:a35c40f49345	1799
boonshen	0:a35c40f49345	1800	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
boonshen	0:a35c40f49345	1801	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
boonshen	0:a35c40f49345	1802
boonshen	0:a35c40f49345	1803	/@} end of group CMSIS_FPU /
boonshen	0:a35c40f49345	1804
boonshen	0:a35c40f49345	1805
boonshen	0:a35c40f49345	1806	/**
boonshen	0:a35c40f49345	1807	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1808	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
boonshen	0:a35c40f49345	1809	\brief Type definitions for the Core Debug Registers
boonshen	0:a35c40f49345	1810	@{
boonshen	0:a35c40f49345	1811	*/
boonshen	0:a35c40f49345	1812
boonshen	0:a35c40f49345	1813	/**
boonshen	0:a35c40f49345	1814	\brief Structure type to access the Core Debug Register (CoreDebug).
boonshen	0:a35c40f49345	1815	*/
boonshen	0:a35c40f49345	1816	typedef struct
boonshen	0:a35c40f49345	1817	{
boonshen	0:a35c40f49345	1818	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
boonshen	0:a35c40f49345	1819	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
boonshen	0:a35c40f49345	1820	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
boonshen	0:a35c40f49345	1821	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
boonshen	0:a35c40f49345	1822	uint32_t RESERVED4[1U];
boonshen	0:a35c40f49345	1823	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
boonshen	0:a35c40f49345	1824	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
boonshen	0:a35c40f49345	1825	} CoreDebug_Type;
boonshen	0:a35c40f49345	1826
boonshen	0:a35c40f49345	1827	/* Debug Halting Control and Status Register Definitions */
boonshen	0:a35c40f49345	1828	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
boonshen	0:a35c40f49345	1829	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
boonshen	0:a35c40f49345	1830
boonshen	0:a35c40f49345	1831	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
boonshen	0:a35c40f49345	1832	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
boonshen	0:a35c40f49345	1833
boonshen	0:a35c40f49345	1834	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
boonshen	0:a35c40f49345	1835	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
boonshen	0:a35c40f49345	1836
boonshen	0:a35c40f49345	1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
boonshen	0:a35c40f49345	1838	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
boonshen	0:a35c40f49345	1839
boonshen	0:a35c40f49345	1840	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
boonshen	0:a35c40f49345	1841	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
boonshen	0:a35c40f49345	1842
boonshen	0:a35c40f49345	1843	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
boonshen	0:a35c40f49345	1844	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
boonshen	0:a35c40f49345	1845
boonshen	0:a35c40f49345	1846	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
boonshen	0:a35c40f49345	1847	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
boonshen	0:a35c40f49345	1848
boonshen	0:a35c40f49345	1849	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
boonshen	0:a35c40f49345	1850	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
boonshen	0:a35c40f49345	1851
boonshen	0:a35c40f49345	1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
boonshen	0:a35c40f49345	1853	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
boonshen	0:a35c40f49345	1854
boonshen	0:a35c40f49345	1855	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
boonshen	0:a35c40f49345	1856	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
boonshen	0:a35c40f49345	1857
boonshen	0:a35c40f49345	1858	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
boonshen	0:a35c40f49345	1859	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
boonshen	0:a35c40f49345	1860
boonshen	0:a35c40f49345	1861	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
boonshen	0:a35c40f49345	1862	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
boonshen	0:a35c40f49345	1863
boonshen	0:a35c40f49345	1864	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
boonshen	0:a35c40f49345	1865	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
boonshen	0:a35c40f49345	1866
boonshen	0:a35c40f49345	1867	/* Debug Core Register Selector Register Definitions */
boonshen	0:a35c40f49345	1868	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
boonshen	0:a35c40f49345	1869	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
boonshen	0:a35c40f49345	1870
boonshen	0:a35c40f49345	1871	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
boonshen	0:a35c40f49345	1872	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
boonshen	0:a35c40f49345	1873
boonshen	0:a35c40f49345	1874	/* Debug Exception and Monitor Control Register Definitions */
boonshen	0:a35c40f49345	1875	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
boonshen	0:a35c40f49345	1876	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
boonshen	0:a35c40f49345	1877
boonshen	0:a35c40f49345	1878	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
boonshen	0:a35c40f49345	1879	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
boonshen	0:a35c40f49345	1880
boonshen	0:a35c40f49345	1881	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
boonshen	0:a35c40f49345	1882	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
boonshen	0:a35c40f49345	1883
boonshen	0:a35c40f49345	1884	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
boonshen	0:a35c40f49345	1885	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
boonshen	0:a35c40f49345	1886
boonshen	0:a35c40f49345	1887	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
boonshen	0:a35c40f49345	1888	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
boonshen	0:a35c40f49345	1889
boonshen	0:a35c40f49345	1890	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
boonshen	0:a35c40f49345	1891	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
boonshen	0:a35c40f49345	1892
boonshen	0:a35c40f49345	1893	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
boonshen	0:a35c40f49345	1894	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
boonshen	0:a35c40f49345	1895
boonshen	0:a35c40f49345	1896	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
boonshen	0:a35c40f49345	1897	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
boonshen	0:a35c40f49345	1898
boonshen	0:a35c40f49345	1899	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
boonshen	0:a35c40f49345	1900	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
boonshen	0:a35c40f49345	1901
boonshen	0:a35c40f49345	1902	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
boonshen	0:a35c40f49345	1903	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
boonshen	0:a35c40f49345	1904
boonshen	0:a35c40f49345	1905	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
boonshen	0:a35c40f49345	1906	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
boonshen	0:a35c40f49345	1907
boonshen	0:a35c40f49345	1908	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
boonshen	0:a35c40f49345	1909	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
boonshen	0:a35c40f49345	1910
boonshen	0:a35c40f49345	1911	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
boonshen	0:a35c40f49345	1912	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
boonshen	0:a35c40f49345	1913
boonshen	0:a35c40f49345	1914	/* Debug Authentication Control Register Definitions */
boonshen	0:a35c40f49345	1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
boonshen	0:a35c40f49345	1916	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
boonshen	0:a35c40f49345	1917
boonshen	0:a35c40f49345	1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
boonshen	0:a35c40f49345	1919	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
boonshen	0:a35c40f49345	1920
boonshen	0:a35c40f49345	1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
boonshen	0:a35c40f49345	1922	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
boonshen	0:a35c40f49345	1923
boonshen	0:a35c40f49345	1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
boonshen	0:a35c40f49345	1925	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
boonshen	0:a35c40f49345	1926
boonshen	0:a35c40f49345	1927	/* Debug Security Control and Status Register Definitions */
boonshen	0:a35c40f49345	1928	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
boonshen	0:a35c40f49345	1929	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
boonshen	0:a35c40f49345	1930
boonshen	0:a35c40f49345	1931	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
boonshen	0:a35c40f49345	1932	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
boonshen	0:a35c40f49345	1933
boonshen	0:a35c40f49345	1934	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
boonshen	0:a35c40f49345	1935	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
boonshen	0:a35c40f49345	1936
boonshen	0:a35c40f49345	1937	/@} end of group CMSIS_CoreDebug /
boonshen	0:a35c40f49345	1938
boonshen	0:a35c40f49345	1939
boonshen	0:a35c40f49345	1940	/**
boonshen	0:a35c40f49345	1941	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1942	\defgroup CMSIS_core_bitfield Core register bit field macros
boonshen	0:a35c40f49345	1943	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
boonshen	0:a35c40f49345	1944	@{
boonshen	0:a35c40f49345	1945	*/
boonshen	0:a35c40f49345	1946
boonshen	0:a35c40f49345	1947	/**
boonshen	0:a35c40f49345	1948	\brief Mask and shift a bit field value for use in a register bit range.
boonshen	0:a35c40f49345	1949	\param[in] field Name of the register bit field.
boonshen	0:a35c40f49345	1950	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
boonshen	0:a35c40f49345	1951	\return Masked and shifted value.
boonshen	0:a35c40f49345	1952	*/
boonshen	0:a35c40f49345	1953	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
boonshen	0:a35c40f49345	1954
boonshen	0:a35c40f49345	1955	/**
boonshen	0:a35c40f49345	1956	\brief Mask and shift a register value to extract a bit filed value.
boonshen	0:a35c40f49345	1957	\param[in] field Name of the register bit field.
boonshen	0:a35c40f49345	1958	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
boonshen	0:a35c40f49345	1959	\return Masked and shifted bit field value.
boonshen	0:a35c40f49345	1960	*/
boonshen	0:a35c40f49345	1961	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
boonshen	0:a35c40f49345	1962
boonshen	0:a35c40f49345	1963	/@} end of group CMSIS_core_bitfield /
boonshen	0:a35c40f49345	1964
boonshen	0:a35c40f49345	1965
boonshen	0:a35c40f49345	1966	/**
boonshen	0:a35c40f49345	1967	\ingroup CMSIS_core_register
boonshen	0:a35c40f49345	1968	\defgroup CMSIS_core_base Core Definitions
boonshen	0:a35c40f49345	1969	\brief Definitions for base addresses, unions, and structures.
boonshen	0:a35c40f49345	1970	@{
boonshen	0:a35c40f49345	1971	*/
boonshen	0:a35c40f49345	1972
boonshen	0:a35c40f49345	1973	/* Memory mapping of Core Hardware */
boonshen	0:a35c40f49345	1974	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
boonshen	0:a35c40f49345	1975	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
boonshen	0:a35c40f49345	1976	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
boonshen	0:a35c40f49345	1977	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
boonshen	0:a35c40f49345	1978	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
boonshen	0:a35c40f49345	1979	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
boonshen	0:a35c40f49345	1980	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
boonshen	0:a35c40f49345	1981	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
boonshen	0:a35c40f49345	1982
boonshen	0:a35c40f49345	1983	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
boonshen	0:a35c40f49345	1984	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
boonshen	0:a35c40f49345	1985	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
boonshen	0:a35c40f49345	1986	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
boonshen	0:a35c40f49345	1987	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
boonshen	0:a35c40f49345	1988	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
boonshen	0:a35c40f49345	1989	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
boonshen	0:a35c40f49345	1990	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
boonshen	0:a35c40f49345	1991
boonshen	0:a35c40f49345	1992	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen	0:a35c40f49345	1993	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
boonshen	0:a35c40f49345	1994	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
boonshen	0:a35c40f49345	1995	#endif
boonshen	0:a35c40f49345	1996
boonshen	0:a35c40f49345	1997	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen	0:a35c40f49345	1998	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
boonshen	0:a35c40f49345	1999	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
boonshen	0:a35c40f49345	2000	#endif
boonshen	0:a35c40f49345	2001
boonshen	0:a35c40f49345	2002	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
boonshen	0:a35c40f49345	2003	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
boonshen	0:a35c40f49345	2004
boonshen	0:a35c40f49345	2005	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen	0:a35c40f49345	2006	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
boonshen	0:a35c40f49345	2007	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
boonshen	0:a35c40f49345	2008	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
boonshen	0:a35c40f49345	2009	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
boonshen	0:a35c40f49345	2010	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
boonshen	0:a35c40f49345	2011
boonshen	0:a35c40f49345	2012	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
boonshen	0:a35c40f49345	2013	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
boonshen	0:a35c40f49345	2014	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
boonshen	0:a35c40f49345	2015	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
boonshen	0:a35c40f49345	2016	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
boonshen	0:a35c40f49345	2017
boonshen	0:a35c40f49345	2018	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
boonshen	0:a35c40f49345	2019	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
boonshen	0:a35c40f49345	2020	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
boonshen	0:a35c40f49345	2021	#endif
boonshen	0:a35c40f49345	2022
boonshen	0:a35c40f49345	2023	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
boonshen	0:a35c40f49345	2024	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
boonshen	0:a35c40f49345	2025
boonshen	0:a35c40f49345	2026	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen	0:a35c40f49345	2027	/@} /
boonshen	0:a35c40f49345	2028
boonshen	0:a35c40f49345	2029
boonshen	0:a35c40f49345	2030
boonshen	0:a35c40f49345	2031	/*******************************************************************************
boonshen	0:a35c40f49345	2032	* Hardware Abstraction Layer
boonshen	0:a35c40f49345	2033	Core Function Interface contains:
boonshen	0:a35c40f49345	2034	- Core NVIC Functions
boonshen	0:a35c40f49345	2035	- Core SysTick Functions
boonshen	0:a35c40f49345	2036	- Core Debug Functions
boonshen	0:a35c40f49345	2037	- Core Register Access Functions
boonshen	0:a35c40f49345	2038	******************************************************************************/
boonshen	0:a35c40f49345	2039	/**
boonshen	0:a35c40f49345	2040	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
boonshen	0:a35c40f49345	2041	*/
boonshen	0:a35c40f49345	2042
boonshen	0:a35c40f49345	2043
boonshen	0:a35c40f49345	2044
boonshen	0:a35c40f49345	2045	/* ########################## NVIC functions #################################### */
boonshen	0:a35c40f49345	2046	/**
boonshen	0:a35c40f49345	2047	\ingroup CMSIS_Core_FunctionInterface
boonshen	0:a35c40f49345	2048	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
boonshen	0:a35c40f49345	2049	\brief Functions that manage interrupts and exceptions via the NVIC.
boonshen	0:a35c40f49345	2050	@{
boonshen	0:a35c40f49345	2051	*/
boonshen	0:a35c40f49345	2052
boonshen	0:a35c40f49345	2053	#ifdef CMSIS_NVIC_VIRTUAL
boonshen	0:a35c40f49345	2054	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen	0:a35c40f49345	2055	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
boonshen	0:a35c40f49345	2056	#endif
boonshen	0:a35c40f49345	2057	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
boonshen	0:a35c40f49345	2058	#else
boonshen	0:a35c40f49345	2059	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
boonshen	0:a35c40f49345	2060	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
boonshen	0:a35c40f49345	2061	#define NVIC_EnableIRQ __NVIC_EnableIRQ
boonshen	0:a35c40f49345	2062	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
boonshen	0:a35c40f49345	2063	#define NVIC_DisableIRQ __NVIC_DisableIRQ
boonshen	0:a35c40f49345	2064	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
boonshen	0:a35c40f49345	2065	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
boonshen	0:a35c40f49345	2066	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
boonshen	0:a35c40f49345	2067	#define NVIC_GetActive __NVIC_GetActive
boonshen	0:a35c40f49345	2068	#define NVIC_SetPriority __NVIC_SetPriority
boonshen	0:a35c40f49345	2069	#define NVIC_GetPriority __NVIC_GetPriority
boonshen	0:a35c40f49345	2070	#define NVIC_SystemReset __NVIC_SystemReset
boonshen	0:a35c40f49345	2071	#endif /* CMSIS_NVIC_VIRTUAL */
boonshen	0:a35c40f49345	2072
boonshen	0:a35c40f49345	2073	#ifdef CMSIS_VECTAB_VIRTUAL
boonshen	0:a35c40f49345	2074	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen	0:a35c40f49345	2075	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
boonshen	0:a35c40f49345	2076	#endif
boonshen	0:a35c40f49345	2077	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
boonshen	0:a35c40f49345	2078	#else
boonshen	0:a35c40f49345	2079	#define NVIC_SetVector __NVIC_SetVector
boonshen	0:a35c40f49345	2080	#define NVIC_GetVector __NVIC_GetVector
boonshen	0:a35c40f49345	2081	#endif /* (CMSIS_VECTAB_VIRTUAL) */
boonshen	0:a35c40f49345	2082
boonshen	0:a35c40f49345	2083	#define NVIC_USER_IRQ_OFFSET 16
boonshen	0:a35c40f49345	2084
boonshen	0:a35c40f49345	2085
boonshen	0:a35c40f49345	2086
boonshen	0:a35c40f49345	2087	/**
boonshen	0:a35c40f49345	2088	\brief Set Priority Grouping
boonshen	0:a35c40f49345	2089	\details Sets the priority grouping field using the required unlock sequence.
boonshen	0:a35c40f49345	2090	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
boonshen	0:a35c40f49345	2091	Only values from 0..7 are used.
boonshen	0:a35c40f49345	2092	In case of a conflict between priority grouping and available
boonshen	0:a35c40f49345	2093	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
boonshen	0:a35c40f49345	2094	\param [in] PriorityGroup Priority grouping field.
boonshen	0:a35c40f49345	2095	*/
boonshen	0:a35c40f49345	2096	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
boonshen	0:a35c40f49345	2097	{
boonshen	0:a35c40f49345	2098	uint32_t reg_value;
boonshen	0:a35c40f49345	2099	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
boonshen	0:a35c40f49345	2100
boonshen	0:a35c40f49345	2101	reg_value = SCB->AIRCR; /* read old register configuration */
boonshen	0:a35c40f49345	2102	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
boonshen	0:a35c40f49345	2103	reg_value = (reg_value \|
boonshen	0:a35c40f49345	2104	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
boonshen	0:a35c40f49345	2105	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
boonshen	0:a35c40f49345	2106	SCB->AIRCR = reg_value;
boonshen	0:a35c40f49345	2107	}
boonshen	0:a35c40f49345	2108
boonshen	0:a35c40f49345	2109
boonshen	0:a35c40f49345	2110	/**
boonshen	0:a35c40f49345	2111	\brief Get Priority Grouping
boonshen	0:a35c40f49345	2112	\details Reads the priority grouping field from the NVIC Interrupt Controller.
boonshen	0:a35c40f49345	2113	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
boonshen	0:a35c40f49345	2114	*/
boonshen	0:a35c40f49345	2115	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
boonshen	0:a35c40f49345	2116	{
boonshen	0:a35c40f49345	2117	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
boonshen	0:a35c40f49345	2118	}
boonshen	0:a35c40f49345	2119
boonshen	0:a35c40f49345	2120
boonshen	0:a35c40f49345	2121	/**
boonshen	0:a35c40f49345	2122	\brief Enable Interrupt
boonshen	0:a35c40f49345	2123	\details Enables a device specific interrupt in the NVIC interrupt controller.
boonshen	0:a35c40f49345	2124	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2125	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2126	*/
boonshen	0:a35c40f49345	2127	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2128	{
boonshen	0:a35c40f49345	2129	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2130	{
boonshen	0:a35c40f49345	2131	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2132	}
boonshen	0:a35c40f49345	2133	}
boonshen	0:a35c40f49345	2134
boonshen	0:a35c40f49345	2135
boonshen	0:a35c40f49345	2136	/**
boonshen	0:a35c40f49345	2137	\brief Get Interrupt Enable status
boonshen	0:a35c40f49345	2138	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
boonshen	0:a35c40f49345	2139	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2140	\return 0 Interrupt is not enabled.
boonshen	0:a35c40f49345	2141	\return 1 Interrupt is enabled.
boonshen	0:a35c40f49345	2142	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2143	*/
boonshen	0:a35c40f49345	2144	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2145	{
boonshen	0:a35c40f49345	2146	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2147	{
boonshen	0:a35c40f49345	2148	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2149	}
boonshen	0:a35c40f49345	2150	else
boonshen	0:a35c40f49345	2151	{
boonshen	0:a35c40f49345	2152	return(0U);
boonshen	0:a35c40f49345	2153	}
boonshen	0:a35c40f49345	2154	}
boonshen	0:a35c40f49345	2155
boonshen	0:a35c40f49345	2156
boonshen	0:a35c40f49345	2157	/**
boonshen	0:a35c40f49345	2158	\brief Disable Interrupt
boonshen	0:a35c40f49345	2159	\details Disables a device specific interrupt in the NVIC interrupt controller.
boonshen	0:a35c40f49345	2160	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2161	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2162	*/
boonshen	0:a35c40f49345	2163	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2164	{
boonshen	0:a35c40f49345	2165	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2166	{
boonshen	0:a35c40f49345	2167	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2168	__DSB();
boonshen	0:a35c40f49345	2169	__ISB();
boonshen	0:a35c40f49345	2170	}
boonshen	0:a35c40f49345	2171	}
boonshen	0:a35c40f49345	2172
boonshen	0:a35c40f49345	2173
boonshen	0:a35c40f49345	2174	/**
boonshen	0:a35c40f49345	2175	\brief Get Pending Interrupt
boonshen	0:a35c40f49345	2176	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
boonshen	0:a35c40f49345	2177	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2178	\return 0 Interrupt status is not pending.
boonshen	0:a35c40f49345	2179	\return 1 Interrupt status is pending.
boonshen	0:a35c40f49345	2180	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2181	*/
boonshen	0:a35c40f49345	2182	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2183	{
boonshen	0:a35c40f49345	2184	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2185	{
boonshen	0:a35c40f49345	2186	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2187	}
boonshen	0:a35c40f49345	2188	else
boonshen	0:a35c40f49345	2189	{
boonshen	0:a35c40f49345	2190	return(0U);
boonshen	0:a35c40f49345	2191	}
boonshen	0:a35c40f49345	2192	}
boonshen	0:a35c40f49345	2193
boonshen	0:a35c40f49345	2194
boonshen	0:a35c40f49345	2195	/**
boonshen	0:a35c40f49345	2196	\brief Set Pending Interrupt
boonshen	0:a35c40f49345	2197	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
boonshen	0:a35c40f49345	2198	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2199	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2200	*/
boonshen	0:a35c40f49345	2201	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2202	{
boonshen	0:a35c40f49345	2203	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2204	{
boonshen	0:a35c40f49345	2205	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2206	}
boonshen	0:a35c40f49345	2207	}
boonshen	0:a35c40f49345	2208
boonshen	0:a35c40f49345	2209
boonshen	0:a35c40f49345	2210	/**
boonshen	0:a35c40f49345	2211	\brief Clear Pending Interrupt
boonshen	0:a35c40f49345	2212	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
boonshen	0:a35c40f49345	2213	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2214	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2215	*/
boonshen	0:a35c40f49345	2216	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2217	{
boonshen	0:a35c40f49345	2218	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2219	{
boonshen	0:a35c40f49345	2220	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2221	}
boonshen	0:a35c40f49345	2222	}
boonshen	0:a35c40f49345	2223
boonshen	0:a35c40f49345	2224
boonshen	0:a35c40f49345	2225	/**
boonshen	0:a35c40f49345	2226	\brief Get Active Interrupt
boonshen	0:a35c40f49345	2227	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
boonshen	0:a35c40f49345	2228	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2229	\return 0 Interrupt status is not active.
boonshen	0:a35c40f49345	2230	\return 1 Interrupt status is active.
boonshen	0:a35c40f49345	2231	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2232	*/
boonshen	0:a35c40f49345	2233	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2234	{
boonshen	0:a35c40f49345	2235	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2236	{
boonshen	0:a35c40f49345	2237	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2238	}
boonshen	0:a35c40f49345	2239	else
boonshen	0:a35c40f49345	2240	{
boonshen	0:a35c40f49345	2241	return(0U);
boonshen	0:a35c40f49345	2242	}
boonshen	0:a35c40f49345	2243	}
boonshen	0:a35c40f49345	2244
boonshen	0:a35c40f49345	2245
boonshen	0:a35c40f49345	2246	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen	0:a35c40f49345	2247	/**
boonshen	0:a35c40f49345	2248	\brief Get Interrupt Target State
boonshen	0:a35c40f49345	2249	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
boonshen	0:a35c40f49345	2250	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2251	\return 0 if interrupt is assigned to Secure
boonshen	0:a35c40f49345	2252	\return 1 if interrupt is assigned to Non Secure
boonshen	0:a35c40f49345	2253	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2254	*/
boonshen	0:a35c40f49345	2255	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2256	{
boonshen	0:a35c40f49345	2257	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2258	{
boonshen	0:a35c40f49345	2259	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2260	}
boonshen	0:a35c40f49345	2261	else
boonshen	0:a35c40f49345	2262	{
boonshen	0:a35c40f49345	2263	return(0U);
boonshen	0:a35c40f49345	2264	}
boonshen	0:a35c40f49345	2265	}
boonshen	0:a35c40f49345	2266
boonshen	0:a35c40f49345	2267
boonshen	0:a35c40f49345	2268	/**
boonshen	0:a35c40f49345	2269	\brief Set Interrupt Target State
boonshen	0:a35c40f49345	2270	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
boonshen	0:a35c40f49345	2271	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2272	\return 0 if interrupt is assigned to Secure
boonshen	0:a35c40f49345	2273	1 if interrupt is assigned to Non Secure
boonshen	0:a35c40f49345	2274	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2275	*/
boonshen	0:a35c40f49345	2276	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2277	{
boonshen	0:a35c40f49345	2278	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2279	{
boonshen	0:a35c40f49345	2280	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
boonshen	0:a35c40f49345	2281	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2282	}
boonshen	0:a35c40f49345	2283	else
boonshen	0:a35c40f49345	2284	{
boonshen	0:a35c40f49345	2285	return(0U);
boonshen	0:a35c40f49345	2286	}
boonshen	0:a35c40f49345	2287	}
boonshen	0:a35c40f49345	2288
boonshen	0:a35c40f49345	2289
boonshen	0:a35c40f49345	2290	/**
boonshen	0:a35c40f49345	2291	\brief Clear Interrupt Target State
boonshen	0:a35c40f49345	2292	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
boonshen	0:a35c40f49345	2293	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2294	\return 0 if interrupt is assigned to Secure
boonshen	0:a35c40f49345	2295	1 if interrupt is assigned to Non Secure
boonshen	0:a35c40f49345	2296	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2297	*/
boonshen	0:a35c40f49345	2298	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2299	{
boonshen	0:a35c40f49345	2300	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2301	{
boonshen	0:a35c40f49345	2302	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
boonshen	0:a35c40f49345	2303	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2304	}
boonshen	0:a35c40f49345	2305	else
boonshen	0:a35c40f49345	2306	{
boonshen	0:a35c40f49345	2307	return(0U);
boonshen	0:a35c40f49345	2308	}
boonshen	0:a35c40f49345	2309	}
boonshen	0:a35c40f49345	2310	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen	0:a35c40f49345	2311
boonshen	0:a35c40f49345	2312
boonshen	0:a35c40f49345	2313	/**
boonshen	0:a35c40f49345	2314	\brief Set Interrupt Priority
boonshen	0:a35c40f49345	2315	\details Sets the priority of a device specific interrupt or a processor exception.
boonshen	0:a35c40f49345	2316	The interrupt number can be positive to specify a device specific interrupt,
boonshen	0:a35c40f49345	2317	or negative to specify a processor exception.
boonshen	0:a35c40f49345	2318	\param [in] IRQn Interrupt number.
boonshen	0:a35c40f49345	2319	\param [in] priority Priority to set.
boonshen	0:a35c40f49345	2320	\note The priority cannot be set for every processor exception.
boonshen	0:a35c40f49345	2321	*/
boonshen	0:a35c40f49345	2322	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
boonshen	0:a35c40f49345	2323	{
boonshen	0:a35c40f49345	2324	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2325	{
boonshen	0:a35c40f49345	2326	NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
boonshen	0:a35c40f49345	2327	}
boonshen	0:a35c40f49345	2328	else
boonshen	0:a35c40f49345	2329	{
boonshen	0:a35c40f49345	2330	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
boonshen	0:a35c40f49345	2331	}
boonshen	0:a35c40f49345	2332	}
boonshen	0:a35c40f49345	2333
boonshen	0:a35c40f49345	2334
boonshen	0:a35c40f49345	2335	/**
boonshen	0:a35c40f49345	2336	\brief Get Interrupt Priority
boonshen	0:a35c40f49345	2337	\details Reads the priority of a device specific interrupt or a processor exception.
boonshen	0:a35c40f49345	2338	The interrupt number can be positive to specify a device specific interrupt,
boonshen	0:a35c40f49345	2339	or negative to specify a processor exception.
boonshen	0:a35c40f49345	2340	\param [in] IRQn Interrupt number.
boonshen	0:a35c40f49345	2341	\return Interrupt Priority.
boonshen	0:a35c40f49345	2342	Value is aligned automatically to the implemented priority bits of the microcontroller.
boonshen	0:a35c40f49345	2343	*/
boonshen	0:a35c40f49345	2344	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2345	{
boonshen	0:a35c40f49345	2346
boonshen	0:a35c40f49345	2347	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2348	{
boonshen	0:a35c40f49345	2349	return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
boonshen	0:a35c40f49345	2350	}
boonshen	0:a35c40f49345	2351	else
boonshen	0:a35c40f49345	2352	{
boonshen	0:a35c40f49345	2353	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
boonshen	0:a35c40f49345	2354	}
boonshen	0:a35c40f49345	2355	}
boonshen	0:a35c40f49345	2356
boonshen	0:a35c40f49345	2357
boonshen	0:a35c40f49345	2358	/**
boonshen	0:a35c40f49345	2359	\brief Encode Priority
boonshen	0:a35c40f49345	2360	\details Encodes the priority for an interrupt with the given priority group,
boonshen	0:a35c40f49345	2361	preemptive priority value, and subpriority value.
boonshen	0:a35c40f49345	2362	In case of a conflict between priority grouping and available
boonshen	0:a35c40f49345	2363	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
boonshen	0:a35c40f49345	2364	\param [in] PriorityGroup Used priority group.
boonshen	0:a35c40f49345	2365	\param [in] PreemptPriority Preemptive priority value (starting from 0).
boonshen	0:a35c40f49345	2366	\param [in] SubPriority Subpriority value (starting from 0).
boonshen	0:a35c40f49345	2367	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
boonshen	0:a35c40f49345	2368	*/
boonshen	0:a35c40f49345	2369	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
boonshen	0:a35c40f49345	2370	{
boonshen	0:a35c40f49345	2371	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
boonshen	0:a35c40f49345	2372	uint32_t PreemptPriorityBits;
boonshen	0:a35c40f49345	2373	uint32_t SubPriorityBits;
boonshen	0:a35c40f49345	2374
boonshen	0:a35c40f49345	2375	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
boonshen	0:a35c40f49345	2376	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
boonshen	0:a35c40f49345	2377
boonshen	0:a35c40f49345	2378	return (
boonshen	0:a35c40f49345	2379	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
boonshen	0:a35c40f49345	2380	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
boonshen	0:a35c40f49345	2381	);
boonshen	0:a35c40f49345	2382	}
boonshen	0:a35c40f49345	2383
boonshen	0:a35c40f49345	2384
boonshen	0:a35c40f49345	2385	/**
boonshen	0:a35c40f49345	2386	\brief Decode Priority
boonshen	0:a35c40f49345	2387	\details Decodes an interrupt priority value with a given priority group to
boonshen	0:a35c40f49345	2388	preemptive priority value and subpriority value.
boonshen	0:a35c40f49345	2389	In case of a conflict between priority grouping and available
boonshen	0:a35c40f49345	2390	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
boonshen	0:a35c40f49345	2391	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
boonshen	0:a35c40f49345	2392	\param [in] PriorityGroup Used priority group.
boonshen	0:a35c40f49345	2393	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
boonshen	0:a35c40f49345	2394	\param [out] pSubPriority Subpriority value (starting from 0).
boonshen	0:a35c40f49345	2395	*/
boonshen	0:a35c40f49345	2396	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
boonshen	0:a35c40f49345	2397	{
boonshen	0:a35c40f49345	2398	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
boonshen	0:a35c40f49345	2399	uint32_t PreemptPriorityBits;
boonshen	0:a35c40f49345	2400	uint32_t SubPriorityBits;
boonshen	0:a35c40f49345	2401
boonshen	0:a35c40f49345	2402	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
boonshen	0:a35c40f49345	2403	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
boonshen	0:a35c40f49345	2404
boonshen	0:a35c40f49345	2405	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
boonshen	0:a35c40f49345	2406	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
boonshen	0:a35c40f49345	2407	}
boonshen	0:a35c40f49345	2408
boonshen	0:a35c40f49345	2409
boonshen	0:a35c40f49345	2410	/**
boonshen	0:a35c40f49345	2411	\brief Set Interrupt Vector
boonshen	0:a35c40f49345	2412	\details Sets an interrupt vector in SRAM based interrupt vector table.
boonshen	0:a35c40f49345	2413	The interrupt number can be positive to specify a device specific interrupt,
boonshen	0:a35c40f49345	2414	or negative to specify a processor exception.
boonshen	0:a35c40f49345	2415	VTOR must been relocated to SRAM before.
boonshen	0:a35c40f49345	2416	\param [in] IRQn Interrupt number
boonshen	0:a35c40f49345	2417	\param [in] vector Address of interrupt handler function
boonshen	0:a35c40f49345	2418	*/
boonshen	0:a35c40f49345	2419	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
boonshen	0:a35c40f49345	2420	{
boonshen	0:a35c40f49345	2421	uint32_t vectors = (uint32_t )SCB->VTOR;
boonshen	0:a35c40f49345	2422	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
boonshen	0:a35c40f49345	2423	}
boonshen	0:a35c40f49345	2424
boonshen	0:a35c40f49345	2425
boonshen	0:a35c40f49345	2426	/**
boonshen	0:a35c40f49345	2427	\brief Get Interrupt Vector
boonshen	0:a35c40f49345	2428	\details Reads an interrupt vector from interrupt vector table.
boonshen	0:a35c40f49345	2429	The interrupt number can be positive to specify a device specific interrupt,
boonshen	0:a35c40f49345	2430	or negative to specify a processor exception.
boonshen	0:a35c40f49345	2431	\param [in] IRQn Interrupt number.
boonshen	0:a35c40f49345	2432	\return Address of interrupt handler function
boonshen	0:a35c40f49345	2433	*/
boonshen	0:a35c40f49345	2434	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2435	{
boonshen	0:a35c40f49345	2436	uint32_t vectors = (uint32_t )SCB->VTOR;
boonshen	0:a35c40f49345	2437	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
boonshen	0:a35c40f49345	2438	}
boonshen	0:a35c40f49345	2439
boonshen	0:a35c40f49345	2440
boonshen	0:a35c40f49345	2441	/**
boonshen	0:a35c40f49345	2442	\brief System Reset
boonshen	0:a35c40f49345	2443	\details Initiates a system reset request to reset the MCU.
boonshen	0:a35c40f49345	2444	*/
boonshen	0:a35c40f49345	2445	__STATIC_INLINE void __NVIC_SystemReset(void)
boonshen	0:a35c40f49345	2446	{
boonshen	0:a35c40f49345	2447	__DSB(); /* Ensure all outstanding memory accesses included
boonshen	0:a35c40f49345	2448	buffered write are completed before reset */
boonshen	0:a35c40f49345	2449	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
boonshen	0:a35c40f49345	2450	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
boonshen	0:a35c40f49345	2451	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
boonshen	0:a35c40f49345	2452	__DSB(); /* Ensure completion of memory access */
boonshen	0:a35c40f49345	2453
boonshen	0:a35c40f49345	2454	for(;;) /* wait until reset */
boonshen	0:a35c40f49345	2455	{
boonshen	0:a35c40f49345	2456	__NOP();
boonshen	0:a35c40f49345	2457	}
boonshen	0:a35c40f49345	2458	}
boonshen	0:a35c40f49345	2459
boonshen	0:a35c40f49345	2460	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen	0:a35c40f49345	2461	/**
boonshen	0:a35c40f49345	2462	\brief Set Priority Grouping (non-secure)
boonshen	0:a35c40f49345	2463	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
boonshen	0:a35c40f49345	2464	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
boonshen	0:a35c40f49345	2465	Only values from 0..7 are used.
boonshen	0:a35c40f49345	2466	In case of a conflict between priority grouping and available
boonshen	0:a35c40f49345	2467	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
boonshen	0:a35c40f49345	2468	\param [in] PriorityGroup Priority grouping field.
boonshen	0:a35c40f49345	2469	*/
boonshen	0:a35c40f49345	2470	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
boonshen	0:a35c40f49345	2471	{
boonshen	0:a35c40f49345	2472	uint32_t reg_value;
boonshen	0:a35c40f49345	2473	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
boonshen	0:a35c40f49345	2474
boonshen	0:a35c40f49345	2475	reg_value = SCB_NS->AIRCR; /* read old register configuration */
boonshen	0:a35c40f49345	2476	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
boonshen	0:a35c40f49345	2477	reg_value = (reg_value \|
boonshen	0:a35c40f49345	2478	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
boonshen	0:a35c40f49345	2479	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
boonshen	0:a35c40f49345	2480	SCB_NS->AIRCR = reg_value;
boonshen	0:a35c40f49345	2481	}
boonshen	0:a35c40f49345	2482
boonshen	0:a35c40f49345	2483
boonshen	0:a35c40f49345	2484	/**
boonshen	0:a35c40f49345	2485	\brief Get Priority Grouping (non-secure)
boonshen	0:a35c40f49345	2486	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
boonshen	0:a35c40f49345	2487	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
boonshen	0:a35c40f49345	2488	*/
boonshen	0:a35c40f49345	2489	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
boonshen	0:a35c40f49345	2490	{
boonshen	0:a35c40f49345	2491	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
boonshen	0:a35c40f49345	2492	}
boonshen	0:a35c40f49345	2493
boonshen	0:a35c40f49345	2494
boonshen	0:a35c40f49345	2495	/**
boonshen	0:a35c40f49345	2496	\brief Enable Interrupt (non-secure)
boonshen	0:a35c40f49345	2497	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
boonshen	0:a35c40f49345	2498	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2499	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2500	*/
boonshen	0:a35c40f49345	2501	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2502	{
boonshen	0:a35c40f49345	2503	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2504	{
boonshen	0:a35c40f49345	2505	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2506	}
boonshen	0:a35c40f49345	2507	}
boonshen	0:a35c40f49345	2508
boonshen	0:a35c40f49345	2509
boonshen	0:a35c40f49345	2510	/**
boonshen	0:a35c40f49345	2511	\brief Get Interrupt Enable status (non-secure)
boonshen	0:a35c40f49345	2512	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
boonshen	0:a35c40f49345	2513	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2514	\return 0 Interrupt is not enabled.
boonshen	0:a35c40f49345	2515	\return 1 Interrupt is enabled.
boonshen	0:a35c40f49345	2516	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2517	*/
boonshen	0:a35c40f49345	2518	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2519	{
boonshen	0:a35c40f49345	2520	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2521	{
boonshen	0:a35c40f49345	2522	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2523	}
boonshen	0:a35c40f49345	2524	else
boonshen	0:a35c40f49345	2525	{
boonshen	0:a35c40f49345	2526	return(0U);
boonshen	0:a35c40f49345	2527	}
boonshen	0:a35c40f49345	2528	}
boonshen	0:a35c40f49345	2529
boonshen	0:a35c40f49345	2530
boonshen	0:a35c40f49345	2531	/**
boonshen	0:a35c40f49345	2532	\brief Disable Interrupt (non-secure)
boonshen	0:a35c40f49345	2533	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
boonshen	0:a35c40f49345	2534	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2535	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2536	*/
boonshen	0:a35c40f49345	2537	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2538	{
boonshen	0:a35c40f49345	2539	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2540	{
boonshen	0:a35c40f49345	2541	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2542	}
boonshen	0:a35c40f49345	2543	}
boonshen	0:a35c40f49345	2544
boonshen	0:a35c40f49345	2545
boonshen	0:a35c40f49345	2546	/**
boonshen	0:a35c40f49345	2547	\brief Get Pending Interrupt (non-secure)
boonshen	0:a35c40f49345	2548	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
boonshen	0:a35c40f49345	2549	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2550	\return 0 Interrupt status is not pending.
boonshen	0:a35c40f49345	2551	\return 1 Interrupt status is pending.
boonshen	0:a35c40f49345	2552	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2553	*/
boonshen	0:a35c40f49345	2554	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2555	{
boonshen	0:a35c40f49345	2556	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2557	{
boonshen	0:a35c40f49345	2558	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2559	}
boonshen	0:a35c40f49345	2560	else
boonshen	0:a35c40f49345	2561	{
boonshen	0:a35c40f49345	2562	return(0U);
boonshen	0:a35c40f49345	2563	}
boonshen	0:a35c40f49345	2564	}
boonshen	0:a35c40f49345	2565
boonshen	0:a35c40f49345	2566
boonshen	0:a35c40f49345	2567	/**
boonshen	0:a35c40f49345	2568	\brief Set Pending Interrupt (non-secure)
boonshen	0:a35c40f49345	2569	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
boonshen	0:a35c40f49345	2570	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2571	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2572	*/
boonshen	0:a35c40f49345	2573	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2574	{
boonshen	0:a35c40f49345	2575	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2576	{
boonshen	0:a35c40f49345	2577	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2578	}
boonshen	0:a35c40f49345	2579	}
boonshen	0:a35c40f49345	2580
boonshen	0:a35c40f49345	2581
boonshen	0:a35c40f49345	2582	/**
boonshen	0:a35c40f49345	2583	\brief Clear Pending Interrupt (non-secure)
boonshen	0:a35c40f49345	2584	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
boonshen	0:a35c40f49345	2585	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2586	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2587	*/
boonshen	0:a35c40f49345	2588	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2589	{
boonshen	0:a35c40f49345	2590	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2591	{
boonshen	0:a35c40f49345	2592	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
boonshen	0:a35c40f49345	2593	}
boonshen	0:a35c40f49345	2594	}
boonshen	0:a35c40f49345	2595
boonshen	0:a35c40f49345	2596
boonshen	0:a35c40f49345	2597	/**
boonshen	0:a35c40f49345	2598	\brief Get Active Interrupt (non-secure)
boonshen	0:a35c40f49345	2599	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
boonshen	0:a35c40f49345	2600	\param [in] IRQn Device specific interrupt number.
boonshen	0:a35c40f49345	2601	\return 0 Interrupt status is not active.
boonshen	0:a35c40f49345	2602	\return 1 Interrupt status is active.
boonshen	0:a35c40f49345	2603	\note IRQn must not be negative.
boonshen	0:a35c40f49345	2604	*/
boonshen	0:a35c40f49345	2605	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2606	{
boonshen	0:a35c40f49345	2607	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2608	{
boonshen	0:a35c40f49345	2609	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
boonshen	0:a35c40f49345	2610	}
boonshen	0:a35c40f49345	2611	else
boonshen	0:a35c40f49345	2612	{
boonshen	0:a35c40f49345	2613	return(0U);
boonshen	0:a35c40f49345	2614	}
boonshen	0:a35c40f49345	2615	}
boonshen	0:a35c40f49345	2616
boonshen	0:a35c40f49345	2617
boonshen	0:a35c40f49345	2618	/**
boonshen	0:a35c40f49345	2619	\brief Set Interrupt Priority (non-secure)
boonshen	0:a35c40f49345	2620	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
boonshen	0:a35c40f49345	2621	The interrupt number can be positive to specify a device specific interrupt,
boonshen	0:a35c40f49345	2622	or negative to specify a processor exception.
boonshen	0:a35c40f49345	2623	\param [in] IRQn Interrupt number.
boonshen	0:a35c40f49345	2624	\param [in] priority Priority to set.
boonshen	0:a35c40f49345	2625	\note The priority cannot be set for every non-secure processor exception.
boonshen	0:a35c40f49345	2626	*/
boonshen	0:a35c40f49345	2627	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
boonshen	0:a35c40f49345	2628	{
boonshen	0:a35c40f49345	2629	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2630	{
boonshen	0:a35c40f49345	2631	NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
boonshen	0:a35c40f49345	2632	}
boonshen	0:a35c40f49345	2633	else
boonshen	0:a35c40f49345	2634	{
boonshen	0:a35c40f49345	2635	SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
boonshen	0:a35c40f49345	2636	}
boonshen	0:a35c40f49345	2637	}
boonshen	0:a35c40f49345	2638
boonshen	0:a35c40f49345	2639
boonshen	0:a35c40f49345	2640	/**
boonshen	0:a35c40f49345	2641	\brief Get Interrupt Priority (non-secure)
boonshen	0:a35c40f49345	2642	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
boonshen	0:a35c40f49345	2643	The interrupt number can be positive to specify a device specific interrupt,
boonshen	0:a35c40f49345	2644	or negative to specify a processor exception.
boonshen	0:a35c40f49345	2645	\param [in] IRQn Interrupt number.
boonshen	0:a35c40f49345	2646	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
boonshen	0:a35c40f49345	2647	*/
boonshen	0:a35c40f49345	2648	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
boonshen	0:a35c40f49345	2649	{
boonshen	0:a35c40f49345	2650
boonshen	0:a35c40f49345	2651	if ((int32_t)(IRQn) >= 0)
boonshen	0:a35c40f49345	2652	{
boonshen	0:a35c40f49345	2653	return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
boonshen	0:a35c40f49345	2654	}
boonshen	0:a35c40f49345	2655	else
boonshen	0:a35c40f49345	2656	{
boonshen	0:a35c40f49345	2657	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
boonshen	0:a35c40f49345	2658	}
boonshen	0:a35c40f49345	2659	}
boonshen	0:a35c40f49345	2660	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
boonshen	0:a35c40f49345	2661
boonshen	0:a35c40f49345	2662	/@} end of CMSIS_Core_NVICFunctions /
boonshen	0:a35c40f49345	2663
boonshen	0:a35c40f49345	2664
boonshen	0:a35c40f49345	2665	/* ########################## FPU functions #################################### */
boonshen	0:a35c40f49345	2666	/**
boonshen	0:a35c40f49345	2667	\ingroup CMSIS_Core_FunctionInterface
boonshen	0:a35c40f49345	2668	\defgroup CMSIS_Core_FpuFunctions FPU Functions
boonshen	0:a35c40f49345	2669	\brief Function that provides FPU type.
boonshen	0:a35c40f49345	2670	@{
boonshen	0:a35c40f49345	2671	*/
boonshen	0:a35c40f49345	2672
boonshen	0:a35c40f49345	2673	/**
boonshen	0:a35c40f49345	2674	\brief get FPU type
boonshen	0:a35c40f49345	2675	\details returns the FPU type
boonshen	0:a35c40f49345	2676	\returns
boonshen	0:a35c40f49345	2677	- \b 0: No FPU
boonshen	0:a35c40f49345	2678	- \b 1: Single precision FPU
boonshen	0:a35c40f49345	2679	- \b 2: Double + Single precision FPU
boonshen	0:a35c40f49345	2680	*/
boonshen	0:a35c40f49345	2681	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
boonshen	0:a35c40f49345	2682	{
boonshen	0:a35c40f49345	2683	uint32_t mvfr0;
boonshen	0:a35c40f49345	2684
boonshen	0:a35c40f49345	2685	mvfr0 = FPU->MVFR0;
boonshen	0:a35c40f49345	2686	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
boonshen	0:a35c40f49345	2687	{
boonshen	0:a35c40f49345	2688	return 2U; /* Double + Single precision FPU */
boonshen	0:a35c40f49345	2689	}
boonshen	0:a35c40f49345	2690	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
boonshen	0:a35c40f49345	2691	{
boonshen	0:a35c40f49345	2692	return 1U; /* Single precision FPU */
boonshen	0:a35c40f49345	2693	}
boonshen	0:a35c40f49345	2694	else
boonshen	0:a35c40f49345	2695	{
boonshen	0:a35c40f49345	2696	return 0U; /* No FPU */
boonshen	0:a35c40f49345	2697	}
boonshen	0:a35c40f49345	2698	}
boonshen	0:a35c40f49345	2699
boonshen	0:a35c40f49345	2700
boonshen	0:a35c40f49345	2701	/@} end of CMSIS_Core_FpuFunctions /
boonshen	0:a35c40f49345	2702
boonshen	0:a35c40f49345	2703
boonshen	0:a35c40f49345	2704
boonshen	0:a35c40f49345	2705	/* ########################## SAU functions #################################### */
boonshen	0:a35c40f49345	2706	/**
boonshen	0:a35c40f49345	2707	\ingroup CMSIS_Core_FunctionInterface
boonshen	0:a35c40f49345	2708	\defgroup CMSIS_Core_SAUFunctions SAU Functions
boonshen	0:a35c40f49345	2709	\brief Functions that configure the SAU.
boonshen	0:a35c40f49345	2710	@{
boonshen	0:a35c40f49345	2711	*/
boonshen	0:a35c40f49345	2712
boonshen	0:a35c40f49345	2713	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen	0:a35c40f49345	2714
boonshen	0:a35c40f49345	2715	/**
boonshen	0:a35c40f49345	2716	\brief Enable SAU
boonshen	0:a35c40f49345	2717	\details Enables the Security Attribution Unit (SAU).
boonshen	0:a35c40f49345	2718	*/
boonshen	0:a35c40f49345	2719	__STATIC_INLINE void TZ_SAU_Enable(void)
boonshen	0:a35c40f49345	2720	{
boonshen	0:a35c40f49345	2721	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
boonshen	0:a35c40f49345	2722	}
boonshen	0:a35c40f49345	2723
boonshen	0:a35c40f49345	2724
boonshen	0:a35c40f49345	2725
boonshen	0:a35c40f49345	2726	/**
boonshen	0:a35c40f49345	2727	\brief Disable SAU
boonshen	0:a35c40f49345	2728	\details Disables the Security Attribution Unit (SAU).
boonshen	0:a35c40f49345	2729	*/
boonshen	0:a35c40f49345	2730	__STATIC_INLINE void TZ_SAU_Disable(void)
boonshen	0:a35c40f49345	2731	{
boonshen	0:a35c40f49345	2732	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
boonshen	0:a35c40f49345	2733	}
boonshen	0:a35c40f49345	2734
boonshen	0:a35c40f49345	2735	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen	0:a35c40f49345	2736
boonshen	0:a35c40f49345	2737	/@} end of CMSIS_Core_SAUFunctions /
boonshen	0:a35c40f49345	2738
boonshen	0:a35c40f49345	2739
boonshen	0:a35c40f49345	2740
boonshen	0:a35c40f49345	2741
boonshen	0:a35c40f49345	2742	/* ################################## SysTick function ############################################ */
boonshen	0:a35c40f49345	2743	/**
boonshen	0:a35c40f49345	2744	\ingroup CMSIS_Core_FunctionInterface
boonshen	0:a35c40f49345	2745	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
boonshen	0:a35c40f49345	2746	\brief Functions that configure the System.
boonshen	0:a35c40f49345	2747	@{
boonshen	0:a35c40f49345	2748	*/
boonshen	0:a35c40f49345	2749
boonshen	0:a35c40f49345	2750	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
boonshen	0:a35c40f49345	2751
boonshen	0:a35c40f49345	2752	/**
boonshen	0:a35c40f49345	2753	\brief System Tick Configuration
boonshen	0:a35c40f49345	2754	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
boonshen	0:a35c40f49345	2755	Counter is in free running mode to generate periodic interrupts.
boonshen	0:a35c40f49345	2756	\param [in] ticks Number of ticks between two interrupts.
boonshen	0:a35c40f49345	2757	\return 0 Function succeeded.
boonshen	0:a35c40f49345	2758	\return 1 Function failed.
boonshen	0:a35c40f49345	2759	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
boonshen	0:a35c40f49345	2760	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
boonshen	0:a35c40f49345	2761	must contain a vendor-specific implementation of this function.
boonshen	0:a35c40f49345	2762	*/
boonshen	0:a35c40f49345	2763	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
boonshen	0:a35c40f49345	2764	{
boonshen	0:a35c40f49345	2765	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
boonshen	0:a35c40f49345	2766	{
boonshen	0:a35c40f49345	2767	return (1UL); /* Reload value impossible */
boonshen	0:a35c40f49345	2768	}
boonshen	0:a35c40f49345	2769
boonshen	0:a35c40f49345	2770	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
boonshen	0:a35c40f49345	2771	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
boonshen	0:a35c40f49345	2772	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
boonshen	0:a35c40f49345	2773	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
boonshen	0:a35c40f49345	2774	SysTick_CTRL_TICKINT_Msk \|
boonshen	0:a35c40f49345	2775	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
boonshen	0:a35c40f49345	2776	return (0UL); /* Function successful */
boonshen	0:a35c40f49345	2777	}
boonshen	0:a35c40f49345	2778
boonshen	0:a35c40f49345	2779	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
boonshen	0:a35c40f49345	2780	/**
boonshen	0:a35c40f49345	2781	\brief System Tick Configuration (non-secure)
boonshen	0:a35c40f49345	2782	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
boonshen	0:a35c40f49345	2783	Counter is in free running mode to generate periodic interrupts.
boonshen	0:a35c40f49345	2784	\param [in] ticks Number of ticks between two interrupts.
boonshen	0:a35c40f49345	2785	\return 0 Function succeeded.
boonshen	0:a35c40f49345	2786	\return 1 Function failed.
boonshen	0:a35c40f49345	2787	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
boonshen	0:a35c40f49345	2788	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
boonshen	0:a35c40f49345	2789	must contain a vendor-specific implementation of this function.
boonshen	0:a35c40f49345	2790
boonshen	0:a35c40f49345	2791	*/
boonshen	0:a35c40f49345	2792	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
boonshen	0:a35c40f49345	2793	{
boonshen	0:a35c40f49345	2794	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
boonshen	0:a35c40f49345	2795	{
boonshen	0:a35c40f49345	2796	return (1UL); /* Reload value impossible */
boonshen	0:a35c40f49345	2797	}
boonshen	0:a35c40f49345	2798
boonshen	0:a35c40f49345	2799	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
boonshen	0:a35c40f49345	2800	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
boonshen	0:a35c40f49345	2801	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
boonshen	0:a35c40f49345	2802	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
boonshen	0:a35c40f49345	2803	SysTick_CTRL_TICKINT_Msk \|
boonshen	0:a35c40f49345	2804	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
boonshen	0:a35c40f49345	2805	return (0UL); /* Function successful */
boonshen	0:a35c40f49345	2806	}
boonshen	0:a35c40f49345	2807	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
boonshen	0:a35c40f49345	2808
boonshen	0:a35c40f49345	2809	#endif
boonshen	0:a35c40f49345	2810
boonshen	0:a35c40f49345	2811	/@} end of CMSIS_Core_SysTickFunctions /
boonshen	0:a35c40f49345	2812
boonshen	0:a35c40f49345	2813
boonshen	0:a35c40f49345	2814
boonshen	0:a35c40f49345	2815	/* ##################################### Debug In/Output function ########################################### */
boonshen	0:a35c40f49345	2816	/**
boonshen	0:a35c40f49345	2817	\ingroup CMSIS_Core_FunctionInterface
boonshen	0:a35c40f49345	2818	\defgroup CMSIS_core_DebugFunctions ITM Functions
boonshen	0:a35c40f49345	2819	\brief Functions that access the ITM debug interface.
boonshen	0:a35c40f49345	2820	@{
boonshen	0:a35c40f49345	2821	*/
boonshen	0:a35c40f49345	2822
boonshen	0:a35c40f49345	2823	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
boonshen	0:a35c40f49345	2824	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
boonshen	0:a35c40f49345	2825
boonshen	0:a35c40f49345	2826
boonshen	0:a35c40f49345	2827	/**
boonshen	0:a35c40f49345	2828	\brief ITM Send Character
boonshen	0:a35c40f49345	2829	\details Transmits a character via the ITM channel 0, and
boonshen	0:a35c40f49345	2830	\li Just returns when no debugger is connected that has booked the output.
boonshen	0:a35c40f49345	2831	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
boonshen	0:a35c40f49345	2832	\param [in] ch Character to transmit.
boonshen	0:a35c40f49345	2833	\returns Character to transmit.
boonshen	0:a35c40f49345	2834	*/
boonshen	0:a35c40f49345	2835	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
boonshen	0:a35c40f49345	2836	{
boonshen	0:a35c40f49345	2837	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
boonshen	0:a35c40f49345	2838	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
boonshen	0:a35c40f49345	2839	{
boonshen	0:a35c40f49345	2840	while (ITM->PORT[0U].u32 == 0UL)
boonshen	0:a35c40f49345	2841	{
boonshen	0:a35c40f49345	2842	__NOP();
boonshen	0:a35c40f49345	2843	}
boonshen	0:a35c40f49345	2844	ITM->PORT[0U].u8 = (uint8_t)ch;
boonshen	0:a35c40f49345	2845	}
boonshen	0:a35c40f49345	2846	return (ch);
boonshen	0:a35c40f49345	2847	}
boonshen	0:a35c40f49345	2848
boonshen	0:a35c40f49345	2849
boonshen	0:a35c40f49345	2850	/**
boonshen	0:a35c40f49345	2851	\brief ITM Receive Character
boonshen	0:a35c40f49345	2852	\details Inputs a character via the external variable \ref ITM_RxBuffer.
boonshen	0:a35c40f49345	2853	\return Received character.
boonshen	0:a35c40f49345	2854	\return -1 No character pending.
boonshen	0:a35c40f49345	2855	*/
boonshen	0:a35c40f49345	2856	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
boonshen	0:a35c40f49345	2857	{
boonshen	0:a35c40f49345	2858	int32_t ch = -1; /* no character available */
boonshen	0:a35c40f49345	2859
boonshen	0:a35c40f49345	2860	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
boonshen	0:a35c40f49345	2861	{
boonshen	0:a35c40f49345	2862	ch = ITM_RxBuffer;
boonshen	0:a35c40f49345	2863	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
boonshen	0:a35c40f49345	2864	}
boonshen	0:a35c40f49345	2865
boonshen	0:a35c40f49345	2866	return (ch);
boonshen	0:a35c40f49345	2867	}
boonshen	0:a35c40f49345	2868
boonshen	0:a35c40f49345	2869
boonshen	0:a35c40f49345	2870	/**
boonshen	0:a35c40f49345	2871	\brief ITM Check Character
boonshen	0:a35c40f49345	2872	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
boonshen	0:a35c40f49345	2873	\return 0 No character available.
boonshen	0:a35c40f49345	2874	\return 1 Character available.
boonshen	0:a35c40f49345	2875	*/
boonshen	0:a35c40f49345	2876	__STATIC_INLINE int32_t ITM_CheckChar (void)
boonshen	0:a35c40f49345	2877	{
boonshen	0:a35c40f49345	2878
boonshen	0:a35c40f49345	2879	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
boonshen	0:a35c40f49345	2880	{
boonshen	0:a35c40f49345	2881	return (0); /* no character available */
boonshen	0:a35c40f49345	2882	}
boonshen	0:a35c40f49345	2883	else
boonshen	0:a35c40f49345	2884	{
boonshen	0:a35c40f49345	2885	return (1); /* character available */
boonshen	0:a35c40f49345	2886	}
boonshen	0:a35c40f49345	2887	}
boonshen	0:a35c40f49345	2888
boonshen	0:a35c40f49345	2889	/@} end of CMSIS_core_DebugFunctions /
boonshen	0:a35c40f49345	2890
boonshen	0:a35c40f49345	2891
boonshen	0:a35c40f49345	2892
boonshen	0:a35c40f49345	2893
boonshen	0:a35c40f49345	2894	#ifdef __cplusplus
boonshen	0:a35c40f49345	2895	}
boonshen	0:a35c40f49345	2896	#endif
boonshen	0:a35c40f49345	2897
boonshen	0:a35c40f49345	2898	#endif /* __CORE_ARMV8MML_H_DEPENDANT */
boonshen	0:a35c40f49345	2899
boonshen	0:a35c40f49345	2900	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	13 Mar 2018
Imports:	127
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

FTHR_USB_serial/mbed-os/cmsis/core_armv8mml.h@0:a35c40f49345, 2018-03-13 (annotated)

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