Diff: WS2811.cpp

Revision:

3:df4319053bfa

Parent:

2:9447404f2d16

Child:

4:990838718b51

diff -r 9447404f2d16 -r df4319053bfa WS2811.cpp
--- a/WS2811.cpp	Thu Jun 11 15:32:07 2015 +0000
+++ b/WS2811.cpp	Fri Jun 12 18:23:03 2015 -0700
@@ -1,331 +1,335 @@
-// 800 KHz WS2811 driver driving potentially many LED strings.
-// Uses 3-phase DMA
-// 16K SRAM less stack, etc.
-//
-// Per LED: 3 bytes (malloc'd) for RGB data
-//
-// Per LED strip / per LED
-//          96 bytes (static) for bit data
-//        + 96 bytes (static) for ones data
-//        = 192 bytes
-//
-//        40 LEDs max per string = 7680 bytes static
-//
-//        40 LEDs: 7680 + 40*3 = 7800 bytes
-//        80 LEDs: 7680 + 80*3 = 7920 bytes
-#include <mbed.h>
-#include "MKL25Z4.h"
-
-#ifndef MBED_WS2811_H
-#include "WS2811.h"
-#endif
-
-#if defined(WS2811_DEBUG_PIN)
-#define DEBUG 1
-#define DEBUG_MASK (1<<WS2811_DEBUG_PIN)
-#define RESET_DEBUG (WS2811_IO_GPIO->PDOR &= ~DEBUG_MASK)
-#define SET_DEBUG (WS2811_IO_GPIO->PDOR |= DEBUG_MASK)
-#else
-#define DEBUG_MASK 0
-#define RESET_DEBUG (void)0
-#define SET_DEBUG (void)0
-#endif
-
-static volatile bool dma_done = true;
-
-// 48 MHz clock, no prescaling.
-#define NSEC_TO_TICKS(nsec) ((nsec)*48/1000)
-#define USEC_TO_TICKS(usec) ((usec)*48)
-#define CLK_NSEC         1250
-#define tpm_period       NSEC_TO_TICKS(CLK_NSEC)
-#define tpm_p0_period    NSEC_TO_TICKS(250)
-#define tpm_p1_period    NSEC_TO_TICKS(650)
-#define guardtime_period USEC_TO_TICKS(55)   /* guardtime minimum 50 usec. */
-
-enum DMA_MUX_SRC {
-    DMA_MUX_SRC_TPM0_CH_0     = 24,
-    DMA_MUX_SRC_TPM0_CH_1,
-    DMA_MUX_SRC_TPM0_Overflow = 54,
-};
-
-enum DMA_CHAN {
-    DMA_CHAN_START = 0,
-    DMA_CHAN_0_LOW = 1,
-    DMA_CHAN_1_LOW = 2,
-    N_DMA_CHANNELS
-};
-
-// class static
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::wait_for_dma_done() { while (!dma_done) __WFI(); }
-
-// class static
-template <unsigned MAX_LEDS_PER_STRIP>
-bool WS2811<MAX_LEDS_PER_STRIP>::initialized = false;
-
-// class static
-template <unsigned MAX_LEDS_PER_STRIP>
-uint32_t WS2811<MAX_LEDS_PER_STRIP>::enabledPins = 0;
-
-#define WORD_ALIGNED __attribute__ ((aligned(4)))
-
-// class static
-template <unsigned MAX_LEDS_PER_STRIP>
-struct WS2811<MAX_LEDS_PER_STRIP>::DMALayout WS2811<MAX_LEDS_PER_STRIP>::dmaData WORD_ALIGNED;
-
-// class static
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::hw_init()
-{
-    if (initialized) return;
-
-    dma_data_init();
-    clock_init();
-    dma_init();
-    io_init();
-    tpm_init();
-
-    initialized = true;
-
-    SET_DEBUG;
-    RESET_DEBUG;
-}
-
-// class static
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::dma_data_init()
-{
-    memset(dmaData.allOnes, 0xFF, sizeof(dmaData.allOnes));
-
-#if DEBUG
-    for (unsigned i = 0; i < BITS_PER_RGB * MAX_LEDS_PER_STRIP; i++)
-        dmaData.dmaWords[i] = DEBUG_MASK;
-#endif
-}
-
-// class static
-
-/// Enable PORTD, DMA and TPM0 clocking
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::clock_init()
-{
-    SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
-    SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK | SIM_SCGC6_TPM0_MASK; // Enable clock to DMA mux and TPM0
-    SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;  // Enable clock to DMA
-
-    SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
-}
-
-// class static
-
-/// Configure GPIO output pins
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::io_init()
-{
-    uint32_t m = 1;
-    for (uint32_t i = 0; i < 32; i++) {
-        // set up each pin
-        if (m & enabledPins) {
-            WS2811_IO_PORT->PCR[i] = PORT_PCR_MUX(1) // GPIO
-                              | PORT_PCR_DSE_MASK; // high drive strength
-        }
-        m <<= 1;
-    }
-
-    WS2811_IO_GPIO->PDDR |= enabledPins;      // set as outputs
-
-#if WS2811_MONITOR_TPM0_PWM
-    // PTD0 CH0 monitor: TPM0, high drive strength
-    WS2811_IO_PORT->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
-    // PTD1 CH1 monitor: TPM0, high drive strength
-    WS2811_IO_PORT->PCR[1] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
-    WS2811_IO_GPIO->PDDR  |= 3;               // set as outputs
-    WS2811_IO_GPIO->PDOR &= ~(enabledPins | 3);     // initially low
-#else
-    WS2811_IO_GPIO->PDOR &= ~enabledPins;     // initially low
-#endif
-
-#if DEBUG
-    WS2811_IO_PORT->PCR[WS2811_DEBUG_PIN] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
-    WS2811_IO_GPIO->PDDR |= DEBUG_MASK;
-    WS2811_IO_GPIO->PDOR &= ~DEBUG_MASK;
-#endif
-}
-
-// class static
-
-/// Configure DMA and DMAMUX
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::dma_init()
-{
-    // reset DMAMUX
-    DMAMUX0->CHCFG[DMA_CHAN_START] = 0;
-    DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = 0;
-    DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = 0;
-
-    // wire our DMA event sources into the first three DMA channels
-    // t=0: all enabled outputs go high on TPM0 overflow
-    DMAMUX0->CHCFG[DMA_CHAN_START] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_Overflow);
-    // t=tpm_p0_period: all of the 0 bits go low.
-    DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_0);
-    // t=tpm_p1_period: all outputs go low.
-    DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_1);
-
-    NVIC_SetVector(DMA0_IRQn, (uint32_t)&DMA0_IRQHandler);
-    NVIC_EnableIRQ(DMA0_IRQn);
-}
-
-// class static
-
-/// Configure TPM0 to do two different PWM periods at 800kHz rate
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::tpm_init()
-{
-    // set up TPM0 for proper period (800 kHz = 1.25 usec ±600nsec)
-    TPM_Type volatile *tpm = TPM0;
-    tpm->SC = TPM_SC_DMA_MASK          // enable DMA
-              | TPM_SC_TOF_MASK        // reset TOF flag if set
-              | TPM_SC_CMOD(0)         // disable clocks
-              | TPM_SC_PS(0);          // 48MHz / 1 = 48MHz clock
-    tpm->MOD = tpm_period - 1;         // 48MHz / 800kHz
-
-    // No Interrupts; High True pulses on Edge Aligned PWM
-    tpm->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
-    tpm->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
-
-    // set TPM0 channel 0 for 0.35 usec (±150nsec) (0 code)
-    // 1.25 usec * 1/3 = 417 nsec
-    tpm->CONTROLS[0].CnV = tpm_p0_period;
-
-    // set TPM0 channel 1 for 0.7 usec (±150nsec) (1 code)
-    // 1.25 usec * 2/3 = 833 nsec
-    tpm->CONTROLS[1].CnV = tpm_p1_period;
-
-    NVIC_SetVector(TPM0_IRQn, (uint32_t)&TPM0_IRQHandler);
-    NVIC_EnableIRQ(TPM0_IRQn);
-}
-
-// class static
-template <unsigned MAX_LEDS_PER_STRIP>
-void WS2811<MAX_LEDS_PER_STRIP>::startDMA()
-{
-    if (!initialized) hw_init();
-    
-    wait_for_dma_done();
-    dma_done = false;
-
-    DMA_Type volatile * dma   = DMA0;
-    TPM_Type volatile *tpm   = TPM0;
-    uint32_t nBytes = sizeof(dmaData.start_t1_low)
-                      + sizeof(dmaData.dmaWords)
-                      + sizeof(dmaData.trailing_zeros_1);
-
-    tpm->SC = TPM_SC_DMA_MASK        // enable DMA
-              | TPM_SC_TOF_MASK  // reset TOF flag if set
-              | TPM_SC_CMOD(0)   // disable clocks
-              | TPM_SC_PS(0);    // 48MHz / 1 = 48MHz clock
-    tpm->MOD = tpm_period - 1;       // 48MHz / 800kHz
-
-    tpm->CNT = tpm_p0_period - 2 ;
-    tpm->STATUS = 0xFFFFFFFF;
-
-    dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
-    dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
-    dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
-
-    // t=0: all outputs go high
-    // triggered by TPM0_Overflow
-    // source is one word of 0 then 24 x 0xffffffff, then another 0 word
-    dma->DMA[DMA_CHAN_START].SAR     = (uint32_t)(void*)dmaData.start_t0_high;
-    dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
-
-    // t=tpm_p0_period: some outputs (the 0 bits) go low.
-    // Triggered by TPM0_CH0
-    // Start 2 words before the actual data to avoid garbage pulses.
-    dma->DMA[DMA_CHAN_0_LOW].SAR     = (uint32_t)(void*)dmaData.start_t1_low; // set source address
-    dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
-
-    // t=tpm_p1_period: all outputs go low.
-    // Triggered by TPM0_CH1
-    // source is constant 0x00000000 (first word of dmaWords)
-    dma->DMA[DMA_CHAN_1_LOW].SAR     = (uint32_t)(void*)dmaData.start_t1_low; // set source address
-    dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
-
-    dma->DMA[DMA_CHAN_0_LOW].DAR
-    = dma->DMA[DMA_CHAN_1_LOW].DAR
-      = dma->DMA[DMA_CHAN_START].DAR
-        = (uint32_t)(void*)&WS2811_IO_GPIO->PDOR;
-
-    SET_DEBUG;
-
-    dma->DMA[DMA_CHAN_0_LOW].DCR     = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
-                                       | DMA_DCR_ERQ_MASK
-                                       | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
-                                       | DMA_DCR_SINC_MASK // increment source each transfer
-                                       | DMA_DCR_CS_MASK
-                                       | DMA_DCR_SSIZE(0) // 32-bit source transfers
-                                       | DMA_DCR_DSIZE(0); // 32-bit destination transfers
-
-    dma->DMA[DMA_CHAN_1_LOW].DCR     = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
-                                       | DMA_DCR_ERQ_MASK
-                                       | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
-                                       | DMA_DCR_CS_MASK
-                                       | DMA_DCR_SSIZE(0) // 32-bit source transfers
-                                       | DMA_DCR_DSIZE(0); // 32-bit destination transfers
-
-    dma->DMA[DMA_CHAN_START].DCR     = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
-                                       | DMA_DCR_ERQ_MASK
-                                       | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
-                                       | DMA_DCR_SINC_MASK // increment source each transfer
-                                       | DMA_DCR_CS_MASK
-                                       | DMA_DCR_SSIZE(0) // 32-bit source transfers
-                                       | DMA_DCR_DSIZE(0);
-
-    tpm->SC |= TPM_SC_CMOD(1);         // enable internal clocking
-}
-
-#if !INSTANTIATE_TEMPLATES
-
-extern "C" void DMA0_IRQHandler()
-{
-    DMA_Type volatile *dma = DMA0;
-    TPM_Type volatile *tpm = TPM0;
-
-    uint32_t db;
-
-    db = dma->DMA[DMA_CHAN_0_LOW].DSR_BCR;
-    if (db & DMA_DSR_BCR_DONE_MASK) {
-        dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
-    }
-
-    db = dma->DMA[DMA_CHAN_1_LOW].DSR_BCR;
-    if (db & DMA_DSR_BCR_DONE_MASK) {
-        dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
-    }
-
-    db = dma->DMA[DMA_CHAN_START].DSR_BCR;
-    if (db & DMA_DSR_BCR_DONE_MASK) {
-        dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
-    }
-
-    tpm->SC = TPM_SC_TOF_MASK;  // reset TOF flag; disable internal clocking
-
-    SET_DEBUG;
-
-    // set TPM0 to interrrupt after guardtime
-    tpm->MOD = guardtime_period - 1; // 48MHz * 55 usec
-    tpm->CNT = 0;
-    tpm->SC  = TPM_SC_PS(0)        // 48MHz / 1 = 48MHz clock
-               | TPM_SC_TOIE_MASK  // enable interrupts
-               | TPM_SC_CMOD(1);   // and internal clocking
-}
-
-extern "C" void TPM0_IRQHandler()
-{
-    TPM0->SC = 0; // disable internal clocking
-    TPM0->SC = TPM_SC_TOF_MASK;        
-    RESET_DEBUG;
-    dma_done = true;
-}
-
-#endif
+// 800 KHz WS2811 driver driving potentially many LED strings.
+// Uses 3-phase DMA
+// 16K SRAM less stack, etc.
+//
+// Per LED: 3 bytes (malloc'd) for RGB data
+//
+// Per LED strip / per LED
+//          96 bytes (static) for bit data
+//        + 96 bytes (static) for ones data
+//        = 192 bytes
+//
+//        40 LEDs max per string = 7680 bytes static
+//
+//        40 LEDs: 7680 + 40*3 = 7800 bytes
+//        80 LEDs: 7680 + 80*3 = 7920 bytes
+#include <mbed.h>
+#include "MKL25Z4.h"
+
+#ifndef MBED_WS2811_H
+#include "WS2811.h"
+#endif
+
+#if defined(WS2811_DEBUG_PIN)
+#define DEBUG 1
+#define DEBUG_MASK (1<<WS2811_DEBUG_PIN)
+#define RESET_DEBUG (WS2811_IO_GPIO->PDOR &= ~DEBUG_MASK)
+#define SET_DEBUG (WS2811_IO_GPIO->PDOR |= DEBUG_MASK)
+#else
+#define DEBUG_MASK 0
+#define RESET_DEBUG (void)0
+#define SET_DEBUG (void)0
+#endif
+
+static volatile unsigned dma_done = 0;
+
+// 48 MHz clock, no prescaling.
+#define NSEC_TO_TICKS(nsec) ((nsec)*48/1000)
+#define USEC_TO_TICKS(usec) ((usec)*48)
+#define CLK_NSEC         1250
+#define tpm_period       NSEC_TO_TICKS(CLK_NSEC)
+#define tpm_p0_period    NSEC_TO_TICKS(250)
+#define tpm_p1_period    NSEC_TO_TICKS(650)
+#define guardtime_period USEC_TO_TICKS(55)   /* guardtime minimum 50 usec. */
+
+enum DMA_MUX_SRC {
+    DMA_MUX_SRC_TPM0_CH_0     = 24,
+    DMA_MUX_SRC_TPM0_CH_1,
+    DMA_MUX_SRC_TPM0_Overflow = 54,
+};
+
+enum DMA_CHAN {
+    DMA_CHAN_START = 0,
+    DMA_CHAN_0_LOW = 1,
+    DMA_CHAN_1_LOW = 2,
+    N_DMA_CHANNELS
+};
+
+// class static
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::wait_for_dma_done() { while (dma_done < 1) __WFI(); }
+
+// class static
+template <unsigned MAX_LEDS_PER_STRIP>
+bool WS2811<MAX_LEDS_PER_STRIP>::initialized = false;
+
+// class static
+template <unsigned MAX_LEDS_PER_STRIP>
+uint32_t WS2811<MAX_LEDS_PER_STRIP>::enabledPins = 0;
+
+#define WORD_ALIGNED __attribute__ ((aligned(4)))
+
+// class static
+template <unsigned MAX_LEDS_PER_STRIP>
+struct WS2811<MAX_LEDS_PER_STRIP>::DMALayout WS2811<MAX_LEDS_PER_STRIP>::dmaData WORD_ALIGNED;
+
+// class static
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::hw_init()
+{
+    if (initialized) return;
+
+    dma_data_init();
+    clock_init();
+    dma_init();
+    io_init();
+    tpm_init();
+
+    initialized = true;
+
+    SET_DEBUG;
+    RESET_DEBUG;
+}
+
+// class static
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::dma_data_init()
+{
+    memset(dmaData.allOnes, 0xFF, sizeof(dmaData.allOnes));
+
+#if DEBUG
+    for (unsigned i = 0; i < BITS_PER_RGB * MAX_LEDS_PER_STRIP; i++)
+        dmaData.dmaWords[i] = DEBUG_MASK;
+#endif
+}
+
+// class static
+
+/// Enable PORTD, DMA and TPM0 clocking
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::clock_init()
+{
+    SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
+    SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK | SIM_SCGC6_TPM0_MASK; // Enable clock to DMA mux and TPM0
+    SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;  // Enable clock to DMA
+
+    SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
+}
+
+// class static
+
+/// Configure GPIO output pins
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::io_init()
+{
+    uint32_t m = 1;
+    for (uint32_t i = 0; i < 32; i++) {
+        // set up each pin
+        if (m & enabledPins) {
+            WS2811_IO_PORT->PCR[i] = PORT_PCR_MUX(1) // GPIO
+                              | PORT_PCR_DSE_MASK; // high drive strength
+        }
+        m <<= 1;
+    }
+
+    WS2811_IO_GPIO->PDDR |= enabledPins;      // set as outputs
+
+#if WS2811_MONITOR_TPM0_PWM
+    // PTD0 CH0 monitor: TPM0, high drive strength
+    WS2811_IO_PORT->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
+    // PTD1 CH1 monitor: TPM0, high drive strength
+    WS2811_IO_PORT->PCR[1] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
+    WS2811_IO_GPIO->PDDR  |= 3;               // set as outputs
+    WS2811_IO_GPIO->PDOR &= ~(enabledPins | 3);     // initially low
+#else
+    WS2811_IO_GPIO->PDOR &= ~enabledPins;     // initially low
+#endif
+
+#if DEBUG
+    WS2811_IO_PORT->PCR[WS2811_DEBUG_PIN] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
+    WS2811_IO_GPIO->PDDR |= DEBUG_MASK;
+    WS2811_IO_GPIO->PDOR &= ~DEBUG_MASK;
+#endif
+}
+
+// class static
+
+/// Configure DMA and DMAMUX
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::dma_init()
+{
+    // reset DMAMUX
+    DMAMUX0->CHCFG[DMA_CHAN_START] = 0;
+    DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = 0;
+    DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = 0;
+
+    // wire our DMA event sources into the first three DMA channels
+    // t=0: all enabled outputs go high on TPM0 overflow
+    DMAMUX0->CHCFG[DMA_CHAN_START] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_Overflow);
+    // t=tpm_p0_period: all of the 0 bits go low.
+    DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_0);
+    // t=tpm_p1_period: all outputs go low.
+    DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_1);
+
+    NVIC_SetVector(DMA0_IRQn, (uint32_t)&DMA0_IRQHandler);
+    NVIC_EnableIRQ(DMA0_IRQn);
+}
+
+// class static
+
+/// Configure TPM0 to do two different PWM periods at 800kHz rate
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::tpm_init()
+{
+    // set up TPM0 for proper period (800 kHz = 1.25 usec ±600nsec)
+    TPM_Type volatile *tpm = TPM0;
+    tpm->SC = TPM_SC_DMA_MASK          // enable DMA
+              | TPM_SC_TOF_MASK        // reset TOF flag if set
+              | TPM_SC_CMOD(0)         // disable clocks
+              | TPM_SC_PS(0);          // 48MHz / 1 = 48MHz clock
+    tpm->MOD = tpm_period - 1;         // 48MHz / 800kHz
+
+    // No Interrupts; High True pulses on Edge Aligned PWM
+    tpm->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
+    tpm->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
+
+    // set TPM0 channel 0 for 0.35 usec (±150nsec) (0 code)
+    // 1.25 usec * 1/3 = 417 nsec
+    tpm->CONTROLS[0].CnV = tpm_p0_period;
+
+    // set TPM0 channel 1 for 0.7 usec (±150nsec) (1 code)
+    // 1.25 usec * 2/3 = 833 nsec
+    tpm->CONTROLS[1].CnV = tpm_p1_period;
+
+    NVIC_SetVector(TPM0_IRQn, (uint32_t)&TPM0_IRQHandler);
+    NVIC_EnableIRQ(TPM0_IRQn);
+}
+
+// class static
+template <unsigned MAX_LEDS_PER_STRIP>
+void WS2811<MAX_LEDS_PER_STRIP>::startDMA()
+{
+    if (!initialized) hw_init();
+    
+    wait_for_dma_done();
+    dma_done = 0;
+
+    DMA_Type volatile * dma   = DMA0;
+    TPM_Type volatile *tpm   = TPM0;
+    uint32_t nBytes = sizeof(dmaData.start_t1_low)
+                      + sizeof(dmaData.dmaWords)
+                      + sizeof(dmaData.trailing_zeros_1);
+
+    tpm->SC = TPM_SC_DMA_MASK        // enable DMA
+              | TPM_SC_TOF_MASK  // reset TOF flag if set
+              | TPM_SC_CMOD(0)   // disable clocks
+              | TPM_SC_PS(0);    // 48MHz / 1 = 48MHz clock
+    tpm->MOD = tpm_period - 1;       // 48MHz / 800kHz
+
+    tpm->CNT = tpm_p0_period - 2 ;
+    tpm->STATUS = 0xFFFFFFFF;
+
+    dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
+    dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
+    dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
+
+    // t=0: all outputs go high
+    // triggered by TPM0_Overflow
+    // source is one word of 0 then 24 x 0xffffffff, then another 0 word
+    dma->DMA[DMA_CHAN_START].SAR     = (uint32_t)(void*)dmaData.start_t0_high;
+    dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
+
+    // t=tpm_p0_period: some outputs (the 0 bits) go low.
+    // Triggered by TPM0_CH0
+    // Start 2 words before the actual data to avoid garbage pulses.
+    dma->DMA[DMA_CHAN_0_LOW].SAR     = (uint32_t)(void*)dmaData.start_t1_low; // set source address
+    dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
+
+    // t=tpm_p1_period: all outputs go low.
+    // Triggered by TPM0_CH1
+    // source is constant 0x00000000 (first word of dmaWords)
+    dma->DMA[DMA_CHAN_1_LOW].SAR     = (uint32_t)(void*)dmaData.start_t1_low; // set source address
+    dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
+
+    dma->DMA[DMA_CHAN_0_LOW].DAR
+    = dma->DMA[DMA_CHAN_1_LOW].DAR
+      = dma->DMA[DMA_CHAN_START].DAR
+        = (uint32_t)(void*)&WS2811_IO_GPIO->PDOR;
+
+    SET_DEBUG;
+
+    dma->DMA[DMA_CHAN_0_LOW].DCR     = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
+                                       | DMA_DCR_ERQ_MASK
+                                       | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
+                                       | DMA_DCR_SINC_MASK // increment source each transfer
+                                       | DMA_DCR_CS_MASK
+                                       | DMA_DCR_SSIZE(0) // 32-bit source transfers
+                                       | DMA_DCR_DSIZE(0); // 32-bit destination transfers
+
+    dma->DMA[DMA_CHAN_1_LOW].DCR     = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
+                                       | DMA_DCR_ERQ_MASK
+                                       | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
+                                       | DMA_DCR_CS_MASK
+                                       | DMA_DCR_SSIZE(0) // 32-bit source transfers
+                                       | DMA_DCR_DSIZE(0); // 32-bit destination transfers
+
+    dma->DMA[DMA_CHAN_START].DCR     = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
+                                       | DMA_DCR_ERQ_MASK
+                                       | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
+                                       | DMA_DCR_SINC_MASK // increment source each transfer
+                                       | DMA_DCR_CS_MASK
+                                       | DMA_DCR_SSIZE(0) // 32-bit source transfers
+                                       | DMA_DCR_DSIZE(0);
+
+    tpm->SC |= TPM_SC_CMOD(1);         // enable internal clocking
+}
+
+#if !INSTANTIATE_TEMPLATES
+
+extern "C" void DMA0_IRQHandler()
+{
+    DMA_Type volatile *dma = DMA0;
+    TPM_Type volatile *tpm = TPM0;
+
+    uint32_t db;
+
+    db = dma->DMA[DMA_CHAN_0_LOW].DSR_BCR;
+    if (db & DMA_DSR_BCR_DONE_MASK) {
+        dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
+    }
+
+    db = dma->DMA[DMA_CHAN_1_LOW].DSR_BCR;
+    if (db & DMA_DSR_BCR_DONE_MASK) {
+        dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
+    }
+
+    db = dma->DMA[DMA_CHAN_START].DSR_BCR;
+    if (db & DMA_DSR_BCR_DONE_MASK) {
+        dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
+    }
+
+    tpm->SC = TPM_SC_TOF_MASK;  // reset TOF flag; disable internal clocking
+
+    SET_DEBUG;
+
+#if 0
+    // set TPM0 to interrrupt after guardtime
+    tpm->MOD = guardtime_period - 1; // 48MHz * 55 usec
+    tpm->CNT = 0;
+    tpm->SC  = TPM_SC_PS(0)        // 48MHz / 1 = 48MHz clock
+               | TPM_SC_TOIE_MASK  // enable interrupts
+               | TPM_SC_CMOD(1);   // and internal clocking
+#endif
+
+    dma_done++;
+}
+
+extern "C" void TPM0_IRQHandler()
+{
+    TPM0->SC = 0; // disable internal clocking
+    TPM0->SC = TPM_SC_TOF_MASK;        
+    RESET_DEBUG;
+    dma_done = 3;
+}
+
+#endif