Ben Katz / mbed-dev_spine

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Fork of mbed-dev-f303 by Ben Katz

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_ll_fmc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_ll_fmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 12-Sept-2014
<> 144:ef7eb2e8f9f7 7 * @brief FMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### FMC peripheral features #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
<> 144:ef7eb2e8f9f7 20 (+) The NOR/PSRAM memory controller
<> 144:ef7eb2e8f9f7 21 (+) The NAND/PC Card memory controller
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 [..] The FMC functional block makes the interface with synchronous and asynchronous static
<> 144:ef7eb2e8f9f7 24 memories, and 16-bit PC memory cards. Its main purposes are:
<> 144:ef7eb2e8f9f7 25 (+) to translate AHB transactions into the appropriate external device protocol
<> 144:ef7eb2e8f9f7 26 (+) to meet the access time requirements of the external memory devices
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 [..] All external memories share the addresses, data and control signals with the controller.
<> 144:ef7eb2e8f9f7 29 Each external device is accessed by means of a unique Chip Select. The FMC performs
<> 144:ef7eb2e8f9f7 30 only one access at a time to an external device.
<> 144:ef7eb2e8f9f7 31 The main features of the FMC controller are the following:
<> 144:ef7eb2e8f9f7 32 (+) Interface with static-memory mapped devices including:
<> 144:ef7eb2e8f9f7 33 (++) Static random access memory (SRAM)
<> 144:ef7eb2e8f9f7 34 (++) Read-only memory (ROM)
<> 144:ef7eb2e8f9f7 35 (++) NOR Flash memory/OneNAND Flash memory
<> 144:ef7eb2e8f9f7 36 (++) PSRAM (4 memory banks)
<> 144:ef7eb2e8f9f7 37 (++) 16-bit PC Card compatible devices
<> 144:ef7eb2e8f9f7 38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
<> 144:ef7eb2e8f9f7 39 data
<> 144:ef7eb2e8f9f7 40 (+) Independent Chip Select control for each memory bank
<> 144:ef7eb2e8f9f7 41 (+) Independent configuration for each memory bank
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 @endverbatim
<> 144:ef7eb2e8f9f7 44 ******************************************************************************
<> 144:ef7eb2e8f9f7 45 * @attention
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 50 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 51 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 52 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 54 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 55 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 57 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 58 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 ******************************************************************************
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @defgroup FMC
<> 144:ef7eb2e8f9f7 82 * @brief FMC driver modules
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 91 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 92 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 93 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 94 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** @defgroup FMC_Private_Functions
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup FMC_NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 102 * @brief NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 @verbatim
<> 144:ef7eb2e8f9f7 105 ==============================================================================
<> 144:ef7eb2e8f9f7 106 ##### How to use NORSRAM device driver #####
<> 144:ef7eb2e8f9f7 107 ==============================================================================
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 [..]
<> 144:ef7eb2e8f9f7 110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
<> 144:ef7eb2e8f9f7 111 to run the NORSRAM external devices.
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
<> 144:ef7eb2e8f9f7 114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 116 (+) FMC NORSRAM bank extended timing configuration using the function
<> 144:ef7eb2e8f9f7 117 FMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 118 (+) FMC NORSRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 @endverbatim
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup FMC_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 127 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 @verbatim
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 132 ==============================================================================
<> 144:ef7eb2e8f9f7 133 [..]
<> 144:ef7eb2e8f9f7 134 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 135 (+) Initialize and configure the FMC NORSRAM interface
<> 144:ef7eb2e8f9f7 136 (+) De-initialize the FMC NORSRAM interface
<> 144:ef7eb2e8f9f7 137 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 @endverbatim
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @brief Initialize the FMC_NORSRAM device according to the specified
<> 144:ef7eb2e8f9f7 145 * control parameters in the FMC_NORSRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 146 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 147 * @param Init: Pointer to NORSRAM Initialization structure
<> 144:ef7eb2e8f9f7 148 * @retval HAL status
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Check the parameters */
<> 144:ef7eb2e8f9f7 155 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
<> 144:ef7eb2e8f9f7 157 assert_param(IS_FMC_MUX(Init->DataAddressMux));
<> 144:ef7eb2e8f9f7 158 assert_param(IS_FMC_MEMORY(Init->MemoryType));
<> 144:ef7eb2e8f9f7 159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
<> 144:ef7eb2e8f9f7 161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
<> 144:ef7eb2e8f9f7 162 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
<> 144:ef7eb2e8f9f7 163 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
<> 144:ef7eb2e8f9f7 164 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
<> 144:ef7eb2e8f9f7 165 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
<> 144:ef7eb2e8f9f7 166 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
<> 144:ef7eb2e8f9f7 167 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
<> 144:ef7eb2e8f9f7 168 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
<> 144:ef7eb2e8f9f7 169 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Set NORSRAM device control parameters */
<> 144:ef7eb2e8f9f7 172 tmpr = (uint32_t)(Init->DataAddressMux |\
<> 144:ef7eb2e8f9f7 173 Init->MemoryType |\
<> 144:ef7eb2e8f9f7 174 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 175 Init->BurstAccessMode |\
<> 144:ef7eb2e8f9f7 176 Init->WaitSignalPolarity |\
<> 144:ef7eb2e8f9f7 177 Init->WrapMode |\
<> 144:ef7eb2e8f9f7 178 Init->WaitSignalActive |\
<> 144:ef7eb2e8f9f7 179 Init->WriteOperation |\
<> 144:ef7eb2e8f9f7 180 Init->WaitSignal |\
<> 144:ef7eb2e8f9f7 181 Init->ExtendedMode |\
<> 144:ef7eb2e8f9f7 182 Init->AsynchronousWait |\
<> 144:ef7eb2e8f9f7 183 Init->WriteBurst |\
<> 144:ef7eb2e8f9f7 184 Init->ContinuousClock
<> 144:ef7eb2e8f9f7 185 );
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 Device->BTCR[Init->NSBank] = tmpr;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
<> 144:ef7eb2e8f9f7 195 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
<> 144:ef7eb2e8f9f7 198 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
<> 144:ef7eb2e8f9f7 199 Init->ContinuousClock);
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 return HAL_OK;
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief DeInitialize the FMC_NORSRAM peripheral
<> 144:ef7eb2e8f9f7 208 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 209 * @param ExDevice: Pointer to NORSRAM extended mode device instance
<> 144:ef7eb2e8f9f7 210 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 211 * @retval HAL status
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 /* Check the parameters */
<> 144:ef7eb2e8f9f7 216 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
<> 144:ef7eb2e8f9f7 218 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Disable the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 221 __FMC_NORSRAM_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* De-initialize the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 224 /* FMC_NORSRAM_BANK1 */
<> 144:ef7eb2e8f9f7 225 if(Bank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 Device->BTCR[Bank] = 0x000030DB;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 230 else
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 Device->BTCR[Bank] = 0x000030D2;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 236 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 return HAL_OK;
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @brief Initialize the FMC_NORSRAM Timing according to the specified
<> 144:ef7eb2e8f9f7 244 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 245 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 246 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 247 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 248 * @retval HAL status
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Check the parameters */
<> 144:ef7eb2e8f9f7 255 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 256 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 257 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 258 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 259 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 260 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 261 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 262 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 263 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Set FMC_NORSRAM device timing parameters */
<> 144:ef7eb2e8f9f7 266 tmpr = (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 267 ((Timing->AddressHoldTime) << 4) |\
<> 144:ef7eb2e8f9f7 268 ((Timing->DataSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 269 ((Timing->BusTurnAroundDuration) << 16) |\
<> 144:ef7eb2e8f9f7 270 (((Timing->CLKDivision)-1) << 20) |\
<> 144:ef7eb2e8f9f7 271 (((Timing->DataLatency)-2) << 24) |\
<> 144:ef7eb2e8f9f7 272 (Timing->AccessMode)
<> 144:ef7eb2e8f9f7 273 );
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 Device->BTCR[Bank + 1] = tmpr;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
<> 144:ef7eb2e8f9f7 278 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
<> 144:ef7eb2e8f9f7 281 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
<> 144:ef7eb2e8f9f7 282 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 return HAL_OK;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
<> 144:ef7eb2e8f9f7 290 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 291 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 292 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 293 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 294 * @retval HAL status
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Check the parameters */
<> 144:ef7eb2e8f9f7 299 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 144:ef7eb2e8f9f7 302 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* Check the parameters */
<> 144:ef7eb2e8f9f7 305 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
<> 144:ef7eb2e8f9f7 306 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 307 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 308 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 309 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 310 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 311 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 312 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 313 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 316 ((Timing->AddressHoldTime) << 4) |\
<> 144:ef7eb2e8f9f7 317 ((Timing->DataSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 318 ((Timing->BusTurnAroundDuration) << 16) |\
<> 144:ef7eb2e8f9f7 319 (((Timing->CLKDivision)-1) << 20) |\
<> 144:ef7eb2e8f9f7 320 (((Timing->DataLatency)-2) << 24) |\
<> 144:ef7eb2e8f9f7 321 (Timing->AccessMode));
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323 else
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 Device->BWTR[Bank] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 return HAL_OK;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /** @defgroup FMC_NORSRAM_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 338 * @brief management functions
<> 144:ef7eb2e8f9f7 339 *
<> 144:ef7eb2e8f9f7 340 @verbatim
<> 144:ef7eb2e8f9f7 341 ==============================================================================
<> 144:ef7eb2e8f9f7 342 ##### FMC_NORSRAM Control functions #####
<> 144:ef7eb2e8f9f7 343 ==============================================================================
<> 144:ef7eb2e8f9f7 344 [..]
<> 144:ef7eb2e8f9f7 345 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 346 the FMC NORSRAM interface.
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 @endverbatim
<> 144:ef7eb2e8f9f7 349 * @{
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /**
<> 144:ef7eb2e8f9f7 353 * @brief Enables dynamically FMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 354 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 355 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 356 * @retval HAL status
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 /* Check the parameters */
<> 144:ef7eb2e8f9f7 361 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 362 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Enable write operation */
<> 144:ef7eb2e8f9f7 365 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 return HAL_OK;
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @brief Disables dynamically FMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 372 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 373 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 374 * @retval HAL status
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 /* Check the parameters */
<> 144:ef7eb2e8f9f7 379 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 380 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Disable write operation */
<> 144:ef7eb2e8f9f7 383 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 return HAL_OK;
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /**
<> 144:ef7eb2e8f9f7 393 * @}
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /** @defgroup FMC_NAND Controller functions
<> 144:ef7eb2e8f9f7 397 * @brief NAND Controller functions
<> 144:ef7eb2e8f9f7 398 *
<> 144:ef7eb2e8f9f7 399 @verbatim
<> 144:ef7eb2e8f9f7 400 ==============================================================================
<> 144:ef7eb2e8f9f7 401 ##### How to use NAND device driver #####
<> 144:ef7eb2e8f9f7 402 ==============================================================================
<> 144:ef7eb2e8f9f7 403 [..]
<> 144:ef7eb2e8f9f7 404 This driver contains a set of APIs to interface with the FMC NAND banks in order
<> 144:ef7eb2e8f9f7 405 to run the NAND external devices.
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
<> 144:ef7eb2e8f9f7 408 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
<> 144:ef7eb2e8f9f7 409 (+) FMC NAND bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 410 FMC_NAND_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 411 (+) FMC NAND bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 412 FMC_NAND_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 413 (+) FMC NAND bank enable/disable ECC correction feature using the functions
<> 144:ef7eb2e8f9f7 414 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
<> 144:ef7eb2e8f9f7 415 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 @endverbatim
<> 144:ef7eb2e8f9f7 418 * @{
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 422 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 423 *
<> 144:ef7eb2e8f9f7 424 @verbatim
<> 144:ef7eb2e8f9f7 425 ==============================================================================
<> 144:ef7eb2e8f9f7 426 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 427 ==============================================================================
<> 144:ef7eb2e8f9f7 428 [..]
<> 144:ef7eb2e8f9f7 429 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 430 (+) Initialize and configure the FMC NAND interface
<> 144:ef7eb2e8f9f7 431 (+) De-initialize the FMC NAND interface
<> 144:ef7eb2e8f9f7 432 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 @endverbatim
<> 144:ef7eb2e8f9f7 435 * @{
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Initializes the FMC_NAND device according to the specified
<> 144:ef7eb2e8f9f7 440 * control parameters in the FMC_NAND_HandleTypeDef
<> 144:ef7eb2e8f9f7 441 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 442 * @param Init: Pointer to NAND Initialization structure
<> 144:ef7eb2e8f9f7 443 * @retval HAL status
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 uint32_t tmppcr = 0;
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Check the parameters */
<> 144:ef7eb2e8f9f7 450 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 451 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
<> 144:ef7eb2e8f9f7 452 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 453 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 454 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
<> 144:ef7eb2e8f9f7 455 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
<> 144:ef7eb2e8f9f7 456 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 457 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Set NAND device control parameters */
<> 144:ef7eb2e8f9f7 460 tmppcr = (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 461 FMC_PCR_MEMORY_TYPE_NAND |\
<> 144:ef7eb2e8f9f7 462 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 463 Init->EccComputation |\
<> 144:ef7eb2e8f9f7 464 Init->ECCPageSize |\
<> 144:ef7eb2e8f9f7 465 ((Init->TCLRSetupTime) << 9) |\
<> 144:ef7eb2e8f9f7 466 ((Init->TARSetupTime) << 13)
<> 144:ef7eb2e8f9f7 467 );
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 if(Init->NandBank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 472 Device->PCR2 = tmppcr;
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474 else
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 477 Device->PCR3 = tmppcr;
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 return HAL_OK;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @brief Initializes the FMC_NAND Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 486 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 487 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 488 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 489 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 490 * @retval HAL status
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 uint32_t tmppmem = 0;
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Check the parameters */
<> 144:ef7eb2e8f9f7 497 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 498 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 499 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 500 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 501 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 502 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 505 tmppmem = (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 506 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 507 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 508 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 509 );
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 514 Device->PMEM2 = tmppmem;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516 else
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 519 Device->PMEM3 = tmppmem;
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 return HAL_OK;
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /**
<> 144:ef7eb2e8f9f7 526 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 527 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 528 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 529 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 530 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 531 * @retval HAL status
<> 144:ef7eb2e8f9f7 532 */
<> 144:ef7eb2e8f9f7 533 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 uint32_t tmppatt = 0;
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Check the parameters */
<> 144:ef7eb2e8f9f7 538 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 539 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 540 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 541 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 542 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 543 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 546 tmppatt = (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 547 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 548 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 549 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 550 );
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 555 Device->PATT2 = tmppatt;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 else
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 560 Device->PATT3 = tmppatt;
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 return HAL_OK;
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @brief DeInitializes the FMC_NAND device
<> 144:ef7eb2e8f9f7 569 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 570 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 571 * @retval HAL status
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* Check the parameters */
<> 144:ef7eb2e8f9f7 576 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 577 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Disable the NAND Bank */
<> 144:ef7eb2e8f9f7 580 __FMC_NAND_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* De-initialize the NAND Bank */
<> 144:ef7eb2e8f9f7 583 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 /* Set the FMC_NAND_BANK2 registers to their reset values */
<> 144:ef7eb2e8f9f7 586 Device->PCR2 = 0x00000018;
<> 144:ef7eb2e8f9f7 587 Device->SR2 = 0x00000040;
<> 144:ef7eb2e8f9f7 588 Device->PMEM2 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 589 Device->PATT2 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591 /* FMC_Bank3_NAND */
<> 144:ef7eb2e8f9f7 592 else
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 /* Set the FMC_NAND_BANK3 registers to their reset values */
<> 144:ef7eb2e8f9f7 595 Device->PCR3 = 0x00000018;
<> 144:ef7eb2e8f9f7 596 Device->SR3 = 0x00000040;
<> 144:ef7eb2e8f9f7 597 Device->PMEM3 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 598 Device->PATT3 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 return HAL_OK;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /**
<> 144:ef7eb2e8f9f7 605 * @}
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /** @defgroup FMC_NAND_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 610 * @brief management functions
<> 144:ef7eb2e8f9f7 611 *
<> 144:ef7eb2e8f9f7 612 @verbatim
<> 144:ef7eb2e8f9f7 613 ==============================================================================
<> 144:ef7eb2e8f9f7 614 ##### FMC_NAND Control functions #####
<> 144:ef7eb2e8f9f7 615 ==============================================================================
<> 144:ef7eb2e8f9f7 616 [..]
<> 144:ef7eb2e8f9f7 617 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 618 the FMC NAND interface.
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 @endverbatim
<> 144:ef7eb2e8f9f7 621 * @{
<> 144:ef7eb2e8f9f7 622 */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /**
<> 144:ef7eb2e8f9f7 626 * @brief Enables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 627 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 628 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 629 * @retval HAL status
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 /* Check the parameters */
<> 144:ef7eb2e8f9f7 634 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 635 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 638 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 639 {
<> 144:ef7eb2e8f9f7 640 Device->PCR2 |= FMC_PCR2_ECCEN;
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642 else
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 Device->PCR3 |= FMC_PCR3_ECCEN;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 return HAL_OK;
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 653 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 654 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 655 * @retval HAL status
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 /* Check the parameters */
<> 144:ef7eb2e8f9f7 660 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 661 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 664 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 Device->PCR2 &= ~FMC_PCR2_ECCEN;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668 else
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 Device->PCR3 &= ~FMC_PCR3_ECCEN;
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 return HAL_OK;
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 678 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 679 * @param ECCval: Pointer to ECC value
<> 144:ef7eb2e8f9f7 680 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 681 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 682 * @retval HAL status
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 uint32_t timeout = 0;
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Check the parameters */
<> 144:ef7eb2e8f9f7 689 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 690 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 timeout = HAL_GetTick() + Timeout;
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Wait untill FIFO is empty */
<> 144:ef7eb2e8f9f7 695 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 698 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 if(HAL_GetTick() >= timeout)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 708 {
<> 144:ef7eb2e8f9f7 709 /* Get the ECCR2 register value */
<> 144:ef7eb2e8f9f7 710 *ECCval = (uint32_t)Device->ECCR2;
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712 else
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 /* Get the ECCR3 register value */
<> 144:ef7eb2e8f9f7 715 *ECCval = (uint32_t)Device->ECCR3;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 return HAL_OK;
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @}
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /**
<> 144:ef7eb2e8f9f7 726 * @}
<> 144:ef7eb2e8f9f7 727 */
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /** @defgroup FMC_PCCARD Controller functions
<> 144:ef7eb2e8f9f7 730 * @brief PCCARD Controller functions
<> 144:ef7eb2e8f9f7 731 *
<> 144:ef7eb2e8f9f7 732 @verbatim
<> 144:ef7eb2e8f9f7 733 ==============================================================================
<> 144:ef7eb2e8f9f7 734 ##### How to use PCCARD device driver #####
<> 144:ef7eb2e8f9f7 735 ==============================================================================
<> 144:ef7eb2e8f9f7 736 [..]
<> 144:ef7eb2e8f9f7 737 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
<> 144:ef7eb2e8f9f7 738 to run the PCCARD/compact flash external devices.
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
<> 144:ef7eb2e8f9f7 741 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
<> 144:ef7eb2e8f9f7 742 (+) FMC PCCARD bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 743 FMC_PCCARD_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 744 (+) FMC PCCARD bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 745 FMC_PCCARD_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 746 (+) FMC PCCARD bank IO space timing configuration using the function
<> 144:ef7eb2e8f9f7 747 FMC_PCCARD_IOSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 @endverbatim
<> 144:ef7eb2e8f9f7 751 * @{
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 755 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 756 *
<> 144:ef7eb2e8f9f7 757 @verbatim
<> 144:ef7eb2e8f9f7 758 ==============================================================================
<> 144:ef7eb2e8f9f7 759 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 760 ==============================================================================
<> 144:ef7eb2e8f9f7 761 [..]
<> 144:ef7eb2e8f9f7 762 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 763 (+) Initialize and configure the FMC PCCARD interface
<> 144:ef7eb2e8f9f7 764 (+) De-initialize the FMC PCCARD interface
<> 144:ef7eb2e8f9f7 765 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 @endverbatim
<> 144:ef7eb2e8f9f7 768 * @{
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /**
<> 144:ef7eb2e8f9f7 772 * @brief Initializes the FMC_PCCARD device according to the specified
<> 144:ef7eb2e8f9f7 773 * control parameters in the FMC_PCCARD_HandleTypeDef
<> 144:ef7eb2e8f9f7 774 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 775 * @param Init: Pointer to PCCARD Initialization structure
<> 144:ef7eb2e8f9f7 776 * @retval HAL status
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 /* Check the parameters */
<> 144:ef7eb2e8f9f7 781 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 782 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 783 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 784 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Set FMC_PCCARD device control parameters */
<> 144:ef7eb2e8f9f7 787 Device->PCR4 = (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 788 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
<> 144:ef7eb2e8f9f7 789 (Init->TCLRSetupTime << 9) |\
<> 144:ef7eb2e8f9f7 790 (Init->TARSetupTime << 13));
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 return HAL_OK;
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 798 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 799 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 800 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 801 * @retval HAL status
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 804 {
<> 144:ef7eb2e8f9f7 805 /* Check the parameters */
<> 144:ef7eb2e8f9f7 806 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 807 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 808 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 809 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 810 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Set PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 813 Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 814 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 815 (Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 816 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 817 );
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 return HAL_OK;
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /**
<> 144:ef7eb2e8f9f7 823 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 824 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 825 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 826 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 827 * @retval HAL status
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* Check the parameters */
<> 144:ef7eb2e8f9f7 832 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 833 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 834 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 835 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 836 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Set PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 839 Device->PATT4 = (uint32_t)((Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 840 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 841 (Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 842 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 843 );
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 return HAL_OK;
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /**
<> 144:ef7eb2e8f9f7 849 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
<> 144:ef7eb2e8f9f7 850 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 851 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 852 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 853 * @retval HAL status
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 /* Check the parameters */
<> 144:ef7eb2e8f9f7 858 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 859 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 860 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 861 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 862 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Set FMC_PCCARD device timing parameters */
<> 144:ef7eb2e8f9f7 865 Device->PIO4 = (uint32_t)((Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 866 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 867 (Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 868 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 869 );
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 return HAL_OK;
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /**
<> 144:ef7eb2e8f9f7 875 * @brief DeInitializes the FMC_PCCARD device
<> 144:ef7eb2e8f9f7 876 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 877 * @retval HAL status
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 /* Check the parameters */
<> 144:ef7eb2e8f9f7 882 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Disable the FMC_PCCARD device */
<> 144:ef7eb2e8f9f7 885 __FMC_PCCARD_DISABLE(Device);
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /* De-initialize the FMC_PCCARD device */
<> 144:ef7eb2e8f9f7 888 Device->PCR4 = 0x00000018;
<> 144:ef7eb2e8f9f7 889 Device->SR4 = 0x00000000;
<> 144:ef7eb2e8f9f7 890 Device->PMEM4 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 891 Device->PATT4 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 892 Device->PIO4 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 return HAL_OK;
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @}
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /**
<> 144:ef7eb2e8f9f7 902 * @}
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /**
<> 144:ef7eb2e8f9f7 906 * @}
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 #endif /* HAL_FMC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /**
<> 144:ef7eb2e8f9f7 913 * @}
<> 144:ef7eb2e8f9f7 914 */
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /**
<> 144:ef7eb2e8f9f7 917 * @}
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/