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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:e614a9f1c9e2 1 /**
AnnaBridge 165:e614a9f1c9e2 2 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 3 * @file stm32f1xx_ll_dma.h
AnnaBridge 165:e614a9f1c9e2 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
AnnaBridge 165:e614a9f1c9e2 7 * @brief Header file of DMA LL module.
AnnaBridge 165:e614a9f1c9e2 8 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 9 * @attention
AnnaBridge 165:e614a9f1c9e2 10 *
AnnaBridge 165:e614a9f1c9e2 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 165:e614a9f1c9e2 12 *
AnnaBridge 165:e614a9f1c9e2 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 165:e614a9f1c9e2 14 * are permitted provided that the following conditions are met:
AnnaBridge 165:e614a9f1c9e2 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 165:e614a9f1c9e2 16 * this list of conditions and the following disclaimer.
AnnaBridge 165:e614a9f1c9e2 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 165:e614a9f1c9e2 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 165:e614a9f1c9e2 19 * and/or other materials provided with the distribution.
AnnaBridge 165:e614a9f1c9e2 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 165:e614a9f1c9e2 21 * may be used to endorse or promote products derived from this software
AnnaBridge 165:e614a9f1c9e2 22 * without specific prior written permission.
AnnaBridge 165:e614a9f1c9e2 23 *
AnnaBridge 165:e614a9f1c9e2 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 165:e614a9f1c9e2 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 165:e614a9f1c9e2 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 165:e614a9f1c9e2 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 165:e614a9f1c9e2 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 165:e614a9f1c9e2 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 165:e614a9f1c9e2 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 165:e614a9f1c9e2 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 165:e614a9f1c9e2 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 165:e614a9f1c9e2 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 165:e614a9f1c9e2 34 *
AnnaBridge 165:e614a9f1c9e2 35 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 36 */
AnnaBridge 165:e614a9f1c9e2 37
AnnaBridge 165:e614a9f1c9e2 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 39 #ifndef __STM32F1xx_LL_DMA_H
AnnaBridge 165:e614a9f1c9e2 40 #define __STM32F1xx_LL_DMA_H
AnnaBridge 165:e614a9f1c9e2 41
AnnaBridge 165:e614a9f1c9e2 42 #ifdef __cplusplus
AnnaBridge 165:e614a9f1c9e2 43 extern "C" {
AnnaBridge 165:e614a9f1c9e2 44 #endif
AnnaBridge 165:e614a9f1c9e2 45
AnnaBridge 165:e614a9f1c9e2 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 47 #include "stm32f1xx.h"
AnnaBridge 165:e614a9f1c9e2 48
AnnaBridge 165:e614a9f1c9e2 49 /** @addtogroup STM32F1xx_LL_Driver
AnnaBridge 165:e614a9f1c9e2 50 * @{
AnnaBridge 165:e614a9f1c9e2 51 */
AnnaBridge 165:e614a9f1c9e2 52
AnnaBridge 165:e614a9f1c9e2 53 #if defined (DMA1) || defined (DMA2)
AnnaBridge 165:e614a9f1c9e2 54
AnnaBridge 165:e614a9f1c9e2 55 /** @defgroup DMA_LL DMA
AnnaBridge 165:e614a9f1c9e2 56 * @{
AnnaBridge 165:e614a9f1c9e2 57 */
AnnaBridge 165:e614a9f1c9e2 58
AnnaBridge 165:e614a9f1c9e2 59 /* Private types -------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 60 /* Private variables ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 61 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge 165:e614a9f1c9e2 62 * @{
AnnaBridge 165:e614a9f1c9e2 63 */
AnnaBridge 165:e614a9f1c9e2 64 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge 165:e614a9f1c9e2 65 static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge 165:e614a9f1c9e2 66 {
AnnaBridge 165:e614a9f1c9e2 67 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge 165:e614a9f1c9e2 68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge 165:e614a9f1c9e2 69 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge 165:e614a9f1c9e2 70 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge 165:e614a9f1c9e2 71 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge 165:e614a9f1c9e2 72 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge 165:e614a9f1c9e2 73 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge 165:e614a9f1c9e2 74 };
AnnaBridge 165:e614a9f1c9e2 75 /**
AnnaBridge 165:e614a9f1c9e2 76 * @}
AnnaBridge 165:e614a9f1c9e2 77 */
AnnaBridge 165:e614a9f1c9e2 78 /* Private constants ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 79 /* Private macros ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 80 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 165:e614a9f1c9e2 81 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge 165:e614a9f1c9e2 82 * @{
AnnaBridge 165:e614a9f1c9e2 83 */
AnnaBridge 165:e614a9f1c9e2 84 /**
AnnaBridge 165:e614a9f1c9e2 85 * @}
AnnaBridge 165:e614a9f1c9e2 86 */
AnnaBridge 165:e614a9f1c9e2 87 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 165:e614a9f1c9e2 88
AnnaBridge 165:e614a9f1c9e2 89 /* Exported types ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 90 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 165:e614a9f1c9e2 91 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge 165:e614a9f1c9e2 92 * @{
AnnaBridge 165:e614a9f1c9e2 93 */
AnnaBridge 165:e614a9f1c9e2 94 typedef struct
AnnaBridge 165:e614a9f1c9e2 95 {
AnnaBridge 165:e614a9f1c9e2 96 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge 165:e614a9f1c9e2 97 or as Source base address in case of memory to memory transfer direction.
AnnaBridge 165:e614a9f1c9e2 98
AnnaBridge 165:e614a9f1c9e2 99 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 165:e614a9f1c9e2 100
AnnaBridge 165:e614a9f1c9e2 101 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge 165:e614a9f1c9e2 102 or as Destination base address in case of memory to memory transfer direction.
AnnaBridge 165:e614a9f1c9e2 103
AnnaBridge 165:e614a9f1c9e2 104 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 165:e614a9f1c9e2 105
AnnaBridge 165:e614a9f1c9e2 106 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 165:e614a9f1c9e2 107 from memory to memory or from peripheral to memory.
AnnaBridge 165:e614a9f1c9e2 108 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge 165:e614a9f1c9e2 109
AnnaBridge 165:e614a9f1c9e2 110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge 165:e614a9f1c9e2 111
AnnaBridge 165:e614a9f1c9e2 112 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge 165:e614a9f1c9e2 113 This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge 165:e614a9f1c9e2 114 @note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge 165:e614a9f1c9e2 115 data transfer direction is configured on the selected Channel
AnnaBridge 165:e614a9f1c9e2 116
AnnaBridge 165:e614a9f1c9e2 117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge 165:e614a9f1c9e2 118
AnnaBridge 165:e614a9f1c9e2 119 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge 165:e614a9f1c9e2 120 is incremented or not.
AnnaBridge 165:e614a9f1c9e2 121 This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge 165:e614a9f1c9e2 122
AnnaBridge 165:e614a9f1c9e2 123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge 165:e614a9f1c9e2 124
AnnaBridge 165:e614a9f1c9e2 125 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge 165:e614a9f1c9e2 126 is incremented or not.
AnnaBridge 165:e614a9f1c9e2 127 This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge 165:e614a9f1c9e2 128
AnnaBridge 165:e614a9f1c9e2 129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge 165:e614a9f1c9e2 130
AnnaBridge 165:e614a9f1c9e2 131 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge 165:e614a9f1c9e2 132 in case of memory to memory transfer direction.
AnnaBridge 165:e614a9f1c9e2 133 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge 165:e614a9f1c9e2 134
AnnaBridge 165:e614a9f1c9e2 135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge 165:e614a9f1c9e2 136
AnnaBridge 165:e614a9f1c9e2 137 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge 165:e614a9f1c9e2 138 in case of memory to memory transfer direction.
AnnaBridge 165:e614a9f1c9e2 139 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge 165:e614a9f1c9e2 140
AnnaBridge 165:e614a9f1c9e2 141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge 165:e614a9f1c9e2 142
AnnaBridge 165:e614a9f1c9e2 143 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge 165:e614a9f1c9e2 144 The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge 165:e614a9f1c9e2 145 or MemorySize parameters depending in the transfer direction.
AnnaBridge 165:e614a9f1c9e2 146 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 165:e614a9f1c9e2 147
AnnaBridge 165:e614a9f1c9e2 148 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge 165:e614a9f1c9e2 149
AnnaBridge 165:e614a9f1c9e2 150 uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge 165:e614a9f1c9e2 151 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge 165:e614a9f1c9e2 152
AnnaBridge 165:e614a9f1c9e2 153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge 165:e614a9f1c9e2 154
AnnaBridge 165:e614a9f1c9e2 155 } LL_DMA_InitTypeDef;
AnnaBridge 165:e614a9f1c9e2 156 /**
AnnaBridge 165:e614a9f1c9e2 157 * @}
AnnaBridge 165:e614a9f1c9e2 158 */
AnnaBridge 165:e614a9f1c9e2 159 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 165:e614a9f1c9e2 160
AnnaBridge 165:e614a9f1c9e2 161 /* Exported constants --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 162 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge 165:e614a9f1c9e2 163 * @{
AnnaBridge 165:e614a9f1c9e2 164 */
AnnaBridge 165:e614a9f1c9e2 165 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge 165:e614a9f1c9e2 166 * @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge 165:e614a9f1c9e2 167 * @{
AnnaBridge 165:e614a9f1c9e2 168 */
AnnaBridge 165:e614a9f1c9e2 169 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
AnnaBridge 165:e614a9f1c9e2 170 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 171 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 172 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 173 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
AnnaBridge 165:e614a9f1c9e2 174 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 175 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 176 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 177 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
AnnaBridge 165:e614a9f1c9e2 178 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 179 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 180 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 181 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
AnnaBridge 165:e614a9f1c9e2 182 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 183 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 184 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 185 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
AnnaBridge 165:e614a9f1c9e2 186 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 187 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 188 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 189 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
AnnaBridge 165:e614a9f1c9e2 190 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 191 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 192 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 193 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
AnnaBridge 165:e614a9f1c9e2 194 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 195 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 196 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 197 /**
AnnaBridge 165:e614a9f1c9e2 198 * @}
AnnaBridge 165:e614a9f1c9e2 199 */
AnnaBridge 165:e614a9f1c9e2 200
AnnaBridge 165:e614a9f1c9e2 201 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 165:e614a9f1c9e2 202 * @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge 165:e614a9f1c9e2 203 * @{
AnnaBridge 165:e614a9f1c9e2 204 */
AnnaBridge 165:e614a9f1c9e2 205 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
AnnaBridge 165:e614a9f1c9e2 206 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 207 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 208 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 209 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
AnnaBridge 165:e614a9f1c9e2 210 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 211 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 212 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 213 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
AnnaBridge 165:e614a9f1c9e2 214 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 215 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 216 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 217 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
AnnaBridge 165:e614a9f1c9e2 218 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 219 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 220 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 221 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
AnnaBridge 165:e614a9f1c9e2 222 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 223 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 224 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 225 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
AnnaBridge 165:e614a9f1c9e2 226 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 227 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 228 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 229 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
AnnaBridge 165:e614a9f1c9e2 230 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 231 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 165:e614a9f1c9e2 232 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 165:e614a9f1c9e2 233 /**
AnnaBridge 165:e614a9f1c9e2 234 * @}
AnnaBridge 165:e614a9f1c9e2 235 */
AnnaBridge 165:e614a9f1c9e2 236
AnnaBridge 165:e614a9f1c9e2 237 /** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge 165:e614a9f1c9e2 238 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge 165:e614a9f1c9e2 239 * @{
AnnaBridge 165:e614a9f1c9e2 240 */
AnnaBridge 165:e614a9f1c9e2 241 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
AnnaBridge 165:e614a9f1c9e2 242 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
AnnaBridge 165:e614a9f1c9e2 243 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
AnnaBridge 165:e614a9f1c9e2 244 /**
AnnaBridge 165:e614a9f1c9e2 245 * @}
AnnaBridge 165:e614a9f1c9e2 246 */
AnnaBridge 165:e614a9f1c9e2 247
AnnaBridge 165:e614a9f1c9e2 248 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge 165:e614a9f1c9e2 249 * @{
AnnaBridge 165:e614a9f1c9e2 250 */
AnnaBridge 165:e614a9f1c9e2 251 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
AnnaBridge 165:e614a9f1c9e2 252 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
AnnaBridge 165:e614a9f1c9e2 253 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
AnnaBridge 165:e614a9f1c9e2 254 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
AnnaBridge 165:e614a9f1c9e2 255 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
AnnaBridge 165:e614a9f1c9e2 256 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
AnnaBridge 165:e614a9f1c9e2 257 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
AnnaBridge 165:e614a9f1c9e2 258 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 165:e614a9f1c9e2 259 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
AnnaBridge 165:e614a9f1c9e2 260 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 165:e614a9f1c9e2 261 /**
AnnaBridge 165:e614a9f1c9e2 262 * @}
AnnaBridge 165:e614a9f1c9e2 263 */
AnnaBridge 165:e614a9f1c9e2 264
AnnaBridge 165:e614a9f1c9e2 265 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge 165:e614a9f1c9e2 266 * @{
AnnaBridge 165:e614a9f1c9e2 267 */
AnnaBridge 165:e614a9f1c9e2 268 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
AnnaBridge 165:e614a9f1c9e2 269 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
AnnaBridge 165:e614a9f1c9e2 270 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
AnnaBridge 165:e614a9f1c9e2 271 /**
AnnaBridge 165:e614a9f1c9e2 272 * @}
AnnaBridge 165:e614a9f1c9e2 273 */
AnnaBridge 165:e614a9f1c9e2 274
AnnaBridge 165:e614a9f1c9e2 275 /** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge 165:e614a9f1c9e2 276 * @{
AnnaBridge 165:e614a9f1c9e2 277 */
AnnaBridge 165:e614a9f1c9e2 278 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
AnnaBridge 165:e614a9f1c9e2 279 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
AnnaBridge 165:e614a9f1c9e2 280 /**
AnnaBridge 165:e614a9f1c9e2 281 * @}
AnnaBridge 165:e614a9f1c9e2 282 */
AnnaBridge 165:e614a9f1c9e2 283
AnnaBridge 165:e614a9f1c9e2 284 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge 165:e614a9f1c9e2 285 * @{
AnnaBridge 165:e614a9f1c9e2 286 */
AnnaBridge 165:e614a9f1c9e2 287 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
AnnaBridge 165:e614a9f1c9e2 288 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
AnnaBridge 165:e614a9f1c9e2 289 /**
AnnaBridge 165:e614a9f1c9e2 290 * @}
AnnaBridge 165:e614a9f1c9e2 291 */
AnnaBridge 165:e614a9f1c9e2 292
AnnaBridge 165:e614a9f1c9e2 293 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge 165:e614a9f1c9e2 294 * @{
AnnaBridge 165:e614a9f1c9e2 295 */
AnnaBridge 165:e614a9f1c9e2 296 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
AnnaBridge 165:e614a9f1c9e2 297 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
AnnaBridge 165:e614a9f1c9e2 298 /**
AnnaBridge 165:e614a9f1c9e2 299 * @}
AnnaBridge 165:e614a9f1c9e2 300 */
AnnaBridge 165:e614a9f1c9e2 301
AnnaBridge 165:e614a9f1c9e2 302 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge 165:e614a9f1c9e2 303 * @{
AnnaBridge 165:e614a9f1c9e2 304 */
AnnaBridge 165:e614a9f1c9e2 305 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
AnnaBridge 165:e614a9f1c9e2 306 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
AnnaBridge 165:e614a9f1c9e2 307 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
AnnaBridge 165:e614a9f1c9e2 308 /**
AnnaBridge 165:e614a9f1c9e2 309 * @}
AnnaBridge 165:e614a9f1c9e2 310 */
AnnaBridge 165:e614a9f1c9e2 311
AnnaBridge 165:e614a9f1c9e2 312 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge 165:e614a9f1c9e2 313 * @{
AnnaBridge 165:e614a9f1c9e2 314 */
AnnaBridge 165:e614a9f1c9e2 315 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
AnnaBridge 165:e614a9f1c9e2 316 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
AnnaBridge 165:e614a9f1c9e2 317 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
AnnaBridge 165:e614a9f1c9e2 318 /**
AnnaBridge 165:e614a9f1c9e2 319 * @}
AnnaBridge 165:e614a9f1c9e2 320 */
AnnaBridge 165:e614a9f1c9e2 321
AnnaBridge 165:e614a9f1c9e2 322 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge 165:e614a9f1c9e2 323 * @{
AnnaBridge 165:e614a9f1c9e2 324 */
AnnaBridge 165:e614a9f1c9e2 325 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
AnnaBridge 165:e614a9f1c9e2 326 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
AnnaBridge 165:e614a9f1c9e2 327 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
AnnaBridge 165:e614a9f1c9e2 328 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
AnnaBridge 165:e614a9f1c9e2 329 /**
AnnaBridge 165:e614a9f1c9e2 330 * @}
AnnaBridge 165:e614a9f1c9e2 331 */
AnnaBridge 165:e614a9f1c9e2 332
AnnaBridge 165:e614a9f1c9e2 333 /**
AnnaBridge 165:e614a9f1c9e2 334 * @}
AnnaBridge 165:e614a9f1c9e2 335 */
AnnaBridge 165:e614a9f1c9e2 336
AnnaBridge 165:e614a9f1c9e2 337 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 338 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge 165:e614a9f1c9e2 339 * @{
AnnaBridge 165:e614a9f1c9e2 340 */
AnnaBridge 165:e614a9f1c9e2 341
AnnaBridge 165:e614a9f1c9e2 342 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge 165:e614a9f1c9e2 343 * @{
AnnaBridge 165:e614a9f1c9e2 344 */
AnnaBridge 165:e614a9f1c9e2 345 /**
AnnaBridge 165:e614a9f1c9e2 346 * @brief Write a value in DMA register
AnnaBridge 165:e614a9f1c9e2 347 * @param __INSTANCE__ DMA Instance
AnnaBridge 165:e614a9f1c9e2 348 * @param __REG__ Register to be written
AnnaBridge 165:e614a9f1c9e2 349 * @param __VALUE__ Value to be written in the register
AnnaBridge 165:e614a9f1c9e2 350 * @retval None
AnnaBridge 165:e614a9f1c9e2 351 */
AnnaBridge 165:e614a9f1c9e2 352 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 165:e614a9f1c9e2 353
AnnaBridge 165:e614a9f1c9e2 354 /**
AnnaBridge 165:e614a9f1c9e2 355 * @brief Read a value in DMA register
AnnaBridge 165:e614a9f1c9e2 356 * @param __INSTANCE__ DMA Instance
AnnaBridge 165:e614a9f1c9e2 357 * @param __REG__ Register to be read
AnnaBridge 165:e614a9f1c9e2 358 * @retval Register value
AnnaBridge 165:e614a9f1c9e2 359 */
AnnaBridge 165:e614a9f1c9e2 360 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 165:e614a9f1c9e2 361 /**
AnnaBridge 165:e614a9f1c9e2 362 * @}
AnnaBridge 165:e614a9f1c9e2 363 */
AnnaBridge 165:e614a9f1c9e2 364
AnnaBridge 165:e614a9f1c9e2 365 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge 165:e614a9f1c9e2 366 * @{
AnnaBridge 165:e614a9f1c9e2 367 */
AnnaBridge 165:e614a9f1c9e2 368
AnnaBridge 165:e614a9f1c9e2 369 /**
AnnaBridge 165:e614a9f1c9e2 370 * @brief Convert DMAx_Channely into DMAx
AnnaBridge 165:e614a9f1c9e2 371 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 165:e614a9f1c9e2 372 * @retval DMAx
AnnaBridge 165:e614a9f1c9e2 373 */
AnnaBridge 165:e614a9f1c9e2 374 #if defined(DMA2)
AnnaBridge 165:e614a9f1c9e2 375 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge 165:e614a9f1c9e2 376 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge 165:e614a9f1c9e2 377 #else
AnnaBridge 165:e614a9f1c9e2 378 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge 165:e614a9f1c9e2 379 #endif
AnnaBridge 165:e614a9f1c9e2 380
AnnaBridge 165:e614a9f1c9e2 381 /**
AnnaBridge 165:e614a9f1c9e2 382 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge 165:e614a9f1c9e2 383 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 165:e614a9f1c9e2 384 * @retval LL_DMA_CHANNEL_y
AnnaBridge 165:e614a9f1c9e2 385 */
AnnaBridge 165:e614a9f1c9e2 386 #if defined (DMA2)
AnnaBridge 165:e614a9f1c9e2 387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 165:e614a9f1c9e2 388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 165:e614a9f1c9e2 389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 165:e614a9f1c9e2 390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 165:e614a9f1c9e2 391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 165:e614a9f1c9e2 392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 165:e614a9f1c9e2 393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 165:e614a9f1c9e2 394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 165:e614a9f1c9e2 395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 165:e614a9f1c9e2 396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 165:e614a9f1c9e2 397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 165:e614a9f1c9e2 398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 165:e614a9f1c9e2 399 LL_DMA_CHANNEL_7)
AnnaBridge 165:e614a9f1c9e2 400 #else
AnnaBridge 165:e614a9f1c9e2 401 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 165:e614a9f1c9e2 402 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 165:e614a9f1c9e2 403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 165:e614a9f1c9e2 404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 165:e614a9f1c9e2 405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 165:e614a9f1c9e2 406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 165:e614a9f1c9e2 407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 165:e614a9f1c9e2 408 LL_DMA_CHANNEL_7)
AnnaBridge 165:e614a9f1c9e2 409 #endif
AnnaBridge 165:e614a9f1c9e2 410
AnnaBridge 165:e614a9f1c9e2 411 /**
AnnaBridge 165:e614a9f1c9e2 412 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge 165:e614a9f1c9e2 413 * @param __DMA_INSTANCE__ DMAx
AnnaBridge 165:e614a9f1c9e2 414 * @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge 165:e614a9f1c9e2 415 * @retval DMAx_Channely
AnnaBridge 165:e614a9f1c9e2 416 */
AnnaBridge 165:e614a9f1c9e2 417 #if defined (DMA2)
AnnaBridge 165:e614a9f1c9e2 418 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 165:e614a9f1c9e2 419 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 165:e614a9f1c9e2 420 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge 165:e614a9f1c9e2 421 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 165:e614a9f1c9e2 422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge 165:e614a9f1c9e2 423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 165:e614a9f1c9e2 424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge 165:e614a9f1c9e2 425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 165:e614a9f1c9e2 426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge 165:e614a9f1c9e2 427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 165:e614a9f1c9e2 428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge 165:e614a9f1c9e2 429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 165:e614a9f1c9e2 430 DMA1_Channel7)
AnnaBridge 165:e614a9f1c9e2 431 #else
AnnaBridge 165:e614a9f1c9e2 432 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 165:e614a9f1c9e2 433 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 165:e614a9f1c9e2 434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 165:e614a9f1c9e2 435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 165:e614a9f1c9e2 436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 165:e614a9f1c9e2 437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 165:e614a9f1c9e2 438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 165:e614a9f1c9e2 439 DMA1_Channel7)
AnnaBridge 165:e614a9f1c9e2 440 #endif
AnnaBridge 165:e614a9f1c9e2 441
AnnaBridge 165:e614a9f1c9e2 442 /**
AnnaBridge 165:e614a9f1c9e2 443 * @}
AnnaBridge 165:e614a9f1c9e2 444 */
AnnaBridge 165:e614a9f1c9e2 445
AnnaBridge 165:e614a9f1c9e2 446 /**
AnnaBridge 165:e614a9f1c9e2 447 * @}
AnnaBridge 165:e614a9f1c9e2 448 */
AnnaBridge 165:e614a9f1c9e2 449
AnnaBridge 165:e614a9f1c9e2 450 /* Exported functions --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 451 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge 165:e614a9f1c9e2 452 * @{
AnnaBridge 165:e614a9f1c9e2 453 */
AnnaBridge 165:e614a9f1c9e2 454
AnnaBridge 165:e614a9f1c9e2 455 /** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge 165:e614a9f1c9e2 456 * @{
AnnaBridge 165:e614a9f1c9e2 457 */
AnnaBridge 165:e614a9f1c9e2 458 /**
AnnaBridge 165:e614a9f1c9e2 459 * @brief Enable DMA channel.
AnnaBridge 165:e614a9f1c9e2 460 * @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge 165:e614a9f1c9e2 461 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 462 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 463 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 464 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 465 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 466 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 467 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 468 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 469 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 470 * @retval None
AnnaBridge 165:e614a9f1c9e2 471 */
AnnaBridge 165:e614a9f1c9e2 472 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 473 {
AnnaBridge 165:e614a9f1c9e2 474 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 165:e614a9f1c9e2 475 }
AnnaBridge 165:e614a9f1c9e2 476
AnnaBridge 165:e614a9f1c9e2 477 /**
AnnaBridge 165:e614a9f1c9e2 478 * @brief Disable DMA channel.
AnnaBridge 165:e614a9f1c9e2 479 * @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge 165:e614a9f1c9e2 480 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 481 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 482 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 483 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 484 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 485 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 486 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 487 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 488 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 489 * @retval None
AnnaBridge 165:e614a9f1c9e2 490 */
AnnaBridge 165:e614a9f1c9e2 491 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 492 {
AnnaBridge 165:e614a9f1c9e2 493 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 165:e614a9f1c9e2 494 }
AnnaBridge 165:e614a9f1c9e2 495
AnnaBridge 165:e614a9f1c9e2 496 /**
AnnaBridge 165:e614a9f1c9e2 497 * @brief Check if DMA channel is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 498 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge 165:e614a9f1c9e2 499 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 500 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 501 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 502 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 503 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 504 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 505 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 506 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 507 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 508 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 509 */
AnnaBridge 165:e614a9f1c9e2 510 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 511 {
AnnaBridge 165:e614a9f1c9e2 512 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 513 DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge 165:e614a9f1c9e2 514 }
AnnaBridge 165:e614a9f1c9e2 515
AnnaBridge 165:e614a9f1c9e2 516 /**
AnnaBridge 165:e614a9f1c9e2 517 * @brief Configure all parameters link to DMA transfer.
AnnaBridge 165:e614a9f1c9e2 518 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge 165:e614a9f1c9e2 519 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge 165:e614a9f1c9e2 520 * CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge 165:e614a9f1c9e2 521 * CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge 165:e614a9f1c9e2 522 * CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge 165:e614a9f1c9e2 523 * CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 165:e614a9f1c9e2 524 * CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 165:e614a9f1c9e2 525 * CCR PL LL_DMA_ConfigTransfer
AnnaBridge 165:e614a9f1c9e2 526 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 527 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 528 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 529 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 530 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 531 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 532 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 533 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 534 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 535 * @param Configuration This parameter must be a combination of all the following values:
AnnaBridge 165:e614a9f1c9e2 536 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 165:e614a9f1c9e2 537 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 165:e614a9f1c9e2 538 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 165:e614a9f1c9e2 539 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 165:e614a9f1c9e2 540 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 165:e614a9f1c9e2 541 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 165:e614a9f1c9e2 542 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 165:e614a9f1c9e2 543 * @retval None
AnnaBridge 165:e614a9f1c9e2 544 */
AnnaBridge 165:e614a9f1c9e2 545 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge 165:e614a9f1c9e2 546 {
AnnaBridge 165:e614a9f1c9e2 547 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 548 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
AnnaBridge 165:e614a9f1c9e2 549 Configuration);
AnnaBridge 165:e614a9f1c9e2 550 }
AnnaBridge 165:e614a9f1c9e2 551
AnnaBridge 165:e614a9f1c9e2 552 /**
AnnaBridge 165:e614a9f1c9e2 553 * @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge 165:e614a9f1c9e2 554 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge 165:e614a9f1c9e2 555 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge 165:e614a9f1c9e2 556 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 557 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 558 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 559 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 560 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 561 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 562 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 563 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 564 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 565 * @param Direction This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 566 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 165:e614a9f1c9e2 567 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 165:e614a9f1c9e2 568 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 165:e614a9f1c9e2 569 * @retval None
AnnaBridge 165:e614a9f1c9e2 570 */
AnnaBridge 165:e614a9f1c9e2 571 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge 165:e614a9f1c9e2 572 {
AnnaBridge 165:e614a9f1c9e2 573 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 574 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
AnnaBridge 165:e614a9f1c9e2 575 }
AnnaBridge 165:e614a9f1c9e2 576
AnnaBridge 165:e614a9f1c9e2 577 /**
AnnaBridge 165:e614a9f1c9e2 578 * @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge 165:e614a9f1c9e2 579 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge 165:e614a9f1c9e2 580 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge 165:e614a9f1c9e2 581 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 582 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 583 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 584 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 585 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 586 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 587 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 588 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 589 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 590 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 591 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 165:e614a9f1c9e2 592 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 165:e614a9f1c9e2 593 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 165:e614a9f1c9e2 594 */
AnnaBridge 165:e614a9f1c9e2 595 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 596 {
AnnaBridge 165:e614a9f1c9e2 597 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 598 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
AnnaBridge 165:e614a9f1c9e2 599 }
AnnaBridge 165:e614a9f1c9e2 600
AnnaBridge 165:e614a9f1c9e2 601 /**
AnnaBridge 165:e614a9f1c9e2 602 * @brief Set DMA mode circular or normal.
AnnaBridge 165:e614a9f1c9e2 603 * @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 165:e614a9f1c9e2 604 * data transfer is configured on the selected Channel.
AnnaBridge 165:e614a9f1c9e2 605 * @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge 165:e614a9f1c9e2 606 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 607 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 608 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 609 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 610 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 611 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 612 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 613 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 614 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 615 * @param Mode This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 616 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 165:e614a9f1c9e2 617 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 165:e614a9f1c9e2 618 * @retval None
AnnaBridge 165:e614a9f1c9e2 619 */
AnnaBridge 165:e614a9f1c9e2 620 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge 165:e614a9f1c9e2 621 {
AnnaBridge 165:e614a9f1c9e2 622 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge 165:e614a9f1c9e2 623 Mode);
AnnaBridge 165:e614a9f1c9e2 624 }
AnnaBridge 165:e614a9f1c9e2 625
AnnaBridge 165:e614a9f1c9e2 626 /**
AnnaBridge 165:e614a9f1c9e2 627 * @brief Get DMA mode circular or normal.
AnnaBridge 165:e614a9f1c9e2 628 * @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge 165:e614a9f1c9e2 629 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 630 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 631 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 632 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 633 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 634 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 635 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 636 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 637 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 638 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 639 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 165:e614a9f1c9e2 640 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 165:e614a9f1c9e2 641 */
AnnaBridge 165:e614a9f1c9e2 642 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 643 {
AnnaBridge 165:e614a9f1c9e2 644 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 645 DMA_CCR_CIRC));
AnnaBridge 165:e614a9f1c9e2 646 }
AnnaBridge 165:e614a9f1c9e2 647
AnnaBridge 165:e614a9f1c9e2 648 /**
AnnaBridge 165:e614a9f1c9e2 649 * @brief Set Peripheral increment mode.
AnnaBridge 165:e614a9f1c9e2 650 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge 165:e614a9f1c9e2 651 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 652 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 653 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 654 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 655 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 656 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 657 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 658 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 659 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 660 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 661 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 165:e614a9f1c9e2 662 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 165:e614a9f1c9e2 663 * @retval None
AnnaBridge 165:e614a9f1c9e2 664 */
AnnaBridge 165:e614a9f1c9e2 665 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge 165:e614a9f1c9e2 666 {
AnnaBridge 165:e614a9f1c9e2 667 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge 165:e614a9f1c9e2 668 PeriphOrM2MSrcIncMode);
AnnaBridge 165:e614a9f1c9e2 669 }
AnnaBridge 165:e614a9f1c9e2 670
AnnaBridge 165:e614a9f1c9e2 671 /**
AnnaBridge 165:e614a9f1c9e2 672 * @brief Get Peripheral increment mode.
AnnaBridge 165:e614a9f1c9e2 673 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge 165:e614a9f1c9e2 674 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 675 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 676 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 677 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 678 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 679 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 680 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 681 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 682 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 683 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 684 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 165:e614a9f1c9e2 685 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 165:e614a9f1c9e2 686 */
AnnaBridge 165:e614a9f1c9e2 687 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 688 {
AnnaBridge 165:e614a9f1c9e2 689 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 690 DMA_CCR_PINC));
AnnaBridge 165:e614a9f1c9e2 691 }
AnnaBridge 165:e614a9f1c9e2 692
AnnaBridge 165:e614a9f1c9e2 693 /**
AnnaBridge 165:e614a9f1c9e2 694 * @brief Set Memory increment mode.
AnnaBridge 165:e614a9f1c9e2 695 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge 165:e614a9f1c9e2 696 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 697 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 698 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 699 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 700 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 701 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 702 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 703 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 704 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 705 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 706 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 165:e614a9f1c9e2 707 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 165:e614a9f1c9e2 708 * @retval None
AnnaBridge 165:e614a9f1c9e2 709 */
AnnaBridge 165:e614a9f1c9e2 710 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge 165:e614a9f1c9e2 711 {
AnnaBridge 165:e614a9f1c9e2 712 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge 165:e614a9f1c9e2 713 MemoryOrM2MDstIncMode);
AnnaBridge 165:e614a9f1c9e2 714 }
AnnaBridge 165:e614a9f1c9e2 715
AnnaBridge 165:e614a9f1c9e2 716 /**
AnnaBridge 165:e614a9f1c9e2 717 * @brief Get Memory increment mode.
AnnaBridge 165:e614a9f1c9e2 718 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge 165:e614a9f1c9e2 719 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 720 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 721 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 722 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 723 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 724 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 725 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 726 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 727 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 728 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 729 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 165:e614a9f1c9e2 730 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 165:e614a9f1c9e2 731 */
AnnaBridge 165:e614a9f1c9e2 732 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 733 {
AnnaBridge 165:e614a9f1c9e2 734 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 735 DMA_CCR_MINC));
AnnaBridge 165:e614a9f1c9e2 736 }
AnnaBridge 165:e614a9f1c9e2 737
AnnaBridge 165:e614a9f1c9e2 738 /**
AnnaBridge 165:e614a9f1c9e2 739 * @brief Set Peripheral size.
AnnaBridge 165:e614a9f1c9e2 740 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge 165:e614a9f1c9e2 741 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 742 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 743 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 744 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 745 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 746 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 747 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 748 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 749 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 750 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 751 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 165:e614a9f1c9e2 752 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 165:e614a9f1c9e2 753 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 165:e614a9f1c9e2 754 * @retval None
AnnaBridge 165:e614a9f1c9e2 755 */
AnnaBridge 165:e614a9f1c9e2 756 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge 165:e614a9f1c9e2 757 {
AnnaBridge 165:e614a9f1c9e2 758 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge 165:e614a9f1c9e2 759 PeriphOrM2MSrcDataSize);
AnnaBridge 165:e614a9f1c9e2 760 }
AnnaBridge 165:e614a9f1c9e2 761
AnnaBridge 165:e614a9f1c9e2 762 /**
AnnaBridge 165:e614a9f1c9e2 763 * @brief Get Peripheral size.
AnnaBridge 165:e614a9f1c9e2 764 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge 165:e614a9f1c9e2 765 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 766 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 767 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 768 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 769 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 770 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 771 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 772 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 773 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 774 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 775 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 165:e614a9f1c9e2 776 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 165:e614a9f1c9e2 777 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 165:e614a9f1c9e2 778 */
AnnaBridge 165:e614a9f1c9e2 779 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 780 {
AnnaBridge 165:e614a9f1c9e2 781 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 782 DMA_CCR_PSIZE));
AnnaBridge 165:e614a9f1c9e2 783 }
AnnaBridge 165:e614a9f1c9e2 784
AnnaBridge 165:e614a9f1c9e2 785 /**
AnnaBridge 165:e614a9f1c9e2 786 * @brief Set Memory size.
AnnaBridge 165:e614a9f1c9e2 787 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge 165:e614a9f1c9e2 788 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 789 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 790 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 791 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 792 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 793 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 794 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 795 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 796 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 797 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 798 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 165:e614a9f1c9e2 799 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 165:e614a9f1c9e2 800 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 165:e614a9f1c9e2 801 * @retval None
AnnaBridge 165:e614a9f1c9e2 802 */
AnnaBridge 165:e614a9f1c9e2 803 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge 165:e614a9f1c9e2 804 {
AnnaBridge 165:e614a9f1c9e2 805 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge 165:e614a9f1c9e2 806 MemoryOrM2MDstDataSize);
AnnaBridge 165:e614a9f1c9e2 807 }
AnnaBridge 165:e614a9f1c9e2 808
AnnaBridge 165:e614a9f1c9e2 809 /**
AnnaBridge 165:e614a9f1c9e2 810 * @brief Get Memory size.
AnnaBridge 165:e614a9f1c9e2 811 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge 165:e614a9f1c9e2 812 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 813 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 814 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 815 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 816 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 817 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 818 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 819 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 820 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 821 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 822 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 165:e614a9f1c9e2 823 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 165:e614a9f1c9e2 824 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 165:e614a9f1c9e2 825 */
AnnaBridge 165:e614a9f1c9e2 826 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 827 {
AnnaBridge 165:e614a9f1c9e2 828 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 829 DMA_CCR_MSIZE));
AnnaBridge 165:e614a9f1c9e2 830 }
AnnaBridge 165:e614a9f1c9e2 831
AnnaBridge 165:e614a9f1c9e2 832 /**
AnnaBridge 165:e614a9f1c9e2 833 * @brief Set Channel priority level.
AnnaBridge 165:e614a9f1c9e2 834 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge 165:e614a9f1c9e2 835 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 836 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 837 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 838 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 839 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 840 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 841 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 842 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 843 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 844 * @param Priority This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 845 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 165:e614a9f1c9e2 846 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 165:e614a9f1c9e2 847 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 165:e614a9f1c9e2 848 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 165:e614a9f1c9e2 849 * @retval None
AnnaBridge 165:e614a9f1c9e2 850 */
AnnaBridge 165:e614a9f1c9e2 851 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge 165:e614a9f1c9e2 852 {
AnnaBridge 165:e614a9f1c9e2 853 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge 165:e614a9f1c9e2 854 Priority);
AnnaBridge 165:e614a9f1c9e2 855 }
AnnaBridge 165:e614a9f1c9e2 856
AnnaBridge 165:e614a9f1c9e2 857 /**
AnnaBridge 165:e614a9f1c9e2 858 * @brief Get Channel priority level.
AnnaBridge 165:e614a9f1c9e2 859 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge 165:e614a9f1c9e2 860 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 861 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 862 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 863 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 864 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 865 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 866 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 867 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 868 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 869 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 870 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 165:e614a9f1c9e2 871 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 165:e614a9f1c9e2 872 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 165:e614a9f1c9e2 873 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 165:e614a9f1c9e2 874 */
AnnaBridge 165:e614a9f1c9e2 875 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 876 {
AnnaBridge 165:e614a9f1c9e2 877 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 878 DMA_CCR_PL));
AnnaBridge 165:e614a9f1c9e2 879 }
AnnaBridge 165:e614a9f1c9e2 880
AnnaBridge 165:e614a9f1c9e2 881 /**
AnnaBridge 165:e614a9f1c9e2 882 * @brief Set Number of data to transfer.
AnnaBridge 165:e614a9f1c9e2 883 * @note This action has no effect if
AnnaBridge 165:e614a9f1c9e2 884 * channel is enabled.
AnnaBridge 165:e614a9f1c9e2 885 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge 165:e614a9f1c9e2 886 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 887 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 888 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 889 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 890 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 891 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 892 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 893 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 894 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 895 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 165:e614a9f1c9e2 896 * @retval None
AnnaBridge 165:e614a9f1c9e2 897 */
AnnaBridge 165:e614a9f1c9e2 898 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge 165:e614a9f1c9e2 899 {
AnnaBridge 165:e614a9f1c9e2 900 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 165:e614a9f1c9e2 901 DMA_CNDTR_NDT, NbData);
AnnaBridge 165:e614a9f1c9e2 902 }
AnnaBridge 165:e614a9f1c9e2 903
AnnaBridge 165:e614a9f1c9e2 904 /**
AnnaBridge 165:e614a9f1c9e2 905 * @brief Get Number of data to transfer.
AnnaBridge 165:e614a9f1c9e2 906 * @note Once the channel is enabled, the return value indicate the
AnnaBridge 165:e614a9f1c9e2 907 * remaining bytes to be transmitted.
AnnaBridge 165:e614a9f1c9e2 908 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge 165:e614a9f1c9e2 909 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 910 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 911 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 912 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 913 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 914 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 915 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 916 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 917 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 918 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 919 */
AnnaBridge 165:e614a9f1c9e2 920 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 921 {
AnnaBridge 165:e614a9f1c9e2 922 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 165:e614a9f1c9e2 923 DMA_CNDTR_NDT));
AnnaBridge 165:e614a9f1c9e2 924 }
AnnaBridge 165:e614a9f1c9e2 925
AnnaBridge 165:e614a9f1c9e2 926 /**
AnnaBridge 165:e614a9f1c9e2 927 * @brief Configure the Source and Destination addresses.
AnnaBridge 165:e614a9f1c9e2 928 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 165:e614a9f1c9e2 929 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge 165:e614a9f1c9e2 930 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge 165:e614a9f1c9e2 931 * CMAR MA LL_DMA_ConfigAddresses
AnnaBridge 165:e614a9f1c9e2 932 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 933 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 934 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 935 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 936 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 937 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 938 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 939 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 940 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 941 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 942 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 943 * @param Direction This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 944 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 165:e614a9f1c9e2 945 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 165:e614a9f1c9e2 946 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 165:e614a9f1c9e2 947 * @retval None
AnnaBridge 165:e614a9f1c9e2 948 */
AnnaBridge 165:e614a9f1c9e2 949 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge 165:e614a9f1c9e2 950 uint32_t DstAddress, uint32_t Direction)
AnnaBridge 165:e614a9f1c9e2 951 {
AnnaBridge 165:e614a9f1c9e2 952 /* Direction Memory to Periph */
AnnaBridge 165:e614a9f1c9e2 953 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge 165:e614a9f1c9e2 954 {
AnnaBridge 165:e614a9f1c9e2 955 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge 165:e614a9f1c9e2 956 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge 165:e614a9f1c9e2 957 }
AnnaBridge 165:e614a9f1c9e2 958 /* Direction Periph to Memory and Memory to Memory */
AnnaBridge 165:e614a9f1c9e2 959 else
AnnaBridge 165:e614a9f1c9e2 960 {
AnnaBridge 165:e614a9f1c9e2 961 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge 165:e614a9f1c9e2 962 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge 165:e614a9f1c9e2 963 }
AnnaBridge 165:e614a9f1c9e2 964 }
AnnaBridge 165:e614a9f1c9e2 965
AnnaBridge 165:e614a9f1c9e2 966 /**
AnnaBridge 165:e614a9f1c9e2 967 * @brief Set the Memory address.
AnnaBridge 165:e614a9f1c9e2 968 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 165:e614a9f1c9e2 969 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 165:e614a9f1c9e2 970 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge 165:e614a9f1c9e2 971 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 972 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 973 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 974 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 975 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 976 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 977 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 978 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 979 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 980 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 981 * @retval None
AnnaBridge 165:e614a9f1c9e2 982 */
AnnaBridge 165:e614a9f1c9e2 983 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 165:e614a9f1c9e2 984 {
AnnaBridge 165:e614a9f1c9e2 985 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 165:e614a9f1c9e2 986 }
AnnaBridge 165:e614a9f1c9e2 987
AnnaBridge 165:e614a9f1c9e2 988 /**
AnnaBridge 165:e614a9f1c9e2 989 * @brief Set the Peripheral address.
AnnaBridge 165:e614a9f1c9e2 990 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 165:e614a9f1c9e2 991 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 165:e614a9f1c9e2 992 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge 165:e614a9f1c9e2 993 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 994 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 995 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 996 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 997 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 998 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 999 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1000 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1001 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1002 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 1003 * @retval None
AnnaBridge 165:e614a9f1c9e2 1004 */
AnnaBridge 165:e614a9f1c9e2 1005 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge 165:e614a9f1c9e2 1006 {
AnnaBridge 165:e614a9f1c9e2 1007 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge 165:e614a9f1c9e2 1008 }
AnnaBridge 165:e614a9f1c9e2 1009
AnnaBridge 165:e614a9f1c9e2 1010 /**
AnnaBridge 165:e614a9f1c9e2 1011 * @brief Get Memory address.
AnnaBridge 165:e614a9f1c9e2 1012 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 165:e614a9f1c9e2 1013 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge 165:e614a9f1c9e2 1014 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1015 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1016 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1017 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1018 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1019 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1020 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1021 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1022 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1023 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 1024 */
AnnaBridge 165:e614a9f1c9e2 1025 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1026 {
AnnaBridge 165:e614a9f1c9e2 1027 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 165:e614a9f1c9e2 1028 }
AnnaBridge 165:e614a9f1c9e2 1029
AnnaBridge 165:e614a9f1c9e2 1030 /**
AnnaBridge 165:e614a9f1c9e2 1031 * @brief Get Peripheral address.
AnnaBridge 165:e614a9f1c9e2 1032 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 165:e614a9f1c9e2 1033 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge 165:e614a9f1c9e2 1034 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1035 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1036 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1037 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1038 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1039 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1040 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1041 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1042 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1043 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 1044 */
AnnaBridge 165:e614a9f1c9e2 1045 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1046 {
AnnaBridge 165:e614a9f1c9e2 1047 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 165:e614a9f1c9e2 1048 }
AnnaBridge 165:e614a9f1c9e2 1049
AnnaBridge 165:e614a9f1c9e2 1050 /**
AnnaBridge 165:e614a9f1c9e2 1051 * @brief Set the Memory to Memory Source address.
AnnaBridge 165:e614a9f1c9e2 1052 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 165:e614a9f1c9e2 1053 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 165:e614a9f1c9e2 1054 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge 165:e614a9f1c9e2 1055 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1056 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1057 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1058 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1059 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1060 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1061 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1062 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1063 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1064 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 1065 * @retval None
AnnaBridge 165:e614a9f1c9e2 1066 */
AnnaBridge 165:e614a9f1c9e2 1067 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 165:e614a9f1c9e2 1068 {
AnnaBridge 165:e614a9f1c9e2 1069 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge 165:e614a9f1c9e2 1070 }
AnnaBridge 165:e614a9f1c9e2 1071
AnnaBridge 165:e614a9f1c9e2 1072 /**
AnnaBridge 165:e614a9f1c9e2 1073 * @brief Set the Memory to Memory Destination address.
AnnaBridge 165:e614a9f1c9e2 1074 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 165:e614a9f1c9e2 1075 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 165:e614a9f1c9e2 1076 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge 165:e614a9f1c9e2 1077 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1078 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1079 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1080 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1081 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1082 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1083 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1084 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1085 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1086 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 1087 * @retval None
AnnaBridge 165:e614a9f1c9e2 1088 */
AnnaBridge 165:e614a9f1c9e2 1089 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 165:e614a9f1c9e2 1090 {
AnnaBridge 165:e614a9f1c9e2 1091 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 165:e614a9f1c9e2 1092 }
AnnaBridge 165:e614a9f1c9e2 1093
AnnaBridge 165:e614a9f1c9e2 1094 /**
AnnaBridge 165:e614a9f1c9e2 1095 * @brief Get the Memory to Memory Source address.
AnnaBridge 165:e614a9f1c9e2 1096 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 165:e614a9f1c9e2 1097 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge 165:e614a9f1c9e2 1098 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1099 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1100 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1101 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1102 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1103 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1104 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1105 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1106 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1107 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 1108 */
AnnaBridge 165:e614a9f1c9e2 1109 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1110 {
AnnaBridge 165:e614a9f1c9e2 1111 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 165:e614a9f1c9e2 1112 }
AnnaBridge 165:e614a9f1c9e2 1113
AnnaBridge 165:e614a9f1c9e2 1114 /**
AnnaBridge 165:e614a9f1c9e2 1115 * @brief Get the Memory to Memory Destination address.
AnnaBridge 165:e614a9f1c9e2 1116 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 165:e614a9f1c9e2 1117 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge 165:e614a9f1c9e2 1118 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1119 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1120 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1121 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1122 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1123 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1124 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1125 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1126 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1127 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 165:e614a9f1c9e2 1128 */
AnnaBridge 165:e614a9f1c9e2 1129 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1130 {
AnnaBridge 165:e614a9f1c9e2 1131 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 165:e614a9f1c9e2 1132 }
AnnaBridge 165:e614a9f1c9e2 1133
AnnaBridge 165:e614a9f1c9e2 1134 /**
AnnaBridge 165:e614a9f1c9e2 1135 * @}
AnnaBridge 165:e614a9f1c9e2 1136 */
AnnaBridge 165:e614a9f1c9e2 1137
AnnaBridge 165:e614a9f1c9e2 1138 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 165:e614a9f1c9e2 1139 * @{
AnnaBridge 165:e614a9f1c9e2 1140 */
AnnaBridge 165:e614a9f1c9e2 1141
AnnaBridge 165:e614a9f1c9e2 1142 /**
AnnaBridge 165:e614a9f1c9e2 1143 * @brief Get Channel 1 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1144 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge 165:e614a9f1c9e2 1145 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1146 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1147 */
AnnaBridge 165:e614a9f1c9e2 1148 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1149 {
AnnaBridge 165:e614a9f1c9e2 1150 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge 165:e614a9f1c9e2 1151 }
AnnaBridge 165:e614a9f1c9e2 1152
AnnaBridge 165:e614a9f1c9e2 1153 /**
AnnaBridge 165:e614a9f1c9e2 1154 * @brief Get Channel 2 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1155 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge 165:e614a9f1c9e2 1156 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1157 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1158 */
AnnaBridge 165:e614a9f1c9e2 1159 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1160 {
AnnaBridge 165:e614a9f1c9e2 1161 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge 165:e614a9f1c9e2 1162 }
AnnaBridge 165:e614a9f1c9e2 1163
AnnaBridge 165:e614a9f1c9e2 1164 /**
AnnaBridge 165:e614a9f1c9e2 1165 * @brief Get Channel 3 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1166 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge 165:e614a9f1c9e2 1167 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1168 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1169 */
AnnaBridge 165:e614a9f1c9e2 1170 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1171 {
AnnaBridge 165:e614a9f1c9e2 1172 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge 165:e614a9f1c9e2 1173 }
AnnaBridge 165:e614a9f1c9e2 1174
AnnaBridge 165:e614a9f1c9e2 1175 /**
AnnaBridge 165:e614a9f1c9e2 1176 * @brief Get Channel 4 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1177 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge 165:e614a9f1c9e2 1178 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1179 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1180 */
AnnaBridge 165:e614a9f1c9e2 1181 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1182 {
AnnaBridge 165:e614a9f1c9e2 1183 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge 165:e614a9f1c9e2 1184 }
AnnaBridge 165:e614a9f1c9e2 1185
AnnaBridge 165:e614a9f1c9e2 1186 /**
AnnaBridge 165:e614a9f1c9e2 1187 * @brief Get Channel 5 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1188 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge 165:e614a9f1c9e2 1189 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1190 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1191 */
AnnaBridge 165:e614a9f1c9e2 1192 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1193 {
AnnaBridge 165:e614a9f1c9e2 1194 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge 165:e614a9f1c9e2 1195 }
AnnaBridge 165:e614a9f1c9e2 1196
AnnaBridge 165:e614a9f1c9e2 1197 /**
AnnaBridge 165:e614a9f1c9e2 1198 * @brief Get Channel 6 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1199 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge 165:e614a9f1c9e2 1200 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1201 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1202 */
AnnaBridge 165:e614a9f1c9e2 1203 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1204 {
AnnaBridge 165:e614a9f1c9e2 1205 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge 165:e614a9f1c9e2 1206 }
AnnaBridge 165:e614a9f1c9e2 1207
AnnaBridge 165:e614a9f1c9e2 1208 /**
AnnaBridge 165:e614a9f1c9e2 1209 * @brief Get Channel 7 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1210 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge 165:e614a9f1c9e2 1211 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1212 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1213 */
AnnaBridge 165:e614a9f1c9e2 1214 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1215 {
AnnaBridge 165:e614a9f1c9e2 1216 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge 165:e614a9f1c9e2 1217 }
AnnaBridge 165:e614a9f1c9e2 1218
AnnaBridge 165:e614a9f1c9e2 1219 /**
AnnaBridge 165:e614a9f1c9e2 1220 * @brief Get Channel 1 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1221 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge 165:e614a9f1c9e2 1222 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1223 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1224 */
AnnaBridge 165:e614a9f1c9e2 1225 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1226 {
AnnaBridge 165:e614a9f1c9e2 1227 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge 165:e614a9f1c9e2 1228 }
AnnaBridge 165:e614a9f1c9e2 1229
AnnaBridge 165:e614a9f1c9e2 1230 /**
AnnaBridge 165:e614a9f1c9e2 1231 * @brief Get Channel 2 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1232 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge 165:e614a9f1c9e2 1233 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1234 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1235 */
AnnaBridge 165:e614a9f1c9e2 1236 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1237 {
AnnaBridge 165:e614a9f1c9e2 1238 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge 165:e614a9f1c9e2 1239 }
AnnaBridge 165:e614a9f1c9e2 1240
AnnaBridge 165:e614a9f1c9e2 1241 /**
AnnaBridge 165:e614a9f1c9e2 1242 * @brief Get Channel 3 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1243 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge 165:e614a9f1c9e2 1244 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1245 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1246 */
AnnaBridge 165:e614a9f1c9e2 1247 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1248 {
AnnaBridge 165:e614a9f1c9e2 1249 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge 165:e614a9f1c9e2 1250 }
AnnaBridge 165:e614a9f1c9e2 1251
AnnaBridge 165:e614a9f1c9e2 1252 /**
AnnaBridge 165:e614a9f1c9e2 1253 * @brief Get Channel 4 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1254 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge 165:e614a9f1c9e2 1255 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1256 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1257 */
AnnaBridge 165:e614a9f1c9e2 1258 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1259 {
AnnaBridge 165:e614a9f1c9e2 1260 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge 165:e614a9f1c9e2 1261 }
AnnaBridge 165:e614a9f1c9e2 1262
AnnaBridge 165:e614a9f1c9e2 1263 /**
AnnaBridge 165:e614a9f1c9e2 1264 * @brief Get Channel 5 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1265 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge 165:e614a9f1c9e2 1266 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1267 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1268 */
AnnaBridge 165:e614a9f1c9e2 1269 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1270 {
AnnaBridge 165:e614a9f1c9e2 1271 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge 165:e614a9f1c9e2 1272 }
AnnaBridge 165:e614a9f1c9e2 1273
AnnaBridge 165:e614a9f1c9e2 1274 /**
AnnaBridge 165:e614a9f1c9e2 1275 * @brief Get Channel 6 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1276 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge 165:e614a9f1c9e2 1277 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1278 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1279 */
AnnaBridge 165:e614a9f1c9e2 1280 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1281 {
AnnaBridge 165:e614a9f1c9e2 1282 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge 165:e614a9f1c9e2 1283 }
AnnaBridge 165:e614a9f1c9e2 1284
AnnaBridge 165:e614a9f1c9e2 1285 /**
AnnaBridge 165:e614a9f1c9e2 1286 * @brief Get Channel 7 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1287 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge 165:e614a9f1c9e2 1288 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1289 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1290 */
AnnaBridge 165:e614a9f1c9e2 1291 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1292 {
AnnaBridge 165:e614a9f1c9e2 1293 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge 165:e614a9f1c9e2 1294 }
AnnaBridge 165:e614a9f1c9e2 1295
AnnaBridge 165:e614a9f1c9e2 1296 /**
AnnaBridge 165:e614a9f1c9e2 1297 * @brief Get Channel 1 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1298 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge 165:e614a9f1c9e2 1299 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1300 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1301 */
AnnaBridge 165:e614a9f1c9e2 1302 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1303 {
AnnaBridge 165:e614a9f1c9e2 1304 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge 165:e614a9f1c9e2 1305 }
AnnaBridge 165:e614a9f1c9e2 1306
AnnaBridge 165:e614a9f1c9e2 1307 /**
AnnaBridge 165:e614a9f1c9e2 1308 * @brief Get Channel 2 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1309 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge 165:e614a9f1c9e2 1310 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1311 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1312 */
AnnaBridge 165:e614a9f1c9e2 1313 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1314 {
AnnaBridge 165:e614a9f1c9e2 1315 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge 165:e614a9f1c9e2 1316 }
AnnaBridge 165:e614a9f1c9e2 1317
AnnaBridge 165:e614a9f1c9e2 1318 /**
AnnaBridge 165:e614a9f1c9e2 1319 * @brief Get Channel 3 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1320 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge 165:e614a9f1c9e2 1321 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1322 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1323 */
AnnaBridge 165:e614a9f1c9e2 1324 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1325 {
AnnaBridge 165:e614a9f1c9e2 1326 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge 165:e614a9f1c9e2 1327 }
AnnaBridge 165:e614a9f1c9e2 1328
AnnaBridge 165:e614a9f1c9e2 1329 /**
AnnaBridge 165:e614a9f1c9e2 1330 * @brief Get Channel 4 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1331 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge 165:e614a9f1c9e2 1332 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1333 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1334 */
AnnaBridge 165:e614a9f1c9e2 1335 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1336 {
AnnaBridge 165:e614a9f1c9e2 1337 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge 165:e614a9f1c9e2 1338 }
AnnaBridge 165:e614a9f1c9e2 1339
AnnaBridge 165:e614a9f1c9e2 1340 /**
AnnaBridge 165:e614a9f1c9e2 1341 * @brief Get Channel 5 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1342 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge 165:e614a9f1c9e2 1343 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1344 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1345 */
AnnaBridge 165:e614a9f1c9e2 1346 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1347 {
AnnaBridge 165:e614a9f1c9e2 1348 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge 165:e614a9f1c9e2 1349 }
AnnaBridge 165:e614a9f1c9e2 1350
AnnaBridge 165:e614a9f1c9e2 1351 /**
AnnaBridge 165:e614a9f1c9e2 1352 * @brief Get Channel 6 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1353 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge 165:e614a9f1c9e2 1354 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1355 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1356 */
AnnaBridge 165:e614a9f1c9e2 1357 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1358 {
AnnaBridge 165:e614a9f1c9e2 1359 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge 165:e614a9f1c9e2 1360 }
AnnaBridge 165:e614a9f1c9e2 1361
AnnaBridge 165:e614a9f1c9e2 1362 /**
AnnaBridge 165:e614a9f1c9e2 1363 * @brief Get Channel 7 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1364 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge 165:e614a9f1c9e2 1365 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1366 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1367 */
AnnaBridge 165:e614a9f1c9e2 1368 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1369 {
AnnaBridge 165:e614a9f1c9e2 1370 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge 165:e614a9f1c9e2 1371 }
AnnaBridge 165:e614a9f1c9e2 1372
AnnaBridge 165:e614a9f1c9e2 1373 /**
AnnaBridge 165:e614a9f1c9e2 1374 * @brief Get Channel 1 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1375 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge 165:e614a9f1c9e2 1376 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1377 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1378 */
AnnaBridge 165:e614a9f1c9e2 1379 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1380 {
AnnaBridge 165:e614a9f1c9e2 1381 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge 165:e614a9f1c9e2 1382 }
AnnaBridge 165:e614a9f1c9e2 1383
AnnaBridge 165:e614a9f1c9e2 1384 /**
AnnaBridge 165:e614a9f1c9e2 1385 * @brief Get Channel 2 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1386 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge 165:e614a9f1c9e2 1387 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1388 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1389 */
AnnaBridge 165:e614a9f1c9e2 1390 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1391 {
AnnaBridge 165:e614a9f1c9e2 1392 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge 165:e614a9f1c9e2 1393 }
AnnaBridge 165:e614a9f1c9e2 1394
AnnaBridge 165:e614a9f1c9e2 1395 /**
AnnaBridge 165:e614a9f1c9e2 1396 * @brief Get Channel 3 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1397 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge 165:e614a9f1c9e2 1398 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1399 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1400 */
AnnaBridge 165:e614a9f1c9e2 1401 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1402 {
AnnaBridge 165:e614a9f1c9e2 1403 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge 165:e614a9f1c9e2 1404 }
AnnaBridge 165:e614a9f1c9e2 1405
AnnaBridge 165:e614a9f1c9e2 1406 /**
AnnaBridge 165:e614a9f1c9e2 1407 * @brief Get Channel 4 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1408 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge 165:e614a9f1c9e2 1409 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1410 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1411 */
AnnaBridge 165:e614a9f1c9e2 1412 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1413 {
AnnaBridge 165:e614a9f1c9e2 1414 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge 165:e614a9f1c9e2 1415 }
AnnaBridge 165:e614a9f1c9e2 1416
AnnaBridge 165:e614a9f1c9e2 1417 /**
AnnaBridge 165:e614a9f1c9e2 1418 * @brief Get Channel 5 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1419 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge 165:e614a9f1c9e2 1420 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1421 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1422 */
AnnaBridge 165:e614a9f1c9e2 1423 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1424 {
AnnaBridge 165:e614a9f1c9e2 1425 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge 165:e614a9f1c9e2 1426 }
AnnaBridge 165:e614a9f1c9e2 1427
AnnaBridge 165:e614a9f1c9e2 1428 /**
AnnaBridge 165:e614a9f1c9e2 1429 * @brief Get Channel 6 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1430 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge 165:e614a9f1c9e2 1431 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1432 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1433 */
AnnaBridge 165:e614a9f1c9e2 1434 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1435 {
AnnaBridge 165:e614a9f1c9e2 1436 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge 165:e614a9f1c9e2 1437 }
AnnaBridge 165:e614a9f1c9e2 1438
AnnaBridge 165:e614a9f1c9e2 1439 /**
AnnaBridge 165:e614a9f1c9e2 1440 * @brief Get Channel 7 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1441 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge 165:e614a9f1c9e2 1442 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1443 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1444 */
AnnaBridge 165:e614a9f1c9e2 1445 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1446 {
AnnaBridge 165:e614a9f1c9e2 1447 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge 165:e614a9f1c9e2 1448 }
AnnaBridge 165:e614a9f1c9e2 1449
AnnaBridge 165:e614a9f1c9e2 1450 /**
AnnaBridge 165:e614a9f1c9e2 1451 * @brief Clear Channel 1 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1452 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge 165:e614a9f1c9e2 1453 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1454 * @retval None
AnnaBridge 165:e614a9f1c9e2 1455 */
AnnaBridge 165:e614a9f1c9e2 1456 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1457 {
AnnaBridge 165:e614a9f1c9e2 1458 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge 165:e614a9f1c9e2 1459 }
AnnaBridge 165:e614a9f1c9e2 1460
AnnaBridge 165:e614a9f1c9e2 1461 /**
AnnaBridge 165:e614a9f1c9e2 1462 * @brief Clear Channel 2 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1463 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge 165:e614a9f1c9e2 1464 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1465 * @retval None
AnnaBridge 165:e614a9f1c9e2 1466 */
AnnaBridge 165:e614a9f1c9e2 1467 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1468 {
AnnaBridge 165:e614a9f1c9e2 1469 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge 165:e614a9f1c9e2 1470 }
AnnaBridge 165:e614a9f1c9e2 1471
AnnaBridge 165:e614a9f1c9e2 1472 /**
AnnaBridge 165:e614a9f1c9e2 1473 * @brief Clear Channel 3 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1474 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge 165:e614a9f1c9e2 1475 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1476 * @retval None
AnnaBridge 165:e614a9f1c9e2 1477 */
AnnaBridge 165:e614a9f1c9e2 1478 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1479 {
AnnaBridge 165:e614a9f1c9e2 1480 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge 165:e614a9f1c9e2 1481 }
AnnaBridge 165:e614a9f1c9e2 1482
AnnaBridge 165:e614a9f1c9e2 1483 /**
AnnaBridge 165:e614a9f1c9e2 1484 * @brief Clear Channel 4 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1485 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge 165:e614a9f1c9e2 1486 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1487 * @retval None
AnnaBridge 165:e614a9f1c9e2 1488 */
AnnaBridge 165:e614a9f1c9e2 1489 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1490 {
AnnaBridge 165:e614a9f1c9e2 1491 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge 165:e614a9f1c9e2 1492 }
AnnaBridge 165:e614a9f1c9e2 1493
AnnaBridge 165:e614a9f1c9e2 1494 /**
AnnaBridge 165:e614a9f1c9e2 1495 * @brief Clear Channel 5 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1496 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge 165:e614a9f1c9e2 1497 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1498 * @retval None
AnnaBridge 165:e614a9f1c9e2 1499 */
AnnaBridge 165:e614a9f1c9e2 1500 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1501 {
AnnaBridge 165:e614a9f1c9e2 1502 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge 165:e614a9f1c9e2 1503 }
AnnaBridge 165:e614a9f1c9e2 1504
AnnaBridge 165:e614a9f1c9e2 1505 /**
AnnaBridge 165:e614a9f1c9e2 1506 * @brief Clear Channel 6 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1507 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge 165:e614a9f1c9e2 1508 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1509 * @retval None
AnnaBridge 165:e614a9f1c9e2 1510 */
AnnaBridge 165:e614a9f1c9e2 1511 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1512 {
AnnaBridge 165:e614a9f1c9e2 1513 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge 165:e614a9f1c9e2 1514 }
AnnaBridge 165:e614a9f1c9e2 1515
AnnaBridge 165:e614a9f1c9e2 1516 /**
AnnaBridge 165:e614a9f1c9e2 1517 * @brief Clear Channel 7 global interrupt flag.
AnnaBridge 165:e614a9f1c9e2 1518 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge 165:e614a9f1c9e2 1519 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1520 * @retval None
AnnaBridge 165:e614a9f1c9e2 1521 */
AnnaBridge 165:e614a9f1c9e2 1522 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1523 {
AnnaBridge 165:e614a9f1c9e2 1524 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge 165:e614a9f1c9e2 1525 }
AnnaBridge 165:e614a9f1c9e2 1526
AnnaBridge 165:e614a9f1c9e2 1527 /**
AnnaBridge 165:e614a9f1c9e2 1528 * @brief Clear Channel 1 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1529 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge 165:e614a9f1c9e2 1530 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1531 * @retval None
AnnaBridge 165:e614a9f1c9e2 1532 */
AnnaBridge 165:e614a9f1c9e2 1533 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1534 {
AnnaBridge 165:e614a9f1c9e2 1535 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge 165:e614a9f1c9e2 1536 }
AnnaBridge 165:e614a9f1c9e2 1537
AnnaBridge 165:e614a9f1c9e2 1538 /**
AnnaBridge 165:e614a9f1c9e2 1539 * @brief Clear Channel 2 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1540 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge 165:e614a9f1c9e2 1541 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1542 * @retval None
AnnaBridge 165:e614a9f1c9e2 1543 */
AnnaBridge 165:e614a9f1c9e2 1544 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1545 {
AnnaBridge 165:e614a9f1c9e2 1546 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge 165:e614a9f1c9e2 1547 }
AnnaBridge 165:e614a9f1c9e2 1548
AnnaBridge 165:e614a9f1c9e2 1549 /**
AnnaBridge 165:e614a9f1c9e2 1550 * @brief Clear Channel 3 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1551 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge 165:e614a9f1c9e2 1552 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1553 * @retval None
AnnaBridge 165:e614a9f1c9e2 1554 */
AnnaBridge 165:e614a9f1c9e2 1555 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1556 {
AnnaBridge 165:e614a9f1c9e2 1557 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge 165:e614a9f1c9e2 1558 }
AnnaBridge 165:e614a9f1c9e2 1559
AnnaBridge 165:e614a9f1c9e2 1560 /**
AnnaBridge 165:e614a9f1c9e2 1561 * @brief Clear Channel 4 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1562 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge 165:e614a9f1c9e2 1563 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1564 * @retval None
AnnaBridge 165:e614a9f1c9e2 1565 */
AnnaBridge 165:e614a9f1c9e2 1566 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1567 {
AnnaBridge 165:e614a9f1c9e2 1568 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge 165:e614a9f1c9e2 1569 }
AnnaBridge 165:e614a9f1c9e2 1570
AnnaBridge 165:e614a9f1c9e2 1571 /**
AnnaBridge 165:e614a9f1c9e2 1572 * @brief Clear Channel 5 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1573 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge 165:e614a9f1c9e2 1574 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1575 * @retval None
AnnaBridge 165:e614a9f1c9e2 1576 */
AnnaBridge 165:e614a9f1c9e2 1577 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1578 {
AnnaBridge 165:e614a9f1c9e2 1579 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge 165:e614a9f1c9e2 1580 }
AnnaBridge 165:e614a9f1c9e2 1581
AnnaBridge 165:e614a9f1c9e2 1582 /**
AnnaBridge 165:e614a9f1c9e2 1583 * @brief Clear Channel 6 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1584 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge 165:e614a9f1c9e2 1585 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1586 * @retval None
AnnaBridge 165:e614a9f1c9e2 1587 */
AnnaBridge 165:e614a9f1c9e2 1588 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1589 {
AnnaBridge 165:e614a9f1c9e2 1590 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge 165:e614a9f1c9e2 1591 }
AnnaBridge 165:e614a9f1c9e2 1592
AnnaBridge 165:e614a9f1c9e2 1593 /**
AnnaBridge 165:e614a9f1c9e2 1594 * @brief Clear Channel 7 transfer complete flag.
AnnaBridge 165:e614a9f1c9e2 1595 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge 165:e614a9f1c9e2 1596 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1597 * @retval None
AnnaBridge 165:e614a9f1c9e2 1598 */
AnnaBridge 165:e614a9f1c9e2 1599 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1600 {
AnnaBridge 165:e614a9f1c9e2 1601 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge 165:e614a9f1c9e2 1602 }
AnnaBridge 165:e614a9f1c9e2 1603
AnnaBridge 165:e614a9f1c9e2 1604 /**
AnnaBridge 165:e614a9f1c9e2 1605 * @brief Clear Channel 1 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1606 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge 165:e614a9f1c9e2 1607 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1608 * @retval None
AnnaBridge 165:e614a9f1c9e2 1609 */
AnnaBridge 165:e614a9f1c9e2 1610 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1611 {
AnnaBridge 165:e614a9f1c9e2 1612 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge 165:e614a9f1c9e2 1613 }
AnnaBridge 165:e614a9f1c9e2 1614
AnnaBridge 165:e614a9f1c9e2 1615 /**
AnnaBridge 165:e614a9f1c9e2 1616 * @brief Clear Channel 2 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1617 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge 165:e614a9f1c9e2 1618 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1619 * @retval None
AnnaBridge 165:e614a9f1c9e2 1620 */
AnnaBridge 165:e614a9f1c9e2 1621 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1622 {
AnnaBridge 165:e614a9f1c9e2 1623 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge 165:e614a9f1c9e2 1624 }
AnnaBridge 165:e614a9f1c9e2 1625
AnnaBridge 165:e614a9f1c9e2 1626 /**
AnnaBridge 165:e614a9f1c9e2 1627 * @brief Clear Channel 3 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1628 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge 165:e614a9f1c9e2 1629 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1630 * @retval None
AnnaBridge 165:e614a9f1c9e2 1631 */
AnnaBridge 165:e614a9f1c9e2 1632 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1633 {
AnnaBridge 165:e614a9f1c9e2 1634 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge 165:e614a9f1c9e2 1635 }
AnnaBridge 165:e614a9f1c9e2 1636
AnnaBridge 165:e614a9f1c9e2 1637 /**
AnnaBridge 165:e614a9f1c9e2 1638 * @brief Clear Channel 4 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1639 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge 165:e614a9f1c9e2 1640 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1641 * @retval None
AnnaBridge 165:e614a9f1c9e2 1642 */
AnnaBridge 165:e614a9f1c9e2 1643 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1644 {
AnnaBridge 165:e614a9f1c9e2 1645 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge 165:e614a9f1c9e2 1646 }
AnnaBridge 165:e614a9f1c9e2 1647
AnnaBridge 165:e614a9f1c9e2 1648 /**
AnnaBridge 165:e614a9f1c9e2 1649 * @brief Clear Channel 5 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1650 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge 165:e614a9f1c9e2 1651 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1652 * @retval None
AnnaBridge 165:e614a9f1c9e2 1653 */
AnnaBridge 165:e614a9f1c9e2 1654 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1655 {
AnnaBridge 165:e614a9f1c9e2 1656 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge 165:e614a9f1c9e2 1657 }
AnnaBridge 165:e614a9f1c9e2 1658
AnnaBridge 165:e614a9f1c9e2 1659 /**
AnnaBridge 165:e614a9f1c9e2 1660 * @brief Clear Channel 6 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1661 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge 165:e614a9f1c9e2 1662 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1663 * @retval None
AnnaBridge 165:e614a9f1c9e2 1664 */
AnnaBridge 165:e614a9f1c9e2 1665 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1666 {
AnnaBridge 165:e614a9f1c9e2 1667 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge 165:e614a9f1c9e2 1668 }
AnnaBridge 165:e614a9f1c9e2 1669
AnnaBridge 165:e614a9f1c9e2 1670 /**
AnnaBridge 165:e614a9f1c9e2 1671 * @brief Clear Channel 7 half transfer flag.
AnnaBridge 165:e614a9f1c9e2 1672 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge 165:e614a9f1c9e2 1673 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1674 * @retval None
AnnaBridge 165:e614a9f1c9e2 1675 */
AnnaBridge 165:e614a9f1c9e2 1676 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1677 {
AnnaBridge 165:e614a9f1c9e2 1678 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge 165:e614a9f1c9e2 1679 }
AnnaBridge 165:e614a9f1c9e2 1680
AnnaBridge 165:e614a9f1c9e2 1681 /**
AnnaBridge 165:e614a9f1c9e2 1682 * @brief Clear Channel 1 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1683 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge 165:e614a9f1c9e2 1684 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1685 * @retval None
AnnaBridge 165:e614a9f1c9e2 1686 */
AnnaBridge 165:e614a9f1c9e2 1687 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1688 {
AnnaBridge 165:e614a9f1c9e2 1689 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge 165:e614a9f1c9e2 1690 }
AnnaBridge 165:e614a9f1c9e2 1691
AnnaBridge 165:e614a9f1c9e2 1692 /**
AnnaBridge 165:e614a9f1c9e2 1693 * @brief Clear Channel 2 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1694 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge 165:e614a9f1c9e2 1695 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1696 * @retval None
AnnaBridge 165:e614a9f1c9e2 1697 */
AnnaBridge 165:e614a9f1c9e2 1698 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1699 {
AnnaBridge 165:e614a9f1c9e2 1700 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge 165:e614a9f1c9e2 1701 }
AnnaBridge 165:e614a9f1c9e2 1702
AnnaBridge 165:e614a9f1c9e2 1703 /**
AnnaBridge 165:e614a9f1c9e2 1704 * @brief Clear Channel 3 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1705 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge 165:e614a9f1c9e2 1706 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1707 * @retval None
AnnaBridge 165:e614a9f1c9e2 1708 */
AnnaBridge 165:e614a9f1c9e2 1709 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1710 {
AnnaBridge 165:e614a9f1c9e2 1711 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge 165:e614a9f1c9e2 1712 }
AnnaBridge 165:e614a9f1c9e2 1713
AnnaBridge 165:e614a9f1c9e2 1714 /**
AnnaBridge 165:e614a9f1c9e2 1715 * @brief Clear Channel 4 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1716 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge 165:e614a9f1c9e2 1717 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1718 * @retval None
AnnaBridge 165:e614a9f1c9e2 1719 */
AnnaBridge 165:e614a9f1c9e2 1720 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1721 {
AnnaBridge 165:e614a9f1c9e2 1722 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge 165:e614a9f1c9e2 1723 }
AnnaBridge 165:e614a9f1c9e2 1724
AnnaBridge 165:e614a9f1c9e2 1725 /**
AnnaBridge 165:e614a9f1c9e2 1726 * @brief Clear Channel 5 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1727 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge 165:e614a9f1c9e2 1728 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1729 * @retval None
AnnaBridge 165:e614a9f1c9e2 1730 */
AnnaBridge 165:e614a9f1c9e2 1731 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1732 {
AnnaBridge 165:e614a9f1c9e2 1733 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge 165:e614a9f1c9e2 1734 }
AnnaBridge 165:e614a9f1c9e2 1735
AnnaBridge 165:e614a9f1c9e2 1736 /**
AnnaBridge 165:e614a9f1c9e2 1737 * @brief Clear Channel 6 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1738 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge 165:e614a9f1c9e2 1739 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1740 * @retval None
AnnaBridge 165:e614a9f1c9e2 1741 */
AnnaBridge 165:e614a9f1c9e2 1742 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1743 {
AnnaBridge 165:e614a9f1c9e2 1744 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge 165:e614a9f1c9e2 1745 }
AnnaBridge 165:e614a9f1c9e2 1746
AnnaBridge 165:e614a9f1c9e2 1747 /**
AnnaBridge 165:e614a9f1c9e2 1748 * @brief Clear Channel 7 transfer error flag.
AnnaBridge 165:e614a9f1c9e2 1749 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge 165:e614a9f1c9e2 1750 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1751 * @retval None
AnnaBridge 165:e614a9f1c9e2 1752 */
AnnaBridge 165:e614a9f1c9e2 1753 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 165:e614a9f1c9e2 1754 {
AnnaBridge 165:e614a9f1c9e2 1755 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge 165:e614a9f1c9e2 1756 }
AnnaBridge 165:e614a9f1c9e2 1757
AnnaBridge 165:e614a9f1c9e2 1758 /**
AnnaBridge 165:e614a9f1c9e2 1759 * @}
AnnaBridge 165:e614a9f1c9e2 1760 */
AnnaBridge 165:e614a9f1c9e2 1761
AnnaBridge 165:e614a9f1c9e2 1762 /** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge 165:e614a9f1c9e2 1763 * @{
AnnaBridge 165:e614a9f1c9e2 1764 */
AnnaBridge 165:e614a9f1c9e2 1765
AnnaBridge 165:e614a9f1c9e2 1766 /**
AnnaBridge 165:e614a9f1c9e2 1767 * @brief Enable Transfer complete interrupt.
AnnaBridge 165:e614a9f1c9e2 1768 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge 165:e614a9f1c9e2 1769 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1770 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1771 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1772 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1773 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1774 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1775 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1776 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1777 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1778 * @retval None
AnnaBridge 165:e614a9f1c9e2 1779 */
AnnaBridge 165:e614a9f1c9e2 1780 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1781 {
AnnaBridge 165:e614a9f1c9e2 1782 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 165:e614a9f1c9e2 1783 }
AnnaBridge 165:e614a9f1c9e2 1784
AnnaBridge 165:e614a9f1c9e2 1785 /**
AnnaBridge 165:e614a9f1c9e2 1786 * @brief Enable Half transfer interrupt.
AnnaBridge 165:e614a9f1c9e2 1787 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge 165:e614a9f1c9e2 1788 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1789 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1790 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1791 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1792 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1793 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1794 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1795 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1796 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1797 * @retval None
AnnaBridge 165:e614a9f1c9e2 1798 */
AnnaBridge 165:e614a9f1c9e2 1799 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1800 {
AnnaBridge 165:e614a9f1c9e2 1801 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 165:e614a9f1c9e2 1802 }
AnnaBridge 165:e614a9f1c9e2 1803
AnnaBridge 165:e614a9f1c9e2 1804 /**
AnnaBridge 165:e614a9f1c9e2 1805 * @brief Enable Transfer error interrupt.
AnnaBridge 165:e614a9f1c9e2 1806 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge 165:e614a9f1c9e2 1807 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1808 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1809 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1810 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1811 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1812 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1813 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1814 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1815 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1816 * @retval None
AnnaBridge 165:e614a9f1c9e2 1817 */
AnnaBridge 165:e614a9f1c9e2 1818 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1819 {
AnnaBridge 165:e614a9f1c9e2 1820 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 165:e614a9f1c9e2 1821 }
AnnaBridge 165:e614a9f1c9e2 1822
AnnaBridge 165:e614a9f1c9e2 1823 /**
AnnaBridge 165:e614a9f1c9e2 1824 * @brief Disable Transfer complete interrupt.
AnnaBridge 165:e614a9f1c9e2 1825 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge 165:e614a9f1c9e2 1826 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1827 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1828 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1829 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1830 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1831 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1832 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1833 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1834 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1835 * @retval None
AnnaBridge 165:e614a9f1c9e2 1836 */
AnnaBridge 165:e614a9f1c9e2 1837 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1838 {
AnnaBridge 165:e614a9f1c9e2 1839 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 165:e614a9f1c9e2 1840 }
AnnaBridge 165:e614a9f1c9e2 1841
AnnaBridge 165:e614a9f1c9e2 1842 /**
AnnaBridge 165:e614a9f1c9e2 1843 * @brief Disable Half transfer interrupt.
AnnaBridge 165:e614a9f1c9e2 1844 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge 165:e614a9f1c9e2 1845 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1846 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1847 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1848 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1849 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1850 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1851 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1852 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1853 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1854 * @retval None
AnnaBridge 165:e614a9f1c9e2 1855 */
AnnaBridge 165:e614a9f1c9e2 1856 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1857 {
AnnaBridge 165:e614a9f1c9e2 1858 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 165:e614a9f1c9e2 1859 }
AnnaBridge 165:e614a9f1c9e2 1860
AnnaBridge 165:e614a9f1c9e2 1861 /**
AnnaBridge 165:e614a9f1c9e2 1862 * @brief Disable Transfer error interrupt.
AnnaBridge 165:e614a9f1c9e2 1863 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge 165:e614a9f1c9e2 1864 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1865 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1866 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1867 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1868 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1869 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1870 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1871 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1872 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1873 * @retval None
AnnaBridge 165:e614a9f1c9e2 1874 */
AnnaBridge 165:e614a9f1c9e2 1875 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1876 {
AnnaBridge 165:e614a9f1c9e2 1877 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 165:e614a9f1c9e2 1878 }
AnnaBridge 165:e614a9f1c9e2 1879
AnnaBridge 165:e614a9f1c9e2 1880 /**
AnnaBridge 165:e614a9f1c9e2 1881 * @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge 165:e614a9f1c9e2 1882 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge 165:e614a9f1c9e2 1883 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1884 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1885 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1886 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1887 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1888 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1889 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1890 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1891 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1892 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1893 */
AnnaBridge 165:e614a9f1c9e2 1894 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1895 {
AnnaBridge 165:e614a9f1c9e2 1896 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 1897 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge 165:e614a9f1c9e2 1898 }
AnnaBridge 165:e614a9f1c9e2 1899
AnnaBridge 165:e614a9f1c9e2 1900 /**
AnnaBridge 165:e614a9f1c9e2 1901 * @brief Check if Half transfer Interrupt is enabled.
AnnaBridge 165:e614a9f1c9e2 1902 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge 165:e614a9f1c9e2 1903 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1904 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1905 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1906 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1907 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1908 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1909 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1910 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1911 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1912 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1913 */
AnnaBridge 165:e614a9f1c9e2 1914 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1915 {
AnnaBridge 165:e614a9f1c9e2 1916 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 1917 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge 165:e614a9f1c9e2 1918 }
AnnaBridge 165:e614a9f1c9e2 1919
AnnaBridge 165:e614a9f1c9e2 1920 /**
AnnaBridge 165:e614a9f1c9e2 1921 * @brief Check if Transfer error Interrupt is enabled.
AnnaBridge 165:e614a9f1c9e2 1922 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge 165:e614a9f1c9e2 1923 * @param DMAx DMAx Instance
AnnaBridge 165:e614a9f1c9e2 1924 * @param Channel This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1925 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 165:e614a9f1c9e2 1926 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 165:e614a9f1c9e2 1927 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 165:e614a9f1c9e2 1928 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 165:e614a9f1c9e2 1929 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 165:e614a9f1c9e2 1930 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 165:e614a9f1c9e2 1931 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 165:e614a9f1c9e2 1932 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1933 */
AnnaBridge 165:e614a9f1c9e2 1934 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 165:e614a9f1c9e2 1935 {
AnnaBridge 165:e614a9f1c9e2 1936 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 165:e614a9f1c9e2 1937 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge 165:e614a9f1c9e2 1938 }
AnnaBridge 165:e614a9f1c9e2 1939
AnnaBridge 165:e614a9f1c9e2 1940 /**
AnnaBridge 165:e614a9f1c9e2 1941 * @}
AnnaBridge 165:e614a9f1c9e2 1942 */
AnnaBridge 165:e614a9f1c9e2 1943
AnnaBridge 165:e614a9f1c9e2 1944 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 165:e614a9f1c9e2 1945 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 1946 * @{
AnnaBridge 165:e614a9f1c9e2 1947 */
AnnaBridge 165:e614a9f1c9e2 1948
AnnaBridge 165:e614a9f1c9e2 1949 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 165:e614a9f1c9e2 1950 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge 165:e614a9f1c9e2 1951 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 165:e614a9f1c9e2 1952
AnnaBridge 165:e614a9f1c9e2 1953 /**
AnnaBridge 165:e614a9f1c9e2 1954 * @}
AnnaBridge 165:e614a9f1c9e2 1955 */
AnnaBridge 165:e614a9f1c9e2 1956 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 165:e614a9f1c9e2 1957
AnnaBridge 165:e614a9f1c9e2 1958 /**
AnnaBridge 165:e614a9f1c9e2 1959 * @}
AnnaBridge 165:e614a9f1c9e2 1960 */
AnnaBridge 165:e614a9f1c9e2 1961
AnnaBridge 165:e614a9f1c9e2 1962 /**
AnnaBridge 165:e614a9f1c9e2 1963 * @}
AnnaBridge 165:e614a9f1c9e2 1964 */
AnnaBridge 165:e614a9f1c9e2 1965
AnnaBridge 165:e614a9f1c9e2 1966 #endif /* DMA1 || DMA2 */
AnnaBridge 165:e614a9f1c9e2 1967
AnnaBridge 165:e614a9f1c9e2 1968 /**
AnnaBridge 165:e614a9f1c9e2 1969 * @}
AnnaBridge 165:e614a9f1c9e2 1970 */
AnnaBridge 165:e614a9f1c9e2 1971
AnnaBridge 165:e614a9f1c9e2 1972 #ifdef __cplusplus
AnnaBridge 165:e614a9f1c9e2 1973 }
AnnaBridge 165:e614a9f1c9e2 1974 #endif
AnnaBridge 165:e614a9f1c9e2 1975
AnnaBridge 165:e614a9f1c9e2 1976 #endif /* __STM32F1xx_LL_DMA_H */
AnnaBridge 165:e614a9f1c9e2 1977
AnnaBridge 165:e614a9f1c9e2 1978 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/