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Fork of mbed-dev-f303 by Ben Katz

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_csen.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**************************************************************************//**
<> 161:2cc1468da177 2 * @file efm32pg12b_csen.h
<> 161:2cc1468da177 3 * @brief EFM32PG12B_CSEN register and bit field definitions
<> 161:2cc1468da177 4 * @version 5.1.2
<> 161:2cc1468da177 5 ******************************************************************************
<> 161:2cc1468da177 6 * @section License
<> 161:2cc1468da177 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 161:2cc1468da177 8 ******************************************************************************
<> 161:2cc1468da177 9 *
<> 161:2cc1468da177 10 * Permission is granted to anyone to use this software for any purpose,
<> 161:2cc1468da177 11 * including commercial applications, and to alter it and redistribute it
<> 161:2cc1468da177 12 * freely, subject to the following restrictions:
<> 161:2cc1468da177 13 *
<> 161:2cc1468da177 14 * 1. The origin of this software must not be misrepresented; you must not
<> 161:2cc1468da177 15 * claim that you wrote the original software.@n
<> 161:2cc1468da177 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 161:2cc1468da177 17 * misrepresented as being the original software.@n
<> 161:2cc1468da177 18 * 3. This notice may not be removed or altered from any source distribution.
<> 161:2cc1468da177 19 *
<> 161:2cc1468da177 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 161:2cc1468da177 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 161:2cc1468da177 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 161:2cc1468da177 23 * kind, including, but not limited to, any implied warranties of
<> 161:2cc1468da177 24 * merchantability or fitness for any particular purpose or warranties against
<> 161:2cc1468da177 25 * infringement of any proprietary rights of a third party.
<> 161:2cc1468da177 26 *
<> 161:2cc1468da177 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 161:2cc1468da177 28 * incidental, or special damages, or any other relief, or for any claim by
<> 161:2cc1468da177 29 * any third party, arising from your use of this Software.
<> 161:2cc1468da177 30 *
<> 161:2cc1468da177 31 *****************************************************************************/
<> 161:2cc1468da177 32 /**************************************************************************//**
<> 161:2cc1468da177 33 * @addtogroup Parts
<> 161:2cc1468da177 34 * @{
<> 161:2cc1468da177 35 ******************************************************************************/
<> 161:2cc1468da177 36 /**************************************************************************//**
<> 161:2cc1468da177 37 * @defgroup EFM32PG12B_CSEN
<> 161:2cc1468da177 38 * @{
<> 161:2cc1468da177 39 * @brief EFM32PG12B_CSEN Register Declaration
<> 161:2cc1468da177 40 *****************************************************************************/
<> 161:2cc1468da177 41 typedef struct
<> 161:2cc1468da177 42 {
<> 161:2cc1468da177 43 __IOM uint32_t CTRL; /**< Control Register */
<> 161:2cc1468da177 44 __IOM uint32_t TIMCTRL; /**< Timing Control Register */
<> 161:2cc1468da177 45 __IOM uint32_t CMD; /**< Command Register */
<> 161:2cc1468da177 46 __IM uint32_t STATUS; /**< Status Register */
<> 161:2cc1468da177 47 __IOM uint32_t PRSSEL; /**< Control Register */
<> 161:2cc1468da177 48 __IOM uint32_t DATA; /**< Control Register */
<> 161:2cc1468da177 49 __IOM uint32_t SCANMASK0; /**< CSEN Channel Scan Mask */
<> 161:2cc1468da177 50 __IOM uint32_t SCANINPUTSEL0; /**< Input Channel Configuration register for Scan mode */
<> 161:2cc1468da177 51 __IOM uint32_t SCANMASK1; /**< CSEN Channel Scan Mask */
<> 161:2cc1468da177 52 __IOM uint32_t SCANINPUTSEL1; /**< Input Channel Configuration register for Scan mode */
<> 161:2cc1468da177 53 __IM uint32_t APORTREQ; /**< APORT Request Status Register */
<> 161:2cc1468da177 54 __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
<> 161:2cc1468da177 55 __IOM uint32_t CMPTHR; /**< CSEN Comparator Threshold */
<> 161:2cc1468da177 56 __IOM uint32_t EMA; /**< Exponential Moving Average */
<> 161:2cc1468da177 57 __IOM uint32_t EMACTRL; /**< Exponential Moving Average */
<> 161:2cc1468da177 58 __IOM uint32_t SINGLECTRL; /**< CSEN Single Conversion Control Register */
<> 161:2cc1468da177 59 __IOM uint32_t DMBASELINE; /**< Control Register */
<> 161:2cc1468da177 60 __IOM uint32_t DMCFG; /**< Control Register */
<> 161:2cc1468da177 61 __IOM uint32_t ANACTRL; /**< Analog Control Register */
<> 161:2cc1468da177 62
<> 161:2cc1468da177 63 uint32_t RESERVED0[2]; /**< Reserved for future use **/
<> 161:2cc1468da177 64 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 161:2cc1468da177 65 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 161:2cc1468da177 66 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 161:2cc1468da177 67 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 161:2cc1468da177 68 } CSEN_TypeDef; /** @} */
<> 161:2cc1468da177 69
<> 161:2cc1468da177 70 /**************************************************************************//**
<> 161:2cc1468da177 71 * @defgroup EFM32PG12B_CSEN_BitFields
<> 161:2cc1468da177 72 * @{
<> 161:2cc1468da177 73 *****************************************************************************/
<> 161:2cc1468da177 74
<> 161:2cc1468da177 75 /* Bit fields for CSEN CTRL */
<> 161:2cc1468da177 76 #define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */
<> 161:2cc1468da177 77 #define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */
<> 161:2cc1468da177 78 #define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */
<> 161:2cc1468da177 79 #define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */
<> 161:2cc1468da177 80 #define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */
<> 161:2cc1468da177 81 #define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 82 #define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 83 #define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 84 #define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 85 #define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 86 #define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 87 #define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */
<> 161:2cc1468da177 88 #define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */
<> 161:2cc1468da177 89 #define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */
<> 161:2cc1468da177 90 #define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 91 #define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */
<> 161:2cc1468da177 92 #define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */
<> 161:2cc1468da177 93 #define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 94 #define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */
<> 161:2cc1468da177 95 #define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */
<> 161:2cc1468da177 96 #define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */
<> 161:2cc1468da177 97 #define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */
<> 161:2cc1468da177 98 #define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 99 #define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */
<> 161:2cc1468da177 100 #define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */
<> 161:2cc1468da177 101 #define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */
<> 161:2cc1468da177 102 #define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */
<> 161:2cc1468da177 103 #define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 104 #define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */
<> 161:2cc1468da177 105 #define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */
<> 161:2cc1468da177 106 #define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */
<> 161:2cc1468da177 107 #define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */
<> 161:2cc1468da177 108 #define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */
<> 161:2cc1468da177 109 #define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */
<> 161:2cc1468da177 110 #define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 111 #define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */
<> 161:2cc1468da177 112 #define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */
<> 161:2cc1468da177 113 #define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */
<> 161:2cc1468da177 114 #define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */
<> 161:2cc1468da177 115 #define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 116 #define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */
<> 161:2cc1468da177 117 #define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */
<> 161:2cc1468da177 118 #define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */
<> 161:2cc1468da177 119 #define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */
<> 161:2cc1468da177 120 #define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */
<> 161:2cc1468da177 121 #define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */
<> 161:2cc1468da177 122 #define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 123 #define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */
<> 161:2cc1468da177 124 #define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */
<> 161:2cc1468da177 125 #define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */
<> 161:2cc1468da177 126 #define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */
<> 161:2cc1468da177 127 #define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */
<> 161:2cc1468da177 128 #define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */
<> 161:2cc1468da177 129 #define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */
<> 161:2cc1468da177 130 #define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 131 #define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */
<> 161:2cc1468da177 132 #define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */
<> 161:2cc1468da177 133 #define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */
<> 161:2cc1468da177 134 #define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */
<> 161:2cc1468da177 135 #define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */
<> 161:2cc1468da177 136 #define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */
<> 161:2cc1468da177 137 #define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */
<> 161:2cc1468da177 138 #define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable. */
<> 161:2cc1468da177 139 #define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */
<> 161:2cc1468da177 140 #define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */
<> 161:2cc1468da177 141 #define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 142 #define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 143 #define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 144 #define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 145 #define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 146 #define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 147 #define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */
<> 161:2cc1468da177 148 #define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */
<> 161:2cc1468da177 149 #define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */
<> 161:2cc1468da177 150 #define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */
<> 161:2cc1468da177 151 #define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */
<> 161:2cc1468da177 152 #define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 153 #define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 154 #define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */
<> 161:2cc1468da177 155 #define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */
<> 161:2cc1468da177 156 #define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */
<> 161:2cc1468da177 157 #define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 158 #define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 159 #define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable Bit. */
<> 161:2cc1468da177 160 #define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */
<> 161:2cc1468da177 161 #define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */
<> 161:2cc1468da177 162 #define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 163 #define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 164 #define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 165 #define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 166 #define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 167 #define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 168 #define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift. */
<> 161:2cc1468da177 169 #define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */
<> 161:2cc1468da177 170 #define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */
<> 161:2cc1468da177 171 #define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 172 #define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 173 #define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 174 #define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 175 #define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 176 #define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 177 #define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit. */
<> 161:2cc1468da177 178 #define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */
<> 161:2cc1468da177 179 #define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */
<> 161:2cc1468da177 180 #define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 181 #define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 182 #define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 183 #define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 184 #define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 185 #define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 186 #define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */
<> 161:2cc1468da177 187 #define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */
<> 161:2cc1468da177 188 #define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */
<> 161:2cc1468da177 189 #define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 190 #define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */
<> 161:2cc1468da177 191 #define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */
<> 161:2cc1468da177 192 #define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 193 #define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */
<> 161:2cc1468da177 194 #define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */
<> 161:2cc1468da177 195 #define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */
<> 161:2cc1468da177 196 #define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */
<> 161:2cc1468da177 197 #define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */
<> 161:2cc1468da177 198 #define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 199 #define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 200 #define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 201 #define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 202 #define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 203 #define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 204 #define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN auto ground enable */
<> 161:2cc1468da177 205 #define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */
<> 161:2cc1468da177 206 #define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */
<> 161:2cc1468da177 207 #define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 208 #define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 209 #define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 210 #define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 211 #define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */
<> 161:2cc1468da177 212 #define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */
<> 161:2cc1468da177 213 #define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect. */
<> 161:2cc1468da177 214 #define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */
<> 161:2cc1468da177 215 #define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */
<> 161:2cc1468da177 216 #define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 217 #define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */
<> 161:2cc1468da177 218 #define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */
<> 161:2cc1468da177 219 #define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 220 #define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */
<> 161:2cc1468da177 221 #define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */
<> 161:2cc1468da177 222 #define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and less than comparison using the exponential moving average (EMA) is enabled. */
<> 161:2cc1468da177 223 #define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */
<> 161:2cc1468da177 224 #define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */
<> 161:2cc1468da177 225 #define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 226 #define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 227 #define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup mode for CSEN */
<> 161:2cc1468da177 228 #define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */
<> 161:2cc1468da177 229 #define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */
<> 161:2cc1468da177 230 #define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 231 #define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */
<> 161:2cc1468da177 232 #define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */
<> 161:2cc1468da177 233 #define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 234 #define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */
<> 161:2cc1468da177 235 #define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */
<> 161:2cc1468da177 236 #define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Sense local cap connection instead of the external kelvin connection. */
<> 161:2cc1468da177 237 #define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */
<> 161:2cc1468da177 238 #define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */
<> 161:2cc1468da177 239 #define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 240 #define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 241 #define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Sets the accuracy of the charge pump. */
<> 161:2cc1468da177 242 #define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */
<> 161:2cc1468da177 243 #define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */
<> 161:2cc1468da177 244 #define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 245 #define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */
<> 161:2cc1468da177 246 #define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */
<> 161:2cc1468da177 247 #define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */
<> 161:2cc1468da177 248 #define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */
<> 161:2cc1468da177 249 #define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */
<> 161:2cc1468da177 250
<> 161:2cc1468da177 251 /* Bit fields for CSEN TIMCTRL */
<> 161:2cc1468da177 252 #define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */
<> 161:2cc1468da177 253 #define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */
<> 161:2cc1468da177 254 #define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */
<> 161:2cc1468da177 255 #define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */
<> 161:2cc1468da177 256 #define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */
<> 161:2cc1468da177 257 #define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */
<> 161:2cc1468da177 258 #define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */
<> 161:2cc1468da177 259 #define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */
<> 161:2cc1468da177 260 #define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */
<> 161:2cc1468da177 261 #define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */
<> 161:2cc1468da177 262 #define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */
<> 161:2cc1468da177 263 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */
<> 161:2cc1468da177 264 #define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */
<> 161:2cc1468da177 265 #define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
<> 161:2cc1468da177 266 #define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */
<> 161:2cc1468da177 267 #define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */
<> 161:2cc1468da177 268 #define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */
<> 161:2cc1468da177 269 #define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */
<> 161:2cc1468da177 270 #define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */
<> 161:2cc1468da177 271 #define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */
<> 161:2cc1468da177 272 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */
<> 161:2cc1468da177 273 #define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */
<> 161:2cc1468da177 274 #define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */
<> 161:2cc1468da177 275 #define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */
<> 161:2cc1468da177 276 #define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */
<> 161:2cc1468da177 277 #define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
<> 161:2cc1468da177 278 #define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */
<> 161:2cc1468da177 279 #define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */
<> 161:2cc1468da177 280 #define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */
<> 161:2cc1468da177 281 #define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
<> 161:2cc1468da177 282
<> 161:2cc1468da177 283 /* Bit fields for CSEN CMD */
<> 161:2cc1468da177 284 #define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */
<> 161:2cc1468da177 285 #define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */
<> 161:2cc1468da177 286 #define CSEN_CMD_START (0x1UL << 0) /**< Start a CSEN conversion. */
<> 161:2cc1468da177 287 #define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */
<> 161:2cc1468da177 288 #define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */
<> 161:2cc1468da177 289 #define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */
<> 161:2cc1468da177 290 #define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */
<> 161:2cc1468da177 291
<> 161:2cc1468da177 292 /* Bit fields for CSEN STATUS */
<> 161:2cc1468da177 293 #define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */
<> 161:2cc1468da177 294 #define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */
<> 161:2cc1468da177 295 #define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< CSEN Busy */
<> 161:2cc1468da177 296 #define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */
<> 161:2cc1468da177 297 #define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */
<> 161:2cc1468da177 298 #define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */
<> 161:2cc1468da177 299 #define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */
<> 161:2cc1468da177 300 #define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */
<> 161:2cc1468da177 301 #define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */
<> 161:2cc1468da177 302 #define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */
<> 161:2cc1468da177 303 #define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */
<> 161:2cc1468da177 304
<> 161:2cc1468da177 305 /* Bit fields for CSEN PRSSEL */
<> 161:2cc1468da177 306 #define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */
<> 161:2cc1468da177 307 #define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */
<> 161:2cc1468da177 308 #define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */
<> 161:2cc1468da177 309 #define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */
<> 161:2cc1468da177 310 #define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */
<> 161:2cc1468da177 311 #define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */
<> 161:2cc1468da177 312 #define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */
<> 161:2cc1468da177 313 #define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */
<> 161:2cc1468da177 314 #define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */
<> 161:2cc1468da177 315 #define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */
<> 161:2cc1468da177 316 #define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */
<> 161:2cc1468da177 317 #define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */
<> 161:2cc1468da177 318 #define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */
<> 161:2cc1468da177 319 #define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */
<> 161:2cc1468da177 320 #define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */
<> 161:2cc1468da177 321 #define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */
<> 161:2cc1468da177 322 #define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */
<> 161:2cc1468da177 323 #define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */
<> 161:2cc1468da177 324 #define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */
<> 161:2cc1468da177 325 #define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */
<> 161:2cc1468da177 326 #define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */
<> 161:2cc1468da177 327 #define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */
<> 161:2cc1468da177 328 #define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */
<> 161:2cc1468da177 329 #define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */
<> 161:2cc1468da177 330 #define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */
<> 161:2cc1468da177 331 #define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */
<> 161:2cc1468da177 332 #define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */
<> 161:2cc1468da177 333 #define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */
<> 161:2cc1468da177 334 #define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */
<> 161:2cc1468da177 335 #define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */
<> 161:2cc1468da177 336
<> 161:2cc1468da177 337 /* Bit fields for CSEN DATA */
<> 161:2cc1468da177 338 #define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */
<> 161:2cc1468da177 339 #define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */
<> 161:2cc1468da177 340 #define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */
<> 161:2cc1468da177 341 #define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */
<> 161:2cc1468da177 342 #define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */
<> 161:2cc1468da177 343 #define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */
<> 161:2cc1468da177 344
<> 161:2cc1468da177 345 /* Bit fields for CSEN SCANMASK0 */
<> 161:2cc1468da177 346 #define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */
<> 161:2cc1468da177 347 #define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */
<> 161:2cc1468da177 348 #define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */
<> 161:2cc1468da177 349 #define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */
<> 161:2cc1468da177 350 #define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */
<> 161:2cc1468da177 351 #define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */
<> 161:2cc1468da177 352
<> 161:2cc1468da177 353 /* Bit fields for CSEN SCANINPUTSEL0 */
<> 161:2cc1468da177 354 #define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 355 #define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 356 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */
<> 161:2cc1468da177 357 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */
<> 161:2cc1468da177 358 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 359 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 360 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 361 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 362 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 363 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 364 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 365 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 366 #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 367 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 368 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 369 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 370 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 371 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 372 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 373 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 374 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 375 #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 376 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */
<> 161:2cc1468da177 377 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */
<> 161:2cc1468da177 378 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 379 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 380 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 381 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 382 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 383 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 384 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 385 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 386 #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 387 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 388 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 389 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 390 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 391 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 392 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 393 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 394 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 395 #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 396 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */
<> 161:2cc1468da177 397 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */
<> 161:2cc1468da177 398 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 399 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 400 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 401 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 402 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 403 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 404 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 405 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 406 #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 407 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 408 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 409 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 410 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 411 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 412 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 413 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 414 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 415 #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 416 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */
<> 161:2cc1468da177 417 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */
<> 161:2cc1468da177 418 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 419 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 420 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 421 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 422 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 423 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 424 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 425 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 426 #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 427 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 428 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 429 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 430 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 431 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 432 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 433 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 434 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 435 #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
<> 161:2cc1468da177 436
<> 161:2cc1468da177 437 /* Bit fields for CSEN SCANMASK1 */
<> 161:2cc1468da177 438 #define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */
<> 161:2cc1468da177 439 #define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */
<> 161:2cc1468da177 440 #define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */
<> 161:2cc1468da177 441 #define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */
<> 161:2cc1468da177 442 #define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */
<> 161:2cc1468da177 443 #define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */
<> 161:2cc1468da177 444
<> 161:2cc1468da177 445 /* Bit fields for CSEN SCANINPUTSEL1 */
<> 161:2cc1468da177 446 #define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 447 #define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 448 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */
<> 161:2cc1468da177 449 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */
<> 161:2cc1468da177 450 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 451 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 452 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 453 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 454 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 455 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 456 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 457 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 458 #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 459 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 460 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 461 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 462 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 463 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 464 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 465 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 466 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 467 #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 468 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */
<> 161:2cc1468da177 469 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */
<> 161:2cc1468da177 470 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 471 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 472 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 473 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 474 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 475 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 476 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 477 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 478 #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 479 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 480 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 481 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 482 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 483 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 484 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 485 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 486 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 487 #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 488 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */
<> 161:2cc1468da177 489 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */
<> 161:2cc1468da177 490 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 491 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 492 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 493 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 494 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 495 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 496 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 497 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 498 #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 499 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 500 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 501 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 502 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 503 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 504 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 505 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 506 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 507 #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 508 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */
<> 161:2cc1468da177 509 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */
<> 161:2cc1468da177 510 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 511 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 512 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 513 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 514 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 515 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 516 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 517 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 518 #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 519 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 520 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 521 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 522 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 523 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 524 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 525 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 526 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 527 #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
<> 161:2cc1468da177 528
<> 161:2cc1468da177 529 /* Bit fields for CSEN APORTREQ */
<> 161:2cc1468da177 530 #define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */
<> 161:2cc1468da177 531 #define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */
<> 161:2cc1468da177 532 #define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */
<> 161:2cc1468da177 533 #define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */
<> 161:2cc1468da177 534 #define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */
<> 161:2cc1468da177 535 #define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 536 #define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 537 #define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */
<> 161:2cc1468da177 538 #define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */
<> 161:2cc1468da177 539 #define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */
<> 161:2cc1468da177 540 #define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 541 #define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 542 #define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
<> 161:2cc1468da177 543 #define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */
<> 161:2cc1468da177 544 #define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */
<> 161:2cc1468da177 545 #define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 546 #define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 547 #define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
<> 161:2cc1468da177 548 #define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */
<> 161:2cc1468da177 549 #define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */
<> 161:2cc1468da177 550 #define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 551 #define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 552 #define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
<> 161:2cc1468da177 553 #define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */
<> 161:2cc1468da177 554 #define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */
<> 161:2cc1468da177 555 #define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 556 #define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 557 #define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
<> 161:2cc1468da177 558 #define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */
<> 161:2cc1468da177 559 #define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */
<> 161:2cc1468da177 560 #define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 561 #define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 562 #define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
<> 161:2cc1468da177 563 #define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */
<> 161:2cc1468da177 564 #define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */
<> 161:2cc1468da177 565 #define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 566 #define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 567 #define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
<> 161:2cc1468da177 568 #define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */
<> 161:2cc1468da177 569 #define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */
<> 161:2cc1468da177 570 #define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 571 #define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
<> 161:2cc1468da177 572
<> 161:2cc1468da177 573 /* Bit fields for CSEN APORTCONFLICT */
<> 161:2cc1468da177 574 #define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 575 #define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 576 #define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
<> 161:2cc1468da177 577 #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */
<> 161:2cc1468da177 578 #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */
<> 161:2cc1468da177 579 #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 580 #define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 581 #define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
<> 161:2cc1468da177 582 #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */
<> 161:2cc1468da177 583 #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */
<> 161:2cc1468da177 584 #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 585 #define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 586 #define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
<> 161:2cc1468da177 587 #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */
<> 161:2cc1468da177 588 #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */
<> 161:2cc1468da177 589 #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 590 #define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 591 #define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
<> 161:2cc1468da177 592 #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */
<> 161:2cc1468da177 593 #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */
<> 161:2cc1468da177 594 #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 595 #define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 596 #define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
<> 161:2cc1468da177 597 #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */
<> 161:2cc1468da177 598 #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */
<> 161:2cc1468da177 599 #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 600 #define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 601 #define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
<> 161:2cc1468da177 602 #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */
<> 161:2cc1468da177 603 #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */
<> 161:2cc1468da177 604 #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 605 #define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 606 #define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
<> 161:2cc1468da177 607 #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */
<> 161:2cc1468da177 608 #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */
<> 161:2cc1468da177 609 #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 610 #define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 611 #define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
<> 161:2cc1468da177 612 #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */
<> 161:2cc1468da177 613 #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */
<> 161:2cc1468da177 614 #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 615 #define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 616
<> 161:2cc1468da177 617 /* Bit fields for CSEN CMPTHR */
<> 161:2cc1468da177 618 #define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */
<> 161:2cc1468da177 619 #define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */
<> 161:2cc1468da177 620 #define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */
<> 161:2cc1468da177 621 #define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */
<> 161:2cc1468da177 622 #define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */
<> 161:2cc1468da177 623 #define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */
<> 161:2cc1468da177 624
<> 161:2cc1468da177 625 /* Bit fields for CSEN EMA */
<> 161:2cc1468da177 626 #define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */
<> 161:2cc1468da177 627 #define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */
<> 161:2cc1468da177 628 #define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */
<> 161:2cc1468da177 629 #define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */
<> 161:2cc1468da177 630 #define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */
<> 161:2cc1468da177 631 #define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */
<> 161:2cc1468da177 632
<> 161:2cc1468da177 633 /* Bit fields for CSEN EMACTRL */
<> 161:2cc1468da177 634 #define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */
<> 161:2cc1468da177 635 #define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */
<> 161:2cc1468da177 636 #define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */
<> 161:2cc1468da177 637 #define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */
<> 161:2cc1468da177 638 #define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */
<> 161:2cc1468da177 639 #define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */
<> 161:2cc1468da177 640 #define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */
<> 161:2cc1468da177 641 #define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */
<> 161:2cc1468da177 642 #define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */
<> 161:2cc1468da177 643 #define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */
<> 161:2cc1468da177 644 #define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */
<> 161:2cc1468da177 645 #define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */
<> 161:2cc1468da177 646 #define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */
<> 161:2cc1468da177 647 #define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */
<> 161:2cc1468da177 648 #define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */
<> 161:2cc1468da177 649 #define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */
<> 161:2cc1468da177 650 #define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */
<> 161:2cc1468da177 651 #define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */
<> 161:2cc1468da177 652 #define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */
<> 161:2cc1468da177 653 #define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */
<> 161:2cc1468da177 654
<> 161:2cc1468da177 655 /* Bit fields for CSEN SINGLECTRL */
<> 161:2cc1468da177 656 #define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */
<> 161:2cc1468da177 657 #define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */
<> 161:2cc1468da177 658 #define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */
<> 161:2cc1468da177 659 #define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */
<> 161:2cc1468da177 660 #define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */
<> 161:2cc1468da177 661 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 662 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 663 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 664 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 665 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 666 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 667 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 668 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 669 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 670 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 671 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 672 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 673 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 674 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 675 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 676 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 677 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 678 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 679 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 680 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 681 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 682 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 683 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 684 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 685 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 686 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 687 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 688 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 689 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 690 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 691 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 692 #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 693 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 694 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 695 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 696 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 697 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 698 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 699 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 700 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 701 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 702 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 703 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 704 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 705 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 706 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 707 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 708 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 709 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 710 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 711 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 712 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 713 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 714 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 715 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 716 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 717 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 718 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 719 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 720 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 721 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 722 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 723 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 724 #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 725 #define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */
<> 161:2cc1468da177 726 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 727 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 728 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 729 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 730 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 731 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 732 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 733 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 734 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 735 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 736 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 737 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 738 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 739 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 740 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 741 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 742 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 743 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 744 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 745 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 746 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 747 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 748 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 749 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 750 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 751 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 752 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 753 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 754 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 755 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 756 #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 757 #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 758 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 759 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 760 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 761 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 762 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 763 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 764 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 765 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 766 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 767 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 768 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 769 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 770 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 771 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 772 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 773 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 774 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 775 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 776 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 777 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 778 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 779 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 780 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 781 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 782 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 783 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 784 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 785 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 786 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 787 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 788 #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 789 #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */
<> 161:2cc1468da177 790
<> 161:2cc1468da177 791 /* Bit fields for CSEN DMBASELINE */
<> 161:2cc1468da177 792 #define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */
<> 161:2cc1468da177 793 #define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */
<> 161:2cc1468da177 794 #define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */
<> 161:2cc1468da177 795 #define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */
<> 161:2cc1468da177 796 #define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */
<> 161:2cc1468da177 797 #define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
<> 161:2cc1468da177 798 #define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */
<> 161:2cc1468da177 799 #define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */
<> 161:2cc1468da177 800 #define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */
<> 161:2cc1468da177 801 #define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
<> 161:2cc1468da177 802
<> 161:2cc1468da177 803 /* Bit fields for CSEN DMCFG */
<> 161:2cc1468da177 804 #define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */
<> 161:2cc1468da177 805 #define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */
<> 161:2cc1468da177 806 #define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */
<> 161:2cc1468da177 807 #define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */
<> 161:2cc1468da177 808 #define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 809 #define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 810 #define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */
<> 161:2cc1468da177 811 #define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */
<> 161:2cc1468da177 812 #define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 813 #define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 814 #define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */
<> 161:2cc1468da177 815 #define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */
<> 161:2cc1468da177 816 #define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 817 #define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 818 #define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */
<> 161:2cc1468da177 819 #define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */
<> 161:2cc1468da177 820 #define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 821 #define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */
<> 161:2cc1468da177 822 #define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */
<> 161:2cc1468da177 823 #define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */
<> 161:2cc1468da177 824 #define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */
<> 161:2cc1468da177 825 #define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 826 #define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */
<> 161:2cc1468da177 827 #define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */
<> 161:2cc1468da177 828 #define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */
<> 161:2cc1468da177 829 #define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */
<> 161:2cc1468da177 830 #define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Disable delta modulator gain reduction. */
<> 161:2cc1468da177 831 #define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */
<> 161:2cc1468da177 832 #define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */
<> 161:2cc1468da177 833 #define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 834 #define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */
<> 161:2cc1468da177 835
<> 161:2cc1468da177 836 /* Bit fields for CSEN ANACTRL */
<> 161:2cc1468da177 837 #define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */
<> 161:2cc1468da177 838 #define _CSEN_ANACTRL_MASK 0x03730771UL /**< Mask for CSEN_ANACTRL */
<> 161:2cc1468da177 839 #define CSEN_ANACTRL_CREFHALF (0x1UL << 0) /**< Reference capacitor divide by half. */
<> 161:2cc1468da177 840 #define _CSEN_ANACTRL_CREFHALF_SHIFT 0 /**< Shift value for CSEN_CREFHALF */
<> 161:2cc1468da177 841 #define _CSEN_ANACTRL_CREFHALF_MASK 0x1UL /**< Bit mask for CSEN_CREFHALF */
<> 161:2cc1468da177 842 #define _CSEN_ANACTRL_CREFHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 843 #define _CSEN_ANACTRL_CREFHALF_FULL 0x00000000UL /**< Mode FULL for CSEN_ANACTRL */
<> 161:2cc1468da177 844 #define _CSEN_ANACTRL_CREFHALF_HALF 0x00000001UL /**< Mode HALF for CSEN_ANACTRL */
<> 161:2cc1468da177 845 #define CSEN_ANACTRL_CREFHALF_DEFAULT (_CSEN_ANACTRL_CREFHALF_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 846 #define CSEN_ANACTRL_CREFHALF_FULL (_CSEN_ANACTRL_CREFHALF_FULL << 0) /**< Shifted mode FULL for CSEN_ANACTRL */
<> 161:2cc1468da177 847 #define CSEN_ANACTRL_CREFHALF_HALF (_CSEN_ANACTRL_CREFHALF_HALF << 0) /**< Shifted mode HALF for CSEN_ANACTRL */
<> 161:2cc1468da177 848 #define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */
<> 161:2cc1468da177 849 #define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */
<> 161:2cc1468da177 850 #define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 851 #define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 852 #define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */
<> 161:2cc1468da177 853 #define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */
<> 161:2cc1468da177 854 #define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 855 #define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 856 #define _CSEN_ANACTRL_DUTYSCALE_SHIFT 16 /**< Shift value for CSEN_DUTYSCALE */
<> 161:2cc1468da177 857 #define _CSEN_ANACTRL_DUTYSCALE_MASK 0x30000UL /**< Bit mask for CSEN_DUTYSCALE */
<> 161:2cc1468da177 858 #define _CSEN_ANACTRL_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 859 #define _CSEN_ANACTRL_DUTYSCALE_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_ANACTRL */
<> 161:2cc1468da177 860 #define _CSEN_ANACTRL_DUTYSCALE_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_ANACTRL */
<> 161:2cc1468da177 861 #define _CSEN_ANACTRL_DUTYSCALE_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_ANACTRL */
<> 161:2cc1468da177 862 #define _CSEN_ANACTRL_DUTYSCALE_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_ANACTRL */
<> 161:2cc1468da177 863 #define CSEN_ANACTRL_DUTYSCALE_DEFAULT (_CSEN_ANACTRL_DUTYSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 864 #define CSEN_ANACTRL_DUTYSCALE_DIV1 (_CSEN_ANACTRL_DUTYSCALE_DIV1 << 16) /**< Shifted mode DIV1 for CSEN_ANACTRL */
<> 161:2cc1468da177 865 #define CSEN_ANACTRL_DUTYSCALE_DIV2 (_CSEN_ANACTRL_DUTYSCALE_DIV2 << 16) /**< Shifted mode DIV2 for CSEN_ANACTRL */
<> 161:2cc1468da177 866 #define CSEN_ANACTRL_DUTYSCALE_DIV4 (_CSEN_ANACTRL_DUTYSCALE_DIV4 << 16) /**< Shifted mode DIV4 for CSEN_ANACTRL */
<> 161:2cc1468da177 867 #define CSEN_ANACTRL_DUTYSCALE_DIV8 (_CSEN_ANACTRL_DUTYSCALE_DIV8 << 16) /**< Shifted mode DIV8 for CSEN_ANACTRL */
<> 161:2cc1468da177 868 #define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */
<> 161:2cc1468da177 869 #define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */
<> 161:2cc1468da177 870 #define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 871 #define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 872 #define _CSEN_ANACTRL_BIASPROG_SHIFT 24 /**< Shift value for CSEN_BIASPROG */
<> 161:2cc1468da177 873 #define _CSEN_ANACTRL_BIASPROG_MASK 0x3000000UL /**< Bit mask for CSEN_BIASPROG */
<> 161:2cc1468da177 874 #define _CSEN_ANACTRL_BIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 875 #define _CSEN_ANACTRL_BIASPROG_ONEX 0x00000000UL /**< Mode ONEX for CSEN_ANACTRL */
<> 161:2cc1468da177 876 #define _CSEN_ANACTRL_BIASPROG_TWOX 0x00000001UL /**< Mode TWOX for CSEN_ANACTRL */
<> 161:2cc1468da177 877 #define _CSEN_ANACTRL_BIASPROG_ONETENTH 0x00000002UL /**< Mode ONETENTH for CSEN_ANACTRL */
<> 161:2cc1468da177 878 #define _CSEN_ANACTRL_BIASPROG_HALF 0x00000003UL /**< Mode HALF for CSEN_ANACTRL */
<> 161:2cc1468da177 879 #define CSEN_ANACTRL_BIASPROG_DEFAULT (_CSEN_ANACTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
<> 161:2cc1468da177 880 #define CSEN_ANACTRL_BIASPROG_ONEX (_CSEN_ANACTRL_BIASPROG_ONEX << 24) /**< Shifted mode ONEX for CSEN_ANACTRL */
<> 161:2cc1468da177 881 #define CSEN_ANACTRL_BIASPROG_TWOX (_CSEN_ANACTRL_BIASPROG_TWOX << 24) /**< Shifted mode TWOX for CSEN_ANACTRL */
<> 161:2cc1468da177 882 #define CSEN_ANACTRL_BIASPROG_ONETENTH (_CSEN_ANACTRL_BIASPROG_ONETENTH << 24) /**< Shifted mode ONETENTH for CSEN_ANACTRL */
<> 161:2cc1468da177 883 #define CSEN_ANACTRL_BIASPROG_HALF (_CSEN_ANACTRL_BIASPROG_HALF << 24) /**< Shifted mode HALF for CSEN_ANACTRL */
<> 161:2cc1468da177 884
<> 161:2cc1468da177 885 /* Bit fields for CSEN IF */
<> 161:2cc1468da177 886 #define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */
<> 161:2cc1468da177 887 #define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */
<> 161:2cc1468da177 888 #define CSEN_IF_CMP (0x1UL << 0) /**< CSEN Digital Comparator Interrupt Flag */
<> 161:2cc1468da177 889 #define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
<> 161:2cc1468da177 890 #define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
<> 161:2cc1468da177 891 #define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 892 #define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 893 #define CSEN_IF_CONV (0x1UL << 1) /**< CSEN Conversion Done Interrupt Flag */
<> 161:2cc1468da177 894 #define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
<> 161:2cc1468da177 895 #define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
<> 161:2cc1468da177 896 #define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 897 #define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 898 #define CSEN_IF_EOS (0x1UL << 2) /**< CSEN End of Scan Interrupt Flag. */
<> 161:2cc1468da177 899 #define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
<> 161:2cc1468da177 900 #define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
<> 161:2cc1468da177 901 #define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 902 #define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 903 #define CSEN_IF_DMAOF (0x1UL << 3) /**< CSEN DMA Overflow Interrupt Flag. */
<> 161:2cc1468da177 904 #define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
<> 161:2cc1468da177 905 #define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
<> 161:2cc1468da177 906 #define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 907 #define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 908 #define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */
<> 161:2cc1468da177 909 #define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 910 #define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 911 #define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 912 #define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */
<> 161:2cc1468da177 913
<> 161:2cc1468da177 914 /* Bit fields for CSEN IFS */
<> 161:2cc1468da177 915 #define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */
<> 161:2cc1468da177 916 #define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */
<> 161:2cc1468da177 917 #define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */
<> 161:2cc1468da177 918 #define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
<> 161:2cc1468da177 919 #define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
<> 161:2cc1468da177 920 #define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 921 #define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 922 #define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */
<> 161:2cc1468da177 923 #define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
<> 161:2cc1468da177 924 #define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
<> 161:2cc1468da177 925 #define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 926 #define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 927 #define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */
<> 161:2cc1468da177 928 #define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
<> 161:2cc1468da177 929 #define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
<> 161:2cc1468da177 930 #define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 931 #define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 932 #define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */
<> 161:2cc1468da177 933 #define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
<> 161:2cc1468da177 934 #define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
<> 161:2cc1468da177 935 #define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 936 #define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 937 #define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */
<> 161:2cc1468da177 938 #define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 939 #define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 940 #define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 941 #define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */
<> 161:2cc1468da177 942
<> 161:2cc1468da177 943 /* Bit fields for CSEN IFC */
<> 161:2cc1468da177 944 #define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */
<> 161:2cc1468da177 945 #define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */
<> 161:2cc1468da177 946 #define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */
<> 161:2cc1468da177 947 #define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
<> 161:2cc1468da177 948 #define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
<> 161:2cc1468da177 949 #define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 950 #define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 951 #define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */
<> 161:2cc1468da177 952 #define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
<> 161:2cc1468da177 953 #define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
<> 161:2cc1468da177 954 #define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 955 #define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 956 #define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */
<> 161:2cc1468da177 957 #define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
<> 161:2cc1468da177 958 #define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
<> 161:2cc1468da177 959 #define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 960 #define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 961 #define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */
<> 161:2cc1468da177 962 #define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
<> 161:2cc1468da177 963 #define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
<> 161:2cc1468da177 964 #define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 965 #define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 966 #define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */
<> 161:2cc1468da177 967 #define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 968 #define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 969 #define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 970 #define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */
<> 161:2cc1468da177 971
<> 161:2cc1468da177 972 /* Bit fields for CSEN IEN */
<> 161:2cc1468da177 973 #define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */
<> 161:2cc1468da177 974 #define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */
<> 161:2cc1468da177 975 #define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */
<> 161:2cc1468da177 976 #define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
<> 161:2cc1468da177 977 #define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
<> 161:2cc1468da177 978 #define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 979 #define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 980 #define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */
<> 161:2cc1468da177 981 #define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
<> 161:2cc1468da177 982 #define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
<> 161:2cc1468da177 983 #define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 984 #define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 985 #define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */
<> 161:2cc1468da177 986 #define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
<> 161:2cc1468da177 987 #define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
<> 161:2cc1468da177 988 #define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 989 #define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 990 #define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */
<> 161:2cc1468da177 991 #define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
<> 161:2cc1468da177 992 #define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
<> 161:2cc1468da177 993 #define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 994 #define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 995 #define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */
<> 161:2cc1468da177 996 #define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 997 #define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
<> 161:2cc1468da177 998 #define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 999 #define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */
<> 161:2cc1468da177 1000
<> 161:2cc1468da177 1001 /** @} End of group EFM32PG12B_CSEN */
<> 161:2cc1468da177 1002 /** @} End of group Parts */
<> 161:2cc1468da177 1003