Ben Katz / mbed-dev-f303

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targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_spi.c@181:36facd806e4a, 2018-07-30 (annotated)

Committer:
benkatz
Date:
Mon Jul 30 20:31:44 2018 +0000
Revision:
181:36facd806e4a
Parent:
174:b96e65c34a4d 
going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 174:b96e65c34a4d 1 /****************************************************************************//**
AnnaBridge 174:b96e65c34a4d 2 * @file spi.c
AnnaBridge 174:b96e65c34a4d 3 * @version V0.10
AnnaBridge 174:b96e65c34a4d 4 * $Revision: 7 $
AnnaBridge 174:b96e65c34a4d 5 * $Date: 15/05/28 1:33p $
AnnaBridge 174:b96e65c34a4d 6 * @brief NANO100 series SPI driver source file
AnnaBridge 174:b96e65c34a4d 7 *
AnnaBridge 174:b96e65c34a4d 8 * @note
AnnaBridge 174:b96e65c34a4d 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
AnnaBridge 174:b96e65c34a4d 10 *****************************************************************************/
AnnaBridge 174:b96e65c34a4d 11
AnnaBridge 174:b96e65c34a4d 12 #include "Nano100Series.h"
AnnaBridge 174:b96e65c34a4d 13
AnnaBridge 174:b96e65c34a4d 14 /** @addtogroup NANO100_Device_Driver NANO100 Device Driver
AnnaBridge 174:b96e65c34a4d 15 @{
AnnaBridge 174:b96e65c34a4d 16 */
AnnaBridge 174:b96e65c34a4d 17
AnnaBridge 174:b96e65c34a4d 18 /** @addtogroup NANO100_SPI_Driver SPI Driver
AnnaBridge 174:b96e65c34a4d 19 @{
AnnaBridge 174:b96e65c34a4d 20 */
AnnaBridge 174:b96e65c34a4d 21
AnnaBridge 174:b96e65c34a4d 22
AnnaBridge 174:b96e65c34a4d 23 /** @addtogroup NANO100_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
AnnaBridge 174:b96e65c34a4d 24 @{
AnnaBridge 174:b96e65c34a4d 25 */
AnnaBridge 174:b96e65c34a4d 26
AnnaBridge 174:b96e65c34a4d 27 /**
AnnaBridge 174:b96e65c34a4d 28 * @brief This function make SPI module be ready to transfer.
AnnaBridge 174:b96e65c34a4d 29 * By default, the SPI transfer sequence is MSB first and
AnnaBridge 174:b96e65c34a4d 30 * the automatic slave select function is disabled. In
AnnaBridge 174:b96e65c34a4d 31 * Slave mode, the u32BusClock must be NULL and the SPI clock
AnnaBridge 174:b96e65c34a4d 32 * divider setting will be 0.
AnnaBridge 174:b96e65c34a4d 33 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 34 * @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are:
AnnaBridge 174:b96e65c34a4d 35 * - \ref SPI_MASTER
AnnaBridge 174:b96e65c34a4d 36 * - \ref SPI_SLAVE
AnnaBridge 174:b96e65c34a4d 37 * @param[in] u32SPIMode decides the transfer timing. Valid values are:
AnnaBridge 174:b96e65c34a4d 38 * - \ref SPI_MODE_0
AnnaBridge 174:b96e65c34a4d 39 * - \ref SPI_MODE_1
AnnaBridge 174:b96e65c34a4d 40 * - \ref SPI_MODE_2
AnnaBridge 174:b96e65c34a4d 41 * - \ref SPI_MODE_3
AnnaBridge 174:b96e65c34a4d 42 * @param[in] u32DataWidth decides the data width of a SPI transaction.
AnnaBridge 174:b96e65c34a4d 43 * @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz.
AnnaBridge 174:b96e65c34a4d 44 * @return Actual frequency of SPI peripheral clock.
AnnaBridge 174:b96e65c34a4d 45 */
AnnaBridge 174:b96e65c34a4d 46 uint32_t SPI_Open(SPI_T *spi,
AnnaBridge 174:b96e65c34a4d 47 uint32_t u32MasterSlave,
AnnaBridge 174:b96e65c34a4d 48 uint32_t u32SPIMode,
AnnaBridge 174:b96e65c34a4d 49 uint32_t u32DataWidth,
AnnaBridge 174:b96e65c34a4d 50 uint32_t u32BusClock)
AnnaBridge 174:b96e65c34a4d 51 {
AnnaBridge 174:b96e65c34a4d 52 if(u32DataWidth == 32)
AnnaBridge 174:b96e65c34a4d 53 u32DataWidth = 0;
AnnaBridge 174:b96e65c34a4d 54
AnnaBridge 174:b96e65c34a4d 55 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode);
AnnaBridge 174:b96e65c34a4d 56
AnnaBridge 174:b96e65c34a4d 57 return ( SPI_SetBusClock(spi, u32BusClock) );
AnnaBridge 174:b96e65c34a4d 58 }
AnnaBridge 174:b96e65c34a4d 59
AnnaBridge 174:b96e65c34a4d 60 /**
AnnaBridge 174:b96e65c34a4d 61 * @brief Reset SPI module and disable SPI peripheral clock.
AnnaBridge 174:b96e65c34a4d 62 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 63 * @return none
AnnaBridge 174:b96e65c34a4d 64 */
AnnaBridge 174:b96e65c34a4d 65 void SPI_Close(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 66 {
AnnaBridge 174:b96e65c34a4d 67 /* Reset SPI */
AnnaBridge 174:b96e65c34a4d 68 if(spi == SPI0) {
AnnaBridge 174:b96e65c34a4d 69 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI0_RST_Msk;
AnnaBridge 174:b96e65c34a4d 70 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk;
AnnaBridge 174:b96e65c34a4d 71 } else if(spi == SPI1) {
AnnaBridge 174:b96e65c34a4d 72 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI1_RST_Msk;
AnnaBridge 174:b96e65c34a4d 73 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk;
AnnaBridge 174:b96e65c34a4d 74 } else {
AnnaBridge 174:b96e65c34a4d 75 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI2_RST_Msk;
AnnaBridge 174:b96e65c34a4d 76 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI2_RST_Msk;
AnnaBridge 174:b96e65c34a4d 77 }
AnnaBridge 174:b96e65c34a4d 78 }
AnnaBridge 174:b96e65c34a4d 79
AnnaBridge 174:b96e65c34a4d 80 /**
AnnaBridge 174:b96e65c34a4d 81 * @brief Clear Rx FIFO buffer.
AnnaBridge 174:b96e65c34a4d 82 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 83 * @return none
AnnaBridge 174:b96e65c34a4d 84 */
AnnaBridge 174:b96e65c34a4d 85 void SPI_ClearRxFIFO(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 86 {
AnnaBridge 174:b96e65c34a4d 87 spi->FFCTL |= SPI_FFCTL_RX_CLR_Msk;
AnnaBridge 174:b96e65c34a4d 88 }
AnnaBridge 174:b96e65c34a4d 89
AnnaBridge 174:b96e65c34a4d 90 /**
AnnaBridge 174:b96e65c34a4d 91 * @brief Clear Tx FIFO buffer.
AnnaBridge 174:b96e65c34a4d 92 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 93 * @return none
AnnaBridge 174:b96e65c34a4d 94 */
AnnaBridge 174:b96e65c34a4d 95 void SPI_ClearTxFIFO(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 96 {
AnnaBridge 174:b96e65c34a4d 97 spi->FFCTL |= SPI_FFCTL_TX_CLR_Msk;
AnnaBridge 174:b96e65c34a4d 98 }
AnnaBridge 174:b96e65c34a4d 99
AnnaBridge 174:b96e65c34a4d 100 /**
AnnaBridge 174:b96e65c34a4d 101 * @brief Disable the automatic slave select function.
AnnaBridge 174:b96e65c34a4d 102 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 103 * @return none
AnnaBridge 174:b96e65c34a4d 104 */
AnnaBridge 174:b96e65c34a4d 105 void SPI_DisableAutoSS(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 106 {
AnnaBridge 174:b96e65c34a4d 107 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
AnnaBridge 174:b96e65c34a4d 108 }
AnnaBridge 174:b96e65c34a4d 109
AnnaBridge 174:b96e65c34a4d 110 /**
AnnaBridge 174:b96e65c34a4d 111 * @brief Enable the automatic slave select function. Only available in Master mode.
AnnaBridge 174:b96e65c34a4d 112 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 113 * @param[in] u32SSPinMask specifies slave select pins. (SPI_SS)
AnnaBridge 174:b96e65c34a4d 114 * @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are:
AnnaBridge 174:b96e65c34a4d 115 * - \ref SPI_SS0_ACTIVE_HIGH
AnnaBridge 174:b96e65c34a4d 116 * - \ref SPI_SS0_ACTIVE_LOW
AnnaBridge 174:b96e65c34a4d 117 * - \ref SPI_SS1_ACTIVE_HIGH
AnnaBridge 174:b96e65c34a4d 118 * - \ref SPI_SS1_ACTIVE_LOW
AnnaBridge 174:b96e65c34a4d 119 * @return none
AnnaBridge 174:b96e65c34a4d 120 */
AnnaBridge 174:b96e65c34a4d 121 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
AnnaBridge 174:b96e65c34a4d 122 {
AnnaBridge 174:b96e65c34a4d 123 spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
AnnaBridge 174:b96e65c34a4d 124 }
AnnaBridge 174:b96e65c34a4d 125
AnnaBridge 174:b96e65c34a4d 126 /**
AnnaBridge 174:b96e65c34a4d 127 * @brief Set the SPI bus clock. Only available in Master mode.
AnnaBridge 174:b96e65c34a4d 128 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 129 * @param[in] u32BusClock is the expected frequency of SPI bus clock.
AnnaBridge 174:b96e65c34a4d 130 * @return Actual frequency of SPI peripheral clock.
AnnaBridge 174:b96e65c34a4d 131 */
AnnaBridge 174:b96e65c34a4d 132 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
AnnaBridge 174:b96e65c34a4d 133 {
AnnaBridge 174:b96e65c34a4d 134 uint32_t u32ClkSrc, u32Div = 0;
AnnaBridge 174:b96e65c34a4d 135
AnnaBridge 174:b96e65c34a4d 136 if(spi == SPI0) {
AnnaBridge 174:b96e65c34a4d 137 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
AnnaBridge 174:b96e65c34a4d 138 u32ClkSrc = CLK_GetHCLKFreq();
AnnaBridge 174:b96e65c34a4d 139 else
AnnaBridge 174:b96e65c34a4d 140 u32ClkSrc = CLK_GetPLLClockFreq();
AnnaBridge 174:b96e65c34a4d 141 } else if(spi == SPI1) {
AnnaBridge 174:b96e65c34a4d 142 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
AnnaBridge 174:b96e65c34a4d 143 u32ClkSrc = CLK_GetHCLKFreq();
AnnaBridge 174:b96e65c34a4d 144 else
AnnaBridge 174:b96e65c34a4d 145 u32ClkSrc = CLK_GetPLLClockFreq();
AnnaBridge 174:b96e65c34a4d 146 } else {
AnnaBridge 174:b96e65c34a4d 147 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
AnnaBridge 174:b96e65c34a4d 148 u32ClkSrc = CLK_GetHCLKFreq();
AnnaBridge 174:b96e65c34a4d 149 else
AnnaBridge 174:b96e65c34a4d 150 u32ClkSrc = CLK_GetPLLClockFreq();
AnnaBridge 174:b96e65c34a4d 151 }
AnnaBridge 174:b96e65c34a4d 152
AnnaBridge 174:b96e65c34a4d 153 if(u32BusClock > u32ClkSrc)
AnnaBridge 174:b96e65c34a4d 154 u32BusClock = u32ClkSrc;
AnnaBridge 174:b96e65c34a4d 155
AnnaBridge 174:b96e65c34a4d 156 if(u32BusClock != 0 ) {
AnnaBridge 174:b96e65c34a4d 157 u32Div = (u32ClkSrc / u32BusClock) - 1;
AnnaBridge 174:b96e65c34a4d 158 if(u32Div > SPI_CLKDIV_DIVIDER1_Msk)
AnnaBridge 174:b96e65c34a4d 159 u32Div = SPI_CLKDIV_DIVIDER1_Msk;
AnnaBridge 174:b96e65c34a4d 160 } else
AnnaBridge 174:b96e65c34a4d 161 u32Div = 0;
AnnaBridge 174:b96e65c34a4d 162
AnnaBridge 174:b96e65c34a4d 163 spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div;
AnnaBridge 174:b96e65c34a4d 164
AnnaBridge 174:b96e65c34a4d 165 return ( u32ClkSrc / (u32Div+1) );
AnnaBridge 174:b96e65c34a4d 166 }
AnnaBridge 174:b96e65c34a4d 167
AnnaBridge 174:b96e65c34a4d 168 /**
AnnaBridge 174:b96e65c34a4d 169 * @brief Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
AnnaBridge 174:b96e65c34a4d 170 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 171 * @param[in] u32TxThreshold decides the Tx FIFO threshold.
AnnaBridge 174:b96e65c34a4d 172 * @param[in] u32RxThreshold decides the Rx FIFO threshold.
AnnaBridge 174:b96e65c34a4d 173 * @return none
AnnaBridge 174:b96e65c34a4d 174 */
AnnaBridge 174:b96e65c34a4d 175 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
AnnaBridge 174:b96e65c34a4d 176 {
AnnaBridge 174:b96e65c34a4d 177 spi->FFCTL = (spi->FFCTL & ~(SPI_FFCTL_TX_THRESHOLD_Msk | SPI_FFCTL_RX_THRESHOLD_Msk) |
AnnaBridge 174:b96e65c34a4d 178 (u32TxThreshold << SPI_FFCTL_TX_THRESHOLD_Pos) |
AnnaBridge 174:b96e65c34a4d 179 (u32RxThreshold << SPI_FFCTL_RX_THRESHOLD_Pos));
AnnaBridge 174:b96e65c34a4d 180
AnnaBridge 174:b96e65c34a4d 181 spi->CTL |= SPI_CTL_FIFOM_Msk;
AnnaBridge 174:b96e65c34a4d 182 }
AnnaBridge 174:b96e65c34a4d 183
AnnaBridge 174:b96e65c34a4d 184 /**
AnnaBridge 174:b96e65c34a4d 185 * @brief Disable FIFO mode.
AnnaBridge 174:b96e65c34a4d 186 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 187 * @return none
AnnaBridge 174:b96e65c34a4d 188 */
AnnaBridge 174:b96e65c34a4d 189 void SPI_DisableFIFO(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 190 {
AnnaBridge 174:b96e65c34a4d 191 spi->CTL &= ~SPI_CTL_FIFOM_Msk;
AnnaBridge 174:b96e65c34a4d 192 }
AnnaBridge 174:b96e65c34a4d 193
AnnaBridge 174:b96e65c34a4d 194 /**
AnnaBridge 174:b96e65c34a4d 195 * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
AnnaBridge 174:b96e65c34a4d 196 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 197 * @return Actual SPI bus clock frequency.
AnnaBridge 174:b96e65c34a4d 198 */
AnnaBridge 174:b96e65c34a4d 199 uint32_t SPI_GetBusClock(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 200 {
AnnaBridge 174:b96e65c34a4d 201 uint32_t u32Div;
AnnaBridge 174:b96e65c34a4d 202 uint32_t u32ClkSrc;
AnnaBridge 174:b96e65c34a4d 203
AnnaBridge 174:b96e65c34a4d 204 if(spi == SPI0) {
AnnaBridge 174:b96e65c34a4d 205 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
AnnaBridge 174:b96e65c34a4d 206 u32ClkSrc = CLK_GetHCLKFreq();
AnnaBridge 174:b96e65c34a4d 207 else
AnnaBridge 174:b96e65c34a4d 208 u32ClkSrc = CLK_GetPLLClockFreq();
AnnaBridge 174:b96e65c34a4d 209 } else if(spi == SPI1) {
AnnaBridge 174:b96e65c34a4d 210 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
AnnaBridge 174:b96e65c34a4d 211 u32ClkSrc = CLK_GetHCLKFreq();
AnnaBridge 174:b96e65c34a4d 212 else
AnnaBridge 174:b96e65c34a4d 213 u32ClkSrc = CLK_GetPLLClockFreq();
AnnaBridge 174:b96e65c34a4d 214 } else {
AnnaBridge 174:b96e65c34a4d 215 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
AnnaBridge 174:b96e65c34a4d 216 u32ClkSrc = CLK_GetHCLKFreq();
AnnaBridge 174:b96e65c34a4d 217 else
AnnaBridge 174:b96e65c34a4d 218 u32ClkSrc = CLK_GetPLLClockFreq();
AnnaBridge 174:b96e65c34a4d 219 }
AnnaBridge 174:b96e65c34a4d 220
AnnaBridge 174:b96e65c34a4d 221 u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER1_Msk;
AnnaBridge 174:b96e65c34a4d 222 return (u32ClkSrc / (u32Div + 1));
AnnaBridge 174:b96e65c34a4d 223 }
AnnaBridge 174:b96e65c34a4d 224
AnnaBridge 174:b96e65c34a4d 225 /**
AnnaBridge 174:b96e65c34a4d 226 * @brief Enable FIFO related interrupts specified by u32Mask parameter.
AnnaBridge 174:b96e65c34a4d 227 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 228 * @param[in] u32Mask is the combination of all related interrupt enable bits.
AnnaBridge 174:b96e65c34a4d 229 * Each bit corresponds to a interrupt bit.
AnnaBridge 174:b96e65c34a4d 230 * This parameter decides which interrupts will be enabled. Valid values are:
AnnaBridge 174:b96e65c34a4d 231 * - \ref SPI_IE_MASK
AnnaBridge 174:b96e65c34a4d 232 * - \ref SPI_SSTA_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 233 * - \ref SPI_FIFO_TX_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 234 * - \ref SPI_FIFO_RX_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 235 * - \ref SPI_FIFO_RXOVR_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 236 * - \ref SPI_FIFO_TIMEOUT_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 237 * @return none
AnnaBridge 174:b96e65c34a4d 238 */
AnnaBridge 174:b96e65c34a4d 239 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
AnnaBridge 174:b96e65c34a4d 240 {
AnnaBridge 174:b96e65c34a4d 241 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
AnnaBridge 174:b96e65c34a4d 242 spi->CTL |= SPI_CTL_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 243
AnnaBridge 174:b96e65c34a4d 244 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 245 spi->SSR |= SPI_SSR_SSTA_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 246
AnnaBridge 174:b96e65c34a4d 247 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 248 spi->FFCTL |= SPI_FFCTL_TX_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 249
AnnaBridge 174:b96e65c34a4d 250 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 251 spi->FFCTL |= SPI_FFCTL_RX_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 252
AnnaBridge 174:b96e65c34a4d 253 if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 254 spi->FFCTL |= SPI_FFCTL_RXOVR_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 255
AnnaBridge 174:b96e65c34a4d 256 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 257 spi->FFCTL |= SPI_FFCTL_TIMEOUT_EN_Msk;
AnnaBridge 174:b96e65c34a4d 258 }
AnnaBridge 174:b96e65c34a4d 259
AnnaBridge 174:b96e65c34a4d 260 /**
AnnaBridge 174:b96e65c34a4d 261 * @brief Disable FIFO related interrupts specified by u32Mask parameter.
AnnaBridge 174:b96e65c34a4d 262 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 263 * @param[in] u32Mask is the combination of all related interrupt enable bits.
AnnaBridge 174:b96e65c34a4d 264 * Each bit corresponds to a interrupt bit.
AnnaBridge 174:b96e65c34a4d 265 * This parameter decides which interrupts will be enabled. Valid values are:
AnnaBridge 174:b96e65c34a4d 266 * - \ref SPI_IE_MASK
AnnaBridge 174:b96e65c34a4d 267 * - \ref SPI_SSTA_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 268 * - \ref SPI_FIFO_TX_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 269 * - \ref SPI_FIFO_RX_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 270 * - \ref SPI_FIFO_RXOVR_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 271 * - \ref SPI_FIFO_TIMEOUT_INTEN_MASK
AnnaBridge 174:b96e65c34a4d 272 * @return none
AnnaBridge 174:b96e65c34a4d 273 */
AnnaBridge 174:b96e65c34a4d 274 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
AnnaBridge 174:b96e65c34a4d 275 {
AnnaBridge 174:b96e65c34a4d 276 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
AnnaBridge 174:b96e65c34a4d 277 spi->CTL &= ~SPI_CTL_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 278
AnnaBridge 174:b96e65c34a4d 279 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 280 spi->SSR &= ~SPI_SSR_SSTA_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 281
AnnaBridge 174:b96e65c34a4d 282 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 283 spi->FFCTL &= ~SPI_FFCTL_TX_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 284
AnnaBridge 174:b96e65c34a4d 285 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 286 spi->FFCTL &= ~SPI_FFCTL_RX_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 287
AnnaBridge 174:b96e65c34a4d 288 if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 289 spi->FFCTL &= ~SPI_FFCTL_RXOVR_INTEN_Msk;
AnnaBridge 174:b96e65c34a4d 290
AnnaBridge 174:b96e65c34a4d 291 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
AnnaBridge 174:b96e65c34a4d 292 spi->FFCTL &= ~SPI_FFCTL_TIMEOUT_EN_Msk;
AnnaBridge 174:b96e65c34a4d 293 }
AnnaBridge 174:b96e65c34a4d 294
AnnaBridge 174:b96e65c34a4d 295 /**
AnnaBridge 174:b96e65c34a4d 296 * @brief Enable wake-up function.
AnnaBridge 174:b96e65c34a4d 297 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 298 * @return none
AnnaBridge 174:b96e65c34a4d 299 */
AnnaBridge 174:b96e65c34a4d 300 void SPI_EnableWakeup(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 301 {
AnnaBridge 174:b96e65c34a4d 302 spi->CTL |= SPI_CTL_WKEUP_EN_Msk;
AnnaBridge 174:b96e65c34a4d 303 }
AnnaBridge 174:b96e65c34a4d 304
AnnaBridge 174:b96e65c34a4d 305 /**
AnnaBridge 174:b96e65c34a4d 306 * @brief Disable wake-up function.
AnnaBridge 174:b96e65c34a4d 307 * @param[in] spi is the base address of SPI module.
AnnaBridge 174:b96e65c34a4d 308 * @return none
AnnaBridge 174:b96e65c34a4d 309 */
AnnaBridge 174:b96e65c34a4d 310 void SPI_DisableWakeup(SPI_T *spi)
AnnaBridge 174:b96e65c34a4d 311 {
AnnaBridge 174:b96e65c34a4d 312 spi->CTL &= ~SPI_CTL_WKEUP_EN_Msk;
AnnaBridge 174:b96e65c34a4d 313 }
AnnaBridge 174:b96e65c34a4d 314
AnnaBridge 174:b96e65c34a4d 315 /*@}*/ /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
AnnaBridge 174:b96e65c34a4d 316
AnnaBridge 174:b96e65c34a4d 317 /*@}*/ /* end of group NANO100_SPI_Driver */
AnnaBridge 174:b96e65c34a4d 318
AnnaBridge 174:b96e65c34a4d 319 /*@}*/ /* end of group NANO100_Device_Driver */
AnnaBridge 174:b96e65c34a4d 320
AnnaBridge 174:b96e65c34a4d 321 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/