mbed-dev-f303

Users » benkatz » Code » mbed-dev-f303

Dependents: Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more

Fork of mbed-dev by mbed official

targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c@175:af195413fb11, 2017-10-11 (annotated)

Committer:: AnnaBridge
Date:: Wed Oct 11 12:45:49 2017 +0100
Revision:: 175:af195413fb11
Parent:: 154:37f96f9d4de2

This updates the lib to the mbed lib v 153

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	154:37f96f9d4de2	1	/*
<>	154:37f96f9d4de2	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge	175:af195413fb11	3	* Copyright (c) 2016 - 2017 , NXP
<>	154:37f96f9d4de2	4	* All rights reserved.
<>	154:37f96f9d4de2	5	*
<>	154:37f96f9d4de2	6	* Redistribution and use in source and binary forms, with or without modification,
<>	154:37f96f9d4de2	7	* are permitted provided that the following conditions are met:
<>	154:37f96f9d4de2	8	*
<>	154:37f96f9d4de2	9	* o Redistributions of source code must retain the above copyright notice, this list
<>	154:37f96f9d4de2	10	* of conditions and the following disclaimer.
<>	154:37f96f9d4de2	11	*
<>	154:37f96f9d4de2	12	* o Redistributions in binary form must reproduce the above copyright notice, this
<>	154:37f96f9d4de2	13	* list of conditions and the following disclaimer in the documentation and/or
<>	154:37f96f9d4de2	14	* other materials provided with the distribution.
<>	154:37f96f9d4de2	15	*
AnnaBridge	175:af195413fb11	16	* o Neither the name of copyright holder nor the names of its
<>	154:37f96f9d4de2	17	* contributors may be used to endorse or promote products derived from this
<>	154:37f96f9d4de2	18	* software without specific prior written permission.
<>	154:37f96f9d4de2	19	*
<>	154:37f96f9d4de2	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<>	154:37f96f9d4de2	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<>	154:37f96f9d4de2	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	154:37f96f9d4de2	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<>	154:37f96f9d4de2	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<>	154:37f96f9d4de2	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<>	154:37f96f9d4de2	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<>	154:37f96f9d4de2	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<>	154:37f96f9d4de2	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<>	154:37f96f9d4de2	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	154:37f96f9d4de2	30	*/
<>	154:37f96f9d4de2	31
<>	154:37f96f9d4de2	32	#include "fsl_clock.h"
<>	154:37f96f9d4de2	33
<>	154:37f96f9d4de2	34	/*******************************************************************************
<>	154:37f96f9d4de2	35	* Definitions
<>	154:37f96f9d4de2	36	******************************************************************************/
<>	154:37f96f9d4de2	37
<>	154:37f96f9d4de2	38	/* Macro definition remap workaround. */
<>	154:37f96f9d4de2	39	#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
<>	154:37f96f9d4de2	40	#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
<>	154:37f96f9d4de2	41	#endif
<>	154:37f96f9d4de2	42	#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
<>	154:37f96f9d4de2	43	#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
<>	154:37f96f9d4de2	44	#endif
<>	154:37f96f9d4de2	45	#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
<>	154:37f96f9d4de2	46	#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
<>	154:37f96f9d4de2	47	#endif
<>	154:37f96f9d4de2	48	#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK)))
<>	154:37f96f9d4de2	49	#define MCG_C6_CME0_MASK MCG_C6_CME_MASK
<>	154:37f96f9d4de2	50	#endif
<>	154:37f96f9d4de2	51
<>	154:37f96f9d4de2	52	/* PLL fixed multiplier when there is not PRDIV and VDIV. */
<>	154:37f96f9d4de2	53	#define PLL_FIXED_MULT (375U)
<>	154:37f96f9d4de2	54	/* Max frequency of the reference clock used for internal clock trim. */
<>	154:37f96f9d4de2	55	#define TRIM_REF_CLK_MIN (8000000U)
<>	154:37f96f9d4de2	56	/* Min frequency of the reference clock used for internal clock trim. */
<>	154:37f96f9d4de2	57	#define TRIM_REF_CLK_MAX (16000000U)
<>	154:37f96f9d4de2	58	/* Max trim value of fast internal reference clock. */
<>	154:37f96f9d4de2	59	#define TRIM_FIRC_MAX (5000000U)
<>	154:37f96f9d4de2	60	/* Min trim value of fast internal reference clock. */
<>	154:37f96f9d4de2	61	#define TRIM_FIRC_MIN (3000000U)
<>	154:37f96f9d4de2	62	/* Max trim value of fast internal reference clock. */
<>	154:37f96f9d4de2	63	#define TRIM_SIRC_MAX (39063U)
<>	154:37f96f9d4de2	64	/* Min trim value of fast internal reference clock. */
<>	154:37f96f9d4de2	65	#define TRIM_SIRC_MIN (31250U)
<>	154:37f96f9d4de2	66
<>	154:37f96f9d4de2	67	#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
<>	154:37f96f9d4de2	68	#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
<>	154:37f96f9d4de2	69	#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
<>	154:37f96f9d4de2	70	#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
<>	154:37f96f9d4de2	71	#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
<>	154:37f96f9d4de2	72	#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
<>	154:37f96f9d4de2	73	#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
<>	154:37f96f9d4de2	74	#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
<>	154:37f96f9d4de2	75	#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT)
<>	154:37f96f9d4de2	76	#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
<>	154:37f96f9d4de2	77	#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
<>	154:37f96f9d4de2	78	#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
<>	154:37f96f9d4de2	79	#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
<>	154:37f96f9d4de2	80	#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
<>	154:37f96f9d4de2	81	#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT)
<>	154:37f96f9d4de2	82	#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT)
<>	154:37f96f9d4de2	83	#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT)
<>	154:37f96f9d4de2	84	#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
<>	154:37f96f9d4de2	85	#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
<>	154:37f96f9d4de2	86
<>	154:37f96f9d4de2	87	#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK \| MCG_C2_HGO0_MASK \| MCG_C2_RANGE0_MASK)
<>	154:37f96f9d4de2	88
<>	154:37f96f9d4de2	89	#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
<>	154:37f96f9d4de2	90	#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
<>	154:37f96f9d4de2	91	#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
<>	154:37f96f9d4de2	92	#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
<>	154:37f96f9d4de2	93	#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
<>	154:37f96f9d4de2	94	#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
<>	154:37f96f9d4de2	95	#define SIM_CLKDIV3_PLLFLLDIV_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLDIV_MASK) >> SIM_CLKDIV3_PLLFLLDIV_SHIFT)
<>	154:37f96f9d4de2	96	#define SIM_CLKDIV3_PLLFLLFRAC_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLFRAC_MASK) >> SIM_CLKDIV3_PLLFLLFRAC_SHIFT)
<>	154:37f96f9d4de2	97
<>	154:37f96f9d4de2	98	/* MCG_S_CLKST definition. */
<>	154:37f96f9d4de2	99	enum _mcg_clkout_stat
<>	154:37f96f9d4de2	100	{
<>	154:37f96f9d4de2	101	kMCG_ClkOutStatFll, /* FLL. */
<>	154:37f96f9d4de2	102	kMCG_ClkOutStatInt, /* Internal clock. */
<>	154:37f96f9d4de2	103	kMCG_ClkOutStatExt, /* External clock. */
<>	154:37f96f9d4de2	104	kMCG_ClkOutStatPll /* PLL. */
<>	154:37f96f9d4de2	105	};
<>	154:37f96f9d4de2	106
<>	154:37f96f9d4de2	107	/* MCG_S_PLLST definition. */
<>	154:37f96f9d4de2	108	enum _mcg_pllst
<>	154:37f96f9d4de2	109	{
<>	154:37f96f9d4de2	110	kMCG_PllstFll, /* FLL is used. */
<>	154:37f96f9d4de2	111	kMCG_PllstPll /* PLL is used. */
<>	154:37f96f9d4de2	112	};
<>	154:37f96f9d4de2	113
<>	154:37f96f9d4de2	114	/*******************************************************************************
<>	154:37f96f9d4de2	115	* Variables
<>	154:37f96f9d4de2	116	******************************************************************************/
<>	154:37f96f9d4de2	117
<>	154:37f96f9d4de2	118	/* Slow internal reference clock frequency. */
<>	154:37f96f9d4de2	119	static uint32_t s_slowIrcFreq = 32768U;
<>	154:37f96f9d4de2	120	/* Fast internal reference clock frequency. */
<>	154:37f96f9d4de2	121	static uint32_t s_fastIrcFreq = 4000000U;
<>	154:37f96f9d4de2	122	/* The MCG external PLL clock frequency. */
<>	154:37f96f9d4de2	123	static uint32_t s_extPllFreq = 0U;
<>	154:37f96f9d4de2	124
<>	154:37f96f9d4de2	125	/* External XTAL0 (OSC0) clock frequency. */
<>	154:37f96f9d4de2	126	uint32_t g_xtal0Freq;
<>	154:37f96f9d4de2	127	/* External XTAL32K clock frequency. */
<>	154:37f96f9d4de2	128	uint32_t g_xtal32Freq;
<>	154:37f96f9d4de2	129
<>	154:37f96f9d4de2	130	/*******************************************************************************
<>	154:37f96f9d4de2	131	* Prototypes
<>	154:37f96f9d4de2	132	******************************************************************************/
<>	154:37f96f9d4de2	133
<>	154:37f96f9d4de2	134	/*!
<>	154:37f96f9d4de2	135	* @brief Get the MCG external reference clock frequency.
<>	154:37f96f9d4de2	136	*
<>	154:37f96f9d4de2	137	* Get the current MCG external reference clock frequency in Hz. It is
<>	154:37f96f9d4de2	138	* the frequency select by MCG_C7[OSCSEL]. This is an internal function.
<>	154:37f96f9d4de2	139	*
<>	154:37f96f9d4de2	140	* @return MCG external reference clock frequency in Hz.
<>	154:37f96f9d4de2	141	*/
<>	154:37f96f9d4de2	142	static uint32_t CLOCK_GetMcgExtClkFreq(void);
<>	154:37f96f9d4de2	143
<>	154:37f96f9d4de2	144	/*!
<>	154:37f96f9d4de2	145	* @brief Get the MCG FLL external reference clock frequency.
<>	154:37f96f9d4de2	146	*
<>	154:37f96f9d4de2	147	* Get the current MCG FLL external reference clock frequency in Hz. It is
<>	154:37f96f9d4de2	148	* the frequency after by MCG_C1[FRDIV]. This is an internal function.
<>	154:37f96f9d4de2	149	*
<>	154:37f96f9d4de2	150	* @return MCG FLL external reference clock frequency in Hz.
<>	154:37f96f9d4de2	151	*/
<>	154:37f96f9d4de2	152	static uint32_t CLOCK_GetFllExtRefClkFreq(void);
<>	154:37f96f9d4de2	153
<>	154:37f96f9d4de2	154	/*!
<>	154:37f96f9d4de2	155	* @brief Get the MCG FLL reference clock frequency.
<>	154:37f96f9d4de2	156	*
<>	154:37f96f9d4de2	157	* Get the current MCG FLL reference clock frequency in Hz. It is
<>	154:37f96f9d4de2	158	* the frequency select by MCG_C1[IREFS]. This is an internal function.
<>	154:37f96f9d4de2	159	*
<>	154:37f96f9d4de2	160	* @return MCG FLL reference clock frequency in Hz.
<>	154:37f96f9d4de2	161	*/
<>	154:37f96f9d4de2	162	static uint32_t CLOCK_GetFllRefClkFreq(void);
<>	154:37f96f9d4de2	163
<>	154:37f96f9d4de2	164	/*!
<>	154:37f96f9d4de2	165	* @brief Get the frequency of clock selected by MCG_C2[IRCS].
<>	154:37f96f9d4de2	166	*
<>	154:37f96f9d4de2	167	* This clock's two output:
<>	154:37f96f9d4de2	168	* 1. MCGOUTCLK when MCG_S[CLKST]=0.
<>	154:37f96f9d4de2	169	* 2. MCGIRCLK when MCG_C1[IRCLKEN]=1.
<>	154:37f96f9d4de2	170	*
<>	154:37f96f9d4de2	171	* @return The frequency in Hz.
<>	154:37f96f9d4de2	172	*/
<>	154:37f96f9d4de2	173	static uint32_t CLOCK_GetInternalRefClkSelectFreq(void);
<>	154:37f96f9d4de2	174
<>	154:37f96f9d4de2	175	/*!
<>	154:37f96f9d4de2	176	* @brief Get the MCG PLL/PLL0 reference clock frequency.
<>	154:37f96f9d4de2	177	*
<>	154:37f96f9d4de2	178	* Get the current MCG PLL/PLL0 reference clock frequency in Hz.
<>	154:37f96f9d4de2	179	* This is an internal function.
<>	154:37f96f9d4de2	180	*
<>	154:37f96f9d4de2	181	* @return MCG PLL/PLL0 reference clock frequency in Hz.
<>	154:37f96f9d4de2	182	*/
<>	154:37f96f9d4de2	183	static uint32_t CLOCK_GetPll0RefFreq(void);
<>	154:37f96f9d4de2	184
<>	154:37f96f9d4de2	185	/*!
<>	154:37f96f9d4de2	186	* @brief Calculate the RANGE value base on crystal frequency.
<>	154:37f96f9d4de2	187	*
<>	154:37f96f9d4de2	188	* To setup external crystal oscillator, must set the register bits RANGE
<>	154:37f96f9d4de2	189	* base on the crystal frequency. This function returns the RANGE base on the
<>	154:37f96f9d4de2	190	* input frequency. This is an internal function.
<>	154:37f96f9d4de2	191	*
<>	154:37f96f9d4de2	192	* @param freq Crystal frequency in Hz.
<>	154:37f96f9d4de2	193	* @return The RANGE value.
<>	154:37f96f9d4de2	194	*/
<>	154:37f96f9d4de2	195	static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
<>	154:37f96f9d4de2	196
AnnaBridge	175:af195413fb11	197	/*******************************************************************************
AnnaBridge	175:af195413fb11	198	* Code
AnnaBridge	175:af195413fb11	199	******************************************************************************/
AnnaBridge	175:af195413fb11	200
AnnaBridge	175:af195413fb11	201	#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
<>	154:37f96f9d4de2	202	/*!
<>	154:37f96f9d4de2	203	* @brief Delay function to wait FLL stable.
<>	154:37f96f9d4de2	204	*
<>	154:37f96f9d4de2	205	* Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least
<>	154:37f96f9d4de2	206	* 1ms. Every time changes FLL setting, should wait this time for FLL stable.
<>	154:37f96f9d4de2	207	*/
AnnaBridge	175:af195413fb11	208	void CLOCK_FllStableDelay(void)
AnnaBridge	175:af195413fb11	209	{
AnnaBridge	175:af195413fb11	210	/*
AnnaBridge	175:af195413fb11	211	Should wait at least 1ms. Because in these modes, the core clock is 100MHz
AnnaBridge	175:af195413fb11	212	at most, so this function could obtain the 1ms delay.
AnnaBridge	175:af195413fb11	213	*/
AnnaBridge	175:af195413fb11	214	volatile uint32_t i = 30000U;
AnnaBridge	175:af195413fb11	215	while (i--)
AnnaBridge	175:af195413fb11	216	{
AnnaBridge	175:af195413fb11	217	__NOP();
AnnaBridge	175:af195413fb11	218	}
AnnaBridge	175:af195413fb11	219	}
AnnaBridge	175:af195413fb11	220	#else /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */
AnnaBridge	175:af195413fb11	221	/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to
AnnaBridge	175:af195413fb11	222	* create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this
AnnaBridge	175:af195413fb11	223	* file would call the CLOCK_FllStableDelay() regardness how it is defined.
AnnaBridge	175:af195413fb11	224	*/
AnnaBridge	175:af195413fb11	225	extern void CLOCK_FllStableDelay(void);
AnnaBridge	175:af195413fb11	226	#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
<>	154:37f96f9d4de2	227
<>	154:37f96f9d4de2	228	static uint32_t CLOCK_GetMcgExtClkFreq(void)
<>	154:37f96f9d4de2	229	{
<>	154:37f96f9d4de2	230	uint32_t freq;
<>	154:37f96f9d4de2	231
<>	154:37f96f9d4de2	232	switch (MCG_C7_OSCSEL_VAL)
<>	154:37f96f9d4de2	233	{
<>	154:37f96f9d4de2	234	case 0U:
<>	154:37f96f9d4de2	235	/* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
<>	154:37f96f9d4de2	236	assert(g_xtal0Freq);
<>	154:37f96f9d4de2	237	freq = g_xtal0Freq;
<>	154:37f96f9d4de2	238	break;
<>	154:37f96f9d4de2	239	case 1U:
<>	154:37f96f9d4de2	240	/* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
<>	154:37f96f9d4de2	241	assert(g_xtal32Freq);
<>	154:37f96f9d4de2	242	freq = g_xtal32Freq;
<>	154:37f96f9d4de2	243	break;
<>	154:37f96f9d4de2	244	case 2U:
<>	154:37f96f9d4de2	245	freq = MCG_INTERNAL_IRC_48M;
<>	154:37f96f9d4de2	246	break;
<>	154:37f96f9d4de2	247	default:
<>	154:37f96f9d4de2	248	freq = 0U;
<>	154:37f96f9d4de2	249	break;
<>	154:37f96f9d4de2	250	}
<>	154:37f96f9d4de2	251
<>	154:37f96f9d4de2	252	return freq;
<>	154:37f96f9d4de2	253	}
<>	154:37f96f9d4de2	254
<>	154:37f96f9d4de2	255	static uint32_t CLOCK_GetFllExtRefClkFreq(void)
<>	154:37f96f9d4de2	256	{
<>	154:37f96f9d4de2	257	/* FllExtRef = McgExtRef / FllExtRefDiv */
<>	154:37f96f9d4de2	258	uint8_t frdiv;
<>	154:37f96f9d4de2	259	uint8_t range;
<>	154:37f96f9d4de2	260	uint8_t oscsel;
<>	154:37f96f9d4de2	261
<>	154:37f96f9d4de2	262	uint32_t freq = CLOCK_GetMcgExtClkFreq();
<>	154:37f96f9d4de2	263
<>	154:37f96f9d4de2	264	if (!freq)
<>	154:37f96f9d4de2	265	{
<>	154:37f96f9d4de2	266	return freq;
<>	154:37f96f9d4de2	267	}
<>	154:37f96f9d4de2	268
<>	154:37f96f9d4de2	269	frdiv = MCG_C1_FRDIV_VAL;
<>	154:37f96f9d4de2	270	freq >>= frdiv;
<>	154:37f96f9d4de2	271
<>	154:37f96f9d4de2	272	range = MCG_C2_RANGE_VAL;
<>	154:37f96f9d4de2	273	oscsel = MCG_C7_OSCSEL_VAL;
<>	154:37f96f9d4de2	274
<>	154:37f96f9d4de2	275	/*
<>	154:37f96f9d4de2	276	When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
<>	154:37f96f9d4de2	277	1. MCG_C7[OSCSEL] selects IRC48M.
<>	154:37f96f9d4de2	278	2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
<>	154:37f96f9d4de2	279	*/
<>	154:37f96f9d4de2	280	if (((0U != range) && (kMCG_OscselOsc == oscsel)) \|\| (kMCG_OscselIrc == oscsel))
<>	154:37f96f9d4de2	281	{
<>	154:37f96f9d4de2	282	switch (frdiv)
<>	154:37f96f9d4de2	283	{
<>	154:37f96f9d4de2	284	case 0:
<>	154:37f96f9d4de2	285	case 1:
<>	154:37f96f9d4de2	286	case 2:
<>	154:37f96f9d4de2	287	case 3:
<>	154:37f96f9d4de2	288	case 4:
<>	154:37f96f9d4de2	289	case 5:
<>	154:37f96f9d4de2	290	freq >>= 5u;
<>	154:37f96f9d4de2	291	break;
<>	154:37f96f9d4de2	292	case 6:
<>	154:37f96f9d4de2	293	/* 6420=1280 /
<>	154:37f96f9d4de2	294	freq /= 20u;
<>	154:37f96f9d4de2	295	break;
<>	154:37f96f9d4de2	296	case 7:
<>	154:37f96f9d4de2	297	/* 12812=1536 /
<>	154:37f96f9d4de2	298	freq /= 12u;
<>	154:37f96f9d4de2	299	break;
<>	154:37f96f9d4de2	300	default:
<>	154:37f96f9d4de2	301	freq = 0u;
<>	154:37f96f9d4de2	302	break;
<>	154:37f96f9d4de2	303	}
<>	154:37f96f9d4de2	304	}
<>	154:37f96f9d4de2	305
<>	154:37f96f9d4de2	306	return freq;
<>	154:37f96f9d4de2	307	}
<>	154:37f96f9d4de2	308
<>	154:37f96f9d4de2	309	static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
<>	154:37f96f9d4de2	310	{
<>	154:37f96f9d4de2	311	if (kMCG_IrcSlow == MCG_S_IRCST_VAL)
<>	154:37f96f9d4de2	312	{
<>	154:37f96f9d4de2	313	/* Slow internal reference clock selected*/
<>	154:37f96f9d4de2	314	return s_slowIrcFreq;
<>	154:37f96f9d4de2	315	}
<>	154:37f96f9d4de2	316	else
<>	154:37f96f9d4de2	317	{
<>	154:37f96f9d4de2	318	/* Fast internal reference clock selected*/
<>	154:37f96f9d4de2	319	return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
<>	154:37f96f9d4de2	320	}
<>	154:37f96f9d4de2	321	}
<>	154:37f96f9d4de2	322
<>	154:37f96f9d4de2	323	static uint32_t CLOCK_GetFllRefClkFreq(void)
<>	154:37f96f9d4de2	324	{
<>	154:37f96f9d4de2	325	/* If use external reference clock. */
<>	154:37f96f9d4de2	326	if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	327	{
<>	154:37f96f9d4de2	328	return CLOCK_GetFllExtRefClkFreq();
<>	154:37f96f9d4de2	329	}
<>	154:37f96f9d4de2	330	/* If use internal reference clock. */
<>	154:37f96f9d4de2	331	else
<>	154:37f96f9d4de2	332	{
<>	154:37f96f9d4de2	333	return s_slowIrcFreq;
<>	154:37f96f9d4de2	334	}
<>	154:37f96f9d4de2	335	}
<>	154:37f96f9d4de2	336
<>	154:37f96f9d4de2	337	static uint32_t CLOCK_GetPll0RefFreq(void)
<>	154:37f96f9d4de2	338	{
<>	154:37f96f9d4de2	339	/* MCG external reference clock. */
<>	154:37f96f9d4de2	340	return CLOCK_GetMcgExtClkFreq();
<>	154:37f96f9d4de2	341	}
<>	154:37f96f9d4de2	342
<>	154:37f96f9d4de2	343	static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
<>	154:37f96f9d4de2	344	{
<>	154:37f96f9d4de2	345	uint8_t range;
<>	154:37f96f9d4de2	346
<>	154:37f96f9d4de2	347	if (freq <= 39063U)
<>	154:37f96f9d4de2	348	{
<>	154:37f96f9d4de2	349	range = 0U;
<>	154:37f96f9d4de2	350	}
<>	154:37f96f9d4de2	351	else if (freq <= 8000000U)
<>	154:37f96f9d4de2	352	{
<>	154:37f96f9d4de2	353	range = 1U;
<>	154:37f96f9d4de2	354	}
<>	154:37f96f9d4de2	355	else
<>	154:37f96f9d4de2	356	{
<>	154:37f96f9d4de2	357	range = 2U;
<>	154:37f96f9d4de2	358	}
<>	154:37f96f9d4de2	359
<>	154:37f96f9d4de2	360	return range;
<>	154:37f96f9d4de2	361	}
<>	154:37f96f9d4de2	362
<>	154:37f96f9d4de2	363	uint32_t CLOCK_GetOsc0ErClkUndivFreq(void)
<>	154:37f96f9d4de2	364	{
<>	154:37f96f9d4de2	365	if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
<>	154:37f96f9d4de2	366	{
<>	154:37f96f9d4de2	367	/* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
<>	154:37f96f9d4de2	368	assert(g_xtal0Freq);
<>	154:37f96f9d4de2	369	return g_xtal0Freq;
<>	154:37f96f9d4de2	370	}
<>	154:37f96f9d4de2	371	else
<>	154:37f96f9d4de2	372	{
<>	154:37f96f9d4de2	373	return 0U;
<>	154:37f96f9d4de2	374	}
<>	154:37f96f9d4de2	375	}
<>	154:37f96f9d4de2	376
<>	154:37f96f9d4de2	377	uint32_t CLOCK_GetOsc0ErClkDivFreq(void)
<>	154:37f96f9d4de2	378	{
<>	154:37f96f9d4de2	379	if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
<>	154:37f96f9d4de2	380	{
<>	154:37f96f9d4de2	381	/* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
<>	154:37f96f9d4de2	382	assert(g_xtal0Freq);
<>	154:37f96f9d4de2	383	return g_xtal0Freq >> ((OSC0->DIV & OSC_DIV_ERPS_MASK) >> OSC_DIV_ERPS_SHIFT);
<>	154:37f96f9d4de2	384	}
<>	154:37f96f9d4de2	385	else
<>	154:37f96f9d4de2	386	{
<>	154:37f96f9d4de2	387	return 0U;
<>	154:37f96f9d4de2	388	}
<>	154:37f96f9d4de2	389	}
<>	154:37f96f9d4de2	390
<>	154:37f96f9d4de2	391	uint32_t CLOCK_GetEr32kClkFreq(void)
<>	154:37f96f9d4de2	392	{
<>	154:37f96f9d4de2	393	uint32_t freq;
<>	154:37f96f9d4de2	394
<>	154:37f96f9d4de2	395	switch (SIM_SOPT1_OSC32KSEL_VAL)
<>	154:37f96f9d4de2	396	{
<>	154:37f96f9d4de2	397	case 0U: /* OSC 32k clock */
<>	154:37f96f9d4de2	398	freq = (CLOCK_GetOsc0ErClkDivFreq() == 32768U) ? 32768U : 0U;
<>	154:37f96f9d4de2	399	break;
<>	154:37f96f9d4de2	400	case 2U: /* RTC 32k clock */
<>	154:37f96f9d4de2	401	/* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
<>	154:37f96f9d4de2	402	assert(g_xtal32Freq);
<>	154:37f96f9d4de2	403	freq = g_xtal32Freq;
<>	154:37f96f9d4de2	404	break;
<>	154:37f96f9d4de2	405	case 3U: /* LPO clock */
<>	154:37f96f9d4de2	406	freq = LPO_CLK_FREQ;
<>	154:37f96f9d4de2	407	break;
<>	154:37f96f9d4de2	408	default:
<>	154:37f96f9d4de2	409	freq = 0U;
<>	154:37f96f9d4de2	410	break;
<>	154:37f96f9d4de2	411	}
<>	154:37f96f9d4de2	412	return freq;
<>	154:37f96f9d4de2	413	}
<>	154:37f96f9d4de2	414
<>	154:37f96f9d4de2	415	uint32_t CLOCK_GetPllFllSelClkFreq(void)
<>	154:37f96f9d4de2	416	{
<>	154:37f96f9d4de2	417	uint32_t freq;
<>	154:37f96f9d4de2	418
<>	154:37f96f9d4de2	419	switch (SIM_SOPT2_PLLFLLSEL_VAL)
<>	154:37f96f9d4de2	420	{
<>	154:37f96f9d4de2	421	case 0U: /* FLL. */
<>	154:37f96f9d4de2	422	freq = CLOCK_GetFllFreq();
<>	154:37f96f9d4de2	423	break;
<>	154:37f96f9d4de2	424	case 1U: /* PLL. */
<>	154:37f96f9d4de2	425	freq = CLOCK_GetPll0Freq();
<>	154:37f96f9d4de2	426	break;
AnnaBridge	175:af195413fb11	427	case 2U: /* USB1 PFD */
AnnaBridge	175:af195413fb11	428	freq = CLOCK_GetExtPllFreq();
AnnaBridge	175:af195413fb11	429	break;
<>	154:37f96f9d4de2	430	case 3U: /* MCG IRC48M. */
<>	154:37f96f9d4de2	431	freq = MCG_INTERNAL_IRC_48M;
<>	154:37f96f9d4de2	432	break;
<>	154:37f96f9d4de2	433	default:
<>	154:37f96f9d4de2	434	freq = 0U;
<>	154:37f96f9d4de2	435	break;
<>	154:37f96f9d4de2	436	}
<>	154:37f96f9d4de2	437
<>	154:37f96f9d4de2	438	return freq * (SIM_CLKDIV3_PLLFLLFRAC_VAL + 1U) / (SIM_CLKDIV3_PLLFLLDIV_VAL + 1U);
<>	154:37f96f9d4de2	439	}
<>	154:37f96f9d4de2	440
<>	154:37f96f9d4de2	441	uint32_t CLOCK_GetOsc0ErClkFreq(void)
<>	154:37f96f9d4de2	442	{
<>	154:37f96f9d4de2	443	return CLOCK_GetOsc0ErClkDivFreq();
<>	154:37f96f9d4de2	444	}
<>	154:37f96f9d4de2	445
<>	154:37f96f9d4de2	446	uint32_t CLOCK_GetPlatClkFreq(void)
<>	154:37f96f9d4de2	447	{
<>	154:37f96f9d4de2	448	return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
<>	154:37f96f9d4de2	449	}
<>	154:37f96f9d4de2	450
<>	154:37f96f9d4de2	451	uint32_t CLOCK_GetFlashClkFreq(void)
<>	154:37f96f9d4de2	452	{
<>	154:37f96f9d4de2	453	return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1);
<>	154:37f96f9d4de2	454	}
<>	154:37f96f9d4de2	455
<>	154:37f96f9d4de2	456	uint32_t CLOCK_GetFlexBusClkFreq(void)
<>	154:37f96f9d4de2	457	{
<>	154:37f96f9d4de2	458	return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1);
<>	154:37f96f9d4de2	459	}
<>	154:37f96f9d4de2	460
<>	154:37f96f9d4de2	461	uint32_t CLOCK_GetBusClkFreq(void)
<>	154:37f96f9d4de2	462	{
<>	154:37f96f9d4de2	463	return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1);
<>	154:37f96f9d4de2	464	}
<>	154:37f96f9d4de2	465
<>	154:37f96f9d4de2	466	uint32_t CLOCK_GetCoreSysClkFreq(void)
<>	154:37f96f9d4de2	467	{
<>	154:37f96f9d4de2	468	return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
<>	154:37f96f9d4de2	469	}
<>	154:37f96f9d4de2	470
<>	154:37f96f9d4de2	471	uint32_t CLOCK_GetFreq(clock_name_t clockName)
<>	154:37f96f9d4de2	472	{
<>	154:37f96f9d4de2	473	uint32_t freq;
<>	154:37f96f9d4de2	474
<>	154:37f96f9d4de2	475	switch (clockName)
<>	154:37f96f9d4de2	476	{
<>	154:37f96f9d4de2	477	case kCLOCK_CoreSysClk:
<>	154:37f96f9d4de2	478	case kCLOCK_PlatClk:
<>	154:37f96f9d4de2	479	freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
<>	154:37f96f9d4de2	480	break;
<>	154:37f96f9d4de2	481	case kCLOCK_BusClk:
<>	154:37f96f9d4de2	482	freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1);
<>	154:37f96f9d4de2	483	break;
<>	154:37f96f9d4de2	484	case kCLOCK_FlexBusClk:
<>	154:37f96f9d4de2	485	freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1);
<>	154:37f96f9d4de2	486	break;
<>	154:37f96f9d4de2	487	case kCLOCK_FlashClk:
<>	154:37f96f9d4de2	488	freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1);
<>	154:37f96f9d4de2	489	break;
<>	154:37f96f9d4de2	490	case kCLOCK_PllFllSelClk:
<>	154:37f96f9d4de2	491	freq = CLOCK_GetPllFllSelClkFreq();
<>	154:37f96f9d4de2	492	break;
<>	154:37f96f9d4de2	493	case kCLOCK_Er32kClk:
<>	154:37f96f9d4de2	494	freq = CLOCK_GetEr32kClkFreq();
<>	154:37f96f9d4de2	495	break;
<>	154:37f96f9d4de2	496	case kCLOCK_Osc0ErClk:
<>	154:37f96f9d4de2	497	freq = CLOCK_GetOsc0ErClkDivFreq();
<>	154:37f96f9d4de2	498	break;
<>	154:37f96f9d4de2	499	case kCLOCK_Osc0ErClkUndiv:
<>	154:37f96f9d4de2	500	freq = CLOCK_GetOsc0ErClkUndivFreq();
<>	154:37f96f9d4de2	501	break;
<>	154:37f96f9d4de2	502	case kCLOCK_McgFixedFreqClk:
<>	154:37f96f9d4de2	503	freq = CLOCK_GetFixedFreqClkFreq();
<>	154:37f96f9d4de2	504	break;
<>	154:37f96f9d4de2	505	case kCLOCK_McgInternalRefClk:
<>	154:37f96f9d4de2	506	freq = CLOCK_GetInternalRefClkFreq();
<>	154:37f96f9d4de2	507	break;
<>	154:37f96f9d4de2	508	case kCLOCK_McgFllClk:
<>	154:37f96f9d4de2	509	freq = CLOCK_GetFllFreq();
<>	154:37f96f9d4de2	510	break;
<>	154:37f96f9d4de2	511	case kCLOCK_McgPll0Clk:
<>	154:37f96f9d4de2	512	freq = CLOCK_GetPll0Freq();
<>	154:37f96f9d4de2	513	break;
<>	154:37f96f9d4de2	514	case kCLOCK_McgIrc48MClk:
<>	154:37f96f9d4de2	515	freq = MCG_INTERNAL_IRC_48M;
<>	154:37f96f9d4de2	516	break;
<>	154:37f96f9d4de2	517	case kCLOCK_LpoClk:
<>	154:37f96f9d4de2	518	freq = LPO_CLK_FREQ;
<>	154:37f96f9d4de2	519	break;
<>	154:37f96f9d4de2	520	default:
<>	154:37f96f9d4de2	521	freq = 0U;
<>	154:37f96f9d4de2	522	break;
<>	154:37f96f9d4de2	523	}
<>	154:37f96f9d4de2	524
<>	154:37f96f9d4de2	525	return freq;
<>	154:37f96f9d4de2	526	}
<>	154:37f96f9d4de2	527
<>	154:37f96f9d4de2	528	void CLOCK_SetSimConfig(sim_clock_config_t const *config)
<>	154:37f96f9d4de2	529	{
<>	154:37f96f9d4de2	530	SIM->CLKDIV1 = config->clkdiv1;
<>	154:37f96f9d4de2	531	CLOCK_SetPllFllSelClock(config->pllFllSel, config->pllFllDiv, config->pllFllFrac);
<>	154:37f96f9d4de2	532	CLOCK_SetEr32kClock(config->er32kSrc);
<>	154:37f96f9d4de2	533	}
<>	154:37f96f9d4de2	534
<>	154:37f96f9d4de2	535	bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
<>	154:37f96f9d4de2	536	{
<>	154:37f96f9d4de2	537	/* In current implementation, USBPFDCLK is not used for USB FS. */
<>	154:37f96f9d4de2	538	assert(kCLOCK_UsbSrcUsbPfd != src);
<>	154:37f96f9d4de2	539
<>	154:37f96f9d4de2	540	bool ret = true;
<>	154:37f96f9d4de2	541
<>	154:37f96f9d4de2	542	CLOCK_DisableClock(kCLOCK_Usbfs0);
<>	154:37f96f9d4de2	543
<>	154:37f96f9d4de2	544	if (kCLOCK_UsbSrcExt == src)
<>	154:37f96f9d4de2	545	{
<>	154:37f96f9d4de2	546	SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
<>	154:37f96f9d4de2	547	}
<>	154:37f96f9d4de2	548	else
<>	154:37f96f9d4de2	549	{
<>	154:37f96f9d4de2	550	switch (freq)
<>	154:37f96f9d4de2	551	{
<>	154:37f96f9d4de2	552	case 120000000U:
<>	154:37f96f9d4de2	553	SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) \| SIM_CLKDIV2_USBFRAC(1);
<>	154:37f96f9d4de2	554	break;
<>	154:37f96f9d4de2	555	case 96000000U:
<>	154:37f96f9d4de2	556	SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) \| SIM_CLKDIV2_USBFRAC(0);
<>	154:37f96f9d4de2	557	break;
<>	154:37f96f9d4de2	558	case 72000000U:
<>	154:37f96f9d4de2	559	SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) \| SIM_CLKDIV2_USBFRAC(1);
<>	154:37f96f9d4de2	560	break;
<>	154:37f96f9d4de2	561	case 48000000U:
<>	154:37f96f9d4de2	562	SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) \| SIM_CLKDIV2_USBFRAC(0);
<>	154:37f96f9d4de2	563	break;
<>	154:37f96f9d4de2	564	default:
<>	154:37f96f9d4de2	565	ret = false;
<>	154:37f96f9d4de2	566	break;
<>	154:37f96f9d4de2	567	}
<>	154:37f96f9d4de2	568
<>	154:37f96f9d4de2	569	SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK \| SIM_SOPT2_USBSRC_MASK)) \| (uint32_t)src);
<>	154:37f96f9d4de2	570	}
<>	154:37f96f9d4de2	571
<>	154:37f96f9d4de2	572	CLOCK_EnableClock(kCLOCK_Usbfs0);
<>	154:37f96f9d4de2	573
<>	154:37f96f9d4de2	574	if (kCLOCK_UsbSrcIrc48M == src)
<>	154:37f96f9d4de2	575	{
<>	154:37f96f9d4de2	576	USB0->CLK_RECOVER_IRC_EN = 0x03U;
<>	154:37f96f9d4de2	577	USB0->CLK_RECOVER_CTRL \|= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
<>	154:37f96f9d4de2	578	}
<>	154:37f96f9d4de2	579	return ret;
<>	154:37f96f9d4de2	580	}
<>	154:37f96f9d4de2	581
<>	154:37f96f9d4de2	582	bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
<>	154:37f96f9d4de2	583	{
AnnaBridge	175:af195413fb11	584	/* Source and freq are not used for USB HS. */
AnnaBridge	175:af195413fb11	585	src = src;
AnnaBridge	175:af195413fb11	586	freq = freq;
AnnaBridge	175:af195413fb11	587
AnnaBridge	175:af195413fb11	588	SIM->SCGC3 \|= SIM_SCGC3_USBHS_MASK;
AnnaBridge	175:af195413fb11	589
AnnaBridge	175:af195413fb11	590	SIM->USBPHYCTL = ((SIM->USBPHYCTL & ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK)) \| SIM_USBPHYCTL_USB3VOUTTRG(6U) /* 3.310V */
AnnaBridge	175:af195413fb11	591	\| SIM_USBPHYCTL_USBVREGSEL_MASK); /* VREG_IN1 */
AnnaBridge	175:af195413fb11	592
AnnaBridge	175:af195413fb11	593	USBPHY->PLL_SIC \|= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PLL */
AnnaBridge	175:af195413fb11	594
AnnaBridge	175:af195413fb11	595	return true;
AnnaBridge	175:af195413fb11	596	}
AnnaBridge	175:af195413fb11	597
AnnaBridge	175:af195413fb11	598	void CLOCK_DisableUsbhs0Clock(void)
AnnaBridge	175:af195413fb11	599	{
AnnaBridge	175:af195413fb11	600	USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY PLL */
AnnaBridge	175:af195413fb11	601	SIM->SCGC3 &= ~SIM_SCGC3_USBHS_MASK;
AnnaBridge	175:af195413fb11	602	}
AnnaBridge	175:af195413fb11	603
AnnaBridge	175:af195413fb11	604	bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
AnnaBridge	175:af195413fb11	605	{
<>	154:37f96f9d4de2	606	volatile uint32_t i;
AnnaBridge	175:af195413fb11	607	uint32_t phyPllDiv = 0U;
<>	154:37f96f9d4de2	608
<>	154:37f96f9d4de2	609	/*
<>	154:37f96f9d4de2	610	* In order to bring up the internal 480MHz USB PLL clock, should make sure:
<>	154:37f96f9d4de2	611	* 1. 32kHz IRC clock enable by setting IRCLKEN bit in MCG_C1 register.
<>	154:37f96f9d4de2	612	* 2. External reference clock enable on XTAL by setting ERCLKEN bit in OSC_CR register.
<>	154:37f96f9d4de2	613	*/
<>	154:37f96f9d4de2	614	assert(MCG->C1 & MCG_C1_IRCLKEN_MASK);
<>	154:37f96f9d4de2	615	assert(!(MCG->C2 & MCG_C2_IRCS_MASK));
<>	154:37f96f9d4de2	616	assert(OSC0->CR & OSC_CR_ERCLKEN_MASK);
<>	154:37f96f9d4de2	617
AnnaBridge	175:af195413fb11	618	if (24000000U == freq)
AnnaBridge	175:af195413fb11	619	{
AnnaBridge	175:af195413fb11	620	phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
AnnaBridge	175:af195413fb11	621	}
AnnaBridge	175:af195413fb11	622	else if (16000000U == freq)
AnnaBridge	175:af195413fb11	623	{
AnnaBridge	175:af195413fb11	624	phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
AnnaBridge	175:af195413fb11	625	}
AnnaBridge	175:af195413fb11	626	else if (12000000U == freq)
AnnaBridge	175:af195413fb11	627	{
AnnaBridge	175:af195413fb11	628	phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
AnnaBridge	175:af195413fb11	629	}
AnnaBridge	175:af195413fb11	630	else
AnnaBridge	175:af195413fb11	631	{
AnnaBridge	175:af195413fb11	632	return false;
AnnaBridge	175:af195413fb11	633	}
AnnaBridge	175:af195413fb11	634
<>	154:37f96f9d4de2	635	/* Source and freq are not used for USB HS. */
<>	154:37f96f9d4de2	636	src = src;
<>	154:37f96f9d4de2	637
AnnaBridge	175:af195413fb11	638	SIM->SCGC3 \|= SIM_SCGC3_USBHSPHY_MASK;
<>	154:37f96f9d4de2	639	SIM->SOPT2 \|= SIM_SOPT2_USBREGEN_MASK;
<>	154:37f96f9d4de2	640
<>	154:37f96f9d4de2	641	i = 500000U;
<>	154:37f96f9d4de2	642	while (i--)
<>	154:37f96f9d4de2	643	{
<>	154:37f96f9d4de2	644	__NOP();
<>	154:37f96f9d4de2	645	}
<>	154:37f96f9d4de2	646
AnnaBridge	175:af195413fb11	647	USBPHY->TRIM_OVERRIDE_EN = 0x01U; /* Override the trim. */
AnnaBridge	175:af195413fb11	648	USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
AnnaBridge	175:af195413fb11	649	USBPHY->PLL_SIC \|= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
AnnaBridge	175:af195413fb11	650	USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) \| phyPllDiv;
AnnaBridge	175:af195413fb11	651	USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */
AnnaBridge	175:af195413fb11	652	USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */
AnnaBridge	175:af195413fb11	653
AnnaBridge	175:af195413fb11	654	/* Wait for lock. */
AnnaBridge	175:af195413fb11	655	while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
AnnaBridge	175:af195413fb11	656	{
AnnaBridge	175:af195413fb11	657	}
<>	154:37f96f9d4de2	658
<>	154:37f96f9d4de2	659	return true;
<>	154:37f96f9d4de2	660	}
<>	154:37f96f9d4de2	661
AnnaBridge	175:af195413fb11	662	void CLOCK_DisableUsbhs0PhyPllClock(void)
AnnaBridge	175:af195413fb11	663	{
AnnaBridge	175:af195413fb11	664	USBPHY->CTRL \|= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
AnnaBridge	175:af195413fb11	665	USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* Power down PLL */
AnnaBridge	175:af195413fb11	666	SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK;
AnnaBridge	175:af195413fb11	667	SIM->SCGC3 &= ~SIM_SCGC3_USBHSPHY_MASK;
AnnaBridge	175:af195413fb11	668	}
AnnaBridge	175:af195413fb11	669
AnnaBridge	175:af195413fb11	670	void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src)
AnnaBridge	175:af195413fb11	671	{
AnnaBridge	175:af195413fb11	672	assert((frac <= 35U) && (frac >= 18U));
AnnaBridge	175:af195413fb11	673	uint32_t fracFreq = (480000U * 18U / frac) * 1000U;
AnnaBridge	175:af195413fb11	674
AnnaBridge	175:af195413fb11	675	USBPHY->ANACTRL = (USBPHY->ANACTRL & ~(USBPHY_ANACTRL_PFD_FRAC_MASK \| USBPHY_ANACTRL_PFD_CLK_SEL_MASK)) \|
AnnaBridge	175:af195413fb11	676	(USBPHY_ANACTRL_PFD_FRAC(frac) \| USBPHY_ANACTRL_PFD_CLK_SEL(src));
AnnaBridge	175:af195413fb11	677
AnnaBridge	175:af195413fb11	678	USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
AnnaBridge	175:af195413fb11	679	while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
AnnaBridge	175:af195413fb11	680	{
AnnaBridge	175:af195413fb11	681	}
AnnaBridge	175:af195413fb11	682
AnnaBridge	175:af195413fb11	683	if (kCLOCK_UsbPfdSrcExt == src)
AnnaBridge	175:af195413fb11	684	{
AnnaBridge	175:af195413fb11	685	s_extPllFreq = g_xtal0Freq;
AnnaBridge	175:af195413fb11	686	}
AnnaBridge	175:af195413fb11	687	else if (kCLOCK_UsbPfdSrcFracDivBy4 == src)
AnnaBridge	175:af195413fb11	688	{
AnnaBridge	175:af195413fb11	689	s_extPllFreq = fracFreq / 4U;
AnnaBridge	175:af195413fb11	690	}
AnnaBridge	175:af195413fb11	691	else if (kCLOCK_UsbPfdSrcFracDivBy2 == src)
AnnaBridge	175:af195413fb11	692	{
AnnaBridge	175:af195413fb11	693	s_extPllFreq = fracFreq / 2U;
AnnaBridge	175:af195413fb11	694	}
AnnaBridge	175:af195413fb11	695	else
AnnaBridge	175:af195413fb11	696	{
AnnaBridge	175:af195413fb11	697	s_extPllFreq = fracFreq;
AnnaBridge	175:af195413fb11	698	}
AnnaBridge	175:af195413fb11	699	}
AnnaBridge	175:af195413fb11	700
AnnaBridge	175:af195413fb11	701	void CLOCK_DisableUsbhs0PfdClock(void)
AnnaBridge	175:af195413fb11	702	{
AnnaBridge	175:af195413fb11	703	USBPHY->ANACTRL \|= USBPHY_ANACTRL_PFD_CLKGATE_MASK;
AnnaBridge	175:af195413fb11	704	s_extPllFreq = 0U;
AnnaBridge	175:af195413fb11	705	}
AnnaBridge	175:af195413fb11	706
<>	154:37f96f9d4de2	707	uint32_t CLOCK_GetOutClkFreq(void)
<>	154:37f96f9d4de2	708	{
<>	154:37f96f9d4de2	709	uint32_t mcgoutclk;
<>	154:37f96f9d4de2	710	uint32_t clkst = MCG_S_CLKST_VAL;
<>	154:37f96f9d4de2	711	uint32_t pllcst = MCG_S2_PLLCST_VAL;
<>	154:37f96f9d4de2	712
<>	154:37f96f9d4de2	713	switch (clkst)
<>	154:37f96f9d4de2	714	{
<>	154:37f96f9d4de2	715	case kMCG_ClkOutStatPll:
<>	154:37f96f9d4de2	716	switch (pllcst)
<>	154:37f96f9d4de2	717	{
<>	154:37f96f9d4de2	718	case kMCG_PllClkSelExtPll:
<>	154:37f96f9d4de2	719	mcgoutclk = CLOCK_GetExtPllFreq();
<>	154:37f96f9d4de2	720	break;
<>	154:37f96f9d4de2	721	case kMCG_PllClkSelPll0:
<>	154:37f96f9d4de2	722	mcgoutclk = CLOCK_GetPll0Freq();
<>	154:37f96f9d4de2	723	break;
<>	154:37f96f9d4de2	724	default:
<>	154:37f96f9d4de2	725	mcgoutclk = 0U;
<>	154:37f96f9d4de2	726	break;
<>	154:37f96f9d4de2	727	}
<>	154:37f96f9d4de2	728	break;
<>	154:37f96f9d4de2	729	case kMCG_ClkOutStatFll:
<>	154:37f96f9d4de2	730	mcgoutclk = CLOCK_GetFllFreq();
<>	154:37f96f9d4de2	731	break;
<>	154:37f96f9d4de2	732	case kMCG_ClkOutStatInt:
<>	154:37f96f9d4de2	733	mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
<>	154:37f96f9d4de2	734	break;
<>	154:37f96f9d4de2	735	case kMCG_ClkOutStatExt:
<>	154:37f96f9d4de2	736	mcgoutclk = CLOCK_GetMcgExtClkFreq();
<>	154:37f96f9d4de2	737	break;
<>	154:37f96f9d4de2	738	default:
<>	154:37f96f9d4de2	739	mcgoutclk = 0U;
<>	154:37f96f9d4de2	740	break;
<>	154:37f96f9d4de2	741	}
<>	154:37f96f9d4de2	742	return mcgoutclk;
<>	154:37f96f9d4de2	743	}
<>	154:37f96f9d4de2	744
<>	154:37f96f9d4de2	745	uint32_t CLOCK_GetFllFreq(void)
<>	154:37f96f9d4de2	746	{
<>	154:37f96f9d4de2	747	static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
<>	154:37f96f9d4de2	748
<>	154:37f96f9d4de2	749	uint8_t drs, dmx32;
<>	154:37f96f9d4de2	750	uint32_t freq;
<>	154:37f96f9d4de2	751
<>	154:37f96f9d4de2	752	/* If FLL is not enabled currently, then return 0U. */
<>	154:37f96f9d4de2	753	if ((MCG->C2 & MCG_C2_LP_MASK) \|\| (MCG->S & MCG_S_PLLST_MASK))
<>	154:37f96f9d4de2	754	{
<>	154:37f96f9d4de2	755	return 0U;
<>	154:37f96f9d4de2	756	}
<>	154:37f96f9d4de2	757
<>	154:37f96f9d4de2	758	/* Get FLL reference clock frequency. */
<>	154:37f96f9d4de2	759	freq = CLOCK_GetFllRefClkFreq();
<>	154:37f96f9d4de2	760	if (!freq)
<>	154:37f96f9d4de2	761	{
<>	154:37f96f9d4de2	762	return freq;
<>	154:37f96f9d4de2	763	}
<>	154:37f96f9d4de2	764
<>	154:37f96f9d4de2	765	drs = MCG_C4_DRST_DRS_VAL;
<>	154:37f96f9d4de2	766	dmx32 = MCG_C4_DMX32_VAL;
<>	154:37f96f9d4de2	767
<>	154:37f96f9d4de2	768	return freq * fllFactorTable[drs][dmx32];
<>	154:37f96f9d4de2	769	}
<>	154:37f96f9d4de2	770
<>	154:37f96f9d4de2	771	uint32_t CLOCK_GetInternalRefClkFreq(void)
<>	154:37f96f9d4de2	772	{
<>	154:37f96f9d4de2	773	/* If MCGIRCLK is gated. */
<>	154:37f96f9d4de2	774	if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK))
<>	154:37f96f9d4de2	775	{
<>	154:37f96f9d4de2	776	return 0U;
<>	154:37f96f9d4de2	777	}
<>	154:37f96f9d4de2	778
<>	154:37f96f9d4de2	779	return CLOCK_GetInternalRefClkSelectFreq();
<>	154:37f96f9d4de2	780	}
<>	154:37f96f9d4de2	781
<>	154:37f96f9d4de2	782	uint32_t CLOCK_GetFixedFreqClkFreq(void)
<>	154:37f96f9d4de2	783	{
<>	154:37f96f9d4de2	784	uint32_t freq = CLOCK_GetFllRefClkFreq();
<>	154:37f96f9d4de2	785
<>	154:37f96f9d4de2	786	/* MCGFFCLK must be no more than MCGOUTCLK/8. */
<>	154:37f96f9d4de2	787	if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U)))
<>	154:37f96f9d4de2	788	{
<>	154:37f96f9d4de2	789	return freq;
<>	154:37f96f9d4de2	790	}
<>	154:37f96f9d4de2	791	else
<>	154:37f96f9d4de2	792	{
<>	154:37f96f9d4de2	793	return 0U;
<>	154:37f96f9d4de2	794	}
<>	154:37f96f9d4de2	795	}
<>	154:37f96f9d4de2	796
<>	154:37f96f9d4de2	797	uint32_t CLOCK_GetPll0Freq(void)
<>	154:37f96f9d4de2	798	{
<>	154:37f96f9d4de2	799	uint32_t mcgpll0clk;
<>	154:37f96f9d4de2	800
<>	154:37f96f9d4de2	801	/* If PLL0 is not enabled, return 0. */
<>	154:37f96f9d4de2	802	if (!(MCG->S & MCG_S_LOCK0_MASK))
<>	154:37f96f9d4de2	803	{
<>	154:37f96f9d4de2	804	return 0U;
<>	154:37f96f9d4de2	805	}
<>	154:37f96f9d4de2	806
<>	154:37f96f9d4de2	807	mcgpll0clk = CLOCK_GetPll0RefFreq();
<>	154:37f96f9d4de2	808
AnnaBridge	175:af195413fb11	809	/*
AnnaBridge	175:af195413fb11	810	* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock.
AnnaBridge	175:af195413fb11	811	* Please call CLOCK_SetXtal1Freq base on board setting before using OSC1 clock.
AnnaBridge	175:af195413fb11	812	*/
AnnaBridge	175:af195413fb11	813	assert(mcgpll0clk);
AnnaBridge	175:af195413fb11	814
<>	154:37f96f9d4de2	815	mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL);
<>	154:37f96f9d4de2	816	mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL);
<>	154:37f96f9d4de2	817
<>	154:37f96f9d4de2	818	mcgpll0clk >>= 1U;
<>	154:37f96f9d4de2	819	return mcgpll0clk;
<>	154:37f96f9d4de2	820	}
<>	154:37f96f9d4de2	821
<>	154:37f96f9d4de2	822	uint32_t CLOCK_GetExtPllFreq(void)
<>	154:37f96f9d4de2	823	{
<>	154:37f96f9d4de2	824	return s_extPllFreq;
<>	154:37f96f9d4de2	825	}
<>	154:37f96f9d4de2	826
<>	154:37f96f9d4de2	827	void CLOCK_SetExtPllFreq(uint32_t freq)
<>	154:37f96f9d4de2	828	{
<>	154:37f96f9d4de2	829	s_extPllFreq = freq;
<>	154:37f96f9d4de2	830	}
<>	154:37f96f9d4de2	831
<>	154:37f96f9d4de2	832	status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
<>	154:37f96f9d4de2	833	{
<>	154:37f96f9d4de2	834	bool needDelay;
<>	154:37f96f9d4de2	835	uint32_t i;
<>	154:37f96f9d4de2	836
<>	154:37f96f9d4de2	837	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	838	/* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
<>	154:37f96f9d4de2	839	if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
<>	154:37f96f9d4de2	840	{
<>	154:37f96f9d4de2	841	return kStatus_MCG_SourceUsed;
<>	154:37f96f9d4de2	842	}
<>	154:37f96f9d4de2	843	#endif /* MCG_CONFIG_CHECK_PARAM */
<>	154:37f96f9d4de2	844
<>	154:37f96f9d4de2	845	if (MCG_C7_OSCSEL_VAL != oscsel)
<>	154:37f96f9d4de2	846	{
<>	154:37f96f9d4de2	847	/* If change OSCSEL, need to delay, ERR009878. */
<>	154:37f96f9d4de2	848	needDelay = true;
<>	154:37f96f9d4de2	849	}
<>	154:37f96f9d4de2	850	else
<>	154:37f96f9d4de2	851	{
<>	154:37f96f9d4de2	852	needDelay = false;
<>	154:37f96f9d4de2	853	}
<>	154:37f96f9d4de2	854
<>	154:37f96f9d4de2	855	MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) \| MCG_C7_OSCSEL(oscsel);
<>	154:37f96f9d4de2	856	if (needDelay)
<>	154:37f96f9d4de2	857	{
<>	154:37f96f9d4de2	858	/* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
<>	154:37f96f9d4de2	859	i = 1500U;
<>	154:37f96f9d4de2	860	while (i--)
<>	154:37f96f9d4de2	861	{
<>	154:37f96f9d4de2	862	__NOP();
<>	154:37f96f9d4de2	863	}
<>	154:37f96f9d4de2	864	}
<>	154:37f96f9d4de2	865
<>	154:37f96f9d4de2	866	return kStatus_Success;
<>	154:37f96f9d4de2	867	}
<>	154:37f96f9d4de2	868
<>	154:37f96f9d4de2	869	status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
<>	154:37f96f9d4de2	870	{
<>	154:37f96f9d4de2	871	uint32_t mcgOutClkState = MCG_S_CLKST_VAL;
<>	154:37f96f9d4de2	872	mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL;
<>	154:37f96f9d4de2	873	uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
<>	154:37f96f9d4de2	874
<>	154:37f96f9d4de2	875	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	876	/* If MCGIRCLK is used as system clock source. */
<>	154:37f96f9d4de2	877	if (kMCG_ClkOutStatInt == mcgOutClkState)
<>	154:37f96f9d4de2	878	{
<>	154:37f96f9d4de2	879	/* If need to change MCGIRCLK source or driver, return error. */
<>	154:37f96f9d4de2	880	if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) \|\| (ircs != curIrcs))
<>	154:37f96f9d4de2	881	{
<>	154:37f96f9d4de2	882	return kStatus_MCG_SourceUsed;
<>	154:37f96f9d4de2	883	}
<>	154:37f96f9d4de2	884	}
<>	154:37f96f9d4de2	885	#endif
<>	154:37f96f9d4de2	886
<>	154:37f96f9d4de2	887	/* If need to update the FCRDIV. */
<>	154:37f96f9d4de2	888	if (fcrdiv != curFcrdiv)
<>	154:37f96f9d4de2	889	{
<>	154:37f96f9d4de2	890	/* If fast IRC is in use currently, change to slow IRC. */
<>	154:37f96f9d4de2	891	if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) \|\| (MCG->C1 & MCG_C1_IRCLKEN_MASK)))
<>	154:37f96f9d4de2	892	{
<>	154:37f96f9d4de2	893	MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) \| (MCG_C2_IRCS(kMCG_IrcSlow)));
<>	154:37f96f9d4de2	894	while (MCG_S_IRCST_VAL != kMCG_IrcSlow)
<>	154:37f96f9d4de2	895	{
<>	154:37f96f9d4de2	896	}
<>	154:37f96f9d4de2	897	}
<>	154:37f96f9d4de2	898	/* Update FCRDIV. */
<>	154:37f96f9d4de2	899	MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK \| MCG_SC_ATMF_MASK \| MCG_SC_LOCS0_MASK)) \| MCG_SC_FCRDIV(fcrdiv);
<>	154:37f96f9d4de2	900	}
<>	154:37f96f9d4de2	901
<>	154:37f96f9d4de2	902	/* Set internal reference clock selection. */
<>	154:37f96f9d4de2	903	MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) \| (MCG_C2_IRCS(ircs));
<>	154:37f96f9d4de2	904	MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK \| MCG_C1_IREFSTEN_MASK)) \| (uint8_t)enableMode;
<>	154:37f96f9d4de2	905
<>	154:37f96f9d4de2	906	/* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
<>	154:37f96f9d4de2	907	if ((mcgOutClkState == kMCG_ClkOutStatInt) \|\| (enableMode & kMCG_IrclkEnable))
<>	154:37f96f9d4de2	908	{
<>	154:37f96f9d4de2	909	while (MCG_S_IRCST_VAL != ircs)
<>	154:37f96f9d4de2	910	{
<>	154:37f96f9d4de2	911	}
<>	154:37f96f9d4de2	912	}
<>	154:37f96f9d4de2	913
<>	154:37f96f9d4de2	914	return kStatus_Success;
<>	154:37f96f9d4de2	915	}
<>	154:37f96f9d4de2	916
<>	154:37f96f9d4de2	917	uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t prdiv, uint8_t vdiv)
<>	154:37f96f9d4de2	918	{
<>	154:37f96f9d4de2	919	uint8_t ret_prdiv; /* PRDIV to return. */
<>	154:37f96f9d4de2	920	uint8_t ret_vdiv; /* VDIV to return. */
<>	154:37f96f9d4de2	921	uint8_t prdiv_min; /* Min PRDIV value to make reference clock in allowed range. */
<>	154:37f96f9d4de2	922	uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */
<>	154:37f96f9d4de2	923	uint8_t prdiv_cur; /* PRDIV value for iteration. */
<>	154:37f96f9d4de2	924	uint8_t vdiv_cur; /* VDIV value for iteration. */
<>	154:37f96f9d4de2	925	uint32_t ret_freq = 0U; /* PLL output fequency to return. */
<>	154:37f96f9d4de2	926	uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
<>	154:37f96f9d4de2	927	uint32_t ref_div; /* Reference frequency after PRDIV. */
<>	154:37f96f9d4de2	928
<>	154:37f96f9d4de2	929	/*
<>	154:37f96f9d4de2	930	Steps:
<>	154:37f96f9d4de2	931	1. Get allowed prdiv with such rules:
<>	154:37f96f9d4de2	932	1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN.
<>	154:37f96f9d4de2	933	2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX.
<>	154:37f96f9d4de2	934	2. For each allowed prdiv, there are two candidate vdiv values:
<>	154:37f96f9d4de2	935	1). (desireFreq / (refFreq / prdiv)).
<>	154:37f96f9d4de2	936	2). (desireFreq / (refFreq / prdiv)) + 1.
<>	154:37f96f9d4de2	937	If could get the precise desired frequency, return current prdiv and
<>	154:37f96f9d4de2	938	vdiv directly. Otherwise choose the one which is closer to desired
<>	154:37f96f9d4de2	939	frequency.
<>	154:37f96f9d4de2	940	*/
<>	154:37f96f9d4de2	941
<>	154:37f96f9d4de2	942	/* Reference frequency is out of range. */
<>	154:37f96f9d4de2	943	if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) \|\|
<>	154:37f96f9d4de2	944	(refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
<>	154:37f96f9d4de2	945	{
<>	154:37f96f9d4de2	946	return 0U;
<>	154:37f96f9d4de2	947	}
<>	154:37f96f9d4de2	948
<>	154:37f96f9d4de2	949	/* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */
<>	154:37f96f9d4de2	950	prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN;
<>	154:37f96f9d4de2	951	prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX;
<>	154:37f96f9d4de2	952
<>	154:37f96f9d4de2	953	desireFreq *= 2U;
<>	154:37f96f9d4de2	954
<>	154:37f96f9d4de2	955	/* PRDIV traversal. */
<>	154:37f96f9d4de2	956	for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
<>	154:37f96f9d4de2	957	{
<>	154:37f96f9d4de2	958	/* Reference frequency after PRDIV. */
<>	154:37f96f9d4de2	959	ref_div = refFreq / prdiv_cur;
<>	154:37f96f9d4de2	960
<>	154:37f96f9d4de2	961	vdiv_cur = desireFreq / ref_div;
<>	154:37f96f9d4de2	962
<>	154:37f96f9d4de2	963	if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) \|\| (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
<>	154:37f96f9d4de2	964	{
<>	154:37f96f9d4de2	965	/* No VDIV is available with this PRDIV. */
<>	154:37f96f9d4de2	966	continue;
<>	154:37f96f9d4de2	967	}
<>	154:37f96f9d4de2	968
<>	154:37f96f9d4de2	969	ret_freq = vdiv_cur * ref_div;
<>	154:37f96f9d4de2	970
<>	154:37f96f9d4de2	971	if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE)
<>	154:37f96f9d4de2	972	{
<>	154:37f96f9d4de2	973	if (ret_freq == desireFreq) /* If desire frequency is got. */
<>	154:37f96f9d4de2	974	{
<>	154:37f96f9d4de2	975	*prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
<>	154:37f96f9d4de2	976	*vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE;
<>	154:37f96f9d4de2	977	return ret_freq / 2U;
<>	154:37f96f9d4de2	978	}
<>	154:37f96f9d4de2	979	/* New PRDIV/VDIV is closer. */
<>	154:37f96f9d4de2	980	if (diff > desireFreq - ret_freq)
<>	154:37f96f9d4de2	981	{
<>	154:37f96f9d4de2	982	diff = desireFreq - ret_freq;
<>	154:37f96f9d4de2	983	ret_prdiv = prdiv_cur;
<>	154:37f96f9d4de2	984	ret_vdiv = vdiv_cur;
<>	154:37f96f9d4de2	985	}
<>	154:37f96f9d4de2	986	}
<>	154:37f96f9d4de2	987	vdiv_cur++;
<>	154:37f96f9d4de2	988	if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
<>	154:37f96f9d4de2	989	{
<>	154:37f96f9d4de2	990	ret_freq += ref_div;
<>	154:37f96f9d4de2	991	/* New PRDIV/VDIV is closer. */
<>	154:37f96f9d4de2	992	if (diff > ret_freq - desireFreq)
<>	154:37f96f9d4de2	993	{
<>	154:37f96f9d4de2	994	diff = ret_freq - desireFreq;
<>	154:37f96f9d4de2	995	ret_prdiv = prdiv_cur;
<>	154:37f96f9d4de2	996	ret_vdiv = vdiv_cur;
<>	154:37f96f9d4de2	997	}
<>	154:37f96f9d4de2	998	}
<>	154:37f96f9d4de2	999	}
<>	154:37f96f9d4de2	1000
<>	154:37f96f9d4de2	1001	if (0xFFFFFFFFU != diff)
<>	154:37f96f9d4de2	1002	{
<>	154:37f96f9d4de2	1003	/* PRDIV/VDIV found. */
<>	154:37f96f9d4de2	1004	*prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
<>	154:37f96f9d4de2	1005	*vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE;
<>	154:37f96f9d4de2	1006	ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
<>	154:37f96f9d4de2	1007	return ret_freq / 2U;
<>	154:37f96f9d4de2	1008	}
<>	154:37f96f9d4de2	1009	else
<>	154:37f96f9d4de2	1010	{
<>	154:37f96f9d4de2	1011	/* No proper PRDIV/VDIV found. */
<>	154:37f96f9d4de2	1012	return 0U;
<>	154:37f96f9d4de2	1013	}
<>	154:37f96f9d4de2	1014	}
<>	154:37f96f9d4de2	1015
<>	154:37f96f9d4de2	1016	void CLOCK_EnablePll0(mcg_pll_config_t const *config)
<>	154:37f96f9d4de2	1017	{
<>	154:37f96f9d4de2	1018	assert(config);
<>	154:37f96f9d4de2	1019
<>	154:37f96f9d4de2	1020	uint8_t mcg_c5 = 0U;
<>	154:37f96f9d4de2	1021
<>	154:37f96f9d4de2	1022	mcg_c5 \|= MCG_C5_PRDIV0(config->prdiv);
<>	154:37f96f9d4de2	1023	MCG->C5 = mcg_c5; /* Disable the PLL first. */
<>	154:37f96f9d4de2	1024
<>	154:37f96f9d4de2	1025	MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) \| MCG_C6_VDIV0(config->vdiv);
<>	154:37f96f9d4de2	1026
<>	154:37f96f9d4de2	1027	/* Set enable mode. */
<>	154:37f96f9d4de2	1028	MCG->C5 \|= ((uint32_t)kMCG_PllEnableIndependent \| (uint32_t)config->enableMode);
<>	154:37f96f9d4de2	1029
<>	154:37f96f9d4de2	1030	/* Wait for PLL lock. */
<>	154:37f96f9d4de2	1031	while (!(MCG->S & MCG_S_LOCK0_MASK))
<>	154:37f96f9d4de2	1032	{
<>	154:37f96f9d4de2	1033	}
<>	154:37f96f9d4de2	1034	}
<>	154:37f96f9d4de2	1035
AnnaBridge	175:af195413fb11	1036	void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs)
AnnaBridge	175:af195413fb11	1037	{
AnnaBridge	175:af195413fb11	1038	MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) \| MCG_C11_PLLCS(pllcs);
AnnaBridge	175:af195413fb11	1039	while (pllcs != MCG_S2_PLLCST_VAL)
AnnaBridge	175:af195413fb11	1040	{
AnnaBridge	175:af195413fb11	1041	}
AnnaBridge	175:af195413fb11	1042	}
AnnaBridge	175:af195413fb11	1043
<>	154:37f96f9d4de2	1044	void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
<>	154:37f96f9d4de2	1045	{
<>	154:37f96f9d4de2	1046	/* Clear the previous flag, MCG_SC[LOCS0]. */
<>	154:37f96f9d4de2	1047	MCG->SC &= ~MCG_SC_ATMF_MASK;
<>	154:37f96f9d4de2	1048
<>	154:37f96f9d4de2	1049	if (kMCG_MonitorNone == mode)
<>	154:37f96f9d4de2	1050	{
<>	154:37f96f9d4de2	1051	MCG->C6 &= ~MCG_C6_CME0_MASK;
<>	154:37f96f9d4de2	1052	}
<>	154:37f96f9d4de2	1053	else
<>	154:37f96f9d4de2	1054	{
<>	154:37f96f9d4de2	1055	if (kMCG_MonitorInt == mode)
<>	154:37f96f9d4de2	1056	{
<>	154:37f96f9d4de2	1057	MCG->C2 &= ~MCG_C2_LOCRE0_MASK;
<>	154:37f96f9d4de2	1058	}
<>	154:37f96f9d4de2	1059	else
<>	154:37f96f9d4de2	1060	{
<>	154:37f96f9d4de2	1061	MCG->C2 \|= MCG_C2_LOCRE0_MASK;
<>	154:37f96f9d4de2	1062	}
<>	154:37f96f9d4de2	1063	MCG->C6 \|= MCG_C6_CME0_MASK;
<>	154:37f96f9d4de2	1064	}
<>	154:37f96f9d4de2	1065	}
<>	154:37f96f9d4de2	1066
<>	154:37f96f9d4de2	1067	void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
<>	154:37f96f9d4de2	1068	{
<>	154:37f96f9d4de2	1069	uint8_t mcg_c8 = MCG->C8;
<>	154:37f96f9d4de2	1070
<>	154:37f96f9d4de2	1071	mcg_c8 &= ~(MCG_C8_CME1_MASK \| MCG_C8_LOCRE1_MASK);
<>	154:37f96f9d4de2	1072
<>	154:37f96f9d4de2	1073	if (kMCG_MonitorNone != mode)
<>	154:37f96f9d4de2	1074	{
<>	154:37f96f9d4de2	1075	if (kMCG_MonitorReset == mode)
<>	154:37f96f9d4de2	1076	{
<>	154:37f96f9d4de2	1077	mcg_c8 \|= MCG_C8_LOCRE1_MASK;
<>	154:37f96f9d4de2	1078	}
<>	154:37f96f9d4de2	1079	mcg_c8 \|= MCG_C8_CME1_MASK;
<>	154:37f96f9d4de2	1080	}
<>	154:37f96f9d4de2	1081	MCG->C8 = mcg_c8;
<>	154:37f96f9d4de2	1082	}
<>	154:37f96f9d4de2	1083
<>	154:37f96f9d4de2	1084	void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
<>	154:37f96f9d4de2	1085	{
<>	154:37f96f9d4de2	1086	uint8_t mcg_c8;
<>	154:37f96f9d4de2	1087
<>	154:37f96f9d4de2	1088	/* Clear previous flag. */
<>	154:37f96f9d4de2	1089	MCG->S = MCG_S_LOLS0_MASK;
<>	154:37f96f9d4de2	1090
<>	154:37f96f9d4de2	1091	if (kMCG_MonitorNone == mode)
<>	154:37f96f9d4de2	1092	{
<>	154:37f96f9d4de2	1093	MCG->C6 &= ~MCG_C6_LOLIE0_MASK;
<>	154:37f96f9d4de2	1094	}
<>	154:37f96f9d4de2	1095	else
<>	154:37f96f9d4de2	1096	{
<>	154:37f96f9d4de2	1097	mcg_c8 = MCG->C8;
<>	154:37f96f9d4de2	1098
<>	154:37f96f9d4de2	1099	mcg_c8 &= ~MCG_C8_LOCS1_MASK;
<>	154:37f96f9d4de2	1100
<>	154:37f96f9d4de2	1101	if (kMCG_MonitorInt == mode)
<>	154:37f96f9d4de2	1102	{
<>	154:37f96f9d4de2	1103	mcg_c8 &= ~MCG_C8_LOLRE_MASK;
<>	154:37f96f9d4de2	1104	}
<>	154:37f96f9d4de2	1105	else
<>	154:37f96f9d4de2	1106	{
<>	154:37f96f9d4de2	1107	mcg_c8 \|= MCG_C8_LOLRE_MASK;
<>	154:37f96f9d4de2	1108	}
<>	154:37f96f9d4de2	1109	MCG->C8 = mcg_c8;
<>	154:37f96f9d4de2	1110	MCG->C6 \|= MCG_C6_LOLIE0_MASK;
<>	154:37f96f9d4de2	1111	}
<>	154:37f96f9d4de2	1112	}
<>	154:37f96f9d4de2	1113
<>	154:37f96f9d4de2	1114	void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode)
<>	154:37f96f9d4de2	1115	{
<>	154:37f96f9d4de2	1116	uint8_t mcg_c9 = MCG->C9;
<>	154:37f96f9d4de2	1117
<>	154:37f96f9d4de2	1118	mcg_c9 &= ~(MCG_C9_PLL_LOCRE_MASK \| MCG_C9_PLL_CME_MASK);
<>	154:37f96f9d4de2	1119
<>	154:37f96f9d4de2	1120	if (kMCG_MonitorNone != mode)
<>	154:37f96f9d4de2	1121	{
<>	154:37f96f9d4de2	1122	if (kMCG_MonitorReset == mode)
<>	154:37f96f9d4de2	1123	{
<>	154:37f96f9d4de2	1124	mcg_c9 \|= MCG_C9_PLL_LOCRE_MASK;
<>	154:37f96f9d4de2	1125	}
<>	154:37f96f9d4de2	1126	mcg_c9 \|= MCG_C9_PLL_CME_MASK;
<>	154:37f96f9d4de2	1127	}
<>	154:37f96f9d4de2	1128	MCG->C9 = mcg_c9;
<>	154:37f96f9d4de2	1129	}
<>	154:37f96f9d4de2	1130
<>	154:37f96f9d4de2	1131	uint32_t CLOCK_GetStatusFlags(void)
<>	154:37f96f9d4de2	1132	{
<>	154:37f96f9d4de2	1133	uint32_t ret = 0U;
<>	154:37f96f9d4de2	1134	uint8_t mcg_s = MCG->S;
<>	154:37f96f9d4de2	1135
<>	154:37f96f9d4de2	1136	if (MCG->SC & MCG_SC_LOCS0_MASK)
<>	154:37f96f9d4de2	1137	{
<>	154:37f96f9d4de2	1138	ret \|= kMCG_Osc0LostFlag;
<>	154:37f96f9d4de2	1139	}
<>	154:37f96f9d4de2	1140	if (mcg_s & MCG_S_OSCINIT0_MASK)
<>	154:37f96f9d4de2	1141	{
<>	154:37f96f9d4de2	1142	ret \|= kMCG_Osc0InitFlag;
<>	154:37f96f9d4de2	1143	}
<>	154:37f96f9d4de2	1144	if (MCG->C8 & MCG_C8_LOCS1_MASK)
<>	154:37f96f9d4de2	1145	{
<>	154:37f96f9d4de2	1146	ret \|= kMCG_RtcOscLostFlag;
<>	154:37f96f9d4de2	1147	}
<>	154:37f96f9d4de2	1148	if (mcg_s & MCG_S_LOLS0_MASK)
<>	154:37f96f9d4de2	1149	{
<>	154:37f96f9d4de2	1150	ret \|= kMCG_Pll0LostFlag;
<>	154:37f96f9d4de2	1151	}
<>	154:37f96f9d4de2	1152	if (mcg_s & MCG_S_LOCK0_MASK)
<>	154:37f96f9d4de2	1153	{
<>	154:37f96f9d4de2	1154	ret \|= kMCG_Pll0LockFlag;
<>	154:37f96f9d4de2	1155	}
<>	154:37f96f9d4de2	1156	if (MCG->C9 & MCG_C9_EXT_PLL_LOCS_MASK)
<>	154:37f96f9d4de2	1157	{
<>	154:37f96f9d4de2	1158	ret \|= kMCG_ExtPllLostFlag;
<>	154:37f96f9d4de2	1159	}
<>	154:37f96f9d4de2	1160	return ret;
<>	154:37f96f9d4de2	1161	}
<>	154:37f96f9d4de2	1162
<>	154:37f96f9d4de2	1163	void CLOCK_ClearStatusFlags(uint32_t mask)
<>	154:37f96f9d4de2	1164	{
<>	154:37f96f9d4de2	1165	uint8_t reg;
<>	154:37f96f9d4de2	1166
<>	154:37f96f9d4de2	1167	if (mask & kMCG_Osc0LostFlag)
<>	154:37f96f9d4de2	1168	{
<>	154:37f96f9d4de2	1169	MCG->SC &= ~MCG_SC_ATMF_MASK;
<>	154:37f96f9d4de2	1170	}
<>	154:37f96f9d4de2	1171	if (mask & kMCG_RtcOscLostFlag)
<>	154:37f96f9d4de2	1172	{
<>	154:37f96f9d4de2	1173	reg = MCG->C8;
<>	154:37f96f9d4de2	1174	MCG->C8 = reg;
<>	154:37f96f9d4de2	1175	}
<>	154:37f96f9d4de2	1176	if (mask & kMCG_Pll0LostFlag)
<>	154:37f96f9d4de2	1177	{
<>	154:37f96f9d4de2	1178	MCG->S = MCG_S_LOLS0_MASK;
<>	154:37f96f9d4de2	1179	}
<>	154:37f96f9d4de2	1180	if (mask & kMCG_ExtPllLostFlag)
<>	154:37f96f9d4de2	1181	{
<>	154:37f96f9d4de2	1182	reg = MCG->C9;
<>	154:37f96f9d4de2	1183	MCG->C9 = reg;
<>	154:37f96f9d4de2	1184	}
<>	154:37f96f9d4de2	1185	}
<>	154:37f96f9d4de2	1186
<>	154:37f96f9d4de2	1187	void CLOCK_InitOsc0(osc_config_t const *config)
<>	154:37f96f9d4de2	1188	{
<>	154:37f96f9d4de2	1189	uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
<>	154:37f96f9d4de2	1190
<>	154:37f96f9d4de2	1191	OSC_SetCapLoad(OSC0, config->capLoad);
<>	154:37f96f9d4de2	1192	OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
<>	154:37f96f9d4de2	1193
<>	154:37f96f9d4de2	1194	MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) \| MCG_C2_RANGE(range) \| (uint8_t)config->workMode);
<>	154:37f96f9d4de2	1195
<>	154:37f96f9d4de2	1196	if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK))
<>	154:37f96f9d4de2	1197	{
<>	154:37f96f9d4de2	1198	/* Wait for stable. */
<>	154:37f96f9d4de2	1199	while (!(MCG->S & MCG_S_OSCINIT0_MASK))
<>	154:37f96f9d4de2	1200	{
<>	154:37f96f9d4de2	1201	}
<>	154:37f96f9d4de2	1202	}
<>	154:37f96f9d4de2	1203	}
<>	154:37f96f9d4de2	1204
<>	154:37f96f9d4de2	1205	void CLOCK_DeinitOsc0(void)
<>	154:37f96f9d4de2	1206	{
<>	154:37f96f9d4de2	1207	OSC0->CR = 0U;
<>	154:37f96f9d4de2	1208	MCG->C2 &= ~OSC_MODE_MASK;
<>	154:37f96f9d4de2	1209	}
<>	154:37f96f9d4de2	1210
<>	154:37f96f9d4de2	1211	status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
<>	154:37f96f9d4de2	1212	{
<>	154:37f96f9d4de2	1213	uint32_t multi; /* extFreq / desireFreq */
<>	154:37f96f9d4de2	1214	uint32_t actv; /* Auto trim value. */
<>	154:37f96f9d4de2	1215	uint8_t mcg_sc;
<>	154:37f96f9d4de2	1216
<>	154:37f96f9d4de2	1217	static const uint32_t trimRange[2][2] = {
<>	154:37f96f9d4de2	1218	/* Min Max */
<>	154:37f96f9d4de2	1219	{TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */
<>	154:37f96f9d4de2	1220	{TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */
<>	154:37f96f9d4de2	1221	};
<>	154:37f96f9d4de2	1222
<>	154:37f96f9d4de2	1223	if ((extFreq > TRIM_REF_CLK_MAX) \|\| (extFreq < TRIM_REF_CLK_MIN))
<>	154:37f96f9d4de2	1224	{
<>	154:37f96f9d4de2	1225	return kStatus_MCG_AtmBusClockInvalid;
<>	154:37f96f9d4de2	1226	}
<>	154:37f96f9d4de2	1227
<>	154:37f96f9d4de2	1228	/* Check desired frequency range. */
<>	154:37f96f9d4de2	1229	if ((desireFreq < trimRange[atms][0]) \|\| (desireFreq > trimRange[atms][1]))
<>	154:37f96f9d4de2	1230	{
<>	154:37f96f9d4de2	1231	return kStatus_MCG_AtmDesiredFreqInvalid;
<>	154:37f96f9d4de2	1232	}
<>	154:37f96f9d4de2	1233
<>	154:37f96f9d4de2	1234	/*
<>	154:37f96f9d4de2	1235	Make sure internal reference clock is not used to generate bus clock.
<>	154:37f96f9d4de2	1236	Here only need to check (MCG_S_IREFST == 1).
<>	154:37f96f9d4de2	1237	*/
<>	154:37f96f9d4de2	1238	if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
<>	154:37f96f9d4de2	1239	{
<>	154:37f96f9d4de2	1240	return kStatus_MCG_AtmIrcUsed;
<>	154:37f96f9d4de2	1241	}
<>	154:37f96f9d4de2	1242
<>	154:37f96f9d4de2	1243	multi = extFreq / desireFreq;
<>	154:37f96f9d4de2	1244	actv = multi * 21U;
<>	154:37f96f9d4de2	1245
<>	154:37f96f9d4de2	1246	if (kMCG_AtmSel4m == atms)
<>	154:37f96f9d4de2	1247	{
<>	154:37f96f9d4de2	1248	actv *= 128U;
<>	154:37f96f9d4de2	1249	}
<>	154:37f96f9d4de2	1250
<>	154:37f96f9d4de2	1251	/* Now begin to start trim. */
<>	154:37f96f9d4de2	1252	MCG->ATCVL = (uint8_t)actv;
<>	154:37f96f9d4de2	1253	MCG->ATCVH = (uint8_t)(actv >> 8U);
<>	154:37f96f9d4de2	1254
<>	154:37f96f9d4de2	1255	mcg_sc = MCG->SC;
<>	154:37f96f9d4de2	1256	mcg_sc &= ~(MCG_SC_ATMS_MASK \| MCG_SC_LOCS0_MASK);
<>	154:37f96f9d4de2	1257	mcg_sc \|= (MCG_SC_ATMF_MASK \| MCG_SC_ATMS(atms));
<>	154:37f96f9d4de2	1258	MCG->SC = (mcg_sc \| MCG_SC_ATME_MASK);
<>	154:37f96f9d4de2	1259
<>	154:37f96f9d4de2	1260	/* Wait for finished. */
<>	154:37f96f9d4de2	1261	while (MCG->SC & MCG_SC_ATME_MASK)
<>	154:37f96f9d4de2	1262	{
<>	154:37f96f9d4de2	1263	}
<>	154:37f96f9d4de2	1264
<>	154:37f96f9d4de2	1265	/* Error occurs? */
<>	154:37f96f9d4de2	1266	if (MCG->SC & MCG_SC_ATMF_MASK)
<>	154:37f96f9d4de2	1267	{
<>	154:37f96f9d4de2	1268	/* Clear the failed flag. */
<>	154:37f96f9d4de2	1269	MCG->SC = mcg_sc;
<>	154:37f96f9d4de2	1270	return kStatus_MCG_AtmHardwareFail;
<>	154:37f96f9d4de2	1271	}
<>	154:37f96f9d4de2	1272
<>	154:37f96f9d4de2	1273	*actualFreq = extFreq / multi;
<>	154:37f96f9d4de2	1274
<>	154:37f96f9d4de2	1275	if (kMCG_AtmSel4m == atms)
<>	154:37f96f9d4de2	1276	{
<>	154:37f96f9d4de2	1277	s_fastIrcFreq = *actualFreq;
<>	154:37f96f9d4de2	1278	}
<>	154:37f96f9d4de2	1279	else
<>	154:37f96f9d4de2	1280	{
<>	154:37f96f9d4de2	1281	s_slowIrcFreq = *actualFreq;
<>	154:37f96f9d4de2	1282	}
<>	154:37f96f9d4de2	1283
<>	154:37f96f9d4de2	1284	return kStatus_Success;
<>	154:37f96f9d4de2	1285	}
<>	154:37f96f9d4de2	1286
<>	154:37f96f9d4de2	1287	mcg_mode_t CLOCK_GetMode(void)
<>	154:37f96f9d4de2	1288	{
<>	154:37f96f9d4de2	1289	mcg_mode_t mode = kMCG_ModeError;
<>	154:37f96f9d4de2	1290	uint32_t clkst = MCG_S_CLKST_VAL;
<>	154:37f96f9d4de2	1291	uint32_t irefst = MCG_S_IREFST_VAL;
<>	154:37f96f9d4de2	1292	uint32_t lp = MCG_C2_LP_VAL;
<>	154:37f96f9d4de2	1293	uint32_t pllst = MCG_S_PLLST_VAL;
<>	154:37f96f9d4de2	1294
<>	154:37f96f9d4de2	1295	/*------------------------------------------------------------------
<>	154:37f96f9d4de2	1296	Mode and Registers
<>	154:37f96f9d4de2	1297	____________________________________________________________________
<>	154:37f96f9d4de2	1298
<>	154:37f96f9d4de2	1299	Mode \| CLKST \| IREFST \| PLLST \| LP
<>	154:37f96f9d4de2	1300	____________________________________________________________________
<>	154:37f96f9d4de2	1301
<>	154:37f96f9d4de2	1302	FEI \| 00(FLL) \| 1(INT) \| 0(FLL) \| X
<>	154:37f96f9d4de2	1303	____________________________________________________________________
<>	154:37f96f9d4de2	1304
<>	154:37f96f9d4de2	1305	FEE \| 00(FLL) \| 0(EXT) \| 0(FLL) \| X
<>	154:37f96f9d4de2	1306	____________________________________________________________________
<>	154:37f96f9d4de2	1307
<>	154:37f96f9d4de2	1308	FBE \| 10(EXT) \| 0(EXT) \| 0(FLL) \| 0(NORMAL)
<>	154:37f96f9d4de2	1309	____________________________________________________________________
<>	154:37f96f9d4de2	1310
<>	154:37f96f9d4de2	1311	FBI \| 01(INT) \| 1(INT) \| 0(FLL) \| 0(NORMAL)
<>	154:37f96f9d4de2	1312	____________________________________________________________________
<>	154:37f96f9d4de2	1313
<>	154:37f96f9d4de2	1314	BLPI \| 01(INT) \| 1(INT) \| 0(FLL) \| 1(LOW POWER)
<>	154:37f96f9d4de2	1315	____________________________________________________________________
<>	154:37f96f9d4de2	1316
<>	154:37f96f9d4de2	1317	BLPE \| 10(EXT) \| 0(EXT) \| X \| 1(LOW POWER)
<>	154:37f96f9d4de2	1318	____________________________________________________________________
<>	154:37f96f9d4de2	1319
<>	154:37f96f9d4de2	1320	PEE \| 11(PLL) \| 0(EXT) \| 1(PLL) \| X
<>	154:37f96f9d4de2	1321	____________________________________________________________________
<>	154:37f96f9d4de2	1322
<>	154:37f96f9d4de2	1323	PBE \| 10(EXT) \| 0(EXT) \| 1(PLL) \| O(NORMAL)
<>	154:37f96f9d4de2	1324	____________________________________________________________________
<>	154:37f96f9d4de2	1325
<>	154:37f96f9d4de2	1326	PBI \| 01(INT) \| 1(INT) \| 1(PLL) \| 0(NORMAL)
<>	154:37f96f9d4de2	1327	____________________________________________________________________
<>	154:37f96f9d4de2	1328
<>	154:37f96f9d4de2	1329	PEI \| 11(PLL) \| 1(INT) \| 1(PLL) \| X
<>	154:37f96f9d4de2	1330	____________________________________________________________________
<>	154:37f96f9d4de2	1331
<>	154:37f96f9d4de2	1332	----------------------------------------------------------------------*/
<>	154:37f96f9d4de2	1333
<>	154:37f96f9d4de2	1334	switch (clkst)
<>	154:37f96f9d4de2	1335	{
<>	154:37f96f9d4de2	1336	case kMCG_ClkOutStatFll:
<>	154:37f96f9d4de2	1337	if (kMCG_FllSrcExternal == irefst)
<>	154:37f96f9d4de2	1338	{
<>	154:37f96f9d4de2	1339	mode = kMCG_ModeFEE;
<>	154:37f96f9d4de2	1340	}
<>	154:37f96f9d4de2	1341	else
<>	154:37f96f9d4de2	1342	{
<>	154:37f96f9d4de2	1343	mode = kMCG_ModeFEI;
<>	154:37f96f9d4de2	1344	}
<>	154:37f96f9d4de2	1345	break;
<>	154:37f96f9d4de2	1346	case kMCG_ClkOutStatInt:
<>	154:37f96f9d4de2	1347	if (lp)
<>	154:37f96f9d4de2	1348	{
<>	154:37f96f9d4de2	1349	mode = kMCG_ModeBLPI;
<>	154:37f96f9d4de2	1350	}
<>	154:37f96f9d4de2	1351	else
<>	154:37f96f9d4de2	1352	{
<>	154:37f96f9d4de2	1353	{
<>	154:37f96f9d4de2	1354	mode = kMCG_ModeFBI;
<>	154:37f96f9d4de2	1355	}
<>	154:37f96f9d4de2	1356	}
<>	154:37f96f9d4de2	1357	break;
<>	154:37f96f9d4de2	1358	case kMCG_ClkOutStatExt:
<>	154:37f96f9d4de2	1359	if (lp)
<>	154:37f96f9d4de2	1360	{
<>	154:37f96f9d4de2	1361	mode = kMCG_ModeBLPE;
<>	154:37f96f9d4de2	1362	}
<>	154:37f96f9d4de2	1363	else
<>	154:37f96f9d4de2	1364	{
<>	154:37f96f9d4de2	1365	if (kMCG_PllstPll == pllst)
<>	154:37f96f9d4de2	1366	{
<>	154:37f96f9d4de2	1367	mode = kMCG_ModePBE;
<>	154:37f96f9d4de2	1368	}
<>	154:37f96f9d4de2	1369	else
<>	154:37f96f9d4de2	1370	{
<>	154:37f96f9d4de2	1371	mode = kMCG_ModeFBE;
<>	154:37f96f9d4de2	1372	}
<>	154:37f96f9d4de2	1373	}
<>	154:37f96f9d4de2	1374	break;
<>	154:37f96f9d4de2	1375	case kMCG_ClkOutStatPll:
<>	154:37f96f9d4de2	1376	{
<>	154:37f96f9d4de2	1377	mode = kMCG_ModePEE;
<>	154:37f96f9d4de2	1378	}
<>	154:37f96f9d4de2	1379	break;
<>	154:37f96f9d4de2	1380	default:
<>	154:37f96f9d4de2	1381	break;
<>	154:37f96f9d4de2	1382	}
<>	154:37f96f9d4de2	1383
<>	154:37f96f9d4de2	1384	return mode;
<>	154:37f96f9d4de2	1385	}
<>	154:37f96f9d4de2	1386
AnnaBridge	175:af195413fb11	1387	status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
<>	154:37f96f9d4de2	1388	{
<>	154:37f96f9d4de2	1389	uint8_t mcg_c4;
<>	154:37f96f9d4de2	1390	bool change_drs = false;
<>	154:37f96f9d4de2	1391
<>	154:37f96f9d4de2	1392	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1393	mcg_mode_t mode = CLOCK_GetMode();
<>	154:37f96f9d4de2	1394	if (!((kMCG_ModeFEI == mode) \|\| (kMCG_ModeFBI == mode) \|\| (kMCG_ModeFBE == mode) \|\| (kMCG_ModeFEE == mode)))
<>	154:37f96f9d4de2	1395	{
<>	154:37f96f9d4de2	1396	return kStatus_MCG_ModeUnreachable;
<>	154:37f96f9d4de2	1397	}
<>	154:37f96f9d4de2	1398	#endif
<>	154:37f96f9d4de2	1399	mcg_c4 = MCG->C4;
<>	154:37f96f9d4de2	1400
<>	154:37f96f9d4de2	1401	/*
<>	154:37f96f9d4de2	1402	Errata: ERR007993
<>	154:37f96f9d4de2	1403	Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
<>	154:37f96f9d4de2	1404	reference clock source changes, then reset to previous value after
<>	154:37f96f9d4de2	1405	reference clock changes.
<>	154:37f96f9d4de2	1406	*/
<>	154:37f96f9d4de2	1407	if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1408	{
<>	154:37f96f9d4de2	1409	change_drs = true;
<>	154:37f96f9d4de2	1410	/* Change the LSB of DRST_DRS. */
<>	154:37f96f9d4de2	1411	MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
<>	154:37f96f9d4de2	1412	}
<>	154:37f96f9d4de2	1413
<>	154:37f96f9d4de2	1414	/* Set CLKS and IREFS. */
<>	154:37f96f9d4de2	1415	MCG->C1 =
<>	154:37f96f9d4de2	1416	((MCG->C1 & ~(MCG_C1_CLKS_MASK \| MCG_C1_IREFS_MASK))) \| (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
<>	154:37f96f9d4de2	1417	\| MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */
<>	154:37f96f9d4de2	1418
<>	154:37f96f9d4de2	1419	/* Wait and check status. */
<>	154:37f96f9d4de2	1420	while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1421	{
<>	154:37f96f9d4de2	1422	}
<>	154:37f96f9d4de2	1423
<>	154:37f96f9d4de2	1424	/* Errata: ERR007993 */
<>	154:37f96f9d4de2	1425	if (change_drs)
<>	154:37f96f9d4de2	1426	{
<>	154:37f96f9d4de2	1427	MCG->C4 = mcg_c4;
<>	154:37f96f9d4de2	1428	}
<>	154:37f96f9d4de2	1429
<>	154:37f96f9d4de2	1430	/* In FEI mode, the MCG_C4[DMX32] is set to 0U. */
AnnaBridge	175:af195413fb11	1431	MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK \| MCG_C4_DRST_DRS_MASK)) \| (MCG_C4_DMX32(dmx32) \| MCG_C4_DRST_DRS(drs));
<>	154:37f96f9d4de2	1432
<>	154:37f96f9d4de2	1433	/* Check MCG_S[CLKST] */
<>	154:37f96f9d4de2	1434	while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
<>	154:37f96f9d4de2	1435	{
<>	154:37f96f9d4de2	1436	}
<>	154:37f96f9d4de2	1437
<>	154:37f96f9d4de2	1438	/* Wait for FLL stable time. */
<>	154:37f96f9d4de2	1439	if (fllStableDelay)
<>	154:37f96f9d4de2	1440	{
<>	154:37f96f9d4de2	1441	fllStableDelay();
<>	154:37f96f9d4de2	1442	}
<>	154:37f96f9d4de2	1443
<>	154:37f96f9d4de2	1444	return kStatus_Success;
<>	154:37f96f9d4de2	1445	}
<>	154:37f96f9d4de2	1446
<>	154:37f96f9d4de2	1447	status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
<>	154:37f96f9d4de2	1448	{
<>	154:37f96f9d4de2	1449	uint8_t mcg_c4;
<>	154:37f96f9d4de2	1450	bool change_drs = false;
<>	154:37f96f9d4de2	1451
<>	154:37f96f9d4de2	1452	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1453	mcg_mode_t mode = CLOCK_GetMode();
<>	154:37f96f9d4de2	1454	if (!((kMCG_ModeFEE == mode) \|\| (kMCG_ModeFBI == mode) \|\| (kMCG_ModeFBE == mode) \|\| (kMCG_ModeFEI == mode)))
<>	154:37f96f9d4de2	1455	{
<>	154:37f96f9d4de2	1456	return kStatus_MCG_ModeUnreachable;
<>	154:37f96f9d4de2	1457	}
<>	154:37f96f9d4de2	1458	#endif
<>	154:37f96f9d4de2	1459	mcg_c4 = MCG->C4;
<>	154:37f96f9d4de2	1460
<>	154:37f96f9d4de2	1461	/*
<>	154:37f96f9d4de2	1462	Errata: ERR007993
<>	154:37f96f9d4de2	1463	Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
<>	154:37f96f9d4de2	1464	reference clock source changes, then reset to previous value after
<>	154:37f96f9d4de2	1465	reference clock changes.
<>	154:37f96f9d4de2	1466	*/
<>	154:37f96f9d4de2	1467	if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1468	{
<>	154:37f96f9d4de2	1469	change_drs = true;
<>	154:37f96f9d4de2	1470	/* Change the LSB of DRST_DRS. */
<>	154:37f96f9d4de2	1471	MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
<>	154:37f96f9d4de2	1472	}
<>	154:37f96f9d4de2	1473
<>	154:37f96f9d4de2	1474	/* Set CLKS and IREFS. */
<>	154:37f96f9d4de2	1475	MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK \| MCG_C1_FRDIV_MASK \| MCG_C1_IREFS_MASK)) \|
<>	154:37f96f9d4de2	1476	(MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
<>	154:37f96f9d4de2	1477	\| MCG_C1_FRDIV(frdiv) /* FRDIV */
<>	154:37f96f9d4de2	1478	\| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
<>	154:37f96f9d4de2	1479
AnnaBridge	175:af195413fb11	1480	/* If use external crystal as clock source, wait for it stable. */
AnnaBridge	175:af195413fb11	1481	if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
AnnaBridge	175:af195413fb11	1482	{
AnnaBridge	175:af195413fb11	1483	if (MCG->C2 & MCG_C2_EREFS_MASK)
AnnaBridge	175:af195413fb11	1484	{
AnnaBridge	175:af195413fb11	1485	while (!(MCG->S & MCG_S_OSCINIT0_MASK))
AnnaBridge	175:af195413fb11	1486	{
AnnaBridge	175:af195413fb11	1487	}
AnnaBridge	175:af195413fb11	1488	}
AnnaBridge	175:af195413fb11	1489	}
AnnaBridge	175:af195413fb11	1490
<>	154:37f96f9d4de2	1491	/* Wait and check status. */
<>	154:37f96f9d4de2	1492	while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1493	{
<>	154:37f96f9d4de2	1494	}
<>	154:37f96f9d4de2	1495
<>	154:37f96f9d4de2	1496	/* Errata: ERR007993 */
<>	154:37f96f9d4de2	1497	if (change_drs)
<>	154:37f96f9d4de2	1498	{
<>	154:37f96f9d4de2	1499	MCG->C4 = mcg_c4;
<>	154:37f96f9d4de2	1500	}
<>	154:37f96f9d4de2	1501
<>	154:37f96f9d4de2	1502	/* Set DRS and DMX32. */
<>	154:37f96f9d4de2	1503	mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK \| MCG_C4_DRST_DRS_MASK)) \| (MCG_C4_DMX32(dmx32) \| MCG_C4_DRST_DRS(drs)));
<>	154:37f96f9d4de2	1504	MCG->C4 = mcg_c4;
<>	154:37f96f9d4de2	1505
<>	154:37f96f9d4de2	1506	/* Wait for DRST_DRS update. */
<>	154:37f96f9d4de2	1507	while (MCG->C4 != mcg_c4)
<>	154:37f96f9d4de2	1508	{
<>	154:37f96f9d4de2	1509	}
<>	154:37f96f9d4de2	1510
<>	154:37f96f9d4de2	1511	/* Check MCG_S[CLKST] */
<>	154:37f96f9d4de2	1512	while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
<>	154:37f96f9d4de2	1513	{
<>	154:37f96f9d4de2	1514	}
<>	154:37f96f9d4de2	1515
<>	154:37f96f9d4de2	1516	/* Wait for FLL stable time. */
<>	154:37f96f9d4de2	1517	if (fllStableDelay)
<>	154:37f96f9d4de2	1518	{
<>	154:37f96f9d4de2	1519	fllStableDelay();
<>	154:37f96f9d4de2	1520	}
<>	154:37f96f9d4de2	1521
<>	154:37f96f9d4de2	1522	return kStatus_Success;
<>	154:37f96f9d4de2	1523	}
<>	154:37f96f9d4de2	1524
AnnaBridge	175:af195413fb11	1525	status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
<>	154:37f96f9d4de2	1526	{
<>	154:37f96f9d4de2	1527	uint8_t mcg_c4;
<>	154:37f96f9d4de2	1528	bool change_drs = false;
<>	154:37f96f9d4de2	1529
<>	154:37f96f9d4de2	1530	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1531	mcg_mode_t mode = CLOCK_GetMode();
<>	154:37f96f9d4de2	1532
<>	154:37f96f9d4de2	1533	if (!((kMCG_ModeFEE == mode) \|\| (kMCG_ModeFBI == mode) \|\| (kMCG_ModeFBE == mode) \|\| (kMCG_ModeFEI == mode) \|\|
<>	154:37f96f9d4de2	1534	(kMCG_ModeBLPI == mode)))
<>	154:37f96f9d4de2	1535
<>	154:37f96f9d4de2	1536	{
<>	154:37f96f9d4de2	1537	return kStatus_MCG_ModeUnreachable;
<>	154:37f96f9d4de2	1538	}
<>	154:37f96f9d4de2	1539	#endif
<>	154:37f96f9d4de2	1540
<>	154:37f96f9d4de2	1541	mcg_c4 = MCG->C4;
<>	154:37f96f9d4de2	1542
<>	154:37f96f9d4de2	1543	MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
<>	154:37f96f9d4de2	1544
<>	154:37f96f9d4de2	1545	/*
<>	154:37f96f9d4de2	1546	Errata: ERR007993
<>	154:37f96f9d4de2	1547	Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
<>	154:37f96f9d4de2	1548	reference clock source changes, then reset to previous value after
<>	154:37f96f9d4de2	1549	reference clock changes.
<>	154:37f96f9d4de2	1550	*/
<>	154:37f96f9d4de2	1551	if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1552	{
<>	154:37f96f9d4de2	1553	change_drs = true;
<>	154:37f96f9d4de2	1554	/* Change the LSB of DRST_DRS. */
<>	154:37f96f9d4de2	1555	MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
<>	154:37f96f9d4de2	1556	}
<>	154:37f96f9d4de2	1557
<>	154:37f96f9d4de2	1558	/* Set CLKS and IREFS. */
<>	154:37f96f9d4de2	1559	MCG->C1 =
<>	154:37f96f9d4de2	1560	((MCG->C1 & ~(MCG_C1_CLKS_MASK \| MCG_C1_IREFS_MASK)) \| (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
<>	154:37f96f9d4de2	1561	\| MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
<>	154:37f96f9d4de2	1562
<>	154:37f96f9d4de2	1563	/* Wait and check status. */
<>	154:37f96f9d4de2	1564	while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1565	{
<>	154:37f96f9d4de2	1566	}
<>	154:37f96f9d4de2	1567
<>	154:37f96f9d4de2	1568	/* Errata: ERR007993 */
<>	154:37f96f9d4de2	1569	if (change_drs)
<>	154:37f96f9d4de2	1570	{
<>	154:37f96f9d4de2	1571	MCG->C4 = mcg_c4;
<>	154:37f96f9d4de2	1572	}
<>	154:37f96f9d4de2	1573
<>	154:37f96f9d4de2	1574	while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
<>	154:37f96f9d4de2	1575	{
<>	154:37f96f9d4de2	1576	}
<>	154:37f96f9d4de2	1577
AnnaBridge	175:af195413fb11	1578	MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK \| MCG_C4_DRST_DRS_MASK)) \| (MCG_C4_DMX32(dmx32) \| MCG_C4_DRST_DRS(drs));
<>	154:37f96f9d4de2	1579
<>	154:37f96f9d4de2	1580	/* Wait for FLL stable time. */
<>	154:37f96f9d4de2	1581	if (fllStableDelay)
<>	154:37f96f9d4de2	1582	{
<>	154:37f96f9d4de2	1583	fllStableDelay();
<>	154:37f96f9d4de2	1584	}
<>	154:37f96f9d4de2	1585
<>	154:37f96f9d4de2	1586	return kStatus_Success;
<>	154:37f96f9d4de2	1587	}
<>	154:37f96f9d4de2	1588
<>	154:37f96f9d4de2	1589	status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
<>	154:37f96f9d4de2	1590	{
<>	154:37f96f9d4de2	1591	uint8_t mcg_c4;
<>	154:37f96f9d4de2	1592	bool change_drs = false;
<>	154:37f96f9d4de2	1593
<>	154:37f96f9d4de2	1594	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1595	mcg_mode_t mode = CLOCK_GetMode();
<>	154:37f96f9d4de2	1596	if (!((kMCG_ModeFEE == mode) \|\| (kMCG_ModeFBI == mode) \|\| (kMCG_ModeFBE == mode) \|\| (kMCG_ModeFEI == mode) \|\|
<>	154:37f96f9d4de2	1597	(kMCG_ModePBE == mode) \|\| (kMCG_ModeBLPE == mode)))
<>	154:37f96f9d4de2	1598	{
<>	154:37f96f9d4de2	1599	return kStatus_MCG_ModeUnreachable;
<>	154:37f96f9d4de2	1600	}
<>	154:37f96f9d4de2	1601	#endif
<>	154:37f96f9d4de2	1602
<>	154:37f96f9d4de2	1603	/* Change to FLL mode. */
<>	154:37f96f9d4de2	1604	MCG->C6 &= ~MCG_C6_PLLS_MASK;
<>	154:37f96f9d4de2	1605	while (MCG->S & MCG_S_PLLST_MASK)
<>	154:37f96f9d4de2	1606	{
<>	154:37f96f9d4de2	1607	}
<>	154:37f96f9d4de2	1608
<>	154:37f96f9d4de2	1609	/* Set LP bit to enable the FLL */
<>	154:37f96f9d4de2	1610	MCG->C2 &= ~MCG_C2_LP_MASK;
<>	154:37f96f9d4de2	1611
<>	154:37f96f9d4de2	1612	mcg_c4 = MCG->C4;
<>	154:37f96f9d4de2	1613
<>	154:37f96f9d4de2	1614	/*
<>	154:37f96f9d4de2	1615	Errata: ERR007993
<>	154:37f96f9d4de2	1616	Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
<>	154:37f96f9d4de2	1617	reference clock source changes, then reset to previous value after
<>	154:37f96f9d4de2	1618	reference clock changes.
<>	154:37f96f9d4de2	1619	*/
<>	154:37f96f9d4de2	1620	if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1621	{
<>	154:37f96f9d4de2	1622	change_drs = true;
<>	154:37f96f9d4de2	1623	/* Change the LSB of DRST_DRS. */
<>	154:37f96f9d4de2	1624	MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
<>	154:37f96f9d4de2	1625	}
<>	154:37f96f9d4de2	1626
<>	154:37f96f9d4de2	1627	/* Set CLKS and IREFS. */
<>	154:37f96f9d4de2	1628	MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK \| MCG_C1_FRDIV_MASK \| MCG_C1_IREFS_MASK)) \|
<>	154:37f96f9d4de2	1629	(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
<>	154:37f96f9d4de2	1630	\| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
<>	154:37f96f9d4de2	1631	\| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
<>	154:37f96f9d4de2	1632
AnnaBridge	175:af195413fb11	1633	/* If use external crystal as clock source, wait for it stable. */
AnnaBridge	175:af195413fb11	1634	if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
AnnaBridge	175:af195413fb11	1635	{
AnnaBridge	175:af195413fb11	1636	if (MCG->C2 & MCG_C2_EREFS_MASK)
AnnaBridge	175:af195413fb11	1637	{
AnnaBridge	175:af195413fb11	1638	while (!(MCG->S & MCG_S_OSCINIT0_MASK))
AnnaBridge	175:af195413fb11	1639	{
AnnaBridge	175:af195413fb11	1640	}
AnnaBridge	175:af195413fb11	1641	}
AnnaBridge	175:af195413fb11	1642	}
AnnaBridge	175:af195413fb11	1643
<>	154:37f96f9d4de2	1644	/* Wait for Reference clock Status bit to clear */
<>	154:37f96f9d4de2	1645	while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
<>	154:37f96f9d4de2	1646	{
<>	154:37f96f9d4de2	1647	}
<>	154:37f96f9d4de2	1648
<>	154:37f96f9d4de2	1649	/* Errata: ERR007993 */
<>	154:37f96f9d4de2	1650	if (change_drs)
<>	154:37f96f9d4de2	1651	{
<>	154:37f96f9d4de2	1652	MCG->C4 = mcg_c4;
<>	154:37f96f9d4de2	1653	}
<>	154:37f96f9d4de2	1654
<>	154:37f96f9d4de2	1655	/* Set DRST_DRS and DMX32. */
<>	154:37f96f9d4de2	1656	mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK \| MCG_C4_DRST_DRS_MASK)) \| (MCG_C4_DMX32(dmx32) \| MCG_C4_DRST_DRS(drs)));
<>	154:37f96f9d4de2	1657
<>	154:37f96f9d4de2	1658	/* Wait for clock status bits to show clock source is ext ref clk */
<>	154:37f96f9d4de2	1659	while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
<>	154:37f96f9d4de2	1660	{
<>	154:37f96f9d4de2	1661	}
<>	154:37f96f9d4de2	1662
<>	154:37f96f9d4de2	1663	/* Wait for fll stable time. */
<>	154:37f96f9d4de2	1664	if (fllStableDelay)
<>	154:37f96f9d4de2	1665	{
<>	154:37f96f9d4de2	1666	fllStableDelay();
<>	154:37f96f9d4de2	1667	}
<>	154:37f96f9d4de2	1668
<>	154:37f96f9d4de2	1669	return kStatus_Success;
<>	154:37f96f9d4de2	1670	}
<>	154:37f96f9d4de2	1671
<>	154:37f96f9d4de2	1672	status_t CLOCK_SetBlpiMode(void)
<>	154:37f96f9d4de2	1673	{
<>	154:37f96f9d4de2	1674	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1675	if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
<>	154:37f96f9d4de2	1676	{
<>	154:37f96f9d4de2	1677	return kStatus_MCG_ModeUnreachable;
<>	154:37f96f9d4de2	1678	}
<>	154:37f96f9d4de2	1679	#endif /* MCG_CONFIG_CHECK_PARAM */
<>	154:37f96f9d4de2	1680
<>	154:37f96f9d4de2	1681	/* Set LP. */
<>	154:37f96f9d4de2	1682	MCG->C2 \|= MCG_C2_LP_MASK;
<>	154:37f96f9d4de2	1683
<>	154:37f96f9d4de2	1684	return kStatus_Success;
<>	154:37f96f9d4de2	1685	}
<>	154:37f96f9d4de2	1686
<>	154:37f96f9d4de2	1687	status_t CLOCK_SetBlpeMode(void)
<>	154:37f96f9d4de2	1688	{
<>	154:37f96f9d4de2	1689	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1690	if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
<>	154:37f96f9d4de2	1691	{
<>	154:37f96f9d4de2	1692	return kStatus_MCG_ModeUnreachable;
<>	154:37f96f9d4de2	1693	}
<>	154:37f96f9d4de2	1694	#endif
<>	154:37f96f9d4de2	1695
<>	154:37f96f9d4de2	1696	/* Set LP bit to enter BLPE mode. */
<>	154:37f96f9d4de2	1697	MCG->C2 \|= MCG_C2_LP_MASK;
<>	154:37f96f9d4de2	1698
<>	154:37f96f9d4de2	1699	return kStatus_Success;
<>	154:37f96f9d4de2	1700	}
<>	154:37f96f9d4de2	1701
<>	154:37f96f9d4de2	1702	status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
<>	154:37f96f9d4de2	1703	{
AnnaBridge	175:af195413fb11	1704	/* If external PLL is used, then the config could be NULL. */
AnnaBridge	175:af195413fb11	1705	if (kMCG_PllClkSelExtPll != pllcs)
AnnaBridge	175:af195413fb11	1706	{
AnnaBridge	175:af195413fb11	1707	assert(config);
AnnaBridge	175:af195413fb11	1708	}
AnnaBridge	175:af195413fb11	1709
<>	154:37f96f9d4de2	1710	/*
<>	154:37f96f9d4de2	1711	This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
<>	154:37f96f9d4de2	1712	but with this workflow, the source mode could be all modes except PEI/PBI.
<>	154:37f96f9d4de2	1713	*/
<>	154:37f96f9d4de2	1714	MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
<>	154:37f96f9d4de2	1715
<>	154:37f96f9d4de2	1716	/* Change to use external clock first. */
<>	154:37f96f9d4de2	1717	MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK \| MCG_C1_IREFS_MASK)) \| MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
<>	154:37f96f9d4de2	1718
<>	154:37f96f9d4de2	1719	/* Wait for CLKST clock status bits to show clock source is ext ref clk */
<>	154:37f96f9d4de2	1720	while ((MCG->S & (MCG_S_IREFST_MASK \| MCG_S_CLKST_MASK)) !=
<>	154:37f96f9d4de2	1721	(MCG_S_IREFST(kMCG_FllSrcExternal) \| MCG_S_CLKST(kMCG_ClkOutStatExt)))
<>	154:37f96f9d4de2	1722	{
<>	154:37f96f9d4de2	1723	}
<>	154:37f96f9d4de2	1724
<>	154:37f96f9d4de2	1725	/* Disable PLL first, then configure PLL. */
<>	154:37f96f9d4de2	1726	MCG->C6 &= ~MCG_C6_PLLS_MASK;
<>	154:37f96f9d4de2	1727	while (MCG->S & MCG_S_PLLST_MASK)
<>	154:37f96f9d4de2	1728	{
<>	154:37f96f9d4de2	1729	}
<>	154:37f96f9d4de2	1730
<>	154:37f96f9d4de2	1731	/* Configure the PLL. */
<>	154:37f96f9d4de2	1732	if (kMCG_PllClkSelPll0 == pllcs)
<>	154:37f96f9d4de2	1733	{
<>	154:37f96f9d4de2	1734	CLOCK_EnablePll0(config);
<>	154:37f96f9d4de2	1735	}
<>	154:37f96f9d4de2	1736
AnnaBridge	175:af195413fb11	1737	/* Change to PLL mode. */
AnnaBridge	175:af195413fb11	1738	MCG->C6 \|= MCG_C6_PLLS_MASK;
AnnaBridge	175:af195413fb11	1739
<>	154:37f96f9d4de2	1740	MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) \| MCG_C11_PLLCS(pllcs);
<>	154:37f96f9d4de2	1741	while (pllcs != MCG_S2_PLLCST_VAL)
<>	154:37f96f9d4de2	1742	{
<>	154:37f96f9d4de2	1743	}
<>	154:37f96f9d4de2	1744
AnnaBridge	175:af195413fb11	1745	/* Wait for PLL mode changed. */
<>	154:37f96f9d4de2	1746	while (!(MCG->S & MCG_S_PLLST_MASK))
<>	154:37f96f9d4de2	1747	{
<>	154:37f96f9d4de2	1748	}
<>	154:37f96f9d4de2	1749
<>	154:37f96f9d4de2	1750	return kStatus_Success;
<>	154:37f96f9d4de2	1751	}
<>	154:37f96f9d4de2	1752
<>	154:37f96f9d4de2	1753	status_t CLOCK_SetPeeMode(void)
<>	154:37f96f9d4de2	1754	{
<>	154:37f96f9d4de2	1755	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1756	mcg_mode_t mode = CLOCK_GetMode();
<>	154:37f96f9d4de2	1757	if (kMCG_ModePBE != mode)
<>	154:37f96f9d4de2	1758	{
<>	154:37f96f9d4de2	1759	return kStatus_MCG_ModeUnreachable;
<>	154:37f96f9d4de2	1760	}
<>	154:37f96f9d4de2	1761	#endif
<>	154:37f96f9d4de2	1762
<>	154:37f96f9d4de2	1763	/* Change to use PLL/FLL output clock first. */
<>	154:37f96f9d4de2	1764	MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) \| MCG_C1_CLKS(kMCG_ClkOutSrcOut);
<>	154:37f96f9d4de2	1765
<>	154:37f96f9d4de2	1766	/* Wait for clock status bits to update */
<>	154:37f96f9d4de2	1767	while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
<>	154:37f96f9d4de2	1768	{
<>	154:37f96f9d4de2	1769	}
<>	154:37f96f9d4de2	1770
<>	154:37f96f9d4de2	1771	return kStatus_Success;
<>	154:37f96f9d4de2	1772	}
<>	154:37f96f9d4de2	1773
<>	154:37f96f9d4de2	1774	status_t CLOCK_ExternalModeToFbeModeQuick(void)
<>	154:37f96f9d4de2	1775	{
<>	154:37f96f9d4de2	1776	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1777	if (MCG->S & MCG_S_IREFST_MASK)
<>	154:37f96f9d4de2	1778	{
<>	154:37f96f9d4de2	1779	return kStatus_MCG_ModeInvalid;
<>	154:37f96f9d4de2	1780	}
<>	154:37f96f9d4de2	1781	#endif /* MCG_CONFIG_CHECK_PARAM */
<>	154:37f96f9d4de2	1782
<>	154:37f96f9d4de2	1783	/* Disable low power */
<>	154:37f96f9d4de2	1784	MCG->C2 &= ~MCG_C2_LP_MASK;
<>	154:37f96f9d4de2	1785
<>	154:37f96f9d4de2	1786	MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) \| MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
<>	154:37f96f9d4de2	1787	while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
<>	154:37f96f9d4de2	1788	{
<>	154:37f96f9d4de2	1789	}
<>	154:37f96f9d4de2	1790
<>	154:37f96f9d4de2	1791	/* Disable PLL. */
<>	154:37f96f9d4de2	1792	MCG->C6 &= ~MCG_C6_PLLS_MASK;
<>	154:37f96f9d4de2	1793	while (MCG->S & MCG_S_PLLST_MASK)
<>	154:37f96f9d4de2	1794	{
<>	154:37f96f9d4de2	1795	}
<>	154:37f96f9d4de2	1796
<>	154:37f96f9d4de2	1797	return kStatus_Success;
<>	154:37f96f9d4de2	1798	}
<>	154:37f96f9d4de2	1799
<>	154:37f96f9d4de2	1800	status_t CLOCK_InternalModeToFbiModeQuick(void)
<>	154:37f96f9d4de2	1801	{
<>	154:37f96f9d4de2	1802	#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
<>	154:37f96f9d4de2	1803	if (!(MCG->S & MCG_S_IREFST_MASK))
<>	154:37f96f9d4de2	1804	{
<>	154:37f96f9d4de2	1805	return kStatus_MCG_ModeInvalid;
<>	154:37f96f9d4de2	1806	}
<>	154:37f96f9d4de2	1807	#endif
<>	154:37f96f9d4de2	1808
<>	154:37f96f9d4de2	1809	/* Disable low power */
<>	154:37f96f9d4de2	1810	MCG->C2 &= ~MCG_C2_LP_MASK;
<>	154:37f96f9d4de2	1811
<>	154:37f96f9d4de2	1812	MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) \| MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
<>	154:37f96f9d4de2	1813	while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
<>	154:37f96f9d4de2	1814	{
<>	154:37f96f9d4de2	1815	}
<>	154:37f96f9d4de2	1816
<>	154:37f96f9d4de2	1817	return kStatus_Success;
<>	154:37f96f9d4de2	1818	}
<>	154:37f96f9d4de2	1819
AnnaBridge	175:af195413fb11	1820	status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
<>	154:37f96f9d4de2	1821	{
AnnaBridge	175:af195413fb11	1822	return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
<>	154:37f96f9d4de2	1823	}
<>	154:37f96f9d4de2	1824
<>	154:37f96f9d4de2	1825	status_t CLOCK_BootToFeeMode(
<>	154:37f96f9d4de2	1826	mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
<>	154:37f96f9d4de2	1827	{
<>	154:37f96f9d4de2	1828	CLOCK_SetExternalRefClkConfig(oscsel);
<>	154:37f96f9d4de2	1829
<>	154:37f96f9d4de2	1830	return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay);
<>	154:37f96f9d4de2	1831	}
<>	154:37f96f9d4de2	1832
<>	154:37f96f9d4de2	1833	status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
<>	154:37f96f9d4de2	1834	{
<>	154:37f96f9d4de2	1835	/* If reset mode is FEI mode, set MCGIRCLK and always success. */
<>	154:37f96f9d4de2	1836	CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
<>	154:37f96f9d4de2	1837
<>	154:37f96f9d4de2	1838	/* If reset mode is not BLPI, first enter FBI mode. */
<>	154:37f96f9d4de2	1839	MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) \| MCG_C1_CLKS(kMCG_ClkOutSrcInternal);
<>	154:37f96f9d4de2	1840	while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
<>	154:37f96f9d4de2	1841	{
<>	154:37f96f9d4de2	1842	}
<>	154:37f96f9d4de2	1843
<>	154:37f96f9d4de2	1844	/* Enter BLPI mode. */
<>	154:37f96f9d4de2	1845	MCG->C2 \|= MCG_C2_LP_MASK;
<>	154:37f96f9d4de2	1846
<>	154:37f96f9d4de2	1847	return kStatus_Success;
<>	154:37f96f9d4de2	1848	}
<>	154:37f96f9d4de2	1849
<>	154:37f96f9d4de2	1850	status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
<>	154:37f96f9d4de2	1851	{
<>	154:37f96f9d4de2	1852	CLOCK_SetExternalRefClkConfig(oscsel);
<>	154:37f96f9d4de2	1853
<>	154:37f96f9d4de2	1854	/* Set to FBE mode. */
<>	154:37f96f9d4de2	1855	MCG->C1 =
<>	154:37f96f9d4de2	1856	((MCG->C1 & ~(MCG_C1_CLKS_MASK \| MCG_C1_IREFS_MASK)) \| (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
<>	154:37f96f9d4de2	1857	\| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
<>	154:37f96f9d4de2	1858
AnnaBridge	175:af195413fb11	1859	/* If use external crystal as clock source, wait for it stable. */
AnnaBridge	175:af195413fb11	1860	if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
AnnaBridge	175:af195413fb11	1861	{
AnnaBridge	175:af195413fb11	1862	if (MCG->C2 & MCG_C2_EREFS_MASK)
AnnaBridge	175:af195413fb11	1863	{
AnnaBridge	175:af195413fb11	1864	while (!(MCG->S & MCG_S_OSCINIT0_MASK))
AnnaBridge	175:af195413fb11	1865	{
AnnaBridge	175:af195413fb11	1866	}
AnnaBridge	175:af195413fb11	1867	}
AnnaBridge	175:af195413fb11	1868	}
AnnaBridge	175:af195413fb11	1869
<>	154:37f96f9d4de2	1870	/* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
<>	154:37f96f9d4de2	1871	while ((MCG->S & (MCG_S_IREFST_MASK \| MCG_S_CLKST_MASK)) !=
<>	154:37f96f9d4de2	1872	(MCG_S_IREFST(kMCG_FllSrcExternal) \| MCG_S_CLKST(kMCG_ClkOutStatExt)))
<>	154:37f96f9d4de2	1873	{
<>	154:37f96f9d4de2	1874	}
<>	154:37f96f9d4de2	1875
<>	154:37f96f9d4de2	1876	/* In FBE now, start to enter BLPE. */
<>	154:37f96f9d4de2	1877	MCG->C2 \|= MCG_C2_LP_MASK;
<>	154:37f96f9d4de2	1878
<>	154:37f96f9d4de2	1879	return kStatus_Success;
<>	154:37f96f9d4de2	1880	}
<>	154:37f96f9d4de2	1881
<>	154:37f96f9d4de2	1882	status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
<>	154:37f96f9d4de2	1883	{
AnnaBridge	175:af195413fb11	1884	/* If external PLL is used, then the config could be NULL. */
AnnaBridge	175:af195413fb11	1885	if (kMCG_PllClkSelExtPll != pllcs)
AnnaBridge	175:af195413fb11	1886	{
AnnaBridge	175:af195413fb11	1887	assert(config);
AnnaBridge	175:af195413fb11	1888	}
<>	154:37f96f9d4de2	1889
<>	154:37f96f9d4de2	1890	CLOCK_SetExternalRefClkConfig(oscsel);
<>	154:37f96f9d4de2	1891
<>	154:37f96f9d4de2	1892	CLOCK_SetPbeMode(pllcs, config);
<>	154:37f96f9d4de2	1893
<>	154:37f96f9d4de2	1894	/* Change to use PLL output clock. */
<>	154:37f96f9d4de2	1895	MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) \| MCG_C1_CLKS(kMCG_ClkOutSrcOut);
<>	154:37f96f9d4de2	1896	while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
<>	154:37f96f9d4de2	1897	{
<>	154:37f96f9d4de2	1898	}
<>	154:37f96f9d4de2	1899
<>	154:37f96f9d4de2	1900	return kStatus_Success;
<>	154:37f96f9d4de2	1901	}
<>	154:37f96f9d4de2	1902
<>	154:37f96f9d4de2	1903	/*
<>	154:37f96f9d4de2	1904	The transaction matrix. It defines the path for mode switch, the row is for
<>	154:37f96f9d4de2	1905	current mode and the column is target mode.
<>	154:37f96f9d4de2	1906	For example, switch from FEI to PEE:
<>	154:37f96f9d4de2	1907	1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE.
<>	154:37f96f9d4de2	1908	2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE.
<>	154:37f96f9d4de2	1909	3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE.
<>	154:37f96f9d4de2	1910	Thus the MCG mode has changed from FEI to PEE.
<>	154:37f96f9d4de2	1911	*/
<>	154:37f96f9d4de2	1912	static const mcg_mode_t mcgModeMatrix[8][8] = {
<>	154:37f96f9d4de2	1913	{kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
<>	154:37f96f9d4de2	1914	kMCG_ModeFBE}, /* FEI */
<>	154:37f96f9d4de2	1915	{kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
<>	154:37f96f9d4de2	1916	kMCG_ModeFBE}, /* FBI */
<>	154:37f96f9d4de2	1917	{kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI,
<>	154:37f96f9d4de2	1918	kMCG_ModeFBI}, /* BLPI */
<>	154:37f96f9d4de2	1919	{kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
<>	154:37f96f9d4de2	1920	kMCG_ModeFBE}, /* FEE */
<>	154:37f96f9d4de2	1921	{kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
<>	154:37f96f9d4de2	1922	kMCG_ModePBE}, /* FBE */
<>	154:37f96f9d4de2	1923	{kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
<>	154:37f96f9d4de2	1924	kMCG_ModePBE}, /* BLPE */
<>	154:37f96f9d4de2	1925	{kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
<>	154:37f96f9d4de2	1926	kMCG_ModePEE}, /* PBE */
<>	154:37f96f9d4de2	1927	{kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE,
<>	154:37f96f9d4de2	1928	kMCG_ModePBE} /* PEE */
<>	154:37f96f9d4de2	1929	/* FEI FBI BLPI FEE FBE BLPE PBE PEE */
<>	154:37f96f9d4de2	1930	};
<>	154:37f96f9d4de2	1931
<>	154:37f96f9d4de2	1932	status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
<>	154:37f96f9d4de2	1933	{
<>	154:37f96f9d4de2	1934	mcg_mode_t next_mode;
<>	154:37f96f9d4de2	1935	status_t status = kStatus_Success;
<>	154:37f96f9d4de2	1936
<>	154:37f96f9d4de2	1937	mcg_pll_clk_select_t pllcs = config->pllcs;
<>	154:37f96f9d4de2	1938
<>	154:37f96f9d4de2	1939	/* If need to change external clock, MCG_C7[OSCSEL]. */
<>	154:37f96f9d4de2	1940	if (MCG_C7_OSCSEL_VAL != config->oscsel)
<>	154:37f96f9d4de2	1941	{
<>	154:37f96f9d4de2	1942	/* If external clock is in use, change to FEI first. */
<>	154:37f96f9d4de2	1943	if (!(MCG->S & MCG_S_IRCST_MASK))
<>	154:37f96f9d4de2	1944	{
<>	154:37f96f9d4de2	1945	CLOCK_ExternalModeToFbeModeQuick();
AnnaBridge	175:af195413fb11	1946	CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
<>	154:37f96f9d4de2	1947	}
<>	154:37f96f9d4de2	1948
<>	154:37f96f9d4de2	1949	CLOCK_SetExternalRefClkConfig(config->oscsel);
<>	154:37f96f9d4de2	1950	}
<>	154:37f96f9d4de2	1951
<>	154:37f96f9d4de2	1952	/* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
<>	154:37f96f9d4de2	1953	if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
<>	154:37f96f9d4de2	1954	{
<>	154:37f96f9d4de2	1955	MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
<>	154:37f96f9d4de2	1956
<>	154:37f96f9d4de2	1957	{
AnnaBridge	175:af195413fb11	1958	CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
<>	154:37f96f9d4de2	1959	}
<>	154:37f96f9d4de2	1960	}
<>	154:37f96f9d4de2	1961
<>	154:37f96f9d4de2	1962	/* Configure MCGIRCLK. */
<>	154:37f96f9d4de2	1963	CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv);
<>	154:37f96f9d4de2	1964
<>	154:37f96f9d4de2	1965	next_mode = CLOCK_GetMode();
<>	154:37f96f9d4de2	1966
<>	154:37f96f9d4de2	1967	do
<>	154:37f96f9d4de2	1968	{
<>	154:37f96f9d4de2	1969	next_mode = mcgModeMatrix[next_mode][config->mcgMode];
<>	154:37f96f9d4de2	1970
<>	154:37f96f9d4de2	1971	switch (next_mode)
<>	154:37f96f9d4de2	1972	{
<>	154:37f96f9d4de2	1973	case kMCG_ModeFEI:
AnnaBridge	175:af195413fb11	1974	status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
<>	154:37f96f9d4de2	1975	break;
<>	154:37f96f9d4de2	1976	case kMCG_ModeFEE:
<>	154:37f96f9d4de2	1977	status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
<>	154:37f96f9d4de2	1978	break;
<>	154:37f96f9d4de2	1979	case kMCG_ModeFBI:
AnnaBridge	175:af195413fb11	1980	status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
<>	154:37f96f9d4de2	1981	break;
<>	154:37f96f9d4de2	1982	case kMCG_ModeFBE:
<>	154:37f96f9d4de2	1983	status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
<>	154:37f96f9d4de2	1984	break;
<>	154:37f96f9d4de2	1985	case kMCG_ModeBLPI:
<>	154:37f96f9d4de2	1986	status = CLOCK_SetBlpiMode();
<>	154:37f96f9d4de2	1987	break;
<>	154:37f96f9d4de2	1988	case kMCG_ModeBLPE:
<>	154:37f96f9d4de2	1989	status = CLOCK_SetBlpeMode();
<>	154:37f96f9d4de2	1990	break;
<>	154:37f96f9d4de2	1991	case kMCG_ModePBE:
<>	154:37f96f9d4de2	1992	/* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
<>	154:37f96f9d4de2	1993	if ((kMCG_ModePEE == config->mcgMode) \|\| (kMCG_ModePBE == config->mcgMode))
<>	154:37f96f9d4de2	1994	{
<>	154:37f96f9d4de2	1995	if (kMCG_PllClkSelPll0 == pllcs)
<>	154:37f96f9d4de2	1996	{
<>	154:37f96f9d4de2	1997	status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
<>	154:37f96f9d4de2	1998	}
<>	154:37f96f9d4de2	1999	else if (kMCG_PllClkSelExtPll == pllcs)
<>	154:37f96f9d4de2	2000	{
<>	154:37f96f9d4de2	2001	status = CLOCK_SetPbeMode(pllcs, NULL);
<>	154:37f96f9d4de2	2002	}
<>	154:37f96f9d4de2	2003	else
<>	154:37f96f9d4de2	2004	{
<>	154:37f96f9d4de2	2005	}
<>	154:37f96f9d4de2	2006	}
<>	154:37f96f9d4de2	2007	else
<>	154:37f96f9d4de2	2008	{
<>	154:37f96f9d4de2	2009	MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) \| MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
<>	154:37f96f9d4de2	2010	while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
<>	154:37f96f9d4de2	2011	{
<>	154:37f96f9d4de2	2012	}
<>	154:37f96f9d4de2	2013	}
<>	154:37f96f9d4de2	2014	break;
<>	154:37f96f9d4de2	2015	case kMCG_ModePEE:
<>	154:37f96f9d4de2	2016	status = CLOCK_SetPeeMode();
<>	154:37f96f9d4de2	2017	break;
<>	154:37f96f9d4de2	2018	default:
<>	154:37f96f9d4de2	2019	break;
<>	154:37f96f9d4de2	2020	}
<>	154:37f96f9d4de2	2021	if (kStatus_Success != status)
<>	154:37f96f9d4de2	2022	{
<>	154:37f96f9d4de2	2023	return status;
<>	154:37f96f9d4de2	2024	}
<>	154:37f96f9d4de2	2025	} while (next_mode != config->mcgMode);
<>	154:37f96f9d4de2	2026
<>	154:37f96f9d4de2	2027	if (config->pll0Config.enableMode & kMCG_PllEnableIndependent)
<>	154:37f96f9d4de2	2028	{
<>	154:37f96f9d4de2	2029	CLOCK_EnablePll0(&config->pll0Config);
<>	154:37f96f9d4de2	2030	}
<>	154:37f96f9d4de2	2031	else
<>	154:37f96f9d4de2	2032	{
<>	154:37f96f9d4de2	2033	MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
<>	154:37f96f9d4de2	2034	}
<>	154:37f96f9d4de2	2035	return kStatus_Success;
<>	154:37f96f9d4de2	2036	}

Repository toolbox

Repository details

Type:	Library
Created:	27 Oct 2017
Imports:	56
Forks:	0
Commits:	182
Dependents:	41
Dependencies:	0
Followers:	12

This repository is Public (Unlisted).

Important changes to repositories hosted on mbed.com

targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c@175:af195413fb11, 2017-10-11 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c@175:af195413fb11, 2017-10-11 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning