Ben Katz / mbed-dev-f303

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_smc.c@181:36facd806e4a, 2018-07-30 (annotated)

Committer:
benkatz
Date:
Mon Jul 30 20:31:44 2018 +0000
Revision:
181:36facd806e4a
Parent:
165:e614a9f1c9e2 
going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:e614a9f1c9e2 1 /*
AnnaBridge 165:e614a9f1c9e2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 165:e614a9f1c9e2 3 * Copyright 2016-2017 NXP
AnnaBridge 165:e614a9f1c9e2 4 *
AnnaBridge 165:e614a9f1c9e2 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 165:e614a9f1c9e2 6 * are permitted provided that the following conditions are met:
AnnaBridge 165:e614a9f1c9e2 7 *
AnnaBridge 165:e614a9f1c9e2 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 165:e614a9f1c9e2 9 * of conditions and the following disclaimer.
AnnaBridge 165:e614a9f1c9e2 10 *
AnnaBridge 165:e614a9f1c9e2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 165:e614a9f1c9e2 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 165:e614a9f1c9e2 13 * other materials provided with the distribution.
AnnaBridge 165:e614a9f1c9e2 14 *
AnnaBridge 165:e614a9f1c9e2 15 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 165:e614a9f1c9e2 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 165:e614a9f1c9e2 17 * software without specific prior written permission.
AnnaBridge 165:e614a9f1c9e2 18 *
AnnaBridge 165:e614a9f1c9e2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 165:e614a9f1c9e2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 165:e614a9f1c9e2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 165:e614a9f1c9e2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 165:e614a9f1c9e2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 165:e614a9f1c9e2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 165:e614a9f1c9e2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 165:e614a9f1c9e2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 165:e614a9f1c9e2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 165:e614a9f1c9e2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 165:e614a9f1c9e2 29 */
AnnaBridge 165:e614a9f1c9e2 30
AnnaBridge 165:e614a9f1c9e2 31 #include "fsl_smc.h"
AnnaBridge 165:e614a9f1c9e2 32 #include "fsl_flash.h"
AnnaBridge 165:e614a9f1c9e2 33
AnnaBridge 165:e614a9f1c9e2 34 #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
AnnaBridge 165:e614a9f1c9e2 35 void SMC_GetParam(SMC_Type *base, smc_param_t *param)
AnnaBridge 165:e614a9f1c9e2 36 {
AnnaBridge 165:e614a9f1c9e2 37 uint32_t reg = base->PARAM;
AnnaBridge 165:e614a9f1c9e2 38 param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK);
AnnaBridge 165:e614a9f1c9e2 39 param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK);
AnnaBridge 165:e614a9f1c9e2 40 param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK);
AnnaBridge 165:e614a9f1c9e2 41 param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK);
AnnaBridge 165:e614a9f1c9e2 42 }
AnnaBridge 165:e614a9f1c9e2 43 #endif /* FSL_FEATURE_SMC_HAS_PARAM */
AnnaBridge 165:e614a9f1c9e2 44
AnnaBridge 165:e614a9f1c9e2 45 void SMC_PreEnterStopModes(void)
AnnaBridge 165:e614a9f1c9e2 46 {
AnnaBridge 165:e614a9f1c9e2 47 flash_prefetch_speculation_status_t speculationStatus =
AnnaBridge 165:e614a9f1c9e2 48 {
AnnaBridge 165:e614a9f1c9e2 49 kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/
AnnaBridge 165:e614a9f1c9e2 50 kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/
AnnaBridge 165:e614a9f1c9e2 51 };
AnnaBridge 165:e614a9f1c9e2 52
AnnaBridge 165:e614a9f1c9e2 53 __disable_irq();
AnnaBridge 165:e614a9f1c9e2 54 __ISB();
AnnaBridge 165:e614a9f1c9e2 55
AnnaBridge 165:e614a9f1c9e2 56 /*
AnnaBridge 165:e614a9f1c9e2 57 * Before enter stop modes, the flash cache prefetch should be disabled.
AnnaBridge 165:e614a9f1c9e2 58 * Otherwise the prefetch might be interrupted by stop, then the data and
AnnaBridge 165:e614a9f1c9e2 59 * and instruction from flash are wrong.
AnnaBridge 165:e614a9f1c9e2 60 */
AnnaBridge 165:e614a9f1c9e2 61 FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
AnnaBridge 165:e614a9f1c9e2 62 }
AnnaBridge 165:e614a9f1c9e2 63
AnnaBridge 165:e614a9f1c9e2 64 void SMC_PostExitStopModes(void)
AnnaBridge 165:e614a9f1c9e2 65 {
AnnaBridge 165:e614a9f1c9e2 66 flash_prefetch_speculation_status_t speculationStatus =
AnnaBridge 165:e614a9f1c9e2 67 {
AnnaBridge 165:e614a9f1c9e2 68 kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/
AnnaBridge 165:e614a9f1c9e2 69 kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/
AnnaBridge 165:e614a9f1c9e2 70 };
AnnaBridge 165:e614a9f1c9e2 71
AnnaBridge 165:e614a9f1c9e2 72 FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
AnnaBridge 165:e614a9f1c9e2 73
AnnaBridge 165:e614a9f1c9e2 74 __enable_irq();
AnnaBridge 165:e614a9f1c9e2 75 __ISB();
AnnaBridge 165:e614a9f1c9e2 76 }
AnnaBridge 165:e614a9f1c9e2 77
AnnaBridge 165:e614a9f1c9e2 78 status_t SMC_SetPowerModeRun(SMC_Type *base)
AnnaBridge 165:e614a9f1c9e2 79 {
AnnaBridge 165:e614a9f1c9e2 80 uint8_t reg;
AnnaBridge 165:e614a9f1c9e2 81
AnnaBridge 165:e614a9f1c9e2 82 reg = base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 83 /* configure Normal RUN mode */
AnnaBridge 165:e614a9f1c9e2 84 reg &= ~SMC_PMCTRL_RUNM_MASK;
AnnaBridge 165:e614a9f1c9e2 85 reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 86 base->PMCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 87
AnnaBridge 165:e614a9f1c9e2 88 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 89 }
AnnaBridge 165:e614a9f1c9e2 90
AnnaBridge 165:e614a9f1c9e2 91 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
AnnaBridge 165:e614a9f1c9e2 92 status_t SMC_SetPowerModeHsrun(SMC_Type *base)
AnnaBridge 165:e614a9f1c9e2 93 {
AnnaBridge 165:e614a9f1c9e2 94 uint8_t reg;
AnnaBridge 165:e614a9f1c9e2 95
AnnaBridge 165:e614a9f1c9e2 96 reg = base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 97 /* configure High Speed RUN mode */
AnnaBridge 165:e614a9f1c9e2 98 reg &= ~SMC_PMCTRL_RUNM_MASK;
AnnaBridge 165:e614a9f1c9e2 99 reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 100 base->PMCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 101
AnnaBridge 165:e614a9f1c9e2 102 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 103 }
AnnaBridge 165:e614a9f1c9e2 104 #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
AnnaBridge 165:e614a9f1c9e2 105
AnnaBridge 165:e614a9f1c9e2 106 status_t SMC_SetPowerModeWait(SMC_Type *base)
AnnaBridge 165:e614a9f1c9e2 107 {
AnnaBridge 165:e614a9f1c9e2 108 /* configure Normal Wait mode */
AnnaBridge 165:e614a9f1c9e2 109 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 165:e614a9f1c9e2 110 __DSB();
AnnaBridge 165:e614a9f1c9e2 111 __WFI();
AnnaBridge 165:e614a9f1c9e2 112 __ISB();
AnnaBridge 165:e614a9f1c9e2 113
AnnaBridge 165:e614a9f1c9e2 114 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 115 }
AnnaBridge 165:e614a9f1c9e2 116
AnnaBridge 165:e614a9f1c9e2 117 status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
AnnaBridge 165:e614a9f1c9e2 118 {
AnnaBridge 165:e614a9f1c9e2 119 uint8_t reg;
AnnaBridge 165:e614a9f1c9e2 120
AnnaBridge 165:e614a9f1c9e2 121 #if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO)
AnnaBridge 165:e614a9f1c9e2 122 /* configure the Partial Stop mode in Noraml Stop mode */
AnnaBridge 165:e614a9f1c9e2 123 reg = base->STOPCTRL;
AnnaBridge 165:e614a9f1c9e2 124 reg &= ~SMC_STOPCTRL_PSTOPO_MASK;
AnnaBridge 165:e614a9f1c9e2 125 reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT);
AnnaBridge 165:e614a9f1c9e2 126 base->STOPCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 127 #endif
AnnaBridge 165:e614a9f1c9e2 128
AnnaBridge 165:e614a9f1c9e2 129 /* configure Normal Stop mode */
AnnaBridge 165:e614a9f1c9e2 130 reg = base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 131 reg &= ~SMC_PMCTRL_STOPM_MASK;
AnnaBridge 165:e614a9f1c9e2 132 reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 133 base->PMCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 134
AnnaBridge 165:e614a9f1c9e2 135 /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
AnnaBridge 165:e614a9f1c9e2 136 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 165:e614a9f1c9e2 137
AnnaBridge 165:e614a9f1c9e2 138 /* read back to make sure the configuration valid before enter stop mode */
AnnaBridge 165:e614a9f1c9e2 139 (void)base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 140 __DSB();
AnnaBridge 165:e614a9f1c9e2 141 __WFI();
AnnaBridge 165:e614a9f1c9e2 142 __ISB();
AnnaBridge 165:e614a9f1c9e2 143
AnnaBridge 165:e614a9f1c9e2 144 /* check whether the power mode enter Stop mode succeed */
AnnaBridge 165:e614a9f1c9e2 145 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 165:e614a9f1c9e2 146 {
AnnaBridge 165:e614a9f1c9e2 147 return kStatus_SMC_StopAbort;
AnnaBridge 165:e614a9f1c9e2 148 }
AnnaBridge 165:e614a9f1c9e2 149 else
AnnaBridge 165:e614a9f1c9e2 150 {
AnnaBridge 165:e614a9f1c9e2 151 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 152 }
AnnaBridge 165:e614a9f1c9e2 153 }
AnnaBridge 165:e614a9f1c9e2 154
AnnaBridge 165:e614a9f1c9e2 155 status_t SMC_SetPowerModeVlpr(SMC_Type *base
AnnaBridge 165:e614a9f1c9e2 156 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
AnnaBridge 165:e614a9f1c9e2 157 ,
AnnaBridge 165:e614a9f1c9e2 158 bool wakeupMode
AnnaBridge 165:e614a9f1c9e2 159 #endif
AnnaBridge 165:e614a9f1c9e2 160 )
AnnaBridge 165:e614a9f1c9e2 161 {
AnnaBridge 165:e614a9f1c9e2 162 uint8_t reg;
AnnaBridge 165:e614a9f1c9e2 163
AnnaBridge 165:e614a9f1c9e2 164 reg = base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 165 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
AnnaBridge 165:e614a9f1c9e2 166 /* configure whether the system remains in VLP mode on an interrupt */
AnnaBridge 165:e614a9f1c9e2 167 if (wakeupMode)
AnnaBridge 165:e614a9f1c9e2 168 {
AnnaBridge 165:e614a9f1c9e2 169 /* exits to RUN mode on an interrupt */
AnnaBridge 165:e614a9f1c9e2 170 reg |= SMC_PMCTRL_LPWUI_MASK;
AnnaBridge 165:e614a9f1c9e2 171 }
AnnaBridge 165:e614a9f1c9e2 172 else
AnnaBridge 165:e614a9f1c9e2 173 {
AnnaBridge 165:e614a9f1c9e2 174 /* remains in VLP mode on an interrupt */
AnnaBridge 165:e614a9f1c9e2 175 reg &= ~SMC_PMCTRL_LPWUI_MASK;
AnnaBridge 165:e614a9f1c9e2 176 }
AnnaBridge 165:e614a9f1c9e2 177 #endif /* FSL_FEATURE_SMC_HAS_LPWUI */
AnnaBridge 165:e614a9f1c9e2 178
AnnaBridge 165:e614a9f1c9e2 179 /* configure VLPR mode */
AnnaBridge 165:e614a9f1c9e2 180 reg &= ~SMC_PMCTRL_RUNM_MASK;
AnnaBridge 165:e614a9f1c9e2 181 reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 182 base->PMCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 183
AnnaBridge 165:e614a9f1c9e2 184 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 185 }
AnnaBridge 165:e614a9f1c9e2 186
AnnaBridge 165:e614a9f1c9e2 187 status_t SMC_SetPowerModeVlpw(SMC_Type *base)
AnnaBridge 165:e614a9f1c9e2 188 {
AnnaBridge 165:e614a9f1c9e2 189 /* configure VLPW mode */
AnnaBridge 165:e614a9f1c9e2 190 /* Set the SLEEPDEEP bit to enable deep sleep mode */
AnnaBridge 165:e614a9f1c9e2 191 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 165:e614a9f1c9e2 192 __DSB();
AnnaBridge 165:e614a9f1c9e2 193 __WFI();
AnnaBridge 165:e614a9f1c9e2 194 __ISB();
AnnaBridge 165:e614a9f1c9e2 195
AnnaBridge 165:e614a9f1c9e2 196 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 197 }
AnnaBridge 165:e614a9f1c9e2 198
AnnaBridge 165:e614a9f1c9e2 199 status_t SMC_SetPowerModeVlps(SMC_Type *base)
AnnaBridge 165:e614a9f1c9e2 200 {
AnnaBridge 165:e614a9f1c9e2 201 uint8_t reg;
AnnaBridge 165:e614a9f1c9e2 202
AnnaBridge 165:e614a9f1c9e2 203 /* configure VLPS mode */
AnnaBridge 165:e614a9f1c9e2 204 reg = base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 205 reg &= ~SMC_PMCTRL_STOPM_MASK;
AnnaBridge 165:e614a9f1c9e2 206 reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 207 base->PMCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 208
AnnaBridge 165:e614a9f1c9e2 209 /* Set the SLEEPDEEP bit to enable deep sleep mode */
AnnaBridge 165:e614a9f1c9e2 210 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 165:e614a9f1c9e2 211
AnnaBridge 165:e614a9f1c9e2 212 /* read back to make sure the configuration valid before enter stop mode */
AnnaBridge 165:e614a9f1c9e2 213 (void)base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 214 __DSB();
AnnaBridge 165:e614a9f1c9e2 215 __WFI();
AnnaBridge 165:e614a9f1c9e2 216 __ISB();
AnnaBridge 165:e614a9f1c9e2 217
AnnaBridge 165:e614a9f1c9e2 218 /* check whether the power mode enter VLPS mode succeed */
AnnaBridge 165:e614a9f1c9e2 219 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 165:e614a9f1c9e2 220 {
AnnaBridge 165:e614a9f1c9e2 221 return kStatus_SMC_StopAbort;
AnnaBridge 165:e614a9f1c9e2 222 }
AnnaBridge 165:e614a9f1c9e2 223 else
AnnaBridge 165:e614a9f1c9e2 224 {
AnnaBridge 165:e614a9f1c9e2 225 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 226 }
AnnaBridge 165:e614a9f1c9e2 227 }
AnnaBridge 165:e614a9f1c9e2 228
AnnaBridge 165:e614a9f1c9e2 229 #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
AnnaBridge 165:e614a9f1c9e2 230 status_t SMC_SetPowerModeLls(SMC_Type *base
AnnaBridge 165:e614a9f1c9e2 231 #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
AnnaBridge 165:e614a9f1c9e2 232 (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
AnnaBridge 165:e614a9f1c9e2 233 ,
AnnaBridge 165:e614a9f1c9e2 234 const smc_power_mode_lls_config_t *config
AnnaBridge 165:e614a9f1c9e2 235 #endif
AnnaBridge 165:e614a9f1c9e2 236 )
AnnaBridge 165:e614a9f1c9e2 237 {
AnnaBridge 165:e614a9f1c9e2 238 uint8_t reg;
AnnaBridge 165:e614a9f1c9e2 239
AnnaBridge 165:e614a9f1c9e2 240 /* configure to LLS mode */
AnnaBridge 165:e614a9f1c9e2 241 reg = base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 242 reg &= ~SMC_PMCTRL_STOPM_MASK;
AnnaBridge 165:e614a9f1c9e2 243 reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 244 base->PMCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 245
AnnaBridge 165:e614a9f1c9e2 246 /* configure LLS sub-mode*/
AnnaBridge 165:e614a9f1c9e2 247 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
AnnaBridge 165:e614a9f1c9e2 248 reg = base->STOPCTRL;
AnnaBridge 165:e614a9f1c9e2 249 reg &= ~SMC_STOPCTRL_LLSM_MASK;
AnnaBridge 165:e614a9f1c9e2 250 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 251 base->STOPCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 252 #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
AnnaBridge 165:e614a9f1c9e2 253
AnnaBridge 165:e614a9f1c9e2 254 #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
AnnaBridge 165:e614a9f1c9e2 255 if (config->enableLpoClock)
AnnaBridge 165:e614a9f1c9e2 256 {
AnnaBridge 165:e614a9f1c9e2 257 base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
AnnaBridge 165:e614a9f1c9e2 258 }
AnnaBridge 165:e614a9f1c9e2 259 else
AnnaBridge 165:e614a9f1c9e2 260 {
AnnaBridge 165:e614a9f1c9e2 261 base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
AnnaBridge 165:e614a9f1c9e2 262 }
AnnaBridge 165:e614a9f1c9e2 263 #endif /* FSL_FEATURE_SMC_HAS_LPOPO */
AnnaBridge 165:e614a9f1c9e2 264
AnnaBridge 165:e614a9f1c9e2 265 /* Set the SLEEPDEEP bit to enable deep sleep mode */
AnnaBridge 165:e614a9f1c9e2 266 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 165:e614a9f1c9e2 267
AnnaBridge 165:e614a9f1c9e2 268 /* read back to make sure the configuration valid before enter stop mode */
AnnaBridge 165:e614a9f1c9e2 269 (void)base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 270 __DSB();
AnnaBridge 165:e614a9f1c9e2 271 __WFI();
AnnaBridge 165:e614a9f1c9e2 272 __ISB();
AnnaBridge 165:e614a9f1c9e2 273
AnnaBridge 165:e614a9f1c9e2 274 /* check whether the power mode enter LLS mode succeed */
AnnaBridge 165:e614a9f1c9e2 275 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 165:e614a9f1c9e2 276 {
AnnaBridge 165:e614a9f1c9e2 277 return kStatus_SMC_StopAbort;
AnnaBridge 165:e614a9f1c9e2 278 }
AnnaBridge 165:e614a9f1c9e2 279 else
AnnaBridge 165:e614a9f1c9e2 280 {
AnnaBridge 165:e614a9f1c9e2 281 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 282 }
AnnaBridge 165:e614a9f1c9e2 283 }
AnnaBridge 165:e614a9f1c9e2 284 #endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
AnnaBridge 165:e614a9f1c9e2 285
AnnaBridge 165:e614a9f1c9e2 286 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
AnnaBridge 165:e614a9f1c9e2 287 status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config)
AnnaBridge 165:e614a9f1c9e2 288 {
AnnaBridge 165:e614a9f1c9e2 289 uint8_t reg;
AnnaBridge 165:e614a9f1c9e2 290
AnnaBridge 165:e614a9f1c9e2 291 #if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
AnnaBridge 165:e614a9f1c9e2 292 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \
AnnaBridge 165:e614a9f1c9e2 293 (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
AnnaBridge 165:e614a9f1c9e2 294 (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
AnnaBridge 165:e614a9f1c9e2 295 if (config->subMode == kSMC_StopSub0)
AnnaBridge 165:e614a9f1c9e2 296 #endif
AnnaBridge 165:e614a9f1c9e2 297 {
AnnaBridge 165:e614a9f1c9e2 298 /* configure whether the Por Detect work in Vlls0 mode */
AnnaBridge 165:e614a9f1c9e2 299 if (config->enablePorDetectInVlls0)
AnnaBridge 165:e614a9f1c9e2 300 {
AnnaBridge 165:e614a9f1c9e2 301 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
AnnaBridge 165:e614a9f1c9e2 302 base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK;
AnnaBridge 165:e614a9f1c9e2 303 #else
AnnaBridge 165:e614a9f1c9e2 304 base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK;
AnnaBridge 165:e614a9f1c9e2 305 #endif
AnnaBridge 165:e614a9f1c9e2 306 }
AnnaBridge 165:e614a9f1c9e2 307 else
AnnaBridge 165:e614a9f1c9e2 308 {
AnnaBridge 165:e614a9f1c9e2 309 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
AnnaBridge 165:e614a9f1c9e2 310 base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK;
AnnaBridge 165:e614a9f1c9e2 311 #else
AnnaBridge 165:e614a9f1c9e2 312 base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK;
AnnaBridge 165:e614a9f1c9e2 313 #endif
AnnaBridge 165:e614a9f1c9e2 314 }
AnnaBridge 165:e614a9f1c9e2 315 }
AnnaBridge 165:e614a9f1c9e2 316 #endif /* FSL_FEATURE_SMC_HAS_PORPO */
AnnaBridge 165:e614a9f1c9e2 317
AnnaBridge 165:e614a9f1c9e2 318 #if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
AnnaBridge 165:e614a9f1c9e2 319 else if (config->subMode == kSMC_StopSub2)
AnnaBridge 165:e614a9f1c9e2 320 {
AnnaBridge 165:e614a9f1c9e2 321 /* configure whether the Por Detect work in Vlls0 mode */
AnnaBridge 165:e614a9f1c9e2 322 if (config->enableRam2InVlls2)
AnnaBridge 165:e614a9f1c9e2 323 {
AnnaBridge 165:e614a9f1c9e2 324 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
AnnaBridge 165:e614a9f1c9e2 325 base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK;
AnnaBridge 165:e614a9f1c9e2 326 #else
AnnaBridge 165:e614a9f1c9e2 327 base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK;
AnnaBridge 165:e614a9f1c9e2 328 #endif
AnnaBridge 165:e614a9f1c9e2 329 }
AnnaBridge 165:e614a9f1c9e2 330 else
AnnaBridge 165:e614a9f1c9e2 331 {
AnnaBridge 165:e614a9f1c9e2 332 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
AnnaBridge 165:e614a9f1c9e2 333 base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK;
AnnaBridge 165:e614a9f1c9e2 334 #else
AnnaBridge 165:e614a9f1c9e2 335 base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK;
AnnaBridge 165:e614a9f1c9e2 336 #endif
AnnaBridge 165:e614a9f1c9e2 337 }
AnnaBridge 165:e614a9f1c9e2 338 }
AnnaBridge 165:e614a9f1c9e2 339 else
AnnaBridge 165:e614a9f1c9e2 340 {
AnnaBridge 165:e614a9f1c9e2 341 }
AnnaBridge 165:e614a9f1c9e2 342 #endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */
AnnaBridge 165:e614a9f1c9e2 343
AnnaBridge 165:e614a9f1c9e2 344 /* configure to VLLS mode */
AnnaBridge 165:e614a9f1c9e2 345 reg = base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 346 reg &= ~SMC_PMCTRL_STOPM_MASK;
AnnaBridge 165:e614a9f1c9e2 347 reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 348 base->PMCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 349
AnnaBridge 165:e614a9f1c9e2 350 /* configure the VLLS sub-mode */
AnnaBridge 165:e614a9f1c9e2 351 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
AnnaBridge 165:e614a9f1c9e2 352 reg = base->VLLSCTRL;
AnnaBridge 165:e614a9f1c9e2 353 reg &= ~SMC_VLLSCTRL_VLLSM_MASK;
AnnaBridge 165:e614a9f1c9e2 354 reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 355 base->VLLSCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 356 #else
AnnaBridge 165:e614a9f1c9e2 357 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
AnnaBridge 165:e614a9f1c9e2 358 reg = base->STOPCTRL;
AnnaBridge 165:e614a9f1c9e2 359 reg &= ~SMC_STOPCTRL_LLSM_MASK;
AnnaBridge 165:e614a9f1c9e2 360 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 361 base->STOPCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 362 #else
AnnaBridge 165:e614a9f1c9e2 363 reg = base->STOPCTRL;
AnnaBridge 165:e614a9f1c9e2 364 reg &= ~SMC_STOPCTRL_VLLSM_MASK;
AnnaBridge 165:e614a9f1c9e2 365 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT);
AnnaBridge 165:e614a9f1c9e2 366 base->STOPCTRL = reg;
AnnaBridge 165:e614a9f1c9e2 367 #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
AnnaBridge 165:e614a9f1c9e2 368 #endif
AnnaBridge 165:e614a9f1c9e2 369
AnnaBridge 165:e614a9f1c9e2 370 #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
AnnaBridge 165:e614a9f1c9e2 371 if (config->enableLpoClock)
AnnaBridge 165:e614a9f1c9e2 372 {
AnnaBridge 165:e614a9f1c9e2 373 base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
AnnaBridge 165:e614a9f1c9e2 374 }
AnnaBridge 165:e614a9f1c9e2 375 else
AnnaBridge 165:e614a9f1c9e2 376 {
AnnaBridge 165:e614a9f1c9e2 377 base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
AnnaBridge 165:e614a9f1c9e2 378 }
AnnaBridge 165:e614a9f1c9e2 379 #endif /* FSL_FEATURE_SMC_HAS_LPOPO */
AnnaBridge 165:e614a9f1c9e2 380
AnnaBridge 165:e614a9f1c9e2 381 /* Set the SLEEPDEEP bit to enable deep sleep mode */
AnnaBridge 165:e614a9f1c9e2 382 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 165:e614a9f1c9e2 383
AnnaBridge 165:e614a9f1c9e2 384 /* read back to make sure the configuration valid before enter stop mode */
AnnaBridge 165:e614a9f1c9e2 385 (void)base->PMCTRL;
AnnaBridge 165:e614a9f1c9e2 386 __DSB();
AnnaBridge 165:e614a9f1c9e2 387 __WFI();
AnnaBridge 165:e614a9f1c9e2 388 __ISB();
AnnaBridge 165:e614a9f1c9e2 389
AnnaBridge 165:e614a9f1c9e2 390 /* check whether the power mode enter LLS mode succeed */
AnnaBridge 165:e614a9f1c9e2 391 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 165:e614a9f1c9e2 392 {
AnnaBridge 165:e614a9f1c9e2 393 return kStatus_SMC_StopAbort;
AnnaBridge 165:e614a9f1c9e2 394 }
AnnaBridge 165:e614a9f1c9e2 395 else
AnnaBridge 165:e614a9f1c9e2 396 {
AnnaBridge 165:e614a9f1c9e2 397 return kStatus_Success;
AnnaBridge 165:e614a9f1c9e2 398 }
AnnaBridge 165:e614a9f1c9e2 399 }
AnnaBridge 165:e614a9f1c9e2 400 #endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */