Ben Katz / mbed-dev-f303

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c@181:36facd806e4a, 2018-07-30 (annotated)

Committer:
benkatz
Date:
Mon Jul 30 20:31:44 2018 +0000
Revision:
181:36facd806e4a
Parent:
154:37f96f9d4de2 
going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_common.h"
<> 154:37f96f9d4de2 32 #include "fsl_smc.h"
<> 154:37f96f9d4de2 33 #include "fsl_clock_config.h"
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*******************************************************************************
<> 154:37f96f9d4de2 36 * Definitions
<> 154:37f96f9d4de2 37 ******************************************************************************/
<> 154:37f96f9d4de2 38 /*! @brief Clock configuration structure. */
<> 154:37f96f9d4de2 39 typedef struct _clock_config
<> 154:37f96f9d4de2 40 {
<> 154:37f96f9d4de2 41 mcglite_config_t mcgliteConfig; /*!< MCG configuration. */
<> 154:37f96f9d4de2 42 sim_clock_config_t simConfig; /*!< SIM configuration. */
<> 154:37f96f9d4de2 43 osc_config_t oscConfig; /*!< OSC configuration. */
<> 154:37f96f9d4de2 44 uint32_t coreClock; /*!< core clock frequency. */
<> 154:37f96f9d4de2 45 } clock_config_t;
<> 154:37f96f9d4de2 46
<> 154:37f96f9d4de2 47 /*******************************************************************************
<> 154:37f96f9d4de2 48 * Variables
<> 154:37f96f9d4de2 49 ******************************************************************************/
<> 154:37f96f9d4de2 50 /* System clock frequency. */
<> 154:37f96f9d4de2 51 extern uint32_t SystemCoreClock;
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 /* Configuration for enter VLPR mode. Core clock = 2MHz. */
<> 154:37f96f9d4de2 54 const clock_config_t g_defaultClockConfigVlpr = {
<> 154:37f96f9d4de2 55 .mcgliteConfig =
<> 154:37f96f9d4de2 56 {
<> 154:37f96f9d4de2 57 .outSrc = kMCGLITE_ClkSrcLirc,
<> 154:37f96f9d4de2 58 .irclkEnableMode = kMCGLITE_IrclkEnable,
<> 154:37f96f9d4de2 59 .ircs = kMCGLITE_Lirc2M,
<> 154:37f96f9d4de2 60 .fcrdiv = kMCGLITE_LircDivBy1,
<> 154:37f96f9d4de2 61 .lircDiv2 = kMCGLITE_LircDivBy1,
<> 154:37f96f9d4de2 62 .hircEnableInNotHircMode = false,
<> 154:37f96f9d4de2 63 },
<> 154:37f96f9d4de2 64 .simConfig =
<> 154:37f96f9d4de2 65 {
<> 154:37f96f9d4de2 66 .clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */
<> 154:37f96f9d4de2 67 },
<> 154:37f96f9d4de2 68 .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
<> 154:37f96f9d4de2 69 .capLoad = 0U,
<> 154:37f96f9d4de2 70 .workMode = kOSC_ModeOscLowPower,
<> 154:37f96f9d4de2 71 .oscerConfig =
<> 154:37f96f9d4de2 72 {
<> 154:37f96f9d4de2 73 .enableMode = kOSC_ErClkEnable,
<> 154:37f96f9d4de2 74 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
<> 154:37f96f9d4de2 75 .erclkDiv = 0U,
<> 154:37f96f9d4de2 76 #endif
<> 154:37f96f9d4de2 77 }},
<> 154:37f96f9d4de2 78 .coreClock = 2000000U, /* Core clock frequency */
<> 154:37f96f9d4de2 79 };
<> 154:37f96f9d4de2 80
<> 154:37f96f9d4de2 81 /* Configuration for enter RUN mode. Core clock = 48000000Hz. */
<> 154:37f96f9d4de2 82 const clock_config_t g_defaultClockConfigRun = {
<> 154:37f96f9d4de2 83 .mcgliteConfig =
<> 154:37f96f9d4de2 84 {
<> 154:37f96f9d4de2 85 .outSrc = kMCGLITE_ClkSrcHirc,
<> 154:37f96f9d4de2 86 .irclkEnableMode = kMCGLITE_IrclkEnable,
<> 154:37f96f9d4de2 87 .ircs = kMCGLITE_Lirc8M,
<> 154:37f96f9d4de2 88 .fcrdiv = kMCGLITE_LircDivBy1,
<> 154:37f96f9d4de2 89 .lircDiv2 = kMCGLITE_LircDivBy1,
<> 154:37f96f9d4de2 90 .hircEnableInNotHircMode = true,
<> 154:37f96f9d4de2 91 },
<> 154:37f96f9d4de2 92 .simConfig =
<> 154:37f96f9d4de2 93 {
<> 154:37f96f9d4de2 94 .clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */
<> 154:37f96f9d4de2 95 },
<> 154:37f96f9d4de2 96 .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
<> 154:37f96f9d4de2 97 .capLoad = 0U,
<> 154:37f96f9d4de2 98 .workMode = kOSC_ModeOscLowPower,
<> 154:37f96f9d4de2 99 .oscerConfig =
<> 154:37f96f9d4de2 100 {
<> 154:37f96f9d4de2 101 .enableMode = kOSC_ErClkEnable,
<> 154:37f96f9d4de2 102 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
<> 154:37f96f9d4de2 103 .erclkDiv = 0U,
<> 154:37f96f9d4de2 104 #endif
<> 154:37f96f9d4de2 105 }},
<> 154:37f96f9d4de2 106 .coreClock = 48000000U, /* Core clock frequency */
<> 154:37f96f9d4de2 107 };
<> 154:37f96f9d4de2 108
<> 154:37f96f9d4de2 109 /*******************************************************************************
<> 154:37f96f9d4de2 110 * Code
<> 154:37f96f9d4de2 111 ******************************************************************************/
<> 154:37f96f9d4de2 112 /*
<> 154:37f96f9d4de2 113 * How to setup clock using clock driver functions:
<> 154:37f96f9d4de2 114 *
<> 154:37f96f9d4de2 115 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
<> 154:37f96f9d4de2 116 * and flash clock are in allowed range during clock mode switch.
<> 154:37f96f9d4de2 117 *
<> 154:37f96f9d4de2 118 * 2. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
<> 154:37f96f9d4de2 119 *
<> 154:37f96f9d4de2 120 * 3. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
<> 154:37f96f9d4de2 121 */
<> 154:37f96f9d4de2 122
<> 154:37f96f9d4de2 123 void BOARD_BootClockVLPR(void)
<> 154:37f96f9d4de2 124 {
<> 154:37f96f9d4de2 125 CLOCK_SetSimSafeDivs();
<> 154:37f96f9d4de2 126
<> 154:37f96f9d4de2 127 CLOCK_SetMcgliteConfig(&g_defaultClockConfigVlpr.mcgliteConfig);
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
<> 154:37f96f9d4de2 130
<> 154:37f96f9d4de2 131 SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
<> 154:37f96f9d4de2 132
<> 154:37f96f9d4de2 133 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
<> 154:37f96f9d4de2 134 SMC_SetPowerModeVlpr(SMC);
<> 154:37f96f9d4de2 135 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
<> 154:37f96f9d4de2 136 {
<> 154:37f96f9d4de2 137 }
<> 154:37f96f9d4de2 138 }
<> 154:37f96f9d4de2 139
<> 154:37f96f9d4de2 140 void BOARD_BootClockRUN(void)
<> 154:37f96f9d4de2 141 {
<> 154:37f96f9d4de2 142 CLOCK_SetSimSafeDivs();
<> 154:37f96f9d4de2 143
<> 154:37f96f9d4de2 144 CLOCK_SetMcgliteConfig(&g_defaultClockConfigRun.mcgliteConfig);
<> 154:37f96f9d4de2 145
<> 154:37f96f9d4de2 146 CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
<> 154:37f96f9d4de2 147
<> 154:37f96f9d4de2 148 SystemCoreClock = g_defaultClockConfigRun.coreClock;
<> 154:37f96f9d4de2 149 }