Ben Katz / mbed-dev-f303

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.s@181:36facd806e4a, 2018-07-30 (annotated)

Committer:
benkatz
Date:
Mon Jul 30 20:31:44 2018 +0000
Revision:
181:36facd806e4a
Parent:
149:156823d33999 
going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ; ---------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2 ; @file: startup_MKL26Z4.s
<> 144:ef7eb2e8f9f7 3 ; @purpose: CMSIS Cortex-M0P Core Device Startup File
<> 144:ef7eb2e8f9f7 4 ; MKL26Z4
<> 144:ef7eb2e8f9f7 5 ; @version: 1.7
<> 144:ef7eb2e8f9f7 6 ; @date: 2015-2-18
<> 144:ef7eb2e8f9f7 7 ; @build: b150218
<> 144:ef7eb2e8f9f7 8 ; ---------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9 ;
<> 144:ef7eb2e8f9f7 10 ; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 11 ; All rights reserved.
<> 144:ef7eb2e8f9f7 12 ;
<> 144:ef7eb2e8f9f7 13 ; Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 ; are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 ;
<> 144:ef7eb2e8f9f7 16 ; o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 17 ; of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 ;
<> 144:ef7eb2e8f9f7 19 ; o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 20 ; list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 21 ; other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 22 ;
<> 144:ef7eb2e8f9f7 23 ; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 24 ; contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 25 ; software without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 ;
<> 144:ef7eb2e8f9f7 27 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 28 ; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 29 ; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 ; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 31 ; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 32 ; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 33 ; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 34 ; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 35 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 36 ; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 ;
<> 144:ef7eb2e8f9f7 38 ; The modules in this file are included in the libraries, and may be replaced
<> 144:ef7eb2e8f9f7 39 ; by any user-defined modules that define the PUBLIC symbol _program_start or
<> 144:ef7eb2e8f9f7 40 ; a user defined start symbol.
<> 144:ef7eb2e8f9f7 41 ; To override the cstartup defined in the library, simply add your modified
<> 144:ef7eb2e8f9f7 42 ; version to the workbench project.
<> 144:ef7eb2e8f9f7 43 ;
<> 144:ef7eb2e8f9f7 44 ; The vector table is normally located at address 0.
<> 144:ef7eb2e8f9f7 45 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
<> 144:ef7eb2e8f9f7 46 ; The name "__vector_table" has special meaning for C-SPY:
<> 144:ef7eb2e8f9f7 47 ; it is where the SP start value is found, and the NVIC vector
<> 144:ef7eb2e8f9f7 48 ; table register (VTOR) is initialized to this address if != 0.
<> 144:ef7eb2e8f9f7 49 ;
<> 144:ef7eb2e8f9f7 50 ; Cortex-M version
<> 144:ef7eb2e8f9f7 51 ;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 MODULE ?cstartup
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 ;; Forward declaration of sections.
<> 144:ef7eb2e8f9f7 56 SECTION CSTACK:DATA:NOROOT(3)
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 SECTION .intvec:CODE:NOROOT(2)
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 EXTERN __iar_program_start
<> 144:ef7eb2e8f9f7 61 EXTERN SystemInit
<> 144:ef7eb2e8f9f7 62 EXTERN init_data_bss
<> 144:ef7eb2e8f9f7 63 PUBLIC __vector_table
<> 144:ef7eb2e8f9f7 64 PUBLIC __vector_table_0x1c
<> 144:ef7eb2e8f9f7 65 PUBLIC __Vectors
<> 144:ef7eb2e8f9f7 66 PUBLIC __Vectors_End
<> 144:ef7eb2e8f9f7 67 PUBLIC __Vectors_Size
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 DATA
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 __vector_table
<> 144:ef7eb2e8f9f7 72 DCD sfe(CSTACK)
<> 144:ef7eb2e8f9f7 73 DCD Reset_Handler
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 DCD NMI_Handler ;NMI Handler
<> 144:ef7eb2e8f9f7 76 DCD HardFault_Handler ;Hard Fault Handler
<> 144:ef7eb2e8f9f7 77 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 78 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 79 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 80 __vector_table_0x1c
<> 144:ef7eb2e8f9f7 81 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 82 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 83 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 84 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 85 DCD SVC_Handler ;SVCall Handler
<> 144:ef7eb2e8f9f7 86 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 87 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 88 DCD PendSV_Handler ;PendSV Handler
<> 144:ef7eb2e8f9f7 89 DCD SysTick_Handler ;SysTick Handler
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 ;External Interrupts
<> 144:ef7eb2e8f9f7 92 DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt
<> 144:ef7eb2e8f9f7 93 DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt
<> 144:ef7eb2e8f9f7 94 DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt
<> 144:ef7eb2e8f9f7 95 DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt
<> 144:ef7eb2e8f9f7 96 DCD Reserved20_IRQHandler ;Reserved interrupt
<> 144:ef7eb2e8f9f7 97 DCD FTFA_IRQHandler ;FTFA command complete and read collision
<> 144:ef7eb2e8f9f7 98 DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning
<> 144:ef7eb2e8f9f7 99 DCD LLWU_IRQHandler ;Low Leakage Wakeup
<> 144:ef7eb2e8f9f7 100 DCD I2C0_IRQHandler ;I2C0 interrupt
<> 144:ef7eb2e8f9f7 101 DCD I2C1_IRQHandler ;I2C1 interrupt
<> 144:ef7eb2e8f9f7 102 DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 103 DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 104 DCD UART0_IRQHandler ;UART0 status and error
<> 144:ef7eb2e8f9f7 105 DCD UART1_IRQHandler ;UART1 status and error
<> 144:ef7eb2e8f9f7 106 DCD UART2_IRQHandler ;UART2 status and error
<> 144:ef7eb2e8f9f7 107 DCD ADC0_IRQHandler ;ADC0 interrupt
<> 144:ef7eb2e8f9f7 108 DCD CMP0_IRQHandler ;CMP0 interrupt
<> 144:ef7eb2e8f9f7 109 DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 110 DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 111 DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 112 DCD RTC_IRQHandler ;RTC alarm interrupt
<> 144:ef7eb2e8f9f7 113 DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt
<> 144:ef7eb2e8f9f7 114 DCD PIT_IRQHandler ;PIT single interrupt vector for all channels
<> 144:ef7eb2e8f9f7 115 DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources
<> 144:ef7eb2e8f9f7 116 DCD USB0_IRQHandler ;USB0 OTG
<> 144:ef7eb2e8f9f7 117 DCD DAC0_IRQHandler ;DAC0 interrupt
<> 144:ef7eb2e8f9f7 118 DCD TSI0_IRQHandler ;TSI0 interrupt
<> 144:ef7eb2e8f9f7 119 DCD MCG_IRQHandler ;MCG interrupt
<> 144:ef7eb2e8f9f7 120 DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
<> 144:ef7eb2e8f9f7 121 DCD Reserved45_IRQHandler ;Reserved interrupt
<> 144:ef7eb2e8f9f7 122 DCD PORTA_IRQHandler ;PORTA pin detect
<> 144:ef7eb2e8f9f7 123 DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect
<> 144:ef7eb2e8f9f7 124 __Vectors_End
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 SECTION FlashConfig:CODE
<> 144:ef7eb2e8f9f7 127 __FlashConfig
<> 144:ef7eb2e8f9f7 128 DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 129 DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 130 DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 131 DCD 0xFFFFFFFE
<> 144:ef7eb2e8f9f7 132 __FlashConfig_End
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 __Vectors EQU __vector_table
<> 144:ef7eb2e8f9f7 135 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 139 ;;
<> 144:ef7eb2e8f9f7 140 ;; Default interrupt handlers.
<> 144:ef7eb2e8f9f7 141 ;;
<> 144:ef7eb2e8f9f7 142 THUMB
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 PUBWEAK Reset_Handler
<> 144:ef7eb2e8f9f7 145 SECTION .text:CODE:REORDER:NOROOT(2)
<> 144:ef7eb2e8f9f7 146 Reset_Handler
<> 144:ef7eb2e8f9f7 147 CPSID I ; Mask interrupts
<> 144:ef7eb2e8f9f7 148 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 149 BLX R0
<> 144:ef7eb2e8f9f7 150 LDR R0, =init_data_bss
<> 144:ef7eb2e8f9f7 151 BLX R0
<> 144:ef7eb2e8f9f7 152 CPSIE I ; Unmask interrupts
<> 144:ef7eb2e8f9f7 153 LDR R0, =__iar_program_start
<> 144:ef7eb2e8f9f7 154 BX R0
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 PUBWEAK NMI_Handler
<> 144:ef7eb2e8f9f7 157 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 158 NMI_Handler
<> 144:ef7eb2e8f9f7 159 B .
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 PUBWEAK HardFault_Handler
<> 144:ef7eb2e8f9f7 162 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 163 HardFault_Handler
<> 144:ef7eb2e8f9f7 164 B .
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 PUBWEAK SVC_Handler
<> 144:ef7eb2e8f9f7 167 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 168 SVC_Handler
<> 144:ef7eb2e8f9f7 169 B .
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 PUBWEAK PendSV_Handler
<> 144:ef7eb2e8f9f7 172 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 173 PendSV_Handler
<> 144:ef7eb2e8f9f7 174 B .
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 PUBWEAK SysTick_Handler
<> 144:ef7eb2e8f9f7 177 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 178 SysTick_Handler
<> 144:ef7eb2e8f9f7 179 B .
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 PUBWEAK DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 182 PUBWEAK DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 183 PUBWEAK DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 184 PUBWEAK DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 185 PUBWEAK Reserved20_IRQHandler
<> 144:ef7eb2e8f9f7 186 PUBWEAK FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 187 PUBWEAK LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 188 PUBWEAK LLWU_IRQHandler
<> 144:ef7eb2e8f9f7 189 PUBWEAK I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 190 PUBWEAK I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 191 PUBWEAK SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 192 PUBWEAK SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 193 PUBWEAK UART0_IRQHandler
<> 144:ef7eb2e8f9f7 194 PUBWEAK UART1_IRQHandler
<> 144:ef7eb2e8f9f7 195 PUBWEAK UART2_IRQHandler
<> 144:ef7eb2e8f9f7 196 PUBWEAK ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 197 PUBWEAK CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 198 PUBWEAK TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 199 PUBWEAK TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 200 PUBWEAK TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 201 PUBWEAK RTC_IRQHandler
<> 144:ef7eb2e8f9f7 202 PUBWEAK RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 203 PUBWEAK PIT_IRQHandler
<> 144:ef7eb2e8f9f7 204 PUBWEAK I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 205 PUBWEAK USB0_IRQHandler
<> 144:ef7eb2e8f9f7 206 PUBWEAK DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 207 PUBWEAK TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 208 PUBWEAK MCG_IRQHandler
<> 144:ef7eb2e8f9f7 209 PUBWEAK LPTMR0_IRQHandler
<> 144:ef7eb2e8f9f7 210 PUBWEAK Reserved45_IRQHandler
<> 144:ef7eb2e8f9f7 211 PUBWEAK PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 212 PUBWEAK PORTC_PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 213 PUBWEAK DefaultISR
<> 144:ef7eb2e8f9f7 214 SECTION .text:CODE:REORDER:NOROOT(2)
<> 144:ef7eb2e8f9f7 215 DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 216 DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 217 DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 218 DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 219 Reserved20_IRQHandler
<> 144:ef7eb2e8f9f7 220 FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 221 LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 222 LLWU_IRQHandler
<> 144:ef7eb2e8f9f7 223 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 224 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 225 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 226 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 227 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 228 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 229 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 230 ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 231 CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 232 TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 233 TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 234 TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 235 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 236 RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 237 PIT_IRQHandler
<> 144:ef7eb2e8f9f7 238 I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 239 USB0_IRQHandler
<> 144:ef7eb2e8f9f7 240 DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 241 TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 242 MCG_IRQHandler
<> 144:ef7eb2e8f9f7 243 LPTMR0_IRQHandler
<> 144:ef7eb2e8f9f7 244 Reserved45_IRQHandler
<> 144:ef7eb2e8f9f7 245 PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 246 PORTC_PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 247 DefaultISR
<> 144:ef7eb2e8f9f7 248 LDR R0, =DefaultISR
<> 144:ef7eb2e8f9f7 249 BX R0
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 END