Ben Katz / mbed-dev-f303

mbed library sources. Supersedes mbed-src.

Dependents:   Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/device/clkman_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Type definitions for the Clock Management Interface
<> 157:ff67d9f36b67 4 *
<> 157:ff67d9f36b67 5 */
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24058 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 **************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_CLKMAN_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_CLKMAN_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* **** Includes **** */
<> 157:ff67d9f36b67 47 #include <stdint.h>
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 /// @cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 /// @endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /**
<> 157:ff67d9f36b67 72 * @ingroup clkman
<> 157:ff67d9f36b67 73 * @defgroup clkman_registers Registers
<> 157:ff67d9f36b67 74 * @brief Registers, Bit Masks and Bit Positions
<> 157:ff67d9f36b67 75 * @{
<> 157:ff67d9f36b67 76 */
<> 157:ff67d9f36b67 77
<> 157:ff67d9f36b67 78 /**
<> 157:ff67d9f36b67 79 * Structure type for the Clock Management module registers allowing direct 32-bit access to each register.
<> 157:ff67d9f36b67 80 */
<> 157:ff67d9f36b67 81 typedef struct {
<> 157:ff67d9f36b67 82 __IO uint32_t clk_config; /**< <tt>\b 0x0000: </tt> CLKMAN_CLK_CONFIG Register - System Clock Configuration */
<> 157:ff67d9f36b67 83 __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> CLKMAN_CLK_CTRL Register - System Clock Controls */
<> 157:ff67d9f36b67 84 __IO uint32_t intfl; /**< <tt>\b 0x0008: </tt> CLKMAN_INTFL Register - Interrupt Flags */
<> 157:ff67d9f36b67 85 __IO uint32_t inten; /**< <tt>\b 0x000C: </tt> CLKMAN_INTEN Register - Interrupt Enable/Disable Controls */
<> 157:ff67d9f36b67 86 __IO uint32_t trim_calc; /**< <tt>\b 0x0010: </tt> CLKMAN_TRIM_CALC Register - Trim Calculation Controls */
<> 157:ff67d9f36b67 87 __IO uint32_t i2c_timer_ctrl; /**< <tt>\b 0x0014: </tt> CLKMAN_I2C_TIMER_CTRL Register - I2C Timer Control */
<> 157:ff67d9f36b67 88 __IO uint32_t cm4_start_clk_en0; /**< <tt>\b 0x0018: </tt> CLKMAN_CM4_START_CLK_EN0 Register - CM4 Start Clock on Interrupt Enable 0 */
<> 157:ff67d9f36b67 89 __IO uint32_t cm4_start_clk_en1; /**< <tt>\b 0x001C: </tt> CLKMAN_CM4_START_CLK_EN1 Register - CM4 Start Clock on Interrupt Enable 1 */
<> 157:ff67d9f36b67 90 __IO uint32_t cm4_start_clk_en2; /**< <tt>\b 0x0020: </tt> CLKMAN_CM4_START_CLK_EN2 Register - CM4 Start Clock on Interrupt Enable 2 */
<> 157:ff67d9f36b67 91 __RO uint32_t rsv024[7]; /**< <tt>\b 0x0024-0x003C:</tt> RESERVED */
<> 157:ff67d9f36b67 92 __IO uint32_t sys_clk_ctrl_0_cm4; /**< <tt>\b 0x0040: </tt> CLKMAN_SYS_CLK_CTRL_0_CM4 Register - Cortex M4 Clock */
<> 157:ff67d9f36b67 93 __IO uint32_t sys_clk_ctrl_1_sync; /**< <tt>\b 0x0044: </tt> CLKMAN_SYS_CLK_CTRL_1_SYNC Register - Synchronizer Clock */
<> 157:ff67d9f36b67 94 __IO uint32_t sys_clk_ctrl_2_spix; /**< <tt>\b 0x0048: </tt> CLKMAN_SYS_CLK_CTRL_2_SPIX Register - SPI XIP Clock */
<> 157:ff67d9f36b67 95 __IO uint32_t sys_clk_ctrl_3_prng; /**< <tt>\b 0x004C: </tt> CLKMAN_SYS_CLK_CTRL_3_PRNG Register - PRNG Clock */
<> 157:ff67d9f36b67 96 __IO uint32_t sys_clk_ctrl_4_wdt0; /**< <tt>\b 0x0050: </tt> CLKMAN_SYS_CLK_CTRL_4_WDT0 Register - Watchdog Timer 0 */
<> 157:ff67d9f36b67 97 __IO uint32_t sys_clk_ctrl_5_wdt1; /**< <tt>\b 0x0054: </tt> CLKMAN_SYS_CLK_CTRL_5_WDT1 Register - Watchdog Timer 1 */
<> 157:ff67d9f36b67 98 __IO uint32_t sys_clk_ctrl_6_gpio; /**< <tt>\b 0x0058: </tt> CLKMAN_SYS_CLK_CTRL_6_GPIO Register - Clock for GPIO Ports */
<> 157:ff67d9f36b67 99 __IO uint32_t sys_clk_ctrl_7_pt; /**< <tt>\b 0x005C: </tt> CLKMAN_SYS_CLK_CTRL_7_PT Register - Source Clock for All Pulse Trains */
<> 157:ff67d9f36b67 100 __IO uint32_t sys_clk_ctrl_8_uart; /**< <tt>\b 0x0060: </tt> CLKMAN_SYS_CLK_CTRL_8_UART Register - Source Clock for All UARTs */
<> 157:ff67d9f36b67 101 __IO uint32_t sys_clk_ctrl_9_i2cm; /**< <tt>\b 0x0064: </tt> CLKMAN_SYS_CLK_CTRL_9_I2CM Register - Source Clock for All I2C Masters */
<> 157:ff67d9f36b67 102 __IO uint32_t sys_clk_ctrl_10_i2cs; /**< <tt>\b 0x0068: </tt> CLKMAN_SYS_CLK_CTRL_10_I2CS Register - Source Clock for I2C Slave */
<> 157:ff67d9f36b67 103 __IO uint32_t sys_clk_ctrl_11_spi0; /**< <tt>\b 0x006C: </tt> CLKMAN_SYS_CLK_CTRL_11_SPI0 Register - SPI Master 0 */
<> 157:ff67d9f36b67 104 __IO uint32_t sys_clk_ctrl_12_spi1; /**< <tt>\b 0x0070: </tt> CLKMAN_SYS_CLK_CTRL_12_SPI1 Register - SPI Master 1 */
<> 157:ff67d9f36b67 105 __IO uint32_t sys_clk_ctrl_13_spi2; /**< <tt>\b 0x0074: </tt> CLKMAN_SYS_CLK_CTRL_13_SPI2 Register - SPI Master 2 */
<> 157:ff67d9f36b67 106 __IO uint32_t sys_clk_ctrl_14_spib; /**< <tt>\b 0x0078: </tt> CLKMAN_SYS_CLK_CTRL_14_SPIB Register - SPI Bridge Clock */
<> 157:ff67d9f36b67 107 __IO uint32_t sys_clk_ctrl_15_owm; /**< <tt>\b 0x007C: </tt> CLKMAN_SYS_CLK_CTRL_15_OWM Register - 1-Wire Master Clock */
<> 157:ff67d9f36b67 108 __IO uint32_t sys_clk_ctrl_16_spis; /**< <tt>\b 0x0080: </tt> CLKMAN_SYS_CLK_CTRL_16_SPIS Register - SPI Slave Clock */
<> 157:ff67d9f36b67 109 __RO uint32_t rsv084[31]; /**< <tt>\b 0x0084-0x00FC:</tt> RESERVED: */
<> 157:ff67d9f36b67 110 __IO uint32_t crypt_clk_ctrl_0_aes; /**< <tt>\b 0x0100: </tt> CLKMAN_CRYPT_CLK_CTRL_0_AES Register - AES */
<> 157:ff67d9f36b67 111 __IO uint32_t crypt_clk_ctrl_1_maa; /**< <tt>\b 0x0104: </tt> CLKMAN_CRYPT_CLK_CTRL_1_MAA Register - MAA */
<> 157:ff67d9f36b67 112 __IO uint32_t crypt_clk_ctrl_2_prng; /**< <tt>\b 0x0108: </tt> CLKMAN_CRYPT_CLK_CTRL_2_PRNG Register - PRNG */
<> 157:ff67d9f36b67 113 __RO uint32_t rsv10C[13]; /**< <tt>\b 0x010C-0x013C:</tt> RESERVED */
<> 157:ff67d9f36b67 114 __IO uint32_t clk_gate_ctrl0; /**< <tt>\b 0x0140: </tt> CLKMAN_CLK_GATE_CTRL0 Register - Dynamic Clock Gating Control Register 0 */
<> 157:ff67d9f36b67 115 __IO uint32_t clk_gate_ctrl1; /**< <tt>\b 0x0144: </tt> CLKMAN_CLK_GATE_CTRL1 Register - Dynamic Clock Gating Control Register 1 */
<> 157:ff67d9f36b67 116 __IO uint32_t clk_gate_ctrl2; /**< <tt>\b 0x0148: </tt> CLKMAN_CLK_GATE_CTRL2 Register - Dynamic Clock Gating Control Register 2 */
<> 157:ff67d9f36b67 117 } mxc_clkman_regs_t;
<> 157:ff67d9f36b67 118 /**@} end of clkman_registers */
<> 157:ff67d9f36b67 119
<> 157:ff67d9f36b67 120 /*
<> 157:ff67d9f36b67 121 Register offsets for module CLKMAN.
<> 157:ff67d9f36b67 122 */
<> 157:ff67d9f36b67 123 /**
<> 157:ff67d9f36b67 124 * @ingroup clkman_registers
<> 157:ff67d9f36b67 125 * @defgroup CLKMAN_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 126 * @brief Clock Management Controller Register Offsets from the CLKMAN Base Peripheral Address.
<> 157:ff67d9f36b67 127 * @{
<> 157:ff67d9f36b67 128 */
<> 157:ff67d9f36b67 129 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 130 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 131 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0008</tt> */
<> 157:ff67d9f36b67 132 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x000C</tt> */
<> 157:ff67d9f36b67 133 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0010</tt> */
<> 157:ff67d9f36b67 134 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0014</tt> */
<> 157:ff67d9f36b67 135 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0018</tt> */
<> 157:ff67d9f36b67 136 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x001C</tt> */
<> 157:ff67d9f36b67 137 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0020</tt> */
<> 157:ff67d9f36b67 138 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0040</tt> */
<> 157:ff67d9f36b67 139 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0044</tt> */
<> 157:ff67d9f36b67 140 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0048</tt> */
<> 157:ff67d9f36b67 141 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x004C</tt> */
<> 157:ff67d9f36b67 142 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0050</tt> */
<> 157:ff67d9f36b67 143 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0054</tt> */
<> 157:ff67d9f36b67 144 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0058</tt> */
<> 157:ff67d9f36b67 145 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x005C</tt> */
<> 157:ff67d9f36b67 146 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0060</tt> */
<> 157:ff67d9f36b67 147 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0064</tt> */
<> 157:ff67d9f36b67 148 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0068</tt> */
<> 157:ff67d9f36b67 149 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x006C</tt> */
<> 157:ff67d9f36b67 150 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0070</tt> */
<> 157:ff67d9f36b67 151 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0074</tt> */
<> 157:ff67d9f36b67 152 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0078</tt> */
<> 157:ff67d9f36b67 153 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x007C</tt> */
<> 157:ff67d9f36b67 154 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0080</tt> */
<> 157:ff67d9f36b67 155 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0100</tt> */
<> 157:ff67d9f36b67 156 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0104</tt> */
<> 157:ff67d9f36b67 157 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0108</tt> */
<> 157:ff67d9f36b67 158 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0140</tt> */
<> 157:ff67d9f36b67 159 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0144</tt> */
<> 157:ff67d9f36b67 160 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0148</tt> */
<> 157:ff67d9f36b67 161 /**@} end of CLKMAN_Register_Offsets */
<> 157:ff67d9f36b67 162 /**
<> 157:ff67d9f36b67 163 * @ingroup clkman_registers
<> 157:ff67d9f36b67 164 * @defgroup clkman_clk_config CLKMAN_CLK_CONFIG Register
<> 157:ff67d9f36b67 165 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 166 */
<> 157:ff67d9f36b67 167 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 /**< CRYPTO_ENABLE Position */
<> 157:ff67d9f36b67 168 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) /**< CRYPTO_ENABLE Mask */
<> 157:ff67d9f36b67 169 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 /**< CRYPTO_STABILITY_COUNT Position */
<> 157:ff67d9f36b67 170 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Mask */
<> 157:ff67d9f36b67 171 /**@}*/
<> 157:ff67d9f36b67 172 /**
<> 157:ff67d9f36b67 173 * @ingroup clkman_registers
<> 157:ff67d9f36b67 174 * @defgroup clkman_clk_ctrl CLKMAN_CLK_CTRL Register
<> 157:ff67d9f36b67 175 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 176 */
<> 157:ff67d9f36b67 177 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 /**< SYSTEM_SOURCE_SELECT Position */
<> 157:ff67d9f36b67 178 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< SYSTEM_SOURCE_SELECT Mask */
<> 157:ff67d9f36b67 179 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 /**< USB_CLOCK_ENABLE Position */
<> 157:ff67d9f36b67 180 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) /**< USB_CLOCK_ENABLE Mask */
<> 157:ff67d9f36b67 181 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 /**< USB_CLOCK_SELECT Position */
<> 157:ff67d9f36b67 182 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) /**< USB_CLOCK_SELECT Mask */
<> 157:ff67d9f36b67 183 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 /**< CRYPTO_CLOCK_ENABLE Position */
<> 157:ff67d9f36b67 184 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) /**< CRYPTO_CLOCK_ENABLE Mask */
<> 157:ff67d9f36b67 185 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 /**< RTOS_MODE Field Position */
<> 157:ff67d9f36b67 186 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) /**< RTOS_MODE Field Mask */
<> 157:ff67d9f36b67 187 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13 /**< CPU_DYNAMIC_CLOCK Field Position */
<> 157:ff67d9f36b67 188 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS)) /**< CPU_DYNAMIC_CLOCK Field Mask */
<> 157:ff67d9f36b67 189 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 /**< WDT0_CLOCK_ENABLE Field Position */
<> 157:ff67d9f36b67 190 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) /**< WDT0_CLOCK_ENABLE Field Mask */
<> 157:ff67d9f36b67 191 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 /**< WDT0_CLOCK_SELECT Field Position */
<> 157:ff67d9f36b67 192 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) /**< WDT0_CLOCK_SELECT Field Mask */
<> 157:ff67d9f36b67 193 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 /**< WDT1_CLOCK_ENABLE Field Position */
<> 157:ff67d9f36b67 194 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) /**< WDT1_CLOCK_ENABLE Field Mask */
<> 157:ff67d9f36b67 195 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 /**< WDT1_CLOCK_SELECT Field Position */
<> 157:ff67d9f36b67 196 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) /**< WDT1_CLOCK_SELECT Field Mask */
<> 157:ff67d9f36b67 197 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 /**< ADC_CLOCK_ENABLE Field Position */
<> 157:ff67d9f36b67 198 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) /**< ADC_CLOCK_ENABLE Field Mask */
<> 157:ff67d9f36b67 199 /**@}*/
<> 157:ff67d9f36b67 200 /**
<> 157:ff67d9f36b67 201 * @ingroup clkman_registers
<> 157:ff67d9f36b67 202 * @defgroup clkman_int_flags CLKMAN_INTFL Register
<> 157:ff67d9f36b67 203 * @brief Interrupt Flag Positions and Masks
<> 157:ff67d9f36b67 204 */
<> 157:ff67d9f36b67 205 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Interrupt Flag Position */
<> 157:ff67d9f36b67 206 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Interrupt Flag Mask */
<> 157:ff67d9f36b67 207 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Interrupt Flag Position */
<> 157:ff67d9f36b67 208 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Interrupt Flag Mask */
<> 157:ff67d9f36b67 209 /**@}*/
<> 157:ff67d9f36b67 210 /**
<> 157:ff67d9f36b67 211 * @ingroup clkman_registers
<> 157:ff67d9f36b67 212 * @defgroup clkman_int_enable CLKMAN_INTEN Register
<> 157:ff67d9f36b67 213 * @brief Interrupt Enable Positions and Masks
<> 157:ff67d9f36b67 214 */
<> 157:ff67d9f36b67 215 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Field Position */
<> 157:ff67d9f36b67 216 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Field Mask */
<> 157:ff67d9f36b67 217 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Field Position */
<> 157:ff67d9f36b67 218 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Field Mask */
<> 157:ff67d9f36b67 219 /**@}*/
<> 157:ff67d9f36b67 220 /**
<> 157:ff67d9f36b67 221 * @ingroup clkman_registers
<> 157:ff67d9f36b67 222 * @defgroup clkman_trim_calc CLKMAN_TRIM_CALC Register
<> 157:ff67d9f36b67 223 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 224 */
<> 157:ff67d9f36b67 225 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 /**< TRIM_CLK_SEL Field Position */
<> 157:ff67d9f36b67 226 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) /**< TRIM_CLK_SEL Field Mask */
<> 157:ff67d9f36b67 227 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 /**< TRIM_CALC_START Field Position */
<> 157:ff67d9f36b67 228 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) /**< TRIM_CALC_START Field Mask */
<> 157:ff67d9f36b67 229 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 /**< TRIM_CALC_COMPLETED Field Position */
<> 157:ff67d9f36b67 230 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) /**< TRIM_CALC_COMPLETED Field Mask */
<> 157:ff67d9f36b67 231 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 /**< TRIM_ENABLE Field Position */
<> 157:ff67d9f36b67 232 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) /**< TRIM_ENABLE Field Mask */
<> 157:ff67d9f36b67 233 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 /**< TRIM_CALC_RESULTS Field Position */
<> 157:ff67d9f36b67 234 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) /**< TRIM_CALC_RESULTS Field Mask */
<> 157:ff67d9f36b67 235 /**@}*/
<> 157:ff67d9f36b67 236 /**
<> 157:ff67d9f36b67 237 * @ingroup clkman_registers
<> 157:ff67d9f36b67 238 * @defgroup clkman_i2c_1ms CLKMAN_I2C_TIMER_CTRL Register
<> 157:ff67d9f36b67 239 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 240 */
<> 157:ff67d9f36b67 241 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 /**< I2C_1MS_TIMER_EN Position */
<> 157:ff67d9f36b67 242 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) /**< I2C_1MS_TIMER_EN Mask */
<> 157:ff67d9f36b67 243 /**@}*/
<> 157:ff67d9f36b67 244 /**
<> 157:ff67d9f36b67 245 * @ingroup clkman_registers
<> 157:ff67d9f36b67 246 * @defgroup clkman_cm4 CLKMAN_CM4 Register
<> 157:ff67d9f36b67 247 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 248 */
<> 157:ff67d9f36b67 249 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 /**< CLK_EN0_INTS Position */
<> 157:ff67d9f36b67 250 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) /**< CLK_EN0_INTS Mask */
<> 157:ff67d9f36b67 251
<> 157:ff67d9f36b67 252 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 /**< CLK_EN1_INTS Position */
<> 157:ff67d9f36b67 253 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) /**< CLK_EN1_INTS Mask */
<> 157:ff67d9f36b67 254
<> 157:ff67d9f36b67 255 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0 /**< CLK_EN2_INTS Position */
<> 157:ff67d9f36b67 256 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS)) /**< CLK_EN2_INTS Mask */
<> 157:ff67d9f36b67 257 /**@}*/
<> 157:ff67d9f36b67 258 /**
<> 157:ff67d9f36b67 259 * @ingroup clkman_registers
<> 157:ff67d9f36b67 260 * @defgroup clkman_sysclk_ctrl CLKMAN_SYS_CLK_CTRL Register
<> 157:ff67d9f36b67 261 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 262 */
<> 157:ff67d9f36b67 263 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 /**< CM4_CM4_CLK_SCALE Position */
<> 157:ff67d9f36b67 264 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) /**< CM4_CM4_CLK_SCALE Mask */
<> 157:ff67d9f36b67 265 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 /**< SYNC_SYNC_CLK_SCALE Position */
<> 157:ff67d9f36b67 266 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) /**< SYNC_SYNC_CLK_SCALE Mask */
<> 157:ff67d9f36b67 267 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 /**< SPIX_SPIX_CLK_SCALE Position */
<> 157:ff67d9f36b67 268 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) /**< SPIX_SPIX_CLK_SCALE Mask */
<> 157:ff67d9f36b67 269 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
<> 157:ff67d9f36b67 270 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
<> 157:ff67d9f36b67 271 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 /**< WDT0_WATCHDOG0_CLK_ Position */
<> 157:ff67d9f36b67 272 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) /**< WDT0_WATCHDOG0_CLK_ Mask */
<> 157:ff67d9f36b67 273 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 /**< WDT1_WATCHDOG1_CLK_ Position */
<> 157:ff67d9f36b67 274 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) /**< WDT1_WATCHDOG1_CLK_ Mask */
<> 157:ff67d9f36b67 275 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 /**< GPIO_GPIO_CLK_SCALE Position */
<> 157:ff67d9f36b67 276 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) /**< GPIO_GPIO_CLK_SCALE Mask */
<> 157:ff67d9f36b67 277 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 /**< PT_PULSE_TRAIN_CLK_ Position */
<> 157:ff67d9f36b67 278 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) /**< PT_PULSE_TRAIN_CLK_ Mask */
<> 157:ff67d9f36b67 279 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 /**< UART_UART_CLK_SCALE Position */
<> 157:ff67d9f36b67 280 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) /**< UART_UART_CLK_SCALE Mask */
<> 157:ff67d9f36b67 281 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 /**< I2CM_I2CM_CLK_SCALE Position */
<> 157:ff67d9f36b67 282 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) /**< I2CM_I2CM_CLK_SCALE Mask */
<> 157:ff67d9f36b67 283 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 /**< I2CS_I2CS_CLK_SCALE Position */
<> 157:ff67d9f36b67 284 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) /**< I2CS_I2CS_CLK_SCALE Mask */
<> 157:ff67d9f36b67 285 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 /**< PI0_SPI0_CLK_SCALE Position */
<> 157:ff67d9f36b67 286 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) /**< SPI0_SPI0_CLK_SCALE Mask */
<> 157:ff67d9f36b67 287 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 /**< SPI1_SPI1_CLK_SCALE Position */
<> 157:ff67d9f36b67 288 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) /**< SPI1_SPI1_CLK_SCALE Mask */
<> 157:ff67d9f36b67 289 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 /**< SPI2_SPI2_CLK_SCALE Position */
<> 157:ff67d9f36b67 290 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) /**< SPI2_SPI2_CLK_SCALE Mask */
<> 157:ff67d9f36b67 291 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 /**< SPIB_SPIB_CLK_SCALE Position */
<> 157:ff67d9f36b67 292 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) /**< SPIB_SPIB_CLK_SCALE Mask */
<> 157:ff67d9f36b67 293 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 /**< OWM_OWM_CLK_SCALE Position */
<> 157:ff67d9f36b67 294 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) /**< OWM_OWM_CLK_SCALE Mask */
<> 157:ff67d9f36b67 295 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0 /**< PIS_SPIS_CLK_SCALE Position */
<> 157:ff67d9f36b67 296 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS)) /**< SPIS_SPIS_CLK_SCALE Mask */
<> 157:ff67d9f36b67 297 /**@}*/
<> 157:ff67d9f36b67 298 /**
<> 157:ff67d9f36b67 299 * @ingroup clkman_registers
<> 157:ff67d9f36b67 300 * @defgroup clkman_crypt_clk_ctrl CLKMAN_CRYPT_CLK_CTRL Register
<> 157:ff67d9f36b67 301 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 302 */
<> 157:ff67d9f36b67 303 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 /**< AES_AES_CLK_SCALE Position */
<> 157:ff67d9f36b67 304 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) /**< AES_AES_CLK_SCALE Mask */
<> 157:ff67d9f36b67 305 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 /**< MAA_MAA_CLK_SCALE Position */
<> 157:ff67d9f36b67 306 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) /**< MAA_MAA_CLK_SCALE Mask */
<> 157:ff67d9f36b67 307 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
<> 157:ff67d9f36b67 308 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
<> 157:ff67d9f36b67 309 /**@}*/
<> 157:ff67d9f36b67 310 /**
<> 157:ff67d9f36b67 311 * @ingroup clkman_registers
<> 157:ff67d9f36b67 312 * @defgroup clkman_clk_gate_ctrl CLKMAN_CLK_GATE_CTRL Register
<> 157:ff67d9f36b67 313 * @brief Peripheral Clock Gating Field Positions and Masks
<> 157:ff67d9f36b67 314 */
<> 157:ff67d9f36b67 315 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 /**< CM4_CLK_GATER Position */
<> 157:ff67d9f36b67 316 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) /**< CM4_CLK_GATER Mask */
<> 157:ff67d9f36b67 317 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 /**< AHB32_CLK_GATER Position */
<> 157:ff67d9f36b67 318 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) /**< AHB32_CLK_GATER Mask */
<> 157:ff67d9f36b67 319 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 /**< ICACHE_CLK_GATER Position */
<> 157:ff67d9f36b67 320 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) /**< ICACHE_CLK_GATER Mask */
<> 157:ff67d9f36b67 321 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 /**< FLASH_CLK_GATER Position */
<> 157:ff67d9f36b67 322 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) /**< FLASH_CLK_GATER Mask */
<> 157:ff67d9f36b67 323 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 /**< SRAM_CLK_GATER Position */
<> 157:ff67d9f36b67 324 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) /**< SRAM_CLK_GATER Mask */
<> 157:ff67d9f36b67 325 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 /**< APB_BRIDGE_CLK_GATER Position */
<> 157:ff67d9f36b67 326 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) /**< APB_BRIDGE_CLK_GATER Mask */
<> 157:ff67d9f36b67 327 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 /**< SYSMAN_CLK_GATER Position */
<> 157:ff67d9f36b67 328 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) /**< SYSMAN_CLK_GATER Mask */
<> 157:ff67d9f36b67 329 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 /**< PTP_CLK_GATER Position */
<> 157:ff67d9f36b67 330 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) /**< PTP_CLK_GATER Mask */
<> 157:ff67d9f36b67 331 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 /**< SSB_MUX_CLK_GATER Position */
<> 157:ff67d9f36b67 332 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) /**< SSB_MUX_CLK_GATER Mask */
<> 157:ff67d9f36b67 333 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 /**< PAD_CLK_GATER Position */
<> 157:ff67d9f36b67 334 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) /**< PAD_CLK_GATER Mask */
<> 157:ff67d9f36b67 335 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 /**< SPIX_CLK_GATER Position */
<> 157:ff67d9f36b67 336 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) /**< SPIX_CLK_GATER Mask */
<> 157:ff67d9f36b67 337 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 /**< PMU_CLK_GATER Position */
<> 157:ff67d9f36b67 338 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) /**< PMU_CLK_GATER Mask */
<> 157:ff67d9f36b67 339 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 /**< USB_CLK_GATER Position */
<> 157:ff67d9f36b67 340 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) /**< USB_CLK_GATER Mask */
<> 157:ff67d9f36b67 341 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 /**< CRC_CLK_GATER Position */
<> 157:ff67d9f36b67 342 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) /**< CRC_CLK_GATER Mask */
<> 157:ff67d9f36b67 343 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 /**< TPU_CLK_GATER Position */
<> 157:ff67d9f36b67 344 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) /**< TPU_CLK_GATER Mask */
<> 157:ff67d9f36b67 345 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 /**< WATCHDOG0_CLK_GATER Position */
<> 157:ff67d9f36b67 346 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) /**< WATCHDOG0_CLK_GATER Mask */
<> 157:ff67d9f36b67 347 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 /**< WATCHDOG1_CLK_GATER Position */
<> 157:ff67d9f36b67 348 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) /**< WATCHDOG1_CLK_GATER Mask */
<> 157:ff67d9f36b67 349 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 /**< GPIO_CLK_GATER Position */
<> 157:ff67d9f36b67 350 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) /**< GPIO_CLK_GATER Mask */
<> 157:ff67d9f36b67 351 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 /**< TIMER0_CLK_GATER Position */
<> 157:ff67d9f36b67 352 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) /**< TIMER0_CLK_GATER Mask */
<> 157:ff67d9f36b67 353 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 /**< TIMER1_CLK_GATER Position */
<> 157:ff67d9f36b67 354 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) /**< TIMER1_CLK_GATER Mask */
<> 157:ff67d9f36b67 355 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 /**< TIMER2_CLK_GATER Position */
<> 157:ff67d9f36b67 356 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) /**< TIMER2_CLK_GATER Mask */
<> 157:ff67d9f36b67 357 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 /**< TIMER3_CLK_GATER Position */
<> 157:ff67d9f36b67 358 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) /**< TIMER3_CLK_GATER Mask */
<> 157:ff67d9f36b67 359 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 /**< TIMER4_CLK_GATER Position */
<> 157:ff67d9f36b67 360 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) /**< TIMER4_CLK_GATER Mask */
<> 157:ff67d9f36b67 361 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 /**< TIMER5_CLK_GATER Position */
<> 157:ff67d9f36b67 362 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) /**< TIMER5_CLK_GATER Mask */
<> 157:ff67d9f36b67 363 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 /**< PULSETRAIN_CLK_GATER Position */
<> 157:ff67d9f36b67 364 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) /**< PULSETRAIN_CLK_GATER Mask */
<> 157:ff67d9f36b67 365 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 /**< UART0_CLK_GATER Position */
<> 157:ff67d9f36b67 366 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) /**< UART0_CLK_GATER Mask */
<> 157:ff67d9f36b67 367 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 /**< UART1_CLK_GATER Position */
<> 157:ff67d9f36b67 368 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) /**< UART1_CLK_GATER Mask */
<> 157:ff67d9f36b67 369 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 /**< UART2_CLK_GATER Position */
<> 157:ff67d9f36b67 370 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) /**< UART2_CLK_GATER Mask */
<> 157:ff67d9f36b67 371 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 /**< UART3_CLK_GATER Position */
<> 157:ff67d9f36b67 372 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) /**< UART3_CLK_GATER Mask */
<> 157:ff67d9f36b67 373 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 /**< I2CM0_CLK_GATER Position */
<> 157:ff67d9f36b67 374 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) /**< I2CM0_CLK_GATER Mask */
<> 157:ff67d9f36b67 375 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 /**< I2CM1_CLK_GATER Position */
<> 157:ff67d9f36b67 376 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) /**< I2CM1_CLK_GATER Mask */
<> 157:ff67d9f36b67 377 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 /**< I2CM2_CLK_GATER Position */
<> 157:ff67d9f36b67 378 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) /**< I2CM2_CLK_GATER Mask */
<> 157:ff67d9f36b67 379 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 /**< I2CS_CLK_GATER Position */
<> 157:ff67d9f36b67 380 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) /**< I2CS_CLK_GATER Mask */
<> 157:ff67d9f36b67 381 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 /**< SPI0_CLK_GATER Position */
<> 157:ff67d9f36b67 382 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) /**< SPI0_CLK_GATER Mask */
<> 157:ff67d9f36b67 383 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 /**< SPI1_CLK_GATER Position */
<> 157:ff67d9f36b67 384 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) /**< SPI1_CLK_GATER Mask */
<> 157:ff67d9f36b67 385 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 /**< SPI2_CLK_GATER Position */
<> 157:ff67d9f36b67 386 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) /**< SPI2_CLK_GATER Mask */
<> 157:ff67d9f36b67 387 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 /**< SPI_BRIDGE_CLK_GATER Position */
<> 157:ff67d9f36b67 388 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) /**< SPI_BRIDGE_CLK_GATER Mask */
<> 157:ff67d9f36b67 389 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 /**< OWM_CLK_GATER Position */
<> 157:ff67d9f36b67 390 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) /**< OWM_CLK_GATER Mask */
<> 157:ff67d9f36b67 391 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 /**< ADC_CLK_GATER Position */
<> 157:ff67d9f36b67 392 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) /**< ADC_CLK_GATER Mask */
<> 157:ff67d9f36b67 393 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14 /**< SPIS_CLK_GATER Position */
<> 157:ff67d9f36b67 394 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS)) /**< SPIS_CLK_GATER Mask */
<> 157:ff67d9f36b67 395 /**@}*/
<> 157:ff67d9f36b67 396 /**
<> 157:ff67d9f36b67 397 * @ingroup clkman_clk_config
<> 157:ff67d9f36b67 398 * @defgroup clkman_crypto_stability_count CRYPTO_STABILITY_COUNT Value Settings and Shifted Value Settings
<> 157:ff67d9f36b67 399 * @brief Crypto Clock Stability Count Setting Values and Shifted Values
<> 157:ff67d9f36b67 400 */
<> 157:ff67d9f36b67 401 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>8</SUP> */
<> 157:ff67d9f36b67 402 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>9</SUP> */
<> 157:ff67d9f36b67 403 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>10</SUP> */
<> 157:ff67d9f36b67 404 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>11</SUP> */
<> 157:ff67d9f36b67 405 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>12</SUP> */
<> 157:ff67d9f36b67 406 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>13</SUP> */
<> 157:ff67d9f36b67 407 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>14</SUP> */
<> 157:ff67d9f36b67 408 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>15</SUP> */
<> 157:ff67d9f36b67 409 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>16</SUP> */
<> 157:ff67d9f36b67 410 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>17</SUP> */
<> 157:ff67d9f36b67 411 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>18</SUP> */
<> 157:ff67d9f36b67 412 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>19</SUP> */
<> 157:ff67d9f36b67 413 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>20</SUP> */
<> 157:ff67d9f36b67 414 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>21</SUP> */
<> 157:ff67d9f36b67 415 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>22</SUP> */
<> 157:ff67d9f36b67 416 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>23</SUP> */
<> 157:ff67d9f36b67 417
<> 157:ff67d9f36b67 418 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>8</SUP> */
<> 157:ff67d9f36b67 419 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>9</SUP> */
<> 157:ff67d9f36b67 420 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>10</SUP> */
<> 157:ff67d9f36b67 421 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>11</SUP> */
<> 157:ff67d9f36b67 422 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>12</SUP> */
<> 157:ff67d9f36b67 423 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>13</SUP> */
<> 157:ff67d9f36b67 424 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>14</SUP> */
<> 157:ff67d9f36b67 425 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>15</SUP> */
<> 157:ff67d9f36b67 426 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>16</SUP> */
<> 157:ff67d9f36b67 427 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>17</SUP> */
<> 157:ff67d9f36b67 428 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>18</SUP> */
<> 157:ff67d9f36b67 429 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>19</SUP> */
<> 157:ff67d9f36b67 430 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>20</SUP> */
<> 157:ff67d9f36b67 431 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>21</SUP> */
<> 157:ff67d9f36b67 432 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>22</SUP> */
<> 157:ff67d9f36b67 433 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>23</SUP> */
<> 157:ff67d9f36b67 434
<> 157:ff67d9f36b67 435 /**@} clkman_crypto_stability_count */
<> 157:ff67d9f36b67 436
<> 157:ff67d9f36b67 437 /**
<> 157:ff67d9f36b67 438 * @ingroup clkman_clk_ctrl
<> 157:ff67d9f36b67 439 * @defgroup clkman_sysclock_select System Clock Select Values
<> 157:ff67d9f36b67 440 * @brief System Clock Selection Values and Shifted Values for selecting the system clock source
<> 157:ff67d9f36b67 441 * @{
<> 157:ff67d9f36b67 442 */
<> 157:ff67d9f36b67 443 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
<> 157:ff67d9f36b67 444 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO */
<> 157:ff67d9f36b67 445 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
<> 157:ff67d9f36b67 446 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO */
<> 157:ff67d9f36b67 447 /**@} end of clkman_sysclock_select group */
<> 157:ff67d9f36b67 448 ///@cond
<> 157:ff67d9f36b67 449
<> 157:ff67d9f36b67 450 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
<> 157:ff67d9f36b67 451 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
<> 157:ff67d9f36b67 452 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
<> 157:ff67d9f36b67 453 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
<> 157:ff67d9f36b67 454 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 455 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 456 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 457 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 458 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
<> 157:ff67d9f36b67 459 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
<> 157:ff67d9f36b67 460 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
<> 157:ff67d9f36b67 461 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
<> 157:ff67d9f36b67 462 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 463 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 464 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 465 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
<> 157:ff67d9f36b67 466 #define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
<> 157:ff67d9f36b67 467 #define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
<> 157:ff67d9f36b67 468 #define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
<> 157:ff67d9f36b67 469 #define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
<> 157:ff67d9f36b67 470 #define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
<> 157:ff67d9f36b67 471 #define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
<> 157:ff67d9f36b67 472 #define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
<> 157:ff67d9f36b67 473 #define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
<> 157:ff67d9f36b67 474 #define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
<> 157:ff67d9f36b67 475 #define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
<> 157:ff67d9f36b67 476 #define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 477 #define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 478 #define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 479 #define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 480 #define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 481 #define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 482 #define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 483 #define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 484 #define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 485 #define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
<> 157:ff67d9f36b67 486 ///@endcond
<> 157:ff67d9f36b67 487
<> 157:ff67d9f36b67 488 #ifdef __cplusplus
<> 157:ff67d9f36b67 489 }
<> 157:ff67d9f36b67 490 #endif
<> 157:ff67d9f36b67 491
<> 157:ff67d9f36b67 492 #endif /* _MXC_CLKMAN_REGS_H_ */
<> 157:ff67d9f36b67 493