Ben Katz / mbed-dev-f303

mbed library sources. Supersedes mbed-src.

Dependents:   Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
72:ad655cb9b50e
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 35 #include "i2c_api.h"
bogdanm 0:9b334a45a8ff 36 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 37 #include "i2cm_regs.h"
bogdanm 0:9b334a45a8ff 38 #include "clkman_regs.h"
bogdanm 0:9b334a45a8ff 39 #include "ioman_regs.h"
bogdanm 0:9b334a45a8ff 40 #include "PeripheralPins.h"
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #define I2C_SLAVE_ADDR_READ_BIT 0x0001
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 #ifndef MXC_I2CM_TX_TIMEOUT
bogdanm 0:9b334a45a8ff 45 #define MXC_I2CM_TX_TIMEOUT 0x5000
bogdanm 0:9b334a45a8ff 46 #endif
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 #ifndef MXC_I2CM_RX_TIMEOUT
bogdanm 0:9b334a45a8ff 49 #define MXC_I2CM_RX_TIMEOUT 0x5000
bogdanm 0:9b334a45a8ff 50 #endif
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 typedef enum {
bogdanm 0:9b334a45a8ff 53 /** 100KHz */
bogdanm 0:9b334a45a8ff 54 MXC_E_I2CM_SPEED_100KHZ = 0,
bogdanm 0:9b334a45a8ff 55 /** 400KHz */
bogdanm 0:9b334a45a8ff 56 MXC_E_I2CM_SPEED_400KHZ,
bogdanm 0:9b334a45a8ff 57 /** 1MHz */
bogdanm 0:9b334a45a8ff 58 MXC_E_I2CM_SPEED_1MHZ
bogdanm 0:9b334a45a8ff 59 } i2cm_speed_t;
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /* Clock divider lookup table */
bogdanm 0:9b334a45a8ff 62 static const uint32_t clk_div_table[3][8] = {
bogdanm 0:9b334a45a8ff 63 /* MXC_E_I2CM_SPEED_100KHZ */
bogdanm 0:9b334a45a8ff 64 {
bogdanm 0:9b334a45a8ff 65 /* 0: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 66 /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 67 /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 68 /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 69 /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 70 /* 5: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 71 /* 6: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 72 /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 73 },
bogdanm 0:9b334a45a8ff 74 /* MXC_E_I2CM_SPEED_400KHZ */
bogdanm 0:9b334a45a8ff 75 {
bogdanm 0:9b334a45a8ff 76 /* 0: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 77 /* 1: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 78 /* 2: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 79 /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 80 /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 81 /* 5: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 82 /* 6: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 83 /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 84 },
bogdanm 0:9b334a45a8ff 85 /* MXC_E_I2CM_SPEED_1MHZ */
bogdanm 0:9b334a45a8ff 86 {
bogdanm 0:9b334a45a8ff 87 /* 0: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 88 /* 1: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 89 /* 2: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 90 /* 3: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 91 /* 4: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 92 /* 5: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 93 /* 6: */ 0, /* not supported */
bogdanm 0:9b334a45a8ff 94 /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
bogdanm 0:9b334a45a8ff 95 },
bogdanm 0:9b334a45a8ff 96 };
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
bogdanm 0:9b334a45a8ff 99 {
bogdanm 0:9b334a45a8ff 100 // determine the I2C to use
bogdanm 0:9b334a45a8ff 101 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
bogdanm 0:9b334a45a8ff 102 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
bogdanm 0:9b334a45a8ff 103 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
bogdanm 0:9b334a45a8ff 104 MBED_ASSERT((int)i2c != NC);
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 obj->i2c = i2c;
bogdanm 0:9b334a45a8ff 107 obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
bogdanm 0:9b334a45a8ff 108 obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
bogdanm 0:9b334a45a8ff 109 obj->start_pending = 0;
bogdanm 0:9b334a45a8ff 110 obj->stop_pending = 0;
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 // configure the pins
bogdanm 0:9b334a45a8ff 113 pinmap_pinout(sda, PinMap_I2C_SDA);
bogdanm 0:9b334a45a8ff 114 pinmap_pinout(scl, PinMap_I2C_SCL);
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 // enable the clock
bogdanm 0:9b334a45a8ff 117 MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 // reset module
bogdanm 0:9b334a45a8ff 120 i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
bogdanm 0:9b334a45a8ff 121 i2c->ctrl = 0;
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 // set default frequency at 100k
bogdanm 0:9b334a45a8ff 124 i2c_frequency(obj, 100000);
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 // set timeout to 255 ms and turn on the auto-stop option
bogdanm 0:9b334a45a8ff 127 i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 // enable tx_fifo and rx_fifo
bogdanm 0:9b334a45a8ff 130 i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 void i2c_frequency(i2c_t *obj, int hz)
bogdanm 0:9b334a45a8ff 134 {
bogdanm 0:9b334a45a8ff 135 // compute clock array index
bogdanm 0:9b334a45a8ff 136 int clki = ((SystemCoreClock + 1500000) / 3000000) - 1;
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 // get clock divider settings from lookup table
bogdanm 0:9b334a45a8ff 139 if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
bogdanm 0:9b334a45a8ff 140 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
bogdanm 0:9b334a45a8ff 141 } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
bogdanm 0:9b334a45a8ff 142 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
bogdanm 0:9b334a45a8ff 143 } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) {
bogdanm 0:9b334a45a8ff 144 obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki];
bogdanm 0:9b334a45a8ff 145 }
bogdanm 0:9b334a45a8ff 146 }
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
bogdanm 0:9b334a45a8ff 149 {
bogdanm 0:9b334a45a8ff 150 int timeout = MXC_I2CM_TX_TIMEOUT;
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 while (*obj->txfifo) {
bogdanm 0:9b334a45a8ff 153 uint32_t intfl = obj->i2c->intfl;
bogdanm 0:9b334a45a8ff 154 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
bogdanm 0:9b334a45a8ff 155 return I2C_ERROR_NO_SLAVE;
bogdanm 0:9b334a45a8ff 156 }
bogdanm 0:9b334a45a8ff 157 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
bogdanm 0:9b334a45a8ff 158 return I2C_ERROR_BUS_BUSY;
bogdanm 0:9b334a45a8ff 159 }
bogdanm 0:9b334a45a8ff 160 timeout--;
bogdanm 0:9b334a45a8ff 161 }
bogdanm 0:9b334a45a8ff 162 *obj->txfifo = data;
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 return 0;
bogdanm 0:9b334a45a8ff 165 }
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 static int wait_tx_in_progress(i2c_t *obj)
bogdanm 0:9b334a45a8ff 168 {
bogdanm 0:9b334a45a8ff 169 int timeout = MXC_I2CM_TX_TIMEOUT;
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 uint32_t intfl = obj->i2c->intfl;
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
bogdanm 0:9b334a45a8ff 176 i2c_reset(obj);
bogdanm 0:9b334a45a8ff 177 return I2C_ERROR_NO_SLAVE;
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
bogdanm 0:9b334a45a8ff 181 i2c_reset(obj);
bogdanm 0:9b334a45a8ff 182 return I2C_ERROR_BUS_BUSY;
bogdanm 0:9b334a45a8ff 183 }
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 return 0;
bogdanm 0:9b334a45a8ff 186 }
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 int i2c_start(i2c_t *obj)
bogdanm 0:9b334a45a8ff 189 {
bogdanm 0:9b334a45a8ff 190 obj->start_pending = 1;
bogdanm 0:9b334a45a8ff 191 return 0;
bogdanm 0:9b334a45a8ff 192 }
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 int i2c_stop(i2c_t *obj)
bogdanm 0:9b334a45a8ff 195 {
bogdanm 0:9b334a45a8ff 196 obj->start_pending = 0;
bogdanm 0:9b334a45a8ff 197 write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 return wait_tx_in_progress(obj);
bogdanm 0:9b334a45a8ff 200 }
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 void i2c_reset(i2c_t *obj)
bogdanm 0:9b334a45a8ff 203 {
bogdanm 0:9b334a45a8ff 204 obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
bogdanm 0:9b334a45a8ff 205 obj->i2c->intfl = 0x3FF; // clear all interrupts
bogdanm 0:9b334a45a8ff 206 obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
bogdanm 0:9b334a45a8ff 207 obj->start_pending = 0;
bogdanm 0:9b334a45a8ff 208 }
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 int i2c_byte_write(i2c_t *obj, int data)
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 int err;
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 // clear all interrupts
bogdanm 0:9b334a45a8ff 215 obj->i2c->intfl = 0x3FF;
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 if (obj->start_pending) {
bogdanm 0:9b334a45a8ff 218 obj->start_pending = 0;
bogdanm 0:9b334a45a8ff 219 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
bogdanm 0:9b334a45a8ff 220 } else {
bogdanm 0:9b334a45a8ff 221 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 if ((err = write_tx_fifo(obj, data)) != 0) {
bogdanm 0:9b334a45a8ff 225 return err;
bogdanm 0:9b334a45a8ff 226 }
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 return 0;
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 int i2c_byte_read(i2c_t *obj, int last)
bogdanm 0:9b334a45a8ff 234 {
bogdanm 0:9b334a45a8ff 235 uint16_t fifo_value;
bogdanm 0:9b334a45a8ff 236 int err;
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 // clear all interrupts
bogdanm 0:9b334a45a8ff 239 obj->i2c->intfl = 0x3FF;
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 if (last) {
bogdanm 0:9b334a45a8ff 242 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
bogdanm 0:9b334a45a8ff 243 } else {
bogdanm 0:9b334a45a8ff 244 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
bogdanm 0:9b334a45a8ff 245 }
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
bogdanm 0:9b334a45a8ff 248 return err;
bogdanm 0:9b334a45a8ff 249 }
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 int timeout = MXC_I2CM_RX_TIMEOUT;
bogdanm 0:9b334a45a8ff 254 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
bogdanm 0:9b334a45a8ff 255 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
bogdanm 0:9b334a45a8ff 256 if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
bogdanm 0:9b334a45a8ff 257 break;
bogdanm 0:9b334a45a8ff 258 }
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
bogdanm 0:9b334a45a8ff 262 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
bogdanm 0:9b334a45a8ff 263 return *obj->rxfifo;
bogdanm 0:9b334a45a8ff 264 }
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 return -1;
bogdanm 0:9b334a45a8ff 267 }
bogdanm 0:9b334a45a8ff 268
bogdanm 0:9b334a45a8ff 269 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
bogdanm 0:9b334a45a8ff 270 {
bogdanm 0:9b334a45a8ff 271 int err, retval = 0;
bogdanm 0:9b334a45a8ff 272 int i;
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
bogdanm 0:9b334a45a8ff 275 return 0;
bogdanm 0:9b334a45a8ff 276 }
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 // clear all interrupts
bogdanm 0:9b334a45a8ff 279 obj->i2c->intfl = 0x3FF;
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 // write the address to the fifo
bogdanm 0:9b334a45a8ff 282 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
bogdanm 0:9b334a45a8ff 283 return err;
bogdanm 0:9b334a45a8ff 284 }
bogdanm 0:9b334a45a8ff 285 obj->start_pending = 0;
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 // start the transaction
bogdanm 0:9b334a45a8ff 288 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 // load as much of the cmd into the FIFO as possible
bogdanm 0:9b334a45a8ff 291 for (i = 0; i < length; i++) {
bogdanm 0:9b334a45a8ff 292 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
bogdanm 0:9b334a45a8ff 293 retval = (retval ? retval : err);
bogdanm 0:9b334a45a8ff 294 break;
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296 }
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 if (stop) {
bogdanm 0:9b334a45a8ff 299 obj->stop_pending = 0;
bogdanm 0:9b334a45a8ff 300 if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
bogdanm 0:9b334a45a8ff 301 retval = (retval ? retval : err);
bogdanm 0:9b334a45a8ff 302 }
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 if ((err = wait_tx_in_progress(obj)) != 0) {
bogdanm 0:9b334a45a8ff 305 retval = (retval ? retval : err);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 } else {
bogdanm 0:9b334a45a8ff 308 obj->stop_pending = 1;
bogdanm 0:9b334a45a8ff 309 int timeout = MXC_I2CM_TX_TIMEOUT;
bogdanm 0:9b334a45a8ff 310 // Wait for TX fifo to be empty
bogdanm 0:9b334a45a8ff 311 while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--) {}
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 if (retval == 0) {
bogdanm 0:9b334a45a8ff 315 return length;
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 return retval;
bogdanm 0:9b334a45a8ff 319 }
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 int err, retval = 0;
bogdanm 0:9b334a45a8ff 324 int i = length;
bogdanm 0:9b334a45a8ff 325 int timeout;
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
bogdanm 0:9b334a45a8ff 328 return 0;
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 // clear all interrupts
bogdanm 0:9b334a45a8ff 332 obj->i2c->intfl = 0x3FF;
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 // start + addr (read)
bogdanm 0:9b334a45a8ff 335 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
bogdanm 0:9b334a45a8ff 336 goto read_done;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338 obj->start_pending = 0;
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 while (i > 256) {
bogdanm 0:9b334a45a8ff 341 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
bogdanm 0:9b334a45a8ff 342 goto read_done;
bogdanm 0:9b334a45a8ff 343 }
bogdanm 0:9b334a45a8ff 344 i -= 256;
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 if (i > 1) {
bogdanm 0:9b334a45a8ff 348 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
bogdanm 0:9b334a45a8ff 349 goto read_done;
bogdanm 0:9b334a45a8ff 350 }
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 // start the transaction
bogdanm 0:9b334a45a8ff 354 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
bogdanm 0:9b334a45a8ff 357 goto read_done;
bogdanm 0:9b334a45a8ff 358 }
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 if (stop) {
bogdanm 0:9b334a45a8ff 361 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
bogdanm 0:9b334a45a8ff 362 goto read_done;
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 timeout = MXC_I2CM_RX_TIMEOUT;
bogdanm 0:9b334a45a8ff 367 i = 0;
bogdanm 0:9b334a45a8ff 368 while (i < length) {
bogdanm 0:9b334a45a8ff 369 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
bogdanm 0:9b334a45a8ff 370 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
bogdanm 0:9b334a45a8ff 371 if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
bogdanm 0:9b334a45a8ff 372 retval = -3;
bogdanm 0:9b334a45a8ff 373 goto read_done;
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375 }
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 timeout = MXC_I2CM_RX_TIMEOUT;
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 uint16_t temp = *obj->rxfifo;
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
bogdanm 0:9b334a45a8ff 384 continue;
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386 data[i++] = (uint8_t) temp;
bogdanm 0:9b334a45a8ff 387 }
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 read_done:
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 if (stop) {
bogdanm 0:9b334a45a8ff 392 obj->stop_pending = 0;
bogdanm 0:9b334a45a8ff 393 if ((err = wait_tx_in_progress(obj)) != 0) {
bogdanm 0:9b334a45a8ff 394 retval = (retval ? retval : err);
bogdanm 0:9b334a45a8ff 395 }
bogdanm 0:9b334a45a8ff 396 } else {
bogdanm 0:9b334a45a8ff 397 obj->stop_pending = 1;
bogdanm 0:9b334a45a8ff 398 }
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 if (retval == 0) {
bogdanm 0:9b334a45a8ff 401 return length;
bogdanm 0:9b334a45a8ff 402 }
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 return retval;
bogdanm 0:9b334a45a8ff 405 }