Ben Katz / mbed-dev-f303

mbed library sources. Supersedes mbed-src.

Dependents:   Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c@181:36facd806e4a, 2018-07-30 (annotated)

Committer:
benkatz
Date:
Mon Jul 30 20:31:44 2018 +0000
Revision:
181:36facd806e4a
Parent:
149:156823d33999 
going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*******************************************************************************
<> 149:156823d33999 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 149:156823d33999 5 * copy of this software and associated documentation files (the "Software"),
<> 149:156823d33999 6 * to deal in the Software without restriction, including without limitation
<> 149:156823d33999 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 149:156823d33999 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 149:156823d33999 9 * Software is furnished to do so, subject to the following conditions:
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * The above copyright notice and this permission notice shall be included
<> 149:156823d33999 12 * in all copies or substantial portions of the Software.
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 149:156823d33999 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 149:156823d33999 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 149:156823d33999 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 149:156823d33999 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 149:156823d33999 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 149:156823d33999 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * Except as contained in this notice, the name of Maxim Integrated
<> 149:156823d33999 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 149:156823d33999 24 * Products, Inc. Branding Policy.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * The mere transfer of this software does not imply any licenses
<> 149:156823d33999 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 149:156823d33999 28 * trademarks, maskwork rights, or any other form of intellectual
<> 149:156823d33999 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 149:156823d33999 30 * ownership rights.
<> 149:156823d33999 31 *******************************************************************************
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 #include <stddef.h>
<> 149:156823d33999 35 #include "cmsis.h"
<> 149:156823d33999 36 #include "gpio_irq_api.h"
<> 149:156823d33999 37 #include "mbed_error.h"
<> 149:156823d33999 38 #include "ioman_regs.h"
<> 149:156823d33999 39 #include "pwrman_regs.h"
<> 149:156823d33999 40 #include "pwrseq_regs.h"
<> 149:156823d33999 41
<> 149:156823d33999 42 static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}};
<> 149:156823d33999 43 static gpio_irq_handler irq_handler;
<> 149:156823d33999 44
<> 149:156823d33999 45 static void gpio_irq_wud_req(gpio_irq_t *obj)
<> 149:156823d33999 46 {
<> 149:156823d33999 47 unsigned int port = obj->port;
<> 149:156823d33999 48 unsigned int pin = obj->pin;
<> 149:156823d33999 49 uint32_t pin_mask = 1 << pin;
<> 149:156823d33999 50
<> 149:156823d33999 51 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1 */
<> 149:156823d33999 52 /* During the time the WUD IOMAN requests are asserted (1), the GPIO Pad */
<> 149:156823d33999 53 /* is in HIGH Z mode, regardless of GPIO setting. This may cause bogus interrupts. */
<> 149:156823d33999 54 if (port < 4) {
<> 149:156823d33999 55 uint32_t mask = pin_mask << (port << 3);
<> 149:156823d33999 56 if (!(MXC_IOMAN->wud_ack0 & mask)) {
<> 149:156823d33999 57 MXC_IOMAN->wud_req0 |= mask;
<> 149:156823d33999 58 while(!(MXC_IOMAN->wud_ack0 & mask));
<> 149:156823d33999 59 }
<> 149:156823d33999 60 } else if (port < 8) {
<> 149:156823d33999 61 uint32_t mask = pin_mask << ((port-4) << 3);
<> 149:156823d33999 62 if (!(MXC_IOMAN->wud_ack1 & mask)) {
<> 149:156823d33999 63 MXC_IOMAN->wud_req1 |= mask;
<> 149:156823d33999 64 while(!(MXC_IOMAN->wud_ack1 & mask));
<> 149:156823d33999 65 }
<> 149:156823d33999 66 }
<> 149:156823d33999 67 }
<> 149:156823d33999 68
<> 149:156823d33999 69 /* Clear the selected pin from wake-up detect */
<> 149:156823d33999 70 static void gpio_irq_wud_clear(gpio_irq_t *obj)
<> 149:156823d33999 71 {
<> 149:156823d33999 72 unsigned int port = obj->port;
<> 149:156823d33999 73 unsigned int pin = obj->pin;
<> 149:156823d33999 74
<> 149:156823d33999 75 /* Enable modifications to WUD configuration */
<> 149:156823d33999 76 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 149:156823d33999 77
<> 149:156823d33999 78 /* Select pad in WUD control */
<> 149:156823d33999 79 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 149:156823d33999 80 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
<> 149:156823d33999 81
<> 149:156823d33999 82 /* Clear any existing WUD configuration for this pad */
<> 149:156823d33999 83 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 149:156823d33999 84 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 149:156823d33999 85 /* Clear with PULSE0; PULSE1 enables WUD */
<> 149:156823d33999 86 MXC_PWRMAN->wud_pulse0 = 1;
<> 149:156823d33999 87
<> 149:156823d33999 88 /* Disable configuration */
<> 149:156823d33999 89 MXC_PWRMAN->wud_ctrl = 0;
<> 149:156823d33999 90 MXC_IOMAN->wud_req0 = 0;
<> 149:156823d33999 91 MXC_IOMAN->wud_req1 = 0;
<> 149:156823d33999 92 }
<> 149:156823d33999 93
<> 149:156823d33999 94 /* Configure the selected pin for wake-up detect */
<> 149:156823d33999 95 static void gpio_irq_wud_config(gpio_irq_t *obj)
<> 149:156823d33999 96 {
<> 149:156823d33999 97 unsigned int port = obj->port;
<> 149:156823d33999 98 unsigned int pin = obj->pin;
<> 149:156823d33999 99 uint32_t pin_mask = 1 << pin;
<> 149:156823d33999 100
<> 149:156823d33999 101 /* Enable modifications to WUD configuration */
<> 149:156823d33999 102 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 149:156823d33999 103
<> 149:156823d33999 104 /* Select pad in WUD control */
<> 149:156823d33999 105 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 149:156823d33999 106 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
<> 149:156823d33999 107
<> 149:156823d33999 108 /* First clear any existing WUD configuration for this pad */
<> 149:156823d33999 109 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 149:156823d33999 110 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 149:156823d33999 111 /* Clear with PULSE0; PULSE1 enables WUD */
<> 149:156823d33999 112 MXC_PWRMAN->wud_pulse0 = 1;
<> 149:156823d33999 113
<> 149:156823d33999 114 if (obj->fall_en || obj->rise_en) {
<> 149:156823d33999 115 /* Configure sense level on this pad */
<> 149:156823d33999 116 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 149:156823d33999 117 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 149:156823d33999 118
<> 149:156823d33999 119 uint32_t in_val = MXC_GPIO->in_val[port] & pin_mask;
<> 149:156823d33999 120 do {
<> 149:156823d33999 121 if (in_val) {
<> 149:156823d33999 122 /* Select active low with PULSE1 (backwards from what you'd expect) */
<> 149:156823d33999 123 MXC_PWRMAN->wud_pulse1 = 1;
<> 149:156823d33999 124 } else {
<> 149:156823d33999 125 /* Select active high with PULSE0 (backwards from what you'd expect) */
<> 149:156823d33999 126 MXC_PWRMAN->wud_pulse0 = 1;
<> 149:156823d33999 127 }
<> 149:156823d33999 128 } while ((MXC_GPIO->in_val[port] & pin_mask) != in_val);
<> 149:156823d33999 129
<> 149:156823d33999 130 /* Select this pad to have the wake-up function enabled */
<> 149:156823d33999 131 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 149:156823d33999 132 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 149:156823d33999 133 /* Activate with PULSE1 */
<> 149:156823d33999 134 MXC_PWRMAN->wud_pulse1 = 1;
<> 149:156823d33999 135
<> 149:156823d33999 136 // NOTE: Low Power Pullup/down is not normally needed in addition to
<> 149:156823d33999 137 // standard GPIO Pullup/downs.
<> 149:156823d33999 138
<> 149:156823d33999 139 /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
<> 149:156823d33999 140 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
<> 149:156823d33999 141 }
<> 149:156823d33999 142
<> 149:156823d33999 143 /* Disable configuration */
<> 149:156823d33999 144 MXC_PWRMAN->wud_ctrl = 0;
<> 149:156823d33999 145 MXC_IOMAN->wud_req0 = 0;
<> 149:156823d33999 146 MXC_IOMAN->wud_req1 = 0;
<> 149:156823d33999 147 }
<> 149:156823d33999 148
<> 149:156823d33999 149 static void handle_irq(unsigned int port)
<> 149:156823d33999 150 {
<> 149:156823d33999 151 uint32_t intfl, in_val;
<> 149:156823d33999 152 uint32_t mask;
<> 149:156823d33999 153 unsigned int pin;
<> 149:156823d33999 154
<> 149:156823d33999 155 /* Read pin state */
<> 149:156823d33999 156 in_val = MXC_GPIO->in_val[port];
<> 149:156823d33999 157
<> 149:156823d33999 158 /* Read interrupts */
<> 149:156823d33999 159 intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
<> 149:156823d33999 160
<> 149:156823d33999 161 mask = 1;
<> 149:156823d33999 162
<> 149:156823d33999 163 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
<> 149:156823d33999 164 if (intfl & mask) {
<> 149:156823d33999 165 MXC_GPIO->intfl[port] = mask; /* clear interrupt */
<> 149:156823d33999 166 gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL;
<> 149:156823d33999 167 gpio_irq_t *obj = objs[port][pin];
<> 149:156823d33999 168 if (obj && obj->id) {
<> 149:156823d33999 169 if ((event == IRQ_RISE) && obj->rise_en) {
<> 149:156823d33999 170 irq_handler(obj->id, IRQ_RISE);
<> 149:156823d33999 171 } else if ((event == IRQ_FALL) && obj->fall_en) {
<> 149:156823d33999 172 irq_handler(obj->id, IRQ_FALL);
<> 149:156823d33999 173 }
<> 149:156823d33999 174 }
<> 149:156823d33999 175
<> 149:156823d33999 176 gpio_irq_wud_config(obj);
<> 149:156823d33999 177 }
<> 149:156823d33999 178 mask <<= 1;
<> 149:156823d33999 179 }
<> 149:156823d33999 180 }
<> 149:156823d33999 181
<> 149:156823d33999 182 void gpio_irq_0(void) { handle_irq(0); }
<> 149:156823d33999 183 void gpio_irq_1(void) { handle_irq(1); }
<> 149:156823d33999 184 void gpio_irq_2(void) { handle_irq(2); }
<> 149:156823d33999 185 void gpio_irq_3(void) { handle_irq(3); }
<> 149:156823d33999 186 void gpio_irq_4(void) { handle_irq(4); }
<> 149:156823d33999 187 void gpio_irq_5(void) { handle_irq(5); }
<> 149:156823d33999 188 void gpio_irq_6(void) { handle_irq(6); }
<> 149:156823d33999 189
<> 149:156823d33999 190 int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
<> 149:156823d33999 191 {
<> 149:156823d33999 192 if (name == NC) {
<> 149:156823d33999 193 return -1;
<> 149:156823d33999 194 }
<> 149:156823d33999 195
<> 149:156823d33999 196 uint8_t port = PINNAME_TO_PORT(name);
<> 149:156823d33999 197 uint8_t pin = PINNAME_TO_PIN(name);
<> 149:156823d33999 198
<> 149:156823d33999 199 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
<> 149:156823d33999 200 return 1;
<> 149:156823d33999 201 }
<> 149:156823d33999 202
<> 149:156823d33999 203 obj->port = port;
<> 149:156823d33999 204 obj->pin = pin;
<> 149:156823d33999 205 obj->id = id;
<> 149:156823d33999 206 objs[port][pin] = obj;
<> 149:156823d33999 207
<> 149:156823d33999 208 /* register handlers */
<> 149:156823d33999 209 irq_handler = handler;
<> 149:156823d33999 210 NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
<> 149:156823d33999 211 NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
<> 149:156823d33999 212 NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
<> 149:156823d33999 213 NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
<> 149:156823d33999 214 NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
<> 149:156823d33999 215 NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
<> 149:156823d33999 216 NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
<> 149:156823d33999 217
<> 149:156823d33999 218 /* request WUD in case the application is going to sleep */
<> 149:156823d33999 219 gpio_irq_wud_req(obj);
<> 149:156823d33999 220
<> 149:156823d33999 221 /* disable the interrupt locally */
<> 149:156823d33999 222 MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
<> 149:156823d33999 223
<> 149:156823d33999 224 /* clear a pending request */
<> 149:156823d33999 225 MXC_GPIO->intfl[port] = 1 << pin;
<> 149:156823d33999 226
<> 149:156823d33999 227 /* enable the requested interrupt */
<> 149:156823d33999 228 MXC_GPIO->inten[port] |= (1 << pin);
<> 149:156823d33999 229 NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
<> 149:156823d33999 230
<> 149:156823d33999 231 return 0;
<> 149:156823d33999 232 }
<> 149:156823d33999 233
<> 149:156823d33999 234 void gpio_irq_free(gpio_irq_t *obj)
<> 149:156823d33999 235 {
<> 149:156823d33999 236 /* disable interrupt */
<> 149:156823d33999 237 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 149:156823d33999 238 MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 149:156823d33999 239 objs[obj->port][obj->pin] = NULL;
<> 149:156823d33999 240 gpio_irq_wud_clear(obj);
<> 149:156823d33999 241 }
<> 149:156823d33999 242
<> 149:156823d33999 243 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 149:156823d33999 244 {
<> 149:156823d33999 245 if (event == IRQ_FALL) {
<> 149:156823d33999 246 obj->fall_en = enable;
<> 149:156823d33999 247 } else if (event == IRQ_RISE) {
<> 149:156823d33999 248 obj->rise_en = enable;
<> 149:156823d33999 249 }
<> 149:156823d33999 250
<> 149:156823d33999 251 if (obj->fall_en || obj->rise_en) {
<> 149:156823d33999 252 MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 149:156823d33999 253 gpio_irq_wud_config(obj); /* enable WUD for this pin so we may wake from deepsleep as well */
<> 149:156823d33999 254 } else {
<> 149:156823d33999 255 MXC_GPIO->int_mode[obj->port] &= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 149:156823d33999 256 gpio_irq_wud_clear(obj);
<> 149:156823d33999 257 }
<> 149:156823d33999 258 }
<> 149:156823d33999 259
<> 149:156823d33999 260 void gpio_irq_enable(gpio_irq_t *obj)
<> 149:156823d33999 261 {
<> 149:156823d33999 262 MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
<> 149:156823d33999 263 gpio_irq_wud_config(obj);
<> 149:156823d33999 264 }
<> 149:156823d33999 265
<> 149:156823d33999 266 void gpio_irq_disable(gpio_irq_t *obj)
<> 149:156823d33999 267 {
<> 149:156823d33999 268 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 149:156823d33999 269 gpio_irq_wud_clear(obj);
<> 149:156823d33999 270 }
<> 149:156823d33999 271
<> 149:156823d33999 272 gpio_irq_t *gpio_irq_get_obj(PinName name)
<> 149:156823d33999 273 {
<> 149:156823d33999 274 if (name == NC) {
<> 149:156823d33999 275 return NULL;
<> 149:156823d33999 276 }
<> 149:156823d33999 277
<> 149:156823d33999 278 unsigned int port = PINNAME_TO_PORT(name);
<> 149:156823d33999 279 unsigned int pin = PINNAME_TO_PIN(name);
<> 149:156823d33999 280
<> 149:156823d33999 281 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
<> 149:156823d33999 282 return NULL;
<> 149:156823d33999 283 }
<> 149:156823d33999 284
<> 149:156823d33999 285 return objs[port][pin];
<> 149:156823d33999 286 }