mbed library sources. Supersedes mbed-src.
Dependents: Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more
Fork of mbed-dev by
cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h@181:36facd806e4a, 2018-07-30 (annotated)
- Committer:
- benkatz
- Date:
- Mon Jul 30 20:31:44 2018 +0000
- Revision:
- 181:36facd806e4a
- Parent:
- 167:e84263d55307
going on the robot. fixed a dumb bug in float_to_uint
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 167:e84263d55307 | 1 | /**************************************************************************//** |
AnnaBridge | 167:e84263d55307 | 2 | * @file cmsis_armcc.h |
AnnaBridge | 167:e84263d55307 | 3 | * @brief CMSIS compiler specific macros, functions, instructions |
AnnaBridge | 167:e84263d55307 | 4 | * @version V1.00 |
AnnaBridge | 167:e84263d55307 | 5 | * @date 22. Feb 2017 |
AnnaBridge | 167:e84263d55307 | 6 | ******************************************************************************/ |
AnnaBridge | 167:e84263d55307 | 7 | /* |
AnnaBridge | 167:e84263d55307 | 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
AnnaBridge | 167:e84263d55307 | 9 | * |
AnnaBridge | 167:e84263d55307 | 10 | * SPDX-License-Identifier: Apache-2.0 |
AnnaBridge | 167:e84263d55307 | 11 | * |
AnnaBridge | 167:e84263d55307 | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
AnnaBridge | 167:e84263d55307 | 13 | * not use this file except in compliance with the License. |
AnnaBridge | 167:e84263d55307 | 14 | * You may obtain a copy of the License at |
AnnaBridge | 167:e84263d55307 | 15 | * |
AnnaBridge | 167:e84263d55307 | 16 | * www.apache.org/licenses/LICENSE-2.0 |
AnnaBridge | 167:e84263d55307 | 17 | * |
AnnaBridge | 167:e84263d55307 | 18 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 167:e84263d55307 | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
AnnaBridge | 167:e84263d55307 | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 167:e84263d55307 | 21 | * See the License for the specific language governing permissions and |
AnnaBridge | 167:e84263d55307 | 22 | * limitations under the License. |
AnnaBridge | 167:e84263d55307 | 23 | */ |
AnnaBridge | 167:e84263d55307 | 24 | |
AnnaBridge | 167:e84263d55307 | 25 | #ifndef __CMSIS_ARMCC_H |
AnnaBridge | 167:e84263d55307 | 26 | #define __CMSIS_ARMCC_H |
AnnaBridge | 167:e84263d55307 | 27 | |
AnnaBridge | 167:e84263d55307 | 28 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) |
AnnaBridge | 167:e84263d55307 | 29 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
AnnaBridge | 167:e84263d55307 | 30 | #endif |
AnnaBridge | 167:e84263d55307 | 31 | |
AnnaBridge | 167:e84263d55307 | 32 | /* CMSIS compiler control architecture macros */ |
AnnaBridge | 167:e84263d55307 | 33 | #if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) |
AnnaBridge | 167:e84263d55307 | 34 | #define __ARM_ARCH_7A__ 1 |
AnnaBridge | 167:e84263d55307 | 35 | #endif |
AnnaBridge | 167:e84263d55307 | 36 | |
AnnaBridge | 167:e84263d55307 | 37 | /* CMSIS compiler specific defines */ |
AnnaBridge | 167:e84263d55307 | 38 | #ifndef __ASM |
AnnaBridge | 167:e84263d55307 | 39 | #define __ASM __asm |
AnnaBridge | 167:e84263d55307 | 40 | #endif |
AnnaBridge | 167:e84263d55307 | 41 | #ifndef __INLINE |
AnnaBridge | 167:e84263d55307 | 42 | #define __INLINE __inline |
AnnaBridge | 167:e84263d55307 | 43 | #endif |
AnnaBridge | 167:e84263d55307 | 44 | #ifndef __STATIC_INLINE |
AnnaBridge | 167:e84263d55307 | 45 | #define __STATIC_INLINE static __inline |
AnnaBridge | 167:e84263d55307 | 46 | #endif |
AnnaBridge | 167:e84263d55307 | 47 | #ifndef __STATIC_ASM |
AnnaBridge | 167:e84263d55307 | 48 | #define __STATIC_ASM static __asm |
AnnaBridge | 167:e84263d55307 | 49 | #endif |
AnnaBridge | 167:e84263d55307 | 50 | #ifndef __NO_RETURN |
AnnaBridge | 167:e84263d55307 | 51 | #define __NO_RETURN __declspec(noreturn) |
AnnaBridge | 167:e84263d55307 | 52 | #endif |
AnnaBridge | 167:e84263d55307 | 53 | #ifndef __USED |
AnnaBridge | 167:e84263d55307 | 54 | #define __USED __attribute__((used)) |
AnnaBridge | 167:e84263d55307 | 55 | #endif |
AnnaBridge | 167:e84263d55307 | 56 | #ifndef __WEAK |
AnnaBridge | 167:e84263d55307 | 57 | #define __WEAK __attribute__((weak)) |
AnnaBridge | 167:e84263d55307 | 58 | #endif |
AnnaBridge | 167:e84263d55307 | 59 | #ifndef __UNALIGNED_UINT32 |
AnnaBridge | 167:e84263d55307 | 60 | #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) |
AnnaBridge | 167:e84263d55307 | 61 | #endif |
AnnaBridge | 167:e84263d55307 | 62 | #ifndef __ALIGNED |
AnnaBridge | 167:e84263d55307 | 63 | #define __ALIGNED(x) __attribute__((aligned(x))) |
AnnaBridge | 167:e84263d55307 | 64 | #endif |
AnnaBridge | 167:e84263d55307 | 65 | #ifndef __PACKED |
AnnaBridge | 167:e84263d55307 | 66 | #define __PACKED __attribute__((packed)) |
AnnaBridge | 167:e84263d55307 | 67 | #endif |
AnnaBridge | 167:e84263d55307 | 68 | |
AnnaBridge | 167:e84263d55307 | 69 | |
AnnaBridge | 167:e84263d55307 | 70 | /* ########################### Core Function Access ########################### */ |
AnnaBridge | 167:e84263d55307 | 71 | |
AnnaBridge | 167:e84263d55307 | 72 | /** |
AnnaBridge | 167:e84263d55307 | 73 | \brief Get FPSCR |
AnnaBridge | 167:e84263d55307 | 74 | \return Floating Point Status/Control register value |
AnnaBridge | 167:e84263d55307 | 75 | */ |
AnnaBridge | 167:e84263d55307 | 76 | __STATIC_INLINE uint32_t __get_FPSCR(void) |
AnnaBridge | 167:e84263d55307 | 77 | { |
AnnaBridge | 167:e84263d55307 | 78 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
AnnaBridge | 167:e84263d55307 | 79 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
AnnaBridge | 167:e84263d55307 | 80 | register uint32_t __regfpscr __ASM("fpscr"); |
AnnaBridge | 167:e84263d55307 | 81 | return(__regfpscr); |
AnnaBridge | 167:e84263d55307 | 82 | #else |
AnnaBridge | 167:e84263d55307 | 83 | return(0U); |
AnnaBridge | 167:e84263d55307 | 84 | #endif |
AnnaBridge | 167:e84263d55307 | 85 | } |
AnnaBridge | 167:e84263d55307 | 86 | |
AnnaBridge | 167:e84263d55307 | 87 | /** |
AnnaBridge | 167:e84263d55307 | 88 | \brief Set FPSCR |
AnnaBridge | 167:e84263d55307 | 89 | \param [in] fpscr Floating Point Status/Control value to set |
AnnaBridge | 167:e84263d55307 | 90 | */ |
AnnaBridge | 167:e84263d55307 | 91 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
AnnaBridge | 167:e84263d55307 | 92 | { |
AnnaBridge | 167:e84263d55307 | 93 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
AnnaBridge | 167:e84263d55307 | 94 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
AnnaBridge | 167:e84263d55307 | 95 | register uint32_t __regfpscr __ASM("fpscr"); |
AnnaBridge | 167:e84263d55307 | 96 | __regfpscr = (fpscr); |
AnnaBridge | 167:e84263d55307 | 97 | #else |
AnnaBridge | 167:e84263d55307 | 98 | (void)fpscr; |
AnnaBridge | 167:e84263d55307 | 99 | #endif |
AnnaBridge | 167:e84263d55307 | 100 | } |
AnnaBridge | 167:e84263d55307 | 101 | |
AnnaBridge | 167:e84263d55307 | 102 | /* ########################## Core Instruction Access ######################### */ |
AnnaBridge | 167:e84263d55307 | 103 | /** |
AnnaBridge | 167:e84263d55307 | 104 | \brief No Operation |
AnnaBridge | 167:e84263d55307 | 105 | */ |
AnnaBridge | 167:e84263d55307 | 106 | #define __NOP __nop |
AnnaBridge | 167:e84263d55307 | 107 | |
AnnaBridge | 167:e84263d55307 | 108 | /** |
AnnaBridge | 167:e84263d55307 | 109 | \brief Wait For Interrupt |
AnnaBridge | 167:e84263d55307 | 110 | */ |
AnnaBridge | 167:e84263d55307 | 111 | #define __WFI __wfi |
AnnaBridge | 167:e84263d55307 | 112 | |
AnnaBridge | 167:e84263d55307 | 113 | /** |
AnnaBridge | 167:e84263d55307 | 114 | \brief Wait For Event |
AnnaBridge | 167:e84263d55307 | 115 | */ |
AnnaBridge | 167:e84263d55307 | 116 | #define __WFE __wfe |
AnnaBridge | 167:e84263d55307 | 117 | |
AnnaBridge | 167:e84263d55307 | 118 | /** |
AnnaBridge | 167:e84263d55307 | 119 | \brief Send Event |
AnnaBridge | 167:e84263d55307 | 120 | */ |
AnnaBridge | 167:e84263d55307 | 121 | #define __SEV __sev |
AnnaBridge | 167:e84263d55307 | 122 | |
AnnaBridge | 167:e84263d55307 | 123 | /** |
AnnaBridge | 167:e84263d55307 | 124 | \brief Instruction Synchronization Barrier |
AnnaBridge | 167:e84263d55307 | 125 | */ |
AnnaBridge | 167:e84263d55307 | 126 | #define __ISB() do {\ |
AnnaBridge | 167:e84263d55307 | 127 | __schedule_barrier();\ |
AnnaBridge | 167:e84263d55307 | 128 | __isb(0xF);\ |
AnnaBridge | 167:e84263d55307 | 129 | __schedule_barrier();\ |
AnnaBridge | 167:e84263d55307 | 130 | } while (0U) |
AnnaBridge | 167:e84263d55307 | 131 | |
AnnaBridge | 167:e84263d55307 | 132 | /** |
AnnaBridge | 167:e84263d55307 | 133 | \brief Data Synchronization Barrier |
AnnaBridge | 167:e84263d55307 | 134 | */ |
AnnaBridge | 167:e84263d55307 | 135 | #define __DSB() do {\ |
AnnaBridge | 167:e84263d55307 | 136 | __schedule_barrier();\ |
AnnaBridge | 167:e84263d55307 | 137 | __dsb(0xF);\ |
AnnaBridge | 167:e84263d55307 | 138 | __schedule_barrier();\ |
AnnaBridge | 167:e84263d55307 | 139 | } while (0U) |
AnnaBridge | 167:e84263d55307 | 140 | |
AnnaBridge | 167:e84263d55307 | 141 | /** |
AnnaBridge | 167:e84263d55307 | 142 | \brief Data Memory Barrier |
AnnaBridge | 167:e84263d55307 | 143 | */ |
AnnaBridge | 167:e84263d55307 | 144 | #define __DMB() do {\ |
AnnaBridge | 167:e84263d55307 | 145 | __schedule_barrier();\ |
AnnaBridge | 167:e84263d55307 | 146 | __dmb(0xF);\ |
AnnaBridge | 167:e84263d55307 | 147 | __schedule_barrier();\ |
AnnaBridge | 167:e84263d55307 | 148 | } while (0U) |
AnnaBridge | 167:e84263d55307 | 149 | |
AnnaBridge | 167:e84263d55307 | 150 | /** |
AnnaBridge | 167:e84263d55307 | 151 | \brief Reverse byte order (32 bit) |
AnnaBridge | 167:e84263d55307 | 152 | \param [in] value Value to reverse |
AnnaBridge | 167:e84263d55307 | 153 | \return Reversed value |
AnnaBridge | 167:e84263d55307 | 154 | */ |
AnnaBridge | 167:e84263d55307 | 155 | #define __REV __rev |
AnnaBridge | 167:e84263d55307 | 156 | |
AnnaBridge | 167:e84263d55307 | 157 | /** |
AnnaBridge | 167:e84263d55307 | 158 | \brief Reverse byte order (16 bit) |
AnnaBridge | 167:e84263d55307 | 159 | \param [in] value Value to reverse |
AnnaBridge | 167:e84263d55307 | 160 | \return Reversed value |
AnnaBridge | 167:e84263d55307 | 161 | */ |
AnnaBridge | 167:e84263d55307 | 162 | #ifndef __NO_EMBEDDED_ASM |
AnnaBridge | 167:e84263d55307 | 163 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
AnnaBridge | 167:e84263d55307 | 164 | { |
AnnaBridge | 167:e84263d55307 | 165 | rev16 r0, r0 |
AnnaBridge | 167:e84263d55307 | 166 | bx lr |
AnnaBridge | 167:e84263d55307 | 167 | } |
AnnaBridge | 167:e84263d55307 | 168 | #endif |
AnnaBridge | 167:e84263d55307 | 169 | |
AnnaBridge | 167:e84263d55307 | 170 | /** |
AnnaBridge | 167:e84263d55307 | 171 | \brief Reverse byte order in signed short value |
AnnaBridge | 167:e84263d55307 | 172 | \param [in] value Value to reverse |
AnnaBridge | 167:e84263d55307 | 173 | \return Reversed value |
AnnaBridge | 167:e84263d55307 | 174 | */ |
AnnaBridge | 167:e84263d55307 | 175 | #ifndef __NO_EMBEDDED_ASM |
AnnaBridge | 167:e84263d55307 | 176 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) |
AnnaBridge | 167:e84263d55307 | 177 | { |
AnnaBridge | 167:e84263d55307 | 178 | revsh r0, r0 |
AnnaBridge | 167:e84263d55307 | 179 | bx lr |
AnnaBridge | 167:e84263d55307 | 180 | } |
AnnaBridge | 167:e84263d55307 | 181 | #endif |
AnnaBridge | 167:e84263d55307 | 182 | |
AnnaBridge | 167:e84263d55307 | 183 | /** |
AnnaBridge | 167:e84263d55307 | 184 | \brief Rotate Right in unsigned value (32 bit) |
AnnaBridge | 167:e84263d55307 | 185 | \param [in] op1 Value to rotate |
AnnaBridge | 167:e84263d55307 | 186 | \param [in] op2 Number of Bits to rotate |
AnnaBridge | 167:e84263d55307 | 187 | \return Rotated value |
AnnaBridge | 167:e84263d55307 | 188 | */ |
AnnaBridge | 167:e84263d55307 | 189 | #define __ROR __ror |
AnnaBridge | 167:e84263d55307 | 190 | |
AnnaBridge | 167:e84263d55307 | 191 | /** |
AnnaBridge | 167:e84263d55307 | 192 | \brief Breakpoint |
AnnaBridge | 167:e84263d55307 | 193 | \param [in] value is ignored by the processor. |
AnnaBridge | 167:e84263d55307 | 194 | If required, a debugger can use it to store additional information about the breakpoint. |
AnnaBridge | 167:e84263d55307 | 195 | */ |
AnnaBridge | 167:e84263d55307 | 196 | #define __BKPT(value) __breakpoint(value) |
AnnaBridge | 167:e84263d55307 | 197 | |
AnnaBridge | 167:e84263d55307 | 198 | /** |
AnnaBridge | 167:e84263d55307 | 199 | \brief Reverse bit order of value |
AnnaBridge | 167:e84263d55307 | 200 | \param [in] value Value to reverse |
AnnaBridge | 167:e84263d55307 | 201 | \return Reversed value |
AnnaBridge | 167:e84263d55307 | 202 | */ |
AnnaBridge | 167:e84263d55307 | 203 | #define __RBIT __rbit |
AnnaBridge | 167:e84263d55307 | 204 | |
AnnaBridge | 167:e84263d55307 | 205 | /** |
AnnaBridge | 167:e84263d55307 | 206 | \brief Count leading zeros |
AnnaBridge | 167:e84263d55307 | 207 | \param [in] value Value to count the leading zeros |
AnnaBridge | 167:e84263d55307 | 208 | \return number of leading zeros in value |
AnnaBridge | 167:e84263d55307 | 209 | */ |
AnnaBridge | 167:e84263d55307 | 210 | #define __CLZ __clz |
AnnaBridge | 167:e84263d55307 | 211 | |
AnnaBridge | 167:e84263d55307 | 212 | /** \brief Get CPSR Register |
AnnaBridge | 167:e84263d55307 | 213 | \return CPSR Register value |
AnnaBridge | 167:e84263d55307 | 214 | */ |
AnnaBridge | 167:e84263d55307 | 215 | __STATIC_INLINE uint32_t __get_CPSR(void) |
AnnaBridge | 167:e84263d55307 | 216 | { |
AnnaBridge | 167:e84263d55307 | 217 | register uint32_t __regCPSR __ASM("cpsr"); |
AnnaBridge | 167:e84263d55307 | 218 | return(__regCPSR); |
AnnaBridge | 167:e84263d55307 | 219 | } |
AnnaBridge | 167:e84263d55307 | 220 | |
AnnaBridge | 167:e84263d55307 | 221 | |
AnnaBridge | 167:e84263d55307 | 222 | /** \brief Set CPSR Register |
AnnaBridge | 167:e84263d55307 | 223 | \param [in] cpsr CPSR value to set |
AnnaBridge | 167:e84263d55307 | 224 | */ |
AnnaBridge | 167:e84263d55307 | 225 | __STATIC_INLINE void __set_CPSR(uint32_t cpsr) |
AnnaBridge | 167:e84263d55307 | 226 | { |
AnnaBridge | 167:e84263d55307 | 227 | register uint32_t __regCPSR __ASM("cpsr"); |
AnnaBridge | 167:e84263d55307 | 228 | __regCPSR = cpsr; |
AnnaBridge | 167:e84263d55307 | 229 | } |
AnnaBridge | 167:e84263d55307 | 230 | |
AnnaBridge | 167:e84263d55307 | 231 | /** \brief Get Mode |
AnnaBridge | 167:e84263d55307 | 232 | \return Processor Mode |
AnnaBridge | 167:e84263d55307 | 233 | */ |
AnnaBridge | 167:e84263d55307 | 234 | __STATIC_INLINE uint32_t __get_mode(void) { |
AnnaBridge | 167:e84263d55307 | 235 | return (__get_CPSR() & 0x1FU); |
AnnaBridge | 167:e84263d55307 | 236 | } |
AnnaBridge | 167:e84263d55307 | 237 | |
AnnaBridge | 167:e84263d55307 | 238 | /** \brief Set Mode |
AnnaBridge | 167:e84263d55307 | 239 | \param [in] mode Mode value to set |
AnnaBridge | 167:e84263d55307 | 240 | */ |
AnnaBridge | 167:e84263d55307 | 241 | __STATIC_INLINE __ASM void __set_mode(uint32_t mode) { |
AnnaBridge | 167:e84263d55307 | 242 | MOV r1, lr |
AnnaBridge | 167:e84263d55307 | 243 | MSR CPSR_C, r0 |
AnnaBridge | 167:e84263d55307 | 244 | BX r1 |
AnnaBridge | 167:e84263d55307 | 245 | } |
AnnaBridge | 167:e84263d55307 | 246 | |
AnnaBridge | 167:e84263d55307 | 247 | /** \brief Set Stack Pointer |
AnnaBridge | 167:e84263d55307 | 248 | \param [in] stack Stack Pointer value to set |
AnnaBridge | 167:e84263d55307 | 249 | */ |
AnnaBridge | 167:e84263d55307 | 250 | __STATIC_INLINE __ASM void __set_SP(uint32_t stack) |
AnnaBridge | 167:e84263d55307 | 251 | { |
AnnaBridge | 167:e84263d55307 | 252 | MOV sp, r0 |
AnnaBridge | 167:e84263d55307 | 253 | BX lr |
AnnaBridge | 167:e84263d55307 | 254 | } |
AnnaBridge | 167:e84263d55307 | 255 | |
AnnaBridge | 167:e84263d55307 | 256 | /** \brief Set Process Stack Pointer |
AnnaBridge | 167:e84263d55307 | 257 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
AnnaBridge | 167:e84263d55307 | 258 | */ |
AnnaBridge | 167:e84263d55307 | 259 | __STATIC_INLINE __ASM void __set_PSP(uint32_t topOfProcStack) |
AnnaBridge | 167:e84263d55307 | 260 | { |
AnnaBridge | 167:e84263d55307 | 261 | ARM |
AnnaBridge | 167:e84263d55307 | 262 | PRESERVE8 |
AnnaBridge | 167:e84263d55307 | 263 | |
AnnaBridge | 167:e84263d55307 | 264 | BIC R0, R0, #7 ;ensure stack is 8-byte aligned |
AnnaBridge | 167:e84263d55307 | 265 | MRS R1, CPSR |
AnnaBridge | 167:e84263d55307 | 266 | CPS #0x1F ;no effect in USR mode |
AnnaBridge | 167:e84263d55307 | 267 | MOV SP, R0 |
AnnaBridge | 167:e84263d55307 | 268 | MSR CPSR_c, R1 ;no effect in USR mode |
AnnaBridge | 167:e84263d55307 | 269 | ISB |
AnnaBridge | 167:e84263d55307 | 270 | BX LR |
AnnaBridge | 167:e84263d55307 | 271 | } |
AnnaBridge | 167:e84263d55307 | 272 | |
AnnaBridge | 167:e84263d55307 | 273 | /** \brief Set User Mode |
AnnaBridge | 167:e84263d55307 | 274 | */ |
AnnaBridge | 167:e84263d55307 | 275 | __STATIC_INLINE __ASM void __set_CPS_USR(void) |
AnnaBridge | 167:e84263d55307 | 276 | { |
AnnaBridge | 167:e84263d55307 | 277 | ARM |
AnnaBridge | 167:e84263d55307 | 278 | |
AnnaBridge | 167:e84263d55307 | 279 | CPS #0x10 |
AnnaBridge | 167:e84263d55307 | 280 | BX LR |
AnnaBridge | 167:e84263d55307 | 281 | } |
AnnaBridge | 167:e84263d55307 | 282 | |
AnnaBridge | 167:e84263d55307 | 283 | /** \brief Get FPEXC |
AnnaBridge | 167:e84263d55307 | 284 | \return Floating Point Exception Control register value |
AnnaBridge | 167:e84263d55307 | 285 | */ |
AnnaBridge | 167:e84263d55307 | 286 | __STATIC_INLINE uint32_t __get_FPEXC(void) |
AnnaBridge | 167:e84263d55307 | 287 | { |
AnnaBridge | 167:e84263d55307 | 288 | #if (__FPU_PRESENT == 1) |
AnnaBridge | 167:e84263d55307 | 289 | register uint32_t __regfpexc __ASM("fpexc"); |
AnnaBridge | 167:e84263d55307 | 290 | return(__regfpexc); |
AnnaBridge | 167:e84263d55307 | 291 | #else |
AnnaBridge | 167:e84263d55307 | 292 | return(0); |
AnnaBridge | 167:e84263d55307 | 293 | #endif |
AnnaBridge | 167:e84263d55307 | 294 | } |
AnnaBridge | 167:e84263d55307 | 295 | |
AnnaBridge | 167:e84263d55307 | 296 | /** \brief Set FPEXC |
AnnaBridge | 167:e84263d55307 | 297 | \param [in] fpexc Floating Point Exception Control value to set |
AnnaBridge | 167:e84263d55307 | 298 | */ |
AnnaBridge | 167:e84263d55307 | 299 | __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
AnnaBridge | 167:e84263d55307 | 300 | { |
AnnaBridge | 167:e84263d55307 | 301 | #if (__FPU_PRESENT == 1) |
AnnaBridge | 167:e84263d55307 | 302 | register uint32_t __regfpexc __ASM("fpexc"); |
AnnaBridge | 167:e84263d55307 | 303 | __regfpexc = (fpexc); |
AnnaBridge | 167:e84263d55307 | 304 | #endif |
AnnaBridge | 167:e84263d55307 | 305 | } |
AnnaBridge | 167:e84263d55307 | 306 | |
AnnaBridge | 167:e84263d55307 | 307 | /** \brief Get CPACR |
AnnaBridge | 167:e84263d55307 | 308 | \return Coprocessor Access Control register value |
AnnaBridge | 167:e84263d55307 | 309 | */ |
AnnaBridge | 167:e84263d55307 | 310 | __STATIC_INLINE uint32_t __get_CPACR(void) |
AnnaBridge | 167:e84263d55307 | 311 | { |
AnnaBridge | 167:e84263d55307 | 312 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
AnnaBridge | 167:e84263d55307 | 313 | return __regCPACR; |
AnnaBridge | 167:e84263d55307 | 314 | } |
AnnaBridge | 167:e84263d55307 | 315 | |
AnnaBridge | 167:e84263d55307 | 316 | /** \brief Set CPACR |
AnnaBridge | 167:e84263d55307 | 317 | \param [in] cpacr Coprocessor Acccess Control value to set |
AnnaBridge | 167:e84263d55307 | 318 | */ |
AnnaBridge | 167:e84263d55307 | 319 | __STATIC_INLINE void __set_CPACR(uint32_t cpacr) |
AnnaBridge | 167:e84263d55307 | 320 | { |
AnnaBridge | 167:e84263d55307 | 321 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
AnnaBridge | 167:e84263d55307 | 322 | __regCPACR = cpacr; |
AnnaBridge | 167:e84263d55307 | 323 | } |
AnnaBridge | 167:e84263d55307 | 324 | |
AnnaBridge | 167:e84263d55307 | 325 | /** \brief Get CBAR |
AnnaBridge | 167:e84263d55307 | 326 | \return Configuration Base Address register value |
AnnaBridge | 167:e84263d55307 | 327 | */ |
AnnaBridge | 167:e84263d55307 | 328 | __STATIC_INLINE uint32_t __get_CBAR() { |
AnnaBridge | 167:e84263d55307 | 329 | register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); |
AnnaBridge | 167:e84263d55307 | 330 | return(__regCBAR); |
AnnaBridge | 167:e84263d55307 | 331 | } |
AnnaBridge | 167:e84263d55307 | 332 | |
AnnaBridge | 167:e84263d55307 | 333 | /** \brief Get TTBR0 |
AnnaBridge | 167:e84263d55307 | 334 | |
AnnaBridge | 167:e84263d55307 | 335 | This function returns the value of the Translation Table Base Register 0. |
AnnaBridge | 167:e84263d55307 | 336 | |
AnnaBridge | 167:e84263d55307 | 337 | \return Translation Table Base Register 0 value |
AnnaBridge | 167:e84263d55307 | 338 | */ |
AnnaBridge | 167:e84263d55307 | 339 | __STATIC_INLINE uint32_t __get_TTBR0() { |
AnnaBridge | 167:e84263d55307 | 340 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
AnnaBridge | 167:e84263d55307 | 341 | return(__regTTBR0); |
AnnaBridge | 167:e84263d55307 | 342 | } |
AnnaBridge | 167:e84263d55307 | 343 | |
AnnaBridge | 167:e84263d55307 | 344 | /** \brief Set TTBR0 |
AnnaBridge | 167:e84263d55307 | 345 | |
AnnaBridge | 167:e84263d55307 | 346 | This function assigns the given value to the Translation Table Base Register 0. |
AnnaBridge | 167:e84263d55307 | 347 | |
AnnaBridge | 167:e84263d55307 | 348 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
AnnaBridge | 167:e84263d55307 | 349 | */ |
AnnaBridge | 167:e84263d55307 | 350 | __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
AnnaBridge | 167:e84263d55307 | 351 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
AnnaBridge | 167:e84263d55307 | 352 | __regTTBR0 = ttbr0; |
AnnaBridge | 167:e84263d55307 | 353 | } |
AnnaBridge | 167:e84263d55307 | 354 | |
AnnaBridge | 167:e84263d55307 | 355 | /** \brief Get DACR |
AnnaBridge | 167:e84263d55307 | 356 | |
AnnaBridge | 167:e84263d55307 | 357 | This function returns the value of the Domain Access Control Register. |
AnnaBridge | 167:e84263d55307 | 358 | |
AnnaBridge | 167:e84263d55307 | 359 | \return Domain Access Control Register value |
AnnaBridge | 167:e84263d55307 | 360 | */ |
AnnaBridge | 167:e84263d55307 | 361 | __STATIC_INLINE uint32_t __get_DACR() { |
AnnaBridge | 167:e84263d55307 | 362 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
AnnaBridge | 167:e84263d55307 | 363 | return(__regDACR); |
AnnaBridge | 167:e84263d55307 | 364 | } |
AnnaBridge | 167:e84263d55307 | 365 | |
AnnaBridge | 167:e84263d55307 | 366 | /** \brief Set DACR |
AnnaBridge | 167:e84263d55307 | 367 | |
AnnaBridge | 167:e84263d55307 | 368 | This function assigns the given value to the Domain Access Control Register. |
AnnaBridge | 167:e84263d55307 | 369 | |
AnnaBridge | 167:e84263d55307 | 370 | \param [in] dacr Domain Access Control Register value to set |
AnnaBridge | 167:e84263d55307 | 371 | */ |
AnnaBridge | 167:e84263d55307 | 372 | __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
AnnaBridge | 167:e84263d55307 | 373 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
AnnaBridge | 167:e84263d55307 | 374 | __regDACR = dacr; |
AnnaBridge | 167:e84263d55307 | 375 | } |
AnnaBridge | 167:e84263d55307 | 376 | |
AnnaBridge | 167:e84263d55307 | 377 | /** \brief Set SCTLR |
AnnaBridge | 167:e84263d55307 | 378 | |
AnnaBridge | 167:e84263d55307 | 379 | This function assigns the given value to the System Control Register. |
AnnaBridge | 167:e84263d55307 | 380 | |
AnnaBridge | 167:e84263d55307 | 381 | \param [in] sctlr System Control Register value to set |
AnnaBridge | 167:e84263d55307 | 382 | */ |
AnnaBridge | 167:e84263d55307 | 383 | __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) |
AnnaBridge | 167:e84263d55307 | 384 | { |
AnnaBridge | 167:e84263d55307 | 385 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
AnnaBridge | 167:e84263d55307 | 386 | __regSCTLR = sctlr; |
AnnaBridge | 167:e84263d55307 | 387 | } |
AnnaBridge | 167:e84263d55307 | 388 | |
AnnaBridge | 167:e84263d55307 | 389 | /** \brief Get SCTLR |
AnnaBridge | 167:e84263d55307 | 390 | \return System Control Register value |
AnnaBridge | 167:e84263d55307 | 391 | */ |
AnnaBridge | 167:e84263d55307 | 392 | __STATIC_INLINE uint32_t __get_SCTLR() { |
AnnaBridge | 167:e84263d55307 | 393 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
AnnaBridge | 167:e84263d55307 | 394 | return(__regSCTLR); |
AnnaBridge | 167:e84263d55307 | 395 | } |
AnnaBridge | 167:e84263d55307 | 396 | |
AnnaBridge | 167:e84263d55307 | 397 | /** \brief Set ACTRL |
AnnaBridge | 167:e84263d55307 | 398 | \param [in] actrl Auxiliary Control Register value to set |
AnnaBridge | 167:e84263d55307 | 399 | */ |
AnnaBridge | 167:e84263d55307 | 400 | __STATIC_INLINE void __set_ACTRL(uint32_t actrl) |
AnnaBridge | 167:e84263d55307 | 401 | { |
AnnaBridge | 167:e84263d55307 | 402 | register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1"); |
AnnaBridge | 167:e84263d55307 | 403 | __regACTRL = actrl; |
AnnaBridge | 167:e84263d55307 | 404 | } |
AnnaBridge | 167:e84263d55307 | 405 | |
AnnaBridge | 167:e84263d55307 | 406 | /** \brief Get ACTRL |
AnnaBridge | 167:e84263d55307 | 407 | \return Auxiliary Control Register value |
AnnaBridge | 167:e84263d55307 | 408 | */ |
AnnaBridge | 167:e84263d55307 | 409 | __STATIC_INLINE uint32_t __get_ACTRL(void) |
AnnaBridge | 167:e84263d55307 | 410 | { |
AnnaBridge | 167:e84263d55307 | 411 | register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1"); |
AnnaBridge | 167:e84263d55307 | 412 | return(__regACTRL); |
AnnaBridge | 167:e84263d55307 | 413 | } |
AnnaBridge | 167:e84263d55307 | 414 | |
AnnaBridge | 167:e84263d55307 | 415 | /** \brief Get MPIDR |
AnnaBridge | 167:e84263d55307 | 416 | |
AnnaBridge | 167:e84263d55307 | 417 | This function returns the value of the Multiprocessor Affinity Register. |
AnnaBridge | 167:e84263d55307 | 418 | |
AnnaBridge | 167:e84263d55307 | 419 | \return Multiprocessor Affinity Register value |
AnnaBridge | 167:e84263d55307 | 420 | */ |
AnnaBridge | 167:e84263d55307 | 421 | __STATIC_INLINE uint32_t __get_MPIDR(void) |
AnnaBridge | 167:e84263d55307 | 422 | { |
AnnaBridge | 167:e84263d55307 | 423 | register uint32_t __regMPIDR __ASM("cp15:0:c0:c0:5"); |
AnnaBridge | 167:e84263d55307 | 424 | return(__regMPIDR); |
AnnaBridge | 167:e84263d55307 | 425 | } |
AnnaBridge | 167:e84263d55307 | 426 | |
AnnaBridge | 167:e84263d55307 | 427 | /** \brief Get VBAR |
AnnaBridge | 167:e84263d55307 | 428 | |
AnnaBridge | 167:e84263d55307 | 429 | This function returns the value of the Vector Base Address Register. |
AnnaBridge | 167:e84263d55307 | 430 | |
AnnaBridge | 167:e84263d55307 | 431 | \return Vector Base Address Register |
AnnaBridge | 167:e84263d55307 | 432 | */ |
AnnaBridge | 167:e84263d55307 | 433 | __STATIC_INLINE uint32_t __get_VBAR(void) |
AnnaBridge | 167:e84263d55307 | 434 | { |
AnnaBridge | 167:e84263d55307 | 435 | register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0"); |
AnnaBridge | 167:e84263d55307 | 436 | return(__regVBAR); |
AnnaBridge | 167:e84263d55307 | 437 | } |
AnnaBridge | 167:e84263d55307 | 438 | |
AnnaBridge | 167:e84263d55307 | 439 | /** \brief Set VBAR |
AnnaBridge | 167:e84263d55307 | 440 | |
AnnaBridge | 167:e84263d55307 | 441 | This function assigns the given value to the Vector Base Address Register. |
AnnaBridge | 167:e84263d55307 | 442 | |
AnnaBridge | 167:e84263d55307 | 443 | \param [in] vbar Vector Base Address Register value to set |
AnnaBridge | 167:e84263d55307 | 444 | */ |
AnnaBridge | 167:e84263d55307 | 445 | __STATIC_INLINE void __set_VBAR(uint32_t vbar) |
AnnaBridge | 167:e84263d55307 | 446 | { |
AnnaBridge | 167:e84263d55307 | 447 | register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0"); |
AnnaBridge | 167:e84263d55307 | 448 | __regVBAR = vbar; |
AnnaBridge | 167:e84263d55307 | 449 | } |
AnnaBridge | 167:e84263d55307 | 450 | |
AnnaBridge | 167:e84263d55307 | 451 | /** \brief Set CNTP_TVAL |
AnnaBridge | 167:e84263d55307 | 452 | |
AnnaBridge | 167:e84263d55307 | 453 | This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). |
AnnaBridge | 167:e84263d55307 | 454 | |
AnnaBridge | 167:e84263d55307 | 455 | \param [in] value CNTP_TVAL Register value to set |
AnnaBridge | 167:e84263d55307 | 456 | */ |
AnnaBridge | 167:e84263d55307 | 457 | __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 458 | register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0"); |
AnnaBridge | 167:e84263d55307 | 459 | __regCNTP_TVAL = value; |
AnnaBridge | 167:e84263d55307 | 460 | } |
AnnaBridge | 167:e84263d55307 | 461 | |
AnnaBridge | 167:e84263d55307 | 462 | /** \brief Get CNTP_TVAL |
AnnaBridge | 167:e84263d55307 | 463 | |
AnnaBridge | 167:e84263d55307 | 464 | This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). |
AnnaBridge | 167:e84263d55307 | 465 | |
AnnaBridge | 167:e84263d55307 | 466 | \return CNTP_TVAL Register value |
AnnaBridge | 167:e84263d55307 | 467 | */ |
AnnaBridge | 167:e84263d55307 | 468 | __STATIC_INLINE uint32_t __get_CNTP_TVAL() { |
AnnaBridge | 167:e84263d55307 | 469 | register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0"); |
AnnaBridge | 167:e84263d55307 | 470 | return(__regCNTP_TVAL); |
AnnaBridge | 167:e84263d55307 | 471 | } |
AnnaBridge | 167:e84263d55307 | 472 | |
AnnaBridge | 167:e84263d55307 | 473 | /** \brief Set CNTP_CTL |
AnnaBridge | 167:e84263d55307 | 474 | |
AnnaBridge | 167:e84263d55307 | 475 | This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). |
AnnaBridge | 167:e84263d55307 | 476 | |
AnnaBridge | 167:e84263d55307 | 477 | \param [in] value CNTP_CTL Register value to set |
AnnaBridge | 167:e84263d55307 | 478 | */ |
AnnaBridge | 167:e84263d55307 | 479 | __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 480 | register uint32_t __regCNTP_CTL __ASM("cp15:0:c14:c2:1"); |
AnnaBridge | 167:e84263d55307 | 481 | __regCNTP_CTL = value; |
AnnaBridge | 167:e84263d55307 | 482 | } |
AnnaBridge | 167:e84263d55307 | 483 | |
AnnaBridge | 167:e84263d55307 | 484 | /** \brief Set TLBIALL |
AnnaBridge | 167:e84263d55307 | 485 | |
AnnaBridge | 167:e84263d55307 | 486 | TLB Invalidate All |
AnnaBridge | 167:e84263d55307 | 487 | */ |
AnnaBridge | 167:e84263d55307 | 488 | __STATIC_INLINE void __set_TLBIALL(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 489 | register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); |
AnnaBridge | 167:e84263d55307 | 490 | __TLBIALL = value; |
AnnaBridge | 167:e84263d55307 | 491 | } |
AnnaBridge | 167:e84263d55307 | 492 | |
AnnaBridge | 167:e84263d55307 | 493 | /** \brief Set BPIALL. |
AnnaBridge | 167:e84263d55307 | 494 | |
AnnaBridge | 167:e84263d55307 | 495 | Branch Predictor Invalidate All |
AnnaBridge | 167:e84263d55307 | 496 | */ |
AnnaBridge | 167:e84263d55307 | 497 | __STATIC_INLINE void __set_BPIALL(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 498 | register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); |
AnnaBridge | 167:e84263d55307 | 499 | __BPIALL = value; |
AnnaBridge | 167:e84263d55307 | 500 | } |
AnnaBridge | 167:e84263d55307 | 501 | |
AnnaBridge | 167:e84263d55307 | 502 | /** \brief Set ICIALLU |
AnnaBridge | 167:e84263d55307 | 503 | |
AnnaBridge | 167:e84263d55307 | 504 | Instruction Cache Invalidate All |
AnnaBridge | 167:e84263d55307 | 505 | */ |
AnnaBridge | 167:e84263d55307 | 506 | __STATIC_INLINE void __set_ICIALLU(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 507 | register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); |
AnnaBridge | 167:e84263d55307 | 508 | __ICIALLU = value; |
AnnaBridge | 167:e84263d55307 | 509 | } |
AnnaBridge | 167:e84263d55307 | 510 | |
AnnaBridge | 167:e84263d55307 | 511 | /** \brief Set DCCMVAC |
AnnaBridge | 167:e84263d55307 | 512 | |
AnnaBridge | 167:e84263d55307 | 513 | Data cache clean |
AnnaBridge | 167:e84263d55307 | 514 | */ |
AnnaBridge | 167:e84263d55307 | 515 | __STATIC_INLINE void __set_DCCMVAC(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 516 | register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); |
AnnaBridge | 167:e84263d55307 | 517 | __DCCMVAC = value; |
AnnaBridge | 167:e84263d55307 | 518 | } |
AnnaBridge | 167:e84263d55307 | 519 | |
AnnaBridge | 167:e84263d55307 | 520 | /** \brief Set DCIMVAC |
AnnaBridge | 167:e84263d55307 | 521 | |
AnnaBridge | 167:e84263d55307 | 522 | Data cache invalidate |
AnnaBridge | 167:e84263d55307 | 523 | */ |
AnnaBridge | 167:e84263d55307 | 524 | __STATIC_INLINE void __set_DCIMVAC(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 525 | register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); |
AnnaBridge | 167:e84263d55307 | 526 | __DCIMVAC = value; |
AnnaBridge | 167:e84263d55307 | 527 | } |
AnnaBridge | 167:e84263d55307 | 528 | |
AnnaBridge | 167:e84263d55307 | 529 | /** \brief Set DCCIMVAC |
AnnaBridge | 167:e84263d55307 | 530 | |
AnnaBridge | 167:e84263d55307 | 531 | Data cache clean and invalidate |
AnnaBridge | 167:e84263d55307 | 532 | */ |
AnnaBridge | 167:e84263d55307 | 533 | __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) { |
AnnaBridge | 167:e84263d55307 | 534 | register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); |
AnnaBridge | 167:e84263d55307 | 535 | __DCCIMVAC = value; |
AnnaBridge | 167:e84263d55307 | 536 | } |
AnnaBridge | 167:e84263d55307 | 537 | |
AnnaBridge | 167:e84263d55307 | 538 | /** \brief Clean and Invalidate the entire data or unified cache |
AnnaBridge | 167:e84263d55307 | 539 | |
AnnaBridge | 167:e84263d55307 | 540 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency |
AnnaBridge | 167:e84263d55307 | 541 | */ |
AnnaBridge | 167:e84263d55307 | 542 | #pragma push |
AnnaBridge | 167:e84263d55307 | 543 | #pragma arm |
AnnaBridge | 167:e84263d55307 | 544 | __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) { |
AnnaBridge | 167:e84263d55307 | 545 | ARM |
AnnaBridge | 167:e84263d55307 | 546 | |
AnnaBridge | 167:e84263d55307 | 547 | PUSH {R4-R11} |
AnnaBridge | 167:e84263d55307 | 548 | |
AnnaBridge | 167:e84263d55307 | 549 | MRC p15, 1, R6, c0, c0, 1 // Read CLIDR |
AnnaBridge | 167:e84263d55307 | 550 | ANDS R3, R6, #0x07000000 // Extract coherency level |
AnnaBridge | 167:e84263d55307 | 551 | MOV R3, R3, LSR #23 // Total cache levels << 1 |
AnnaBridge | 167:e84263d55307 | 552 | BEQ Finished // If 0, no need to clean |
AnnaBridge | 167:e84263d55307 | 553 | |
AnnaBridge | 167:e84263d55307 | 554 | MOV R10, #0 // R10 holds current cache level << 1 |
AnnaBridge | 167:e84263d55307 | 555 | Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position |
AnnaBridge | 167:e84263d55307 | 556 | MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level |
AnnaBridge | 167:e84263d55307 | 557 | AND R1, R1, #7 // Isolate those lower 3 bits |
AnnaBridge | 167:e84263d55307 | 558 | CMP R1, #2 |
AnnaBridge | 167:e84263d55307 | 559 | BLT Skip // No cache or only instruction cache at this level |
AnnaBridge | 167:e84263d55307 | 560 | |
AnnaBridge | 167:e84263d55307 | 561 | MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register |
AnnaBridge | 167:e84263d55307 | 562 | ISB // ISB to sync the change to the CacheSizeID reg |
AnnaBridge | 167:e84263d55307 | 563 | MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register |
AnnaBridge | 167:e84263d55307 | 564 | AND R2, R1, #7 // Extract the line length field |
AnnaBridge | 167:e84263d55307 | 565 | ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) |
AnnaBridge | 167:e84263d55307 | 566 | LDR R4, =0x3FF |
AnnaBridge | 167:e84263d55307 | 567 | ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) |
AnnaBridge | 167:e84263d55307 | 568 | CLZ R5, R4 // R5 is the bit position of the way size increment |
AnnaBridge | 167:e84263d55307 | 569 | LDR R7, =0x7FFF |
AnnaBridge | 167:e84263d55307 | 570 | ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) |
AnnaBridge | 167:e84263d55307 | 571 | |
AnnaBridge | 167:e84263d55307 | 572 | Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned) |
AnnaBridge | 167:e84263d55307 | 573 | |
AnnaBridge | 167:e84263d55307 | 574 | Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 |
AnnaBridge | 167:e84263d55307 | 575 | ORR R11, R11, R7, LSL R2 // Factor in the Set number |
AnnaBridge | 167:e84263d55307 | 576 | CMP R0, #0 |
AnnaBridge | 167:e84263d55307 | 577 | BNE Dccsw |
AnnaBridge | 167:e84263d55307 | 578 | MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way |
AnnaBridge | 167:e84263d55307 | 579 | B cont |
AnnaBridge | 167:e84263d55307 | 580 | Dccsw CMP R0, #1 |
AnnaBridge | 167:e84263d55307 | 581 | BNE Dccisw |
AnnaBridge | 167:e84263d55307 | 582 | MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way |
AnnaBridge | 167:e84263d55307 | 583 | B cont |
AnnaBridge | 167:e84263d55307 | 584 | Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way |
AnnaBridge | 167:e84263d55307 | 585 | cont SUBS R9, R9, #1 // Decrement the Way number |
AnnaBridge | 167:e84263d55307 | 586 | BGE Loop3 |
AnnaBridge | 167:e84263d55307 | 587 | SUBS R7, R7, #1 // Decrement the Set number |
AnnaBridge | 167:e84263d55307 | 588 | BGE Loop2 |
AnnaBridge | 167:e84263d55307 | 589 | Skip ADD R10, R10, #2 // Increment the cache number |
AnnaBridge | 167:e84263d55307 | 590 | CMP R3, R10 |
AnnaBridge | 167:e84263d55307 | 591 | BGT Loop1 |
AnnaBridge | 167:e84263d55307 | 592 | |
AnnaBridge | 167:e84263d55307 | 593 | Finished |
AnnaBridge | 167:e84263d55307 | 594 | DSB |
AnnaBridge | 167:e84263d55307 | 595 | POP {R4-R11} |
AnnaBridge | 167:e84263d55307 | 596 | BX lr |
AnnaBridge | 167:e84263d55307 | 597 | } |
AnnaBridge | 167:e84263d55307 | 598 | #pragma pop |
AnnaBridge | 167:e84263d55307 | 599 | |
AnnaBridge | 167:e84263d55307 | 600 | /** \brief Enable Floating Point Unit |
AnnaBridge | 167:e84263d55307 | 601 | |
AnnaBridge | 167:e84263d55307 | 602 | Critical section, called from undef handler, so systick is disabled |
AnnaBridge | 167:e84263d55307 | 603 | */ |
AnnaBridge | 167:e84263d55307 | 604 | #pragma push |
AnnaBridge | 167:e84263d55307 | 605 | #pragma arm |
AnnaBridge | 167:e84263d55307 | 606 | __STATIC_INLINE __ASM void __FPU_Enable(void) { |
AnnaBridge | 167:e84263d55307 | 607 | ARM |
AnnaBridge | 167:e84263d55307 | 608 | |
AnnaBridge | 167:e84263d55307 | 609 | //Permit access to VFP/NEON, registers by modifying CPACR |
AnnaBridge | 167:e84263d55307 | 610 | MRC p15,0,R1,c1,c0,2 |
AnnaBridge | 167:e84263d55307 | 611 | ORR R1,R1,#0x00F00000 |
AnnaBridge | 167:e84263d55307 | 612 | MCR p15,0,R1,c1,c0,2 |
AnnaBridge | 167:e84263d55307 | 613 | |
AnnaBridge | 167:e84263d55307 | 614 | //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted |
AnnaBridge | 167:e84263d55307 | 615 | ISB |
AnnaBridge | 167:e84263d55307 | 616 | |
AnnaBridge | 167:e84263d55307 | 617 | //Enable VFP/NEON |
AnnaBridge | 167:e84263d55307 | 618 | VMRS R1,FPEXC |
AnnaBridge | 167:e84263d55307 | 619 | ORR R1,R1,#0x40000000 |
AnnaBridge | 167:e84263d55307 | 620 | VMSR FPEXC,R1 |
AnnaBridge | 167:e84263d55307 | 621 | |
AnnaBridge | 167:e84263d55307 | 622 | //Initialise VFP/NEON registers to 0 |
AnnaBridge | 167:e84263d55307 | 623 | MOV R2,#0 |
AnnaBridge | 167:e84263d55307 | 624 | IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 |
AnnaBridge | 167:e84263d55307 | 625 | //Initialise D16 registers to 0 |
AnnaBridge | 167:e84263d55307 | 626 | VMOV D0, R2,R2 |
AnnaBridge | 167:e84263d55307 | 627 | VMOV D1, R2,R2 |
AnnaBridge | 167:e84263d55307 | 628 | VMOV D2, R2,R2 |
AnnaBridge | 167:e84263d55307 | 629 | VMOV D3, R2,R2 |
AnnaBridge | 167:e84263d55307 | 630 | VMOV D4, R2,R2 |
AnnaBridge | 167:e84263d55307 | 631 | VMOV D5, R2,R2 |
AnnaBridge | 167:e84263d55307 | 632 | VMOV D6, R2,R2 |
AnnaBridge | 167:e84263d55307 | 633 | VMOV D7, R2,R2 |
AnnaBridge | 167:e84263d55307 | 634 | VMOV D8, R2,R2 |
AnnaBridge | 167:e84263d55307 | 635 | VMOV D9, R2,R2 |
AnnaBridge | 167:e84263d55307 | 636 | VMOV D10,R2,R2 |
AnnaBridge | 167:e84263d55307 | 637 | VMOV D11,R2,R2 |
AnnaBridge | 167:e84263d55307 | 638 | VMOV D12,R2,R2 |
AnnaBridge | 167:e84263d55307 | 639 | VMOV D13,R2,R2 |
AnnaBridge | 167:e84263d55307 | 640 | VMOV D14,R2,R2 |
AnnaBridge | 167:e84263d55307 | 641 | VMOV D15,R2,R2 |
AnnaBridge | 167:e84263d55307 | 642 | ENDIF |
AnnaBridge | 167:e84263d55307 | 643 | IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 |
AnnaBridge | 167:e84263d55307 | 644 | //Initialise D32 registers to 0 |
AnnaBridge | 167:e84263d55307 | 645 | VMOV D16,R2,R2 |
AnnaBridge | 167:e84263d55307 | 646 | VMOV D17,R2,R2 |
AnnaBridge | 167:e84263d55307 | 647 | VMOV D18,R2,R2 |
AnnaBridge | 167:e84263d55307 | 648 | VMOV D19,R2,R2 |
AnnaBridge | 167:e84263d55307 | 649 | VMOV D20,R2,R2 |
AnnaBridge | 167:e84263d55307 | 650 | VMOV D21,R2,R2 |
AnnaBridge | 167:e84263d55307 | 651 | VMOV D22,R2,R2 |
AnnaBridge | 167:e84263d55307 | 652 | VMOV D23,R2,R2 |
AnnaBridge | 167:e84263d55307 | 653 | VMOV D24,R2,R2 |
AnnaBridge | 167:e84263d55307 | 654 | VMOV D25,R2,R2 |
AnnaBridge | 167:e84263d55307 | 655 | VMOV D26,R2,R2 |
AnnaBridge | 167:e84263d55307 | 656 | VMOV D27,R2,R2 |
AnnaBridge | 167:e84263d55307 | 657 | VMOV D28,R2,R2 |
AnnaBridge | 167:e84263d55307 | 658 | VMOV D29,R2,R2 |
AnnaBridge | 167:e84263d55307 | 659 | VMOV D30,R2,R2 |
AnnaBridge | 167:e84263d55307 | 660 | VMOV D31,R2,R2 |
AnnaBridge | 167:e84263d55307 | 661 | ENDIF |
AnnaBridge | 167:e84263d55307 | 662 | |
AnnaBridge | 167:e84263d55307 | 663 | //Initialise FPSCR to a known state |
AnnaBridge | 167:e84263d55307 | 664 | VMRS R2,FPSCR |
AnnaBridge | 167:e84263d55307 | 665 | LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. |
AnnaBridge | 167:e84263d55307 | 666 | AND R2,R2,R3 |
AnnaBridge | 167:e84263d55307 | 667 | VMSR FPSCR,R2 |
AnnaBridge | 167:e84263d55307 | 668 | |
AnnaBridge | 167:e84263d55307 | 669 | BX LR |
AnnaBridge | 167:e84263d55307 | 670 | } |
AnnaBridge | 167:e84263d55307 | 671 | #pragma pop |
AnnaBridge | 167:e84263d55307 | 672 | |
AnnaBridge | 167:e84263d55307 | 673 | #endif /* __CMSIS_ARMCC_H */ |