Ben Katz / mbed-dev-f303

mbed library sources. Supersedes mbed-src.

Dependents:   Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32610/device/uart_regs.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_UART_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_UART_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file uart_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup uart UART
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Offset Register Description
<> 144:ef7eb2e8f9f7 50 ====== ============================================== */
<> 144:ef7eb2e8f9f7 51 typedef struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t ctrl; /* 0x0000 UART Control Register */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t status; /* 0x0004 UART Status Register */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t intfl; /* 0x000C Interrupt Flags */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t baud_int; /* 0x0010 Baud Rate Setting (Integer Portion) */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t baud_div_128; /* 0x0014 Baud Rate Setting */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t tx_fifo_out; /* 0x0018 TX FIFO Output End (read-only) */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t hw_flow_ctrl; /* 0x001C Hardware Flow Control Register */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t tx_rx_fifo; /* 0x0020 Write to load TX FIFO, Read to unload RX FIFO */
<> 144:ef7eb2e8f9f7 61 } mxc_uart_regs_t;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*
<> 144:ef7eb2e8f9f7 65 Register offsets for module UART.
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 #define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 68 #define MXC_R_UART_OFFS_STATUS ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 69 #define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 70 #define MXC_R_UART_OFFS_INTFL ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 71 #define MXC_R_UART_OFFS_BAUD_INT ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 72 #define MXC_R_UART_OFFS_BAUD_DIV_128 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 73 #define MXC_R_UART_OFFS_TX_FIFO_OUT ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 74 #define MXC_R_UART_OFFS_HW_FLOW_CTRL ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 75 #define MXC_R_UART_OFFS_TX_RX_FIFO ((uint32_t)0x00000020UL)
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /*
<> 144:ef7eb2e8f9f7 78 Field positions and masks for module UART.
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80 #define MXC_F_UART_CTRL_RX_THRESHOLD_POS 0
<> 144:ef7eb2e8f9f7 81 #define MXC_F_UART_CTRL_RX_THRESHOLD ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS))
<> 144:ef7eb2e8f9f7 82 #define MXC_F_UART_CTRL_PARITY_ENABLE_POS 4
<> 144:ef7eb2e8f9f7 83 #define MXC_F_UART_CTRL_PARITY_ENABLE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS))
<> 144:ef7eb2e8f9f7 84 #define MXC_F_UART_CTRL_PARITY_MODE_POS 5
<> 144:ef7eb2e8f9f7 85 #define MXC_F_UART_CTRL_PARITY_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS))
<> 144:ef7eb2e8f9f7 86 #define MXC_F_UART_CTRL_PARITY_BIAS_POS 6
<> 144:ef7eb2e8f9f7 87 #define MXC_F_UART_CTRL_PARITY_BIAS ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS))
<> 144:ef7eb2e8f9f7 88 #define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS 8
<> 144:ef7eb2e8f9f7 89 #define MXC_F_UART_CTRL_TX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS))
<> 144:ef7eb2e8f9f7 90 #define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS 9
<> 144:ef7eb2e8f9f7 91 #define MXC_F_UART_CTRL_RX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS))
<> 144:ef7eb2e8f9f7 92 #define MXC_F_UART_CTRL_CHAR_LENGTH_POS 10
<> 144:ef7eb2e8f9f7 93 #define MXC_F_UART_CTRL_CHAR_LENGTH ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS))
<> 144:ef7eb2e8f9f7 94 #define MXC_F_UART_CTRL_STOP_BIT_MODE_POS 12
<> 144:ef7eb2e8f9f7 95 #define MXC_F_UART_CTRL_STOP_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS))
<> 144:ef7eb2e8f9f7 96 #define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS 13
<> 144:ef7eb2e8f9f7 97 #define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS))
<> 144:ef7eb2e8f9f7 98 #define MXC_F_UART_CTRL_BAUD_CLK_EN_POS 14
<> 144:ef7eb2e8f9f7 99 #define MXC_F_UART_CTRL_BAUD_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS))
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #define MXC_F_UART_STATUS_TX_BUSY_POS 0
<> 144:ef7eb2e8f9f7 102 #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS))
<> 144:ef7eb2e8f9f7 103 #define MXC_F_UART_STATUS_RX_BUSY_POS 1
<> 144:ef7eb2e8f9f7 104 #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS))
<> 144:ef7eb2e8f9f7 105 #define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS 4
<> 144:ef7eb2e8f9f7 106 #define MXC_F_UART_STATUS_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS))
<> 144:ef7eb2e8f9f7 107 #define MXC_F_UART_STATUS_RX_FIFO_FULL_POS 5
<> 144:ef7eb2e8f9f7 108 #define MXC_F_UART_STATUS_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS))
<> 144:ef7eb2e8f9f7 109 #define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS 6
<> 144:ef7eb2e8f9f7 110 #define MXC_F_UART_STATUS_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS))
<> 144:ef7eb2e8f9f7 111 #define MXC_F_UART_STATUS_TX_FIFO_FULL_POS 7
<> 144:ef7eb2e8f9f7 112 #define MXC_F_UART_STATUS_TX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS))
<> 144:ef7eb2e8f9f7 113 #define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS 8
<> 144:ef7eb2e8f9f7 114 #define MXC_F_UART_STATUS_RX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS))
<> 144:ef7eb2e8f9f7 115 #define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS 12
<> 144:ef7eb2e8f9f7 116 #define MXC_F_UART_STATUS_TX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS))
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS 0
<> 144:ef7eb2e8f9f7 119 #define MXC_F_UART_INTEN_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS))
<> 144:ef7eb2e8f9f7 120 #define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS 1
<> 144:ef7eb2e8f9f7 121 #define MXC_F_UART_INTEN_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS))
<> 144:ef7eb2e8f9f7 122 #define MXC_F_UART_INTEN_CTS_CHANGE_POS 2
<> 144:ef7eb2e8f9f7 123 #define MXC_F_UART_INTEN_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS))
<> 144:ef7eb2e8f9f7 124 #define MXC_F_UART_INTEN_RX_OVERRUN_POS 3
<> 144:ef7eb2e8f9f7 125 #define MXC_F_UART_INTEN_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS))
<> 144:ef7eb2e8f9f7 126 #define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS 4
<> 144:ef7eb2e8f9f7 127 #define MXC_F_UART_INTEN_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS))
<> 144:ef7eb2e8f9f7 128 #define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS 5
<> 144:ef7eb2e8f9f7 129 #define MXC_F_UART_INTEN_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS))
<> 144:ef7eb2e8f9f7 130 #define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS 6
<> 144:ef7eb2e8f9f7 131 #define MXC_F_UART_INTEN_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS))
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 #define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS 0
<> 144:ef7eb2e8f9f7 134 #define MXC_F_UART_INTFL_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS 1
<> 144:ef7eb2e8f9f7 136 #define MXC_F_UART_INTFL_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_F_UART_INTFL_CTS_CHANGE_POS 2
<> 144:ef7eb2e8f9f7 138 #define MXC_F_UART_INTFL_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS))
<> 144:ef7eb2e8f9f7 139 #define MXC_F_UART_INTFL_RX_OVERRUN_POS 3
<> 144:ef7eb2e8f9f7 140 #define MXC_F_UART_INTFL_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS))
<> 144:ef7eb2e8f9f7 141 #define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS 4
<> 144:ef7eb2e8f9f7 142 #define MXC_F_UART_INTFL_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS 5
<> 144:ef7eb2e8f9f7 144 #define MXC_F_UART_INTFL_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS))
<> 144:ef7eb2e8f9f7 145 #define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS 6
<> 144:ef7eb2e8f9f7 146 #define MXC_F_UART_INTFL_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS))
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #define MXC_F_UART_BAUD_INT_FBAUD_POS 0
<> 144:ef7eb2e8f9f7 149 #define MXC_F_UART_BAUD_INT_FBAUD ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS))
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #define MXC_F_UART_BAUD_DIV_128_DIV_POS 0
<> 144:ef7eb2e8f9f7 152 #define MXC_F_UART_BAUD_DIV_128_DIV ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS))
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 #define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS 0
<> 144:ef7eb2e8f9f7 155 #define MXC_F_UART_TX_FIFO_OUT_TX_FIFO ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS))
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS 0
<> 144:ef7eb2e8f9f7 158 #define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS))
<> 144:ef7eb2e8f9f7 159 #define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS 1
<> 144:ef7eb2e8f9f7 160 #define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS))
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS 0
<> 144:ef7eb2e8f9f7 163 #define MXC_F_UART_TX_RX_FIFO_FIFO_DATA ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS))
<> 144:ef7eb2e8f9f7 164 #define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS 8
<> 144:ef7eb2e8f9f7 165 #define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS))
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169 #endif
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @}
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #endif /* _MXC_UART_REGS_H_ */