Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry_print_V_I

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Dependencies:   mbed-dsp mbed

Fork of Impedance_Fast_Circuitry by Jared Baxter

DMA_sampling/dma.cpp@58:4bee89daccff, 2016-02-19 (annotated)

Committer:
bmazzeo
Date:
Fri Feb 19 19:01:30 2016 +0000
Revision:
58:4bee89daccff
Parent:
57:7b8c49e1c1f6
Child:
59:1cfd9d9fb99d
Definitely working at 100 kHz sampling - however, because of the DMA, there are some artifacts at the time of the sampling because the DMA is not instantaneous.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 45:d591d138cdeb 1 /**
timmey9 45:d591d138cdeb 2 * Setup triggering for DMA2 and PortC
timmey9 34:44cc9b76a507 3 */
timmey9 34:44cc9b76a507 4 #include "dma.h"
timmey9 34:44cc9b76a507 5
bmazzeo 58:4bee89daccff 6 #define TOTAL_SAMPLES 256
timmey9 45:d591d138cdeb 7 int len = TOTAL_SAMPLES;
timmey9 45:d591d138cdeb 8 uint16_t sample_array0[TOTAL_SAMPLES];
timmey9 45:d591d138cdeb 9 uint16_t sample_array1[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 10
bmazzeo 54:1697dc574b96 11 uint16_t static_input_array0[TOTAL_SAMPLES];
bmazzeo 54:1697dc574b96 12 uint16_t static_input_array1[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 13
bmazzeo 55:2526b3317bc8 14 uint16_t static_output_array0[TOTAL_SAMPLES];
bmazzeo 56:7e08cbc3a4f1 15 uint16_t output_array0[TOTAL_SAMPLES];
timmey9 45:d591d138cdeb 16
bmazzeo 57:7b8c49e1c1f6 17 uint16_t sampling_status;
bmazzeo 57:7b8c49e1c1f6 18 uint16_t sampling_status_done = 1;
bmazzeo 57:7b8c49e1c1f6 19
timmey9 45:d591d138cdeb 20 void dma_init()
timmey9 34:44cc9b76a507 21 {
bmazzeo 54:1697dc574b96 22 // Enable clock for DMAMUX and DMA - all the peripherals need clocks to function
bmazzeo 54:1697dc574b96 23 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
bmazzeo 54:1697dc574b96 24 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
bmazzeo 54:1697dc574b96 25
bmazzeo 54:1697dc574b96 26
timmey9 45:d591d138cdeb 27 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
bmazzeo 54:1697dc574b96 28 DMAMUX_CHCFG0 = 0;
bmazzeo 54:1697dc574b96 29 DMAMUX_CHCFG1 = 0;
bmazzeo 54:1697dc574b96 30
timmey9 36:07d8a3143967 31
bmazzeo 54:1697dc574b96 32 // Enable request signal for channel 0, 1
bmazzeo 54:1697dc574b96 33 DMA_ERQ = 0;
bmazzeo 54:1697dc574b96 34 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK;
timmey9 45:d591d138cdeb 35
timmey9 45:d591d138cdeb 36 // select round-robin arbitration priority
timmey9 45:d591d138cdeb 37 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 45:d591d138cdeb 38
bmazzeo 55:2526b3317bc8 39 // Disable minor loop
bmazzeo 55:2526b3317bc8 40 DMA_CR &= ~DMA_CR_EMLM_MASK;
bmazzeo 56:7e08cbc3a4f1 41
bmazzeo 56:7e08cbc3a4f1 42 // DMA setup for ADC sampling
bmazzeo 54:1697dc574b96 43 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 54:1697dc574b96 44 DMA_TCD0_SADDR = (uint32_t) &ADC0_RA;
timmey9 45:d591d138cdeb 45 DMA_TCD0_DADDR = (uint32_t) sample_array0;
timmey9 50:33524a27e08c 46 DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
timmey9 45:d591d138cdeb 47 DMA_TCD1_DADDR = (uint32_t) sample_array1;
timmey9 36:07d8a3143967 48
timmey9 34:44cc9b76a507 49 // Set an offset for source and destination address
bmazzeo 55:2526b3317bc8 50 DMA_TCD0_SOFF = 0x00; // Source address offset of 0 bytes per transaction
bmazzeo 55:2526b3317bc8 51 DMA_TCD0_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
bmazzeo 55:2526b3317bc8 52 DMA_TCD1_SOFF = 0x00; // Source address offset of 0 bytes per transaction
bmazzeo 55:2526b3317bc8 53 DMA_TCD1_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
timmey9 34:44cc9b76a507 54
timmey9 34:44cc9b76a507 55 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 56 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 57 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 58
timmey9 34:44cc9b76a507 59 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 60 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 61 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 62
bmazzeo 54:1697dc574b96 63 // Major iteration count
timmey9 45:d591d138cdeb 64 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 65 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 45:d591d138cdeb 66 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 67 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 34:44cc9b76a507 68
timmey9 34:44cc9b76a507 69 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 45:d591d138cdeb 70 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
timmey9 45:d591d138cdeb 71
timmey9 44:41c262caf898 72 DMA_TCD0_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 73 DMA_TCD0_DLASTSGA = -len*2; // Destination address adjustment
timmey9 44:41c262caf898 74 DMA_TCD1_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 75 DMA_TCD1_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 76 // DMA_TCD2_SLAST = 0; // Source address adjustment
bmazzeo 54:1697dc574b96 77 // DMA_TCD2_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 78
bmazzeo 54:1697dc574b96 79 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
bmazzeo 54:1697dc574b96 80 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
bmazzeo 54:1697dc574b96 81 /* Source number Source module
bmazzeo 54:1697dc574b96 82 40 ADC0
bmazzeo 54:1697dc574b96 83 41 ADC1
bmazzeo 54:1697dc574b96 84 */
bmazzeo 54:1697dc574b96 85
bmazzeo 54:1697dc574b96 86
timmey9 34:44cc9b76a507 87 // Setup control and status register
timmey9 34:44cc9b76a507 88 DMA_TCD0_CSR = 0;
timmey9 36:07d8a3143967 89 DMA_TCD1_CSR = 0;
bmazzeo 54:1697dc574b96 90
bmazzeo 56:7e08cbc3a4f1 91 //
bmazzeo 56:7e08cbc3a4f1 92 // Now set up DAC DMA outputs from the output array
bmazzeo 56:7e08cbc3a4f1 93 //
bmazzeo 56:7e08cbc3a4f1 94 DMA_ERQ |= DMA_ERQ_ERQ2_MASK;
bmazzeo 54:1697dc574b96 95 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 56:7e08cbc3a4f1 96 DMA_TCD2_SADDR = (uint32_t) output_array0;
bmazzeo 56:7e08cbc3a4f1 97 DMA_TCD2_DADDR = (uint32_t) &DAC0_DAT0L;
bmazzeo 54:1697dc574b96 98
bmazzeo 54:1697dc574b96 99 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 100 DMA_TCD2_SOFF = 0x02; // Source address offset of 1 per transaction
bmazzeo 56:7e08cbc3a4f1 101 DMA_TCD2_DOFF = 0x00; // Destination address offset of 0 bytes per transaction
bmazzeo 54:1697dc574b96 102
bmazzeo 54:1697dc574b96 103 // Set source and destination data transfer size
bmazzeo 54:1697dc574b96 104 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 54:1697dc574b96 105
bmazzeo 54:1697dc574b96 106 // Number of bytes to be transfered in each service request of the channel
bmazzeo 56:7e08cbc3a4f1 107 DMA_TCD2_NBYTES_MLNO = 0x02;
bmazzeo 54:1697dc574b96 108
bmazzeo 56:7e08cbc3a4f1 109 // Major iteration count
bmazzeo 56:7e08cbc3a4f1 110 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 56:7e08cbc3a4f1 111 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 54:1697dc574b96 112
bmazzeo 54:1697dc574b96 113 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 54:1697dc574b96 114 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 54:1697dc574b96 115
bmazzeo 54:1697dc574b96 116 DMA_TCD2_SLAST = -len*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 117 DMA_TCD2_DLASTSGA = 0; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 118
bmazzeo 56:7e08cbc3a4f1 119 DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // PDB source
bmazzeo 56:7e08cbc3a4f1 120
bmazzeo 56:7e08cbc3a4f1 121
bmazzeo 56:7e08cbc3a4f1 122 //
bmazzeo 56:7e08cbc3a4f1 123 // Now set up static dataset linking once the ADC samples are recorded
bmazzeo 56:7e08cbc3a4f1 124 //
bmazzeo 56:7e08cbc3a4f1 125 // DMA Channels 4 and 5 now will be enabled
bmazzeo 56:7e08cbc3a4f1 126 DMA_ERQ |= DMA_ERQ_ERQ4_MASK | DMA_ERQ_ERQ5_MASK;
bmazzeo 56:7e08cbc3a4f1 127 DMA_TCD0_CSR |= DMA_CSR_MAJORLINKCH(4) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 56:7e08cbc3a4f1 128 DMA_TCD1_CSR |= DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 54:1697dc574b96 129
bmazzeo 56:7e08cbc3a4f1 130 // Set memory address for source and destination for DMA4 and DMA5
bmazzeo 56:7e08cbc3a4f1 131 DMA_TCD4_SADDR = (uint32_t) sample_array0;
bmazzeo 56:7e08cbc3a4f1 132 DMA_TCD4_DADDR = (uint32_t) static_input_array0;
bmazzeo 56:7e08cbc3a4f1 133 DMA_TCD5_SADDR = (uint32_t) sample_array1;
bmazzeo 56:7e08cbc3a4f1 134 DMA_TCD5_DADDR = (uint32_t) static_input_array1;
bmazzeo 56:7e08cbc3a4f1 135
bmazzeo 56:7e08cbc3a4f1 136 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 137 DMA_TCD4_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 138 DMA_TCD4_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 139 DMA_TCD5_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 140 DMA_TCD5_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 141
bmazzeo 56:7e08cbc3a4f1 142 // Set source and destination data transfer size
bmazzeo 56:7e08cbc3a4f1 143 DMA_TCD4_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 144 DMA_TCD5_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 145
bmazzeo 56:7e08cbc3a4f1 146 // Number of bytes to be transfered in each service request of the channel
bmazzeo 56:7e08cbc3a4f1 147 //DMA_TCD4_NBYTES_MLNO = 0x02 * TOTAL_SAMPLES;
bmazzeo 56:7e08cbc3a4f1 148 //DMA_TCD5_NBYTES_MLNO = 0x02 * TOTAL_SAMPLES;
bmazzeo 56:7e08cbc3a4f1 149 DMA_TCD4_NBYTES_MLNO = 0x02 * len;
bmazzeo 56:7e08cbc3a4f1 150 DMA_TCD5_NBYTES_MLNO = 0x02 * len;
bmazzeo 56:7e08cbc3a4f1 151
bmazzeo 56:7e08cbc3a4f1 152 // Current major iteration count
bmazzeo 56:7e08cbc3a4f1 153 DMA_TCD4_CITER_ELINKNO = 0x01;
bmazzeo 56:7e08cbc3a4f1 154 DMA_TCD4_BITER_ELINKNO = 0x01;
bmazzeo 56:7e08cbc3a4f1 155 DMA_TCD5_CITER_ELINKNO = 0x01;
bmazzeo 56:7e08cbc3a4f1 156 DMA_TCD5_BITER_ELINKNO = 0x01;
bmazzeo 56:7e08cbc3a4f1 157
bmazzeo 56:7e08cbc3a4f1 158 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 56:7e08cbc3a4f1 159 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 56:7e08cbc3a4f1 160
bmazzeo 56:7e08cbc3a4f1 161 DMA_TCD4_SLAST = -len*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 162 DMA_TCD4_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 163 DMA_TCD5_SLAST = -len*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 164 DMA_TCD5_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 165
bmazzeo 56:7e08cbc3a4f1 166 DMA_TCD4_CSR = 0;
bmazzeo 56:7e08cbc3a4f1 167 DMA_TCD5_CSR = 0;
bmazzeo 56:7e08cbc3a4f1 168
bmazzeo 56:7e08cbc3a4f1 169 //
bmazzeo 56:7e08cbc3a4f1 170 // Now set up linking from static DAC to memory for output through DMA
bmazzeo 56:7e08cbc3a4f1 171 //
bmazzeo 56:7e08cbc3a4f1 172 // DMA Channel 6 will be enabled
bmazzeo 56:7e08cbc3a4f1 173
bmazzeo 56:7e08cbc3a4f1 174 DMA_ERQ |= DMA_ERQ_ERQ6_MASK;
bmazzeo 56:7e08cbc3a4f1 175 DMA_TCD4_CSR |= DMA_CSR_MAJORLINKCH(6) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 55:2526b3317bc8 176
bmazzeo 56:7e08cbc3a4f1 177 // Set memory address for source and destination for DMA6
bmazzeo 56:7e08cbc3a4f1 178 DMA_TCD6_SADDR = (uint32_t) static_output_array0;
bmazzeo 56:7e08cbc3a4f1 179 DMA_TCD6_DADDR = (uint32_t) output_array0;
bmazzeo 56:7e08cbc3a4f1 180
bmazzeo 56:7e08cbc3a4f1 181 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 182 DMA_TCD6_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 183 DMA_TCD6_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 184
bmazzeo 56:7e08cbc3a4f1 185 // Set source and destination data transfer size
bmazzeo 56:7e08cbc3a4f1 186 DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 187 DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 188
bmazzeo 56:7e08cbc3a4f1 189 // Number of bytes to be transfered in each service request of the channel
bmazzeo 56:7e08cbc3a4f1 190 DMA_TCD6_NBYTES_MLNO = 0x02 * len;
bmazzeo 56:7e08cbc3a4f1 191
bmazzeo 56:7e08cbc3a4f1 192 // Current major iteration count
bmazzeo 56:7e08cbc3a4f1 193 DMA_TCD6_CITER_ELINKNO = 0x01;
bmazzeo 56:7e08cbc3a4f1 194 DMA_TCD6_BITER_ELINKNO = 0x01;
bmazzeo 56:7e08cbc3a4f1 195
bmazzeo 56:7e08cbc3a4f1 196 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 56:7e08cbc3a4f1 197 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 56:7e08cbc3a4f1 198
bmazzeo 56:7e08cbc3a4f1 199 DMA_TCD6_SLAST = -len*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 200 DMA_TCD6_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 201
bmazzeo 56:7e08cbc3a4f1 202 DMA_TCD6_CSR = 0;
bmazzeo 54:1697dc574b96 203
bmazzeo 57:7b8c49e1c1f6 204 //
bmazzeo 57:7b8c49e1c1f6 205 // Provide status
bmazzeo 57:7b8c49e1c1f6 206 //
bmazzeo 57:7b8c49e1c1f6 207
bmazzeo 57:7b8c49e1c1f6 208 // DMA Channel 8
bmazzeo 57:7b8c49e1c1f6 209 DMA_ERQ |= DMA_ERQ_ERQ8_MASK;
bmazzeo 57:7b8c49e1c1f6 210 DMA_TCD6_CSR |= DMA_CSR_MAJORLINKCH(8) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 57:7b8c49e1c1f6 211
bmazzeo 57:7b8c49e1c1f6 212 // Set memory address for source and destiantion for DMA 8
bmazzeo 57:7b8c49e1c1f6 213 DMA_TCD8_SADDR = (uint32_t) &sampling_status_done;
bmazzeo 57:7b8c49e1c1f6 214 DMA_TCD8_DADDR = (uint32_t) &sampling_status;
bmazzeo 57:7b8c49e1c1f6 215
bmazzeo 57:7b8c49e1c1f6 216 // Set an offset for source and destination address
bmazzeo 57:7b8c49e1c1f6 217 DMA_TCD8_SOFF = 0x00; // Source address offset of 2 bits per transaction
bmazzeo 57:7b8c49e1c1f6 218 DMA_TCD8_DOFF = 0x00; // Destination address offset of 1 bit per transaction
bmazzeo 57:7b8c49e1c1f6 219
bmazzeo 57:7b8c49e1c1f6 220 // Set source and destination data transfer size
bmazzeo 57:7b8c49e1c1f6 221 DMA_TCD8_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 57:7b8c49e1c1f6 222 DMA_TCD8_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 57:7b8c49e1c1f6 223
bmazzeo 57:7b8c49e1c1f6 224 // Number of bytes to be transfered in each service request of the channel
bmazzeo 57:7b8c49e1c1f6 225 DMA_TCD8_NBYTES_MLNO = 0x02;
bmazzeo 57:7b8c49e1c1f6 226
bmazzeo 57:7b8c49e1c1f6 227 // Current major iteration count
bmazzeo 57:7b8c49e1c1f6 228 DMA_TCD8_CITER_ELINKNO = 0x01;
bmazzeo 57:7b8c49e1c1f6 229 DMA_TCD8_BITER_ELINKNO = 0x01;
bmazzeo 57:7b8c49e1c1f6 230
bmazzeo 57:7b8c49e1c1f6 231 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 57:7b8c49e1c1f6 232 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 57:7b8c49e1c1f6 233
bmazzeo 57:7b8c49e1c1f6 234 DMA_TCD8_SLAST = 0; // Source address adjustment
bmazzeo 57:7b8c49e1c1f6 235 DMA_TCD8_DLASTSGA = 0; // Destination address adjustment
bmazzeo 57:7b8c49e1c1f6 236
bmazzeo 57:7b8c49e1c1f6 237 DMA_TCD8_CSR = 0;
bmazzeo 57:7b8c49e1c1f6 238
timmey9 51:43143a3fc2d7 239 }
timmey9 51:43143a3fc2d7 240
timmey9 51:43143a3fc2d7 241 void dma_reset() {
timmey9 51:43143a3fc2d7 242 // Set memory address for destinations back to the beginning
timmey9 51:43143a3fc2d7 243 dma_init();
timmey9 51:43143a3fc2d7 244 }
timmey9 51:43143a3fc2d7 245
timmey9 51:43143a3fc2d7 246
timmey9 51:43143a3fc2d7 247
timmey9 51:43143a3fc2d7 248
timmey9 51:43143a3fc2d7 249 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 50:33524a27e08c 250 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 50:33524a27e08c 251 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 50:33524a27e08c 252 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 50:33524a27e08c 253 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 50:33524a27e08c 254 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 50:33524a27e08c 255 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 50:33524a27e08c 256 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 50:33524a27e08c 257 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 50:33524a27e08c 258 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 50:33524a27e08c 259 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 50:33524a27e08c 260 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 50:33524a27e08c 261 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 50:33524a27e08c 262 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 51:43143a3fc2d7 263 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/