Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry_print_V_I

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Dependencies:   mbed-dsp mbed

Fork of Impedance_Fast_Circuitry by Jared Baxter

DMA_sampling/dma.cpp@70:8cd7a8a2c153, 2017-05-17 (annotated)

Committer:
baxterja
Date:
Wed May 17 23:10:03 2017 +0000
Revision:
70:8cd7a8a2c153
Parent:
69:014d4bbd4e03
Child:
72:0b554f5026b9
This is mostly working, however I get 4 samples repeated for each actual sample.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 45:d591d138cdeb 1 /**
timmey9 45:d591d138cdeb 2 * Setup triggering for DMA2 and PortC
timmey9 34:44cc9b76a507 3 */
timmey9 34:44cc9b76a507 4 #include "dma.h"
timmey9 34:44cc9b76a507 5
bmazzeo 65:f022535bed5d 6 #define TOTAL_SAMPLES 64
bmazzeo 65:f022535bed5d 7 #define SAMPLE_BUFFER_LENGTH 128
timmey9 45:d591d138cdeb 8 int len = TOTAL_SAMPLES;
bmazzeo 63:7903a33e2fd4 9 uint16_t sample_array0[SAMPLE_BUFFER_LENGTH];
bmazzeo 63:7903a33e2fd4 10 uint16_t sample_array1[SAMPLE_BUFFER_LENGTH];
timmey9 51:43143a3fc2d7 11
bmazzeo 54:1697dc574b96 12 uint16_t static_input_array0[TOTAL_SAMPLES];
bmazzeo 54:1697dc574b96 13 uint16_t static_input_array1[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 14
bmazzeo 55:2526b3317bc8 15 uint16_t static_output_array0[TOTAL_SAMPLES];
bmazzeo 63:7903a33e2fd4 16 uint16_t output_array0[SAMPLE_BUFFER_LENGTH];
baxterja 70:8cd7a8a2c153 17 uint32_t ADC0_LOCATION[2];
timmey9 45:d591d138cdeb 18
bmazzeo 57:7b8c49e1c1f6 19 uint16_t sampling_status;
bmazzeo 57:7b8c49e1c1f6 20 uint16_t sampling_status_done = 1;
bmazzeo 57:7b8c49e1c1f6 21
bmazzeo 63:7903a33e2fd4 22 uint16_t intermediate_status;
bmazzeo 63:7903a33e2fd4 23 uint16_t intermediate_status_done = 1;
bmazzeo 63:7903a33e2fd4 24
timmey9 45:d591d138cdeb 25 void dma_init()
timmey9 34:44cc9b76a507 26 {
baxterja 70:8cd7a8a2c153 27 ADC0_LOCATION[0] = 0x0C;
baxterja 70:8cd7a8a2c153 28 ADC0_LOCATION[1] = 0x0D;
bmazzeo 54:1697dc574b96 29 // Enable clock for DMAMUX and DMA - all the peripherals need clocks to function
bmazzeo 54:1697dc574b96 30 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
bmazzeo 54:1697dc574b96 31 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
bmazzeo 54:1697dc574b96 32
bmazzeo 54:1697dc574b96 33
timmey9 45:d591d138cdeb 34 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
bmazzeo 54:1697dc574b96 35 DMAMUX_CHCFG0 = 0;
bmazzeo 54:1697dc574b96 36 DMAMUX_CHCFG1 = 0;
bmazzeo 63:7903a33e2fd4 37 DMAMUX_CHCFG2 = 0;
bmazzeo 63:7903a33e2fd4 38 DMAMUX_CHCFG3 = 0;
bmazzeo 63:7903a33e2fd4 39 DMAMUX_CHCFG4 = 0;
bmazzeo 63:7903a33e2fd4 40 DMAMUX_CHCFG5 = 0;
bmazzeo 63:7903a33e2fd4 41 DMAMUX_CHCFG6 = 0;
bmazzeo 63:7903a33e2fd4 42 DMAMUX_CHCFG7 = 0;
bmazzeo 63:7903a33e2fd4 43 DMAMUX_CHCFG8 = 0;
bmazzeo 63:7903a33e2fd4 44 DMAMUX_CHCFG9 = 0;
baxterja 70:8cd7a8a2c153 45 DMAMUX_CHCFG10 = 0;
bmazzeo 54:1697dc574b96 46
bmazzeo 63:7903a33e2fd4 47
bmazzeo 54:1697dc574b96 48 // Enable request signal for channel 0, 1
bmazzeo 54:1697dc574b96 49 DMA_ERQ = 0;
bmazzeo 54:1697dc574b96 50 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK;
timmey9 45:d591d138cdeb 51
timmey9 45:d591d138cdeb 52 // select round-robin arbitration priority
timmey9 45:d591d138cdeb 53 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 45:d591d138cdeb 54
bmazzeo 55:2526b3317bc8 55 // Disable minor loop
bmazzeo 60:873a6d60c5d5 56 //DMA_CR &= ~DMA_CR_EMLM_MASK;
bmazzeo 60:873a6d60c5d5 57 DMA_CR |= DMA_CR_EMLM_MASK;
bmazzeo 56:7e08cbc3a4f1 58
bmazzeo 63:7903a33e2fd4 59 DMA_TCD0_CSR = 0;
bmazzeo 63:7903a33e2fd4 60 DMA_TCD1_CSR = 0;
bmazzeo 63:7903a33e2fd4 61 DMA_TCD2_CSR = 0;
bmazzeo 63:7903a33e2fd4 62 DMA_TCD3_CSR = 0;
bmazzeo 63:7903a33e2fd4 63 DMA_TCD4_CSR = 0;
bmazzeo 63:7903a33e2fd4 64 DMA_TCD5_CSR = 0;
bmazzeo 63:7903a33e2fd4 65 DMA_TCD6_CSR = 0;
bmazzeo 63:7903a33e2fd4 66 DMA_TCD7_CSR = 0;
bmazzeo 63:7903a33e2fd4 67 DMA_TCD8_CSR = 0;
bmazzeo 63:7903a33e2fd4 68 DMA_TCD9_CSR = 0;
baxterja 70:8cd7a8a2c153 69 DMA_TCD10_CSR = 0;
bmazzeo 63:7903a33e2fd4 70
bmazzeo 63:7903a33e2fd4 71
bmazzeo 56:7e08cbc3a4f1 72 // DMA setup for ADC sampling
bmazzeo 54:1697dc574b96 73 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 54:1697dc574b96 74 DMA_TCD0_SADDR = (uint32_t) &ADC0_RA;
timmey9 45:d591d138cdeb 75 DMA_TCD0_DADDR = (uint32_t) sample_array0;
timmey9 50:33524a27e08c 76 DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
timmey9 45:d591d138cdeb 77 DMA_TCD1_DADDR = (uint32_t) sample_array1;
timmey9 36:07d8a3143967 78
timmey9 34:44cc9b76a507 79 // Set an offset for source and destination address
bmazzeo 55:2526b3317bc8 80 DMA_TCD0_SOFF = 0x00; // Source address offset of 0 bytes per transaction
bmazzeo 55:2526b3317bc8 81 DMA_TCD0_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
bmazzeo 55:2526b3317bc8 82 DMA_TCD1_SOFF = 0x00; // Source address offset of 0 bytes per transaction
bmazzeo 55:2526b3317bc8 83 DMA_TCD1_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
timmey9 34:44cc9b76a507 84
timmey9 34:44cc9b76a507 85 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 86 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 87 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 88
timmey9 34:44cc9b76a507 89 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 90 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 91 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 92
bmazzeo 63:7903a33e2fd4 93
timmey9 44:41c262caf898 94 DMA_TCD0_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 95 DMA_TCD0_DLASTSGA = -len*2*2; // Destination address adjustment
timmey9 44:41c262caf898 96 DMA_TCD1_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 97 DMA_TCD1_DLASTSGA = -len*2*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 98 // DMA_TCD2_SLAST = 0; // Source address adjustment
bmazzeo 54:1697dc574b96 99 // DMA_TCD2_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 100
bmazzeo 62:51f722ef9cb1 101 //DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
bmazzeo 61:a56cca07d4a6 102 //DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
bmazzeo 54:1697dc574b96 103 /* Source number Source module
bmazzeo 54:1697dc574b96 104 40 ADC0
bmazzeo 54:1697dc574b96 105 41 ADC1
bmazzeo 54:1697dc574b96 106 */
bmazzeo 54:1697dc574b96 107
bmazzeo 63:7903a33e2fd4 108 DMA_TCD0_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(1) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 109 DMA_TCD0_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(1) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 110 DMA_TCD0_CSR = DMA_CSR_MAJORLINKCH(1) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 111 DMA_TCD1_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(8) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 112 DMA_TCD1_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(8) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 113 DMA_TCD1_CSR = DMA_CSR_MAJORLINKCH(8) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 114
bmazzeo 61:a56cca07d4a6 115 // Setup control and status register
bmazzeo 54:1697dc574b96 116
bmazzeo 56:7e08cbc3a4f1 117 //
bmazzeo 56:7e08cbc3a4f1 118 // Now set up DAC DMA outputs from the output array
bmazzeo 56:7e08cbc3a4f1 119 //
bmazzeo 56:7e08cbc3a4f1 120 DMA_ERQ |= DMA_ERQ_ERQ2_MASK;
bmazzeo 59:1cfd9d9fb99d 121 //DMA_TCD1_CSR |= DMA_CSR_MAJORLINKCH(2) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 59:1cfd9d9fb99d 122
bmazzeo 54:1697dc574b96 123 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 56:7e08cbc3a4f1 124 DMA_TCD2_SADDR = (uint32_t) output_array0;
bmazzeo 56:7e08cbc3a4f1 125 DMA_TCD2_DADDR = (uint32_t) &DAC0_DAT0L;
bmazzeo 54:1697dc574b96 126
bmazzeo 54:1697dc574b96 127 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 128 DMA_TCD2_SOFF = 0x02; // Source address offset of 1 per transaction
bmazzeo 56:7e08cbc3a4f1 129 DMA_TCD2_DOFF = 0x00; // Destination address offset of 0 bytes per transaction
bmazzeo 54:1697dc574b96 130
bmazzeo 54:1697dc574b96 131 // Set source and destination data transfer size
bmazzeo 54:1697dc574b96 132 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 54:1697dc574b96 133
bmazzeo 54:1697dc574b96 134 // Number of bytes to be transfered in each service request of the channel
bmazzeo 56:7e08cbc3a4f1 135 DMA_TCD2_NBYTES_MLNO = 0x02;
bmazzeo 63:7903a33e2fd4 136 //DMA_TCD2_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x00) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
bmazzeo 63:7903a33e2fd4 137 //DMA_TCD1_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x02) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
bmazzeo 63:7903a33e2fd4 138
bmazzeo 54:1697dc574b96 139
bmazzeo 56:7e08cbc3a4f1 140 // Major iteration count
bmazzeo 62:51f722ef9cb1 141 //DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 62:51f722ef9cb1 142 //DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 54:1697dc574b96 143
bmazzeo 54:1697dc574b96 144 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 54:1697dc574b96 145 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 54:1697dc574b96 146
bmazzeo 63:7903a33e2fd4 147 DMA_TCD2_SLAST = -len*2*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 148 DMA_TCD2_DLASTSGA = 0; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 149
baxterja 69:014d4bbd4e03 150 DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // ADC0 Source Jared's Note I think that this is actually the pdb timer
bmazzeo 62:51f722ef9cb1 151
bmazzeo 63:7903a33e2fd4 152 DMA_TCD2_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(0) | DMA_BITER_ELINKYES_BITER(len*2);
bmazzeo 63:7903a33e2fd4 153 DMA_TCD2_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(0) | DMA_CITER_ELINKYES_CITER(len*2);
bmazzeo 63:7903a33e2fd4 154 DMA_TCD2_CSR |= DMA_CSR_MAJORLINKCH(0) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 155
bmazzeo 56:7e08cbc3a4f1 156 //
bmazzeo 56:7e08cbc3a4f1 157 // Now set up static dataset linking once the ADC samples are recorded
bmazzeo 56:7e08cbc3a4f1 158 //
bmazzeo 56:7e08cbc3a4f1 159 // DMA Channels 4 and 5 now will be enabled
bmazzeo 56:7e08cbc3a4f1 160 DMA_ERQ |= DMA_ERQ_ERQ4_MASK | DMA_ERQ_ERQ5_MASK;
bmazzeo 54:1697dc574b96 161
bmazzeo 56:7e08cbc3a4f1 162 // Set memory address for source and destination for DMA4 and DMA5
bmazzeo 63:7903a33e2fd4 163 DMA_TCD4_SADDR = (uint32_t) &sample_array0;
bmazzeo 63:7903a33e2fd4 164 DMA_TCD4_DADDR = (uint32_t) &static_input_array0;
bmazzeo 63:7903a33e2fd4 165 DMA_TCD5_SADDR = (uint32_t) &sample_array1;
bmazzeo 63:7903a33e2fd4 166 DMA_TCD5_DADDR = (uint32_t) &static_input_array1;
bmazzeo 56:7e08cbc3a4f1 167
bmazzeo 56:7e08cbc3a4f1 168 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 169 DMA_TCD4_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 170 DMA_TCD4_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 171 DMA_TCD5_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 172 DMA_TCD5_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 173
bmazzeo 56:7e08cbc3a4f1 174 // Set source and destination data transfer size
bmazzeo 56:7e08cbc3a4f1 175 DMA_TCD4_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 176 DMA_TCD5_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 177
bmazzeo 63:7903a33e2fd4 178 DMA_TCD4_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 63:7903a33e2fd4 179 DMA_TCD5_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 56:7e08cbc3a4f1 180
bmazzeo 63:7903a33e2fd4 181 DMA_TCD4_SLAST = -len*2*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 182 DMA_TCD4_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 183 //DMA_TCD4_DLASTSGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 184 DMA_TCD5_SLAST = -len*2*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 185 DMA_TCD5_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 186 //DMA_TCD5_DLASTSGA = 0; // Destination address adjustment
bmazzeo 54:1697dc574b96 187
bmazzeo 63:7903a33e2fd4 188 //DMA_TCD4_CSR |= DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 189 DMA_TCD4_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(5) | DMA_BITER_ELINKYES_BITER(2);
bmazzeo 63:7903a33e2fd4 190 DMA_TCD4_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(5) | DMA_CITER_ELINKYES_CITER(2);
bmazzeo 63:7903a33e2fd4 191 DMA_TCD4_CSR = DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 192 DMA_TCD5_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(6) | DMA_BITER_ELINKYES_BITER(2);
bmazzeo 63:7903a33e2fd4 193 DMA_TCD5_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(6) | DMA_CITER_ELINKYES_CITER(2);
bmazzeo 63:7903a33e2fd4 194 DMA_TCD5_CSR = DMA_CSR_MAJORLINKCH(6) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 56:7e08cbc3a4f1 195
bmazzeo 56:7e08cbc3a4f1 196 //
bmazzeo 56:7e08cbc3a4f1 197 // Now set up linking from static DAC to memory for output through DMA
bmazzeo 56:7e08cbc3a4f1 198 //
bmazzeo 56:7e08cbc3a4f1 199 // DMA Channel 6 will be enabled
bmazzeo 56:7e08cbc3a4f1 200
bmazzeo 56:7e08cbc3a4f1 201 DMA_ERQ |= DMA_ERQ_ERQ6_MASK;
bmazzeo 55:2526b3317bc8 202
bmazzeo 56:7e08cbc3a4f1 203 // Set memory address for source and destination for DMA6
bmazzeo 56:7e08cbc3a4f1 204 DMA_TCD6_SADDR = (uint32_t) static_output_array0;
bmazzeo 56:7e08cbc3a4f1 205 DMA_TCD6_DADDR = (uint32_t) output_array0;
bmazzeo 56:7e08cbc3a4f1 206
bmazzeo 56:7e08cbc3a4f1 207 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 208 DMA_TCD6_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 209 DMA_TCD6_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 210
bmazzeo 56:7e08cbc3a4f1 211 // Set source and destination data transfer size
bmazzeo 56:7e08cbc3a4f1 212 DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 213 DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 214
bmazzeo 56:7e08cbc3a4f1 215
bmazzeo 63:7903a33e2fd4 216 DMA_TCD6_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 56:7e08cbc3a4f1 217
bmazzeo 56:7e08cbc3a4f1 218 DMA_TCD6_SLAST = -len*2; // Source address adjustment
bmazzeo 63:7903a33e2fd4 219 //DMA_TCD6_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 220 DMA_TCD6_DLASTSGA = -len*2*2; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 221
bmazzeo 63:7903a33e2fd4 222 DMA_TCD6_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(9) | DMA_BITER_ELINKYES_BITER(2);
bmazzeo 63:7903a33e2fd4 223 DMA_TCD6_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(9) | DMA_CITER_ELINKYES_CITER(2);
bmazzeo 63:7903a33e2fd4 224
bmazzeo 63:7903a33e2fd4 225 DMA_TCD6_CSR |= DMA_CSR_MAJORLINKCH(9) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 226
bmazzeo 57:7b8c49e1c1f6 227 //
bmazzeo 63:7903a33e2fd4 228 // Provide control for intermediate loops
bmazzeo 57:7b8c49e1c1f6 229 //
bmazzeo 57:7b8c49e1c1f6 230
bmazzeo 57:7b8c49e1c1f6 231 // DMA Channel 8
bmazzeo 57:7b8c49e1c1f6 232 DMA_ERQ |= DMA_ERQ_ERQ8_MASK;
bmazzeo 57:7b8c49e1c1f6 233
bmazzeo 57:7b8c49e1c1f6 234 // Set memory address for source and destiantion for DMA 8
bmazzeo 63:7903a33e2fd4 235 DMA_TCD8_SADDR = (uint32_t) &intermediate_status_done;
bmazzeo 63:7903a33e2fd4 236 DMA_TCD8_DADDR = (uint32_t) &intermediate_status;
bmazzeo 57:7b8c49e1c1f6 237
bmazzeo 57:7b8c49e1c1f6 238 // Set an offset for source and destination address
bmazzeo 57:7b8c49e1c1f6 239 DMA_TCD8_SOFF = 0x00; // Source address offset of 2 bits per transaction
bmazzeo 57:7b8c49e1c1f6 240 DMA_TCD8_DOFF = 0x00; // Destination address offset of 1 bit per transaction
bmazzeo 57:7b8c49e1c1f6 241
bmazzeo 57:7b8c49e1c1f6 242 // Set source and destination data transfer size
bmazzeo 57:7b8c49e1c1f6 243 DMA_TCD8_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 57:7b8c49e1c1f6 244 DMA_TCD8_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 57:7b8c49e1c1f6 245
bmazzeo 57:7b8c49e1c1f6 246 // Number of bytes to be transfered in each service request of the channel
bmazzeo 57:7b8c49e1c1f6 247 DMA_TCD8_NBYTES_MLNO = 0x02;
bmazzeo 57:7b8c49e1c1f6 248
bmazzeo 57:7b8c49e1c1f6 249 // Current major iteration count
bmazzeo 63:7903a33e2fd4 250 DMA_TCD8_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 63:7903a33e2fd4 251 DMA_TCD8_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 63:7903a33e2fd4 252
bmazzeo 57:7b8c49e1c1f6 253 DMA_TCD8_SLAST = 0; // Source address adjustment
bmazzeo 57:7b8c49e1c1f6 254 DMA_TCD8_DLASTSGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 255
bmazzeo 63:7903a33e2fd4 256 DMA_TCD8_CSR |= DMA_CSR_MAJORLINKCH(4) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 57:7b8c49e1c1f6 257
bmazzeo 63:7903a33e2fd4 258 //
bmazzeo 63:7903a33e2fd4 259 // Provide status
bmazzeo 63:7903a33e2fd4 260 //
bmazzeo 63:7903a33e2fd4 261
bmazzeo 63:7903a33e2fd4 262 // DMA Channel 9
bmazzeo 63:7903a33e2fd4 263 DMA_ERQ |= DMA_ERQ_ERQ9_MASK;
bmazzeo 63:7903a33e2fd4 264
bmazzeo 63:7903a33e2fd4 265 // Set memory address for source and destiantion for DMA 8
bmazzeo 63:7903a33e2fd4 266 DMA_TCD9_SADDR = (uint32_t) &sampling_status_done;
bmazzeo 63:7903a33e2fd4 267 DMA_TCD9_DADDR = (uint32_t) &sampling_status;
bmazzeo 57:7b8c49e1c1f6 268
bmazzeo 63:7903a33e2fd4 269 // Set an offset for source and destination address
bmazzeo 63:7903a33e2fd4 270 DMA_TCD9_SOFF = 0x00; // Source address offset of 2 bits per transaction
bmazzeo 63:7903a33e2fd4 271 DMA_TCD9_DOFF = 0x00; // Destination address offset of 1 bit per transaction
bmazzeo 63:7903a33e2fd4 272
bmazzeo 63:7903a33e2fd4 273 // Set source and destination data transfer size
bmazzeo 63:7903a33e2fd4 274 DMA_TCD9_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 63:7903a33e2fd4 275 DMA_TCD9_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 63:7903a33e2fd4 276
bmazzeo 63:7903a33e2fd4 277 // Number of bytes to be transfered in each service request of the channel
bmazzeo 63:7903a33e2fd4 278 DMA_TCD9_NBYTES_MLNO = 0x02;
bmazzeo 63:7903a33e2fd4 279
bmazzeo 63:7903a33e2fd4 280 // Current major iteration count
bmazzeo 63:7903a33e2fd4 281 DMA_TCD9_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 63:7903a33e2fd4 282 DMA_TCD9_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 63:7903a33e2fd4 283
bmazzeo 63:7903a33e2fd4 284 DMA_TCD9_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 285 DMA_TCD9_DLASTSGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 286
baxterja 70:8cd7a8a2c153 287 //JARED THIS IS WHERE YOU STARTED TO CHANGE THINGS
baxterja 70:8cd7a8a2c153 288 // Enable request signal for channel 10 this DMA swaps ADC0 between a0 and a1.
baxterja 70:8cd7a8a2c153 289 DMA_ERQ |= DMA_ERQ_ERQ10_MASK;
baxterja 70:8cd7a8a2c153 290
baxterja 70:8cd7a8a2c153 291
baxterja 70:8cd7a8a2c153 292 // DMA setup for ADC sampling
baxterja 70:8cd7a8a2c153 293 // Set memory address for source and destination for DMA0 and DMA1
baxterja 70:8cd7a8a2c153 294 //DMA_TCD10_SADDR = (uint32_t) &ADC0_RA;
baxterja 70:8cd7a8a2c153 295 //DMA_TCD10_DADDR = (uint32_t) sample_array0;
baxterja 70:8cd7a8a2c153 296 DMA_TCD10_SADDR = (uint32_t) ADC0_LOCATION;
baxterja 70:8cd7a8a2c153 297 DMA_TCD10_DADDR = (uint32_t) &ADC0_SC1A;
baxterja 70:8cd7a8a2c153 298
baxterja 70:8cd7a8a2c153 299
baxterja 70:8cd7a8a2c153 300
baxterja 70:8cd7a8a2c153 301 // Set an offset for source and destination address
baxterja 70:8cd7a8a2c153 302 DMA_TCD10_SOFF = 0x04; // Source address offset of 0 bytes per transaction
baxterja 70:8cd7a8a2c153 303 DMA_TCD10_DOFF = 0x00; // Destination address offset of 2 bytes per transaction
baxterja 70:8cd7a8a2c153 304
baxterja 70:8cd7a8a2c153 305
baxterja 70:8cd7a8a2c153 306 // Set source and destination data transfer size
baxterja 70:8cd7a8a2c153 307 DMA_TCD10_ATTR = DMA_ATTR_SSIZE(2) | DMA_ATTR_DSIZE(2);
baxterja 70:8cd7a8a2c153 308
baxterja 70:8cd7a8a2c153 309 // Number of bytes to be transfered in each service request of the channel
baxterja 70:8cd7a8a2c153 310 DMA_TCD10_NBYTES_MLNO = 0x04;
baxterja 70:8cd7a8a2c153 311
baxterja 70:8cd7a8a2c153 312
baxterja 70:8cd7a8a2c153 313
baxterja 70:8cd7a8a2c153 314 DMA_TCD10_SLAST = -(4*2); // Source address adjustment
baxterja 70:8cd7a8a2c153 315 DMA_TCD10_DLASTSGA = 0; // Destination address adjustment
baxterja 70:8cd7a8a2c153 316
baxterja 70:8cd7a8a2c153 317 //DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
baxterja 70:8cd7a8a2c153 318 //DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
baxterja 70:8cd7a8a2c153 319 /* Source number Source module
baxterja 70:8cd7a8a2c153 320 40 ADC0
baxterja 70:8cd7a8a2c153 321 41 ADC1
baxterja 70:8cd7a8a2c153 322 */
baxterja 70:8cd7a8a2c153 323
baxterja 70:8cd7a8a2c153 324
baxterja 70:8cd7a8a2c153 325 DMAMUX_CHCFG10 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC0 Source Jared's Note I think that this is actually the pdb timer
baxterja 70:8cd7a8a2c153 326
baxterja 70:8cd7a8a2c153 327 DMA_TCD10_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(0) | DMA_BITER_ELINKYES_BITER(2);
baxterja 70:8cd7a8a2c153 328 DMA_TCD10_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(0) | DMA_CITER_ELINKYES_CITER(2);
baxterja 70:8cd7a8a2c153 329 DMA_TCD10_CSR |= DMA_CSR_MAJORLINKCH(0) | DMA_CSR_MAJORELINK_MASK;
baxterja 69:014d4bbd4e03 330
baxterja 69:014d4bbd4e03 331
timmey9 51:43143a3fc2d7 332 }
timmey9 51:43143a3fc2d7 333
timmey9 51:43143a3fc2d7 334 void dma_reset() {
timmey9 51:43143a3fc2d7 335 // Set memory address for destinations back to the beginning
timmey9 51:43143a3fc2d7 336 dma_init();
timmey9 51:43143a3fc2d7 337 }
timmey9 51:43143a3fc2d7 338
timmey9 51:43143a3fc2d7 339
timmey9 51:43143a3fc2d7 340
timmey9 51:43143a3fc2d7 341
timmey9 51:43143a3fc2d7 342 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 50:33524a27e08c 343 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 50:33524a27e08c 344 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 50:33524a27e08c 345 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 50:33524a27e08c 346 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 50:33524a27e08c 347 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 50:33524a27e08c 348 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 50:33524a27e08c 349 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 50:33524a27e08c 350 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 50:33524a27e08c 351 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 50:33524a27e08c 352 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 50:33524a27e08c 353 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 50:33524a27e08c 354 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 50:33524a27e08c 355 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 51:43143a3fc2d7 356 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/