File content as of revision 53:83a90a47c1fd:

/**
 *  Setup triggering for DMA2 and PortC
 */
#include "dma.h"

#define TOTAL_SAMPLES 10
int len = TOTAL_SAMPLES;
uint16_t sample_array0[TOTAL_SAMPLES];
uint16_t sample_array1[TOTAL_SAMPLES];



/*  DMA0 and DMA1 are triggered by ADC0 and ADC1 (which are triggered
 *  by the PDB).  However, DMA2 is triggered directly by the PDB.  This
 *  is becuase DMA2 is reading FTM2, which cannot trigger the DMA.   */
void dma_init()
{
            
    // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
    DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
    DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
    /* Source number    Source module
           40                ADC0
           41                ADC1
    */
    
    
    // Enable request signal for channel 0 
    DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
    
    // select round-robin arbitration priority
    DMA_CR |= DMA_CR_ERCA_MASK;
    
    // Set memory address for source and destination for DMA0, DMA1, and DMA2
    DMA_TCD0_SADDR = (uint32_t) &ADC0_RB;
    DMA_TCD0_DADDR = (uint32_t) sample_array0;
    DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
    DMA_TCD1_DADDR = (uint32_t) sample_array1;
    
    // Set an offset for source and destination address
    DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
    DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
    DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
    DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
        
    // Set source and destination data transfer size
    DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
    DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
        
    // Number of bytes to be transfered in each service request of the channel
    DMA_TCD0_NBYTES_MLNO = 0x02;
    DMA_TCD1_NBYTES_MLNO = 0x02;
        
    // Current major iteration count (a single iteration of 5 bytes)
    DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
    DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
    DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
    DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
    
    // Adjustment value used to restore the source and destiny address to the initial value
    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
    
    DMA_TCD0_SLAST = 0;      // Source address adjustment
    DMA_TCD0_DLASTSGA = -len*2;  // Destination address adjustment
    DMA_TCD1_SLAST = 0;      // Source address adjustment
    DMA_TCD1_DLASTSGA = -len*2;  // Destination address adjustment
    DMA_TCD2_SLAST = 0;      // Source address adjustment
    DMA_TCD2_DLASTSGA = -len*2;  // Destination address adjustment
    
    // Setup control and status register
    DMA_TCD0_CSR = 0;
    DMA_TCD1_CSR = 0;
    DMA_TCD2_CSR = 0;
}

void dma_reset() {
    // Set memory address for destinations back to the beginning
    dma_init();
}




/*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
    pc.printf("DMA_ES: %08x\r\n", DMA_ES);
    pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
    pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
    pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
    pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
    pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
    pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
    pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
    pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
    pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
    pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
    pc.printf("DMA_INT: %08x\r\n", DMA_INT);
    pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
    pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/