Diff: dma.cpp

Revision:

45:d591d138cdeb

Parent:

44:41c262caf898

Child:

46:a015ebf4663b

--- a/dma.cpp	Fri Jan 30 14:56:58 2015 +0000
+++ b/dma.cpp	Sat Jan 31 07:25:52 2015 +0000
@@ -1,57 +1,42 @@
-/*
- * dma.c
- *
- *  Created on: Nov 25, 2014
- *      Author: Manuel Alejandro
+/**
+ *  Setup triggering for DMA2 and PortC
  */
 #include "dma.h"
 
-/*  dma_init()
- * Initializes the DMA module to read the ADC results every time a conversion has
- * finished and stores its value in a buffer
- * 
- * @array0 = destination where DMA0 writes
- * @array1 = destination where DMA1 writes
- * @array2 = destination where DMA2 writes
- * @len = the length of array1 and array2, and the number of reads the DMA completes
- * */
- 
-DMA::DMA(uint16_t* sample_array1, uint16_t* sample_array2, uint16_t* sample_array3,int len, int* relative_angle)
+#define TOTAL_SAMPLES 10
+int len = TOTAL_SAMPLES;
+uint16_t sample_array0[TOTAL_SAMPLES];
+uint16_t sample_array1[TOTAL_SAMPLES];
+uint16_t angle_array[TOTAL_SAMPLES];
+DigitalIn AMT20_A(PTC0); // FTM2_QD_PHA, apparently the k64f has a quadrature decoder.  look into this (page 264)
+DigitalIn AMT20_B(PTC1);
+
+void dma_init()
 {
-    _array1 = sample_array1;
-    _array2 = sample_array2;
-    _array3 = sample_array3;
-    _len = len;
-    _angle = (int*)PORTC_BASE_PTR;//relative_angle;
-    init();
-}
-
-
-void DMA::init()
-{
-    // select round-robin arbitration priority
-    DMA_CR |= DMA_CR_ERCA_MASK;
-    
     // Enable clock for DMAMUX and DMA
     SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
-    SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;    
+    SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;  
+    SIM_SCGC3 |= SIM_SCGC3_FTM2_MASK; // make sure clock is enabled for FTM2  
             
-    // Enable Channel 0 and set ADC0 as DMA request source 
-    DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // see page 95 of user manual
-    DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41);
+    // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
+    DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
+    DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
     DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_TRIG_MASK | DMAMUX_CHCFG_SOURCE(51); // PortC
     
     
     // Enable request signal for channel 0 
     DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
-        
+    
+    // select round-robin arbitration priority
+    DMA_CR |= DMA_CR_ERCA_MASK;
+    
     // Set memory address for source and destination for DMA0, DMA1, and DMA2
-    DMA_TCD0_SADDR = (uint32_t)&ADC0_RA;
-    DMA_TCD0_DADDR = (uint32_t) _array1;
-    DMA_TCD1_SADDR = (uint32_t)&ADC1_RA;
-    DMA_TCD1_DADDR = (uint32_t) _array2;
-    DMA_TCD2_SADDR = (uint32_t) PORTC_BASE_PTR;
-    DMA_TCD2_DADDR = (uint32_t) _array3;
+    DMA_TCD0_SADDR = (uint32_t) &ADC0_RA;
+    DMA_TCD0_DADDR = (uint32_t) sample_array0;
+    DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
+    DMA_TCD1_DADDR = (uint32_t) sample_array1;
+    DMA_TCD2_SADDR = (uint32_t) &FTM2_CNT;
+    DMA_TCD2_DADDR = (uint32_t) angle_array;
     
     // Set an offset for source and destination address
     DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
@@ -72,27 +57,29 @@
     DMA_TCD2_NBYTES_MLNO = 0x02;
         
     // Current major iteration count (a single iteration of 5 bytes)
-    DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(_len);
-    DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(_len);
-    DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(_len);
-    DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(_len);
-    DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(_len);
-    DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(_len);
+    DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+    DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+    DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
     
     // Adjustment value used to restore the source and destiny address to the initial value
-    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the address of 'array0')
+    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
+    
     DMA_TCD0_SLAST = 0;      // Source address adjustment
-    DMA_TCD0_DLASTSGA = 0;//-(_len*2);  // Destination address adjustment
+    DMA_TCD0_DLASTSGA = -len*2;  // Destination address adjustment
     DMA_TCD1_SLAST = 0;      // Source address adjustment
-    DMA_TCD1_DLASTSGA = 0;//-(_len*2);  // Destination address adjustment
+    DMA_TCD1_DLASTSGA = -len*2;  // Destination address adjustment
     DMA_TCD2_SLAST = 0;      // Source address adjustment
-    DMA_TCD2_DLASTSGA = 0;//-(_len*2);  // Destination address adjustment
+    DMA_TCD2_DLASTSGA = -len*2;  // Destination address adjustment
     
     // Setup control and status register
     DMA_TCD0_CSR = 0;
     DMA_TCD1_CSR = 0;
     DMA_TCD2_CSR = 1;
     
+    
     /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
     pc.printf("DMA_ES: %08x\r\n", DMA_ES);
     pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
@@ -110,7 +97,7 @@
     pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/
 }
 
-void DMA::reset() {
+void dma_reset() {
     // Set memory address for destinations back to the beginning
-    init();
+    dma_init();
 }