Diff: pdb.cpp

Revision:

47:54fafe151669

Parent:

46:a015ebf4663b

Child:

48:29f14bc30ba6

--- a/pdb.cpp	Sat Jan 31 08:13:33 2015 +0000
+++ b/pdb.cpp	Sat Jan 31 16:44:40 2015 +0000
@@ -7,14 +7,14 @@
     // initialize the Programmable Delay Block
     
     // turn on the clock to the PDB
-    SIM->SCGC6 |= SIM_SCGC6_PDB_MASK; 
+    SIM->SCGC6 |= SIM_SCGC6_PDB_MASK;
     
     // set ADC trigger to PDB0
     SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); 
-            
+    
     // Configure the Peripheral Delay Block (PDB):
-    PDB0_IDLY = 0x05;   // need to trigger interrupt every counter reset which happens when modulus reached
-    PDB0_MOD = 0xd2;
+    PDB0_IDLY = 0x01;   // need to trigger interrupt every counter reset which happens when modulus reached
+    PDB0_MOD = 0xffffffff;
     PDB0_CH0DLY0 = 0xa0;
     PDB0_CH0DLY1 = 0xa0;
     PDB0_CH1DLY0 = 0x00;
@@ -31,6 +31,7 @@
              | PDB_SC_MULT(0)     // Multiplication factor 20 for the prescale divider for the counter clock
              | PDB_SC_CONT_MASK   // Contintuous, rather than one-shot, mode
              | PDB_SC_LDOK_MASK;  // Need to ok the loading or it will not load certain regsiters!
+    //PDB0_SC &= ~PDB_SC_CONT_MASK;  // enable one-shot mode for debugging.
     
     debug2.printf("PDB0_SC:       %08x\r\n",PDB0_SC);
     debug2.printf("PDB0_MOD:      %08x\r\n",PDB0_MOD);
@@ -53,14 +54,14 @@
     debug2.printf("PDB0_PO1DLY:   %08x\r\n",PDB0_PO1DLY);
     debug2.printf("PDB0_PO2DLY:   %08x\r\n\n",PDB0_PO2DLY);
     
-    NVIC_SetVector(PDB0_IRQn, (uint32_t)&PDB0_IRQHandler);
-    NVIC_EnableIRQ(PDB0_IRQn);
-    
+    //NVIC_SetVector(PDB0_IRQn, (uint32_t)&PDB0_IRQHandler);
+    //NVIC_EnableIRQ(PDB0_IRQn);
 }
 
 
 void PDB0_IRQHandler() {
-    switcher = !switcher;
+    //switcher = !switcher;
+
 }