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Diff: adc.cpp
- Revision:
- 47:54fafe151669
- Parent:
- 46:a015ebf4663b
- Child:
- 48:29f14bc30ba6
--- a/adc.cpp Sat Jan 31 08:13:33 2015 +0000
+++ b/adc.cpp Sat Jan 31 16:44:40 2015 +0000
@@ -49,17 +49,17 @@
// Setup Configuration Register 2
ADC0_CFG2 = 0; // clear register
- ADC0_CFG2 |= ADC_CFG2_ADHSC_MASK ; // select high-speed conversion
+ ADC0_CFG2 |= ADC_CFG2_ADHSC_MASK ; // select high-speed conversion
ADC0_CFG2 &= ~ADC_CFG2_MUXSEL_MASK; // select a channels
// Setup Status and Control Register 2
- ADC0_SC2 = 0; // clear register
- ADC0_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
- ADC0_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
+ ADC0_SC2 = 0; // clear register
+ ADC0_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
+ ADC0_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
- ADC1_SC2 = 0; // clear register
- ADC1_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
- ADC1_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
+ ADC1_SC2 = 0; // clear register
+ ADC1_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
+ ADC1_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
// Setup Status and Control Register 3
@@ -103,9 +103,6 @@
-
-
-
// yellow indicating calibration complete
red = 0;
green = 0;
@@ -130,15 +127,10 @@
gain = ADC1_RA; // read the register to clear SC1A[COCO]
-
-
-
-
// green indicating calibration and initialization complete
red = 1;
green = 0;
-
debug.printf("ADC0_SC1a: %08x\r\n",ADC0_SC1A); //(0x0000004d)
debug.printf("ADC0_SC1b: %08x\r\n",ADC0_SC1B); //(0x0000001f)
debug.printf("ADC0_CFG1: %08x\r\n",ADC0_CFG1); //(0x0000000c)
@@ -149,8 +141,8 @@
debug.printf("ADC0_SC3: %08x\r\n\n",ADC0_SC3); //(0x00000000)
// Enable the ISR vector
- NVIC_SetVector(ADC0_IRQn, (uint32_t)&ADC0_IRQHandler);
- NVIC_EnableIRQ(ADC0_IRQn);
+ //NVIC_SetVector(ADC0_IRQn, (uint32_t)&ADC0_IRQHandler);
+ //NVIC_EnableIRQ(ADC0_IRQn);
}
void adc_start() {
@@ -162,12 +154,12 @@
ADC1_SC3 |= ADC_SC3_ADCO_MASK;
// set ADC to software trigger
+ ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK;
ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK;
// start ADC conversion (SW trigger)
ADC0_SC1A |= ADC_SC1_ADCH(13); // write to SC1A causing a trigger
ADC1_SC1A |= ADC_SC1_ADCH(14); // write to SC1A causing a trigger
- //BW_ADC_SC1n_ADCH(0, 0, kAdcChannel13); // trigger the ADC
}
void adc_stop() {
@@ -190,5 +182,6 @@
}
void ADC0_IRQHandler() {
+
toggle1 = !toggle1;
}
\ No newline at end of file

