Diff: DMA_sampling/dma.cpp

Revision:

55:2526b3317bc8

Parent:

54:1697dc574b96

Child:

56:7e08cbc3a4f1

--- a/DMA_sampling/dma.cpp	Tue Feb 16 18:33:44 2016 +0000
+++ b/DMA_sampling/dma.cpp	Wed Feb 17 20:26:26 2016 +0000
@@ -3,7 +3,7 @@
  */
 #include "dma.h"
 
-#define TOTAL_SAMPLES 1024
+#define TOTAL_SAMPLES 16
 int len = TOTAL_SAMPLES;
 uint16_t sample_array0[TOTAL_SAMPLES];
 uint16_t sample_array1[TOTAL_SAMPLES];
@@ -11,6 +11,7 @@
 uint16_t static_input_array0[TOTAL_SAMPLES];
 uint16_t static_input_array1[TOTAL_SAMPLES];
 
+uint16_t static_output_array0[TOTAL_SAMPLES];
 
 void dma_init()
 {
@@ -19,7 +20,6 @@
     SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;  
 
 
-// This first loop is what allows the DMA to get ADC samples            
     // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
     DMAMUX_CHCFG0 = 0;
     DMAMUX_CHCFG1 = 0;
@@ -32,6 +32,9 @@
     // select round-robin arbitration priority
     DMA_CR |= DMA_CR_ERCA_MASK;
     
+    // Disable minor loop
+    DMA_CR &= ~DMA_CR_EMLM_MASK;
+    
     // Set memory address for source and destination for DMA0 and DMA1
     DMA_TCD0_SADDR = (uint32_t) &ADC0_RA;
     DMA_TCD0_DADDR = (uint32_t) sample_array0;
@@ -39,10 +42,10 @@
     DMA_TCD1_DADDR = (uint32_t) sample_array1;
     
     // Set an offset for source and destination address
-    DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
-    DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
-    DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
-    DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
+    DMA_TCD0_SOFF = 0x00; // Source address offset of 0 bytes per transaction
+    DMA_TCD0_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
+    DMA_TCD1_SOFF = 0x00; // Source address offset of 0 bytes per transaction
+    DMA_TCD1_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
         
     // Set source and destination data transfer size
     DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
@@ -104,14 +107,16 @@
     DMA_TCD3_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
         
     // Number of bytes to be transfered in each service request of the channel
-    DMA_TCD2_NBYTES_MLNO = 0x02;
-    DMA_TCD3_NBYTES_MLNO = 0x02;
+    //DMA_TCD2_NBYTES_MLNO = 0x02 * TOTAL_SAMPLES;
+    //DMA_TCD3_NBYTES_MLNO = 0x02 * TOTAL_SAMPLES;
+    DMA_TCD2_NBYTES_MLNO = 0x02 * len; 
+    DMA_TCD3_NBYTES_MLNO = 0x02 * len; 
         
     // Current major iteration count
-    DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
-    DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
-    DMA_TCD3_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
-    DMA_TCD3_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+    DMA_TCD2_CITER_ELINKNO = 0x01;
+    DMA_TCD2_BITER_ELINKNO = 0x01;
+    DMA_TCD3_CITER_ELINKNO = 0x01;
+    DMA_TCD3_BITER_ELINKNO = 0x01;
     
     // Adjustment value used to restore the source and destiny address to the initial value
     // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
@@ -124,6 +129,10 @@
     DMA_TCD2_CSR = 0;
     DMA_TCD3_CSR = 0;
 
+// Now set up DAC
+    DMA_ERQ |= DMA_ERQ_ERQ4_MASK;
+    DMA_TCD0_CSR |= DMA_CSR_MAJORLINKCH(2) | DMA_CSR_MAJORELINK_MASK;
+
     
 }