Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Impedance Fast Circuitry Software

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

main.cpp@38:ec3b16c130d7, 2015-01-28 (annotated)

Committer:
timmey9
Date:
Wed Jan 28 04:56:07 2015 +0000
Revision:
38:ec3b16c130d7
Parent:
37:8bdc71f3e874
Child:
39:82dc3daecf32
Added lots of extra code, but the PDB still isn't working.  For this commit, I set the ADC so it works from a SW trigger in "timed_sampling".  The ADC and DMA are both working as of this commit.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 20:f533b3c9296f 1 // Server code
donatien 0:bb128f0e952f 2 #include "mbed.h"
timmey9 24:a5891669afc5 3 #include <stdio.h>
timmey9 22:523e316cbe70 4
timmey9 22:523e316cbe70 5 // Analog sampling
timmey9 22:523e316cbe70 6 #include "PeripheralNames.h"
timmey9 22:523e316cbe70 7 #include "PeripheralPins.h"
timmey9 22:523e316cbe70 8 #include "fsl_adc_hal.h"
timmey9 22:523e316cbe70 9 #include "fsl_clock_manager.h"
timmey9 22:523e316cbe70 10 #include "fsl_dspi_hal.h"
timmey9 22:523e316cbe70 11 #include "AngleEncoder.h"
timmey9 22:523e316cbe70 12
timmey9 34:44cc9b76a507 13 #include "dma.h"
timmey9 28:4a833d59897b 14
timmey9 22:523e316cbe70 15 // Analog sampling
timmey9 22:523e316cbe70 16 #define MAX_FADC 6000000
timmey9 36:07d8a3143967 17 #define SAMPLING_RATE 10 // In microseconds, so 10 us will be a sampling rate of 100 kHz
timmey9 36:07d8a3143967 18 #define TOTAL_SAMPLES 3 // originally 30000 for 0.3 ms of sampling.
timmey9 22:523e316cbe70 19
timmey9 22:523e316cbe70 20 #define LAST_SAMPLE_INDEX (TOTAL_SAMPLES-1) // If sampling time is 25 us, then 2000 corresponds to 50 ms
timmey9 22:523e316cbe70 21 #define FIRST_SAMPLE_INDEX 0
timmey9 22:523e316cbe70 22 #define BEGIN_SAMPLING 0xFFFFFFFF
timmey9 22:523e316cbe70 23 #define WAITING_TO_BEGIN (BEGIN_SAMPLING-1)
timmey9 22:523e316cbe70 24
timmey9 21:1fb5023b72af 25
timmey9 22:523e316cbe70 26 // for debug purposes
timmey9 18:b17ddeeb1c09 27 Serial pc(USBTX, USBRX);
timmey9 18:b17ddeeb1c09 28 DigitalOut led_red(LED_RED);
timmey9 18:b17ddeeb1c09 29 DigitalOut led_green(LED_GREEN);
timmey9 18:b17ddeeb1c09 30 DigitalOut led_blue(LED_BLUE);
timmey9 18:b17ddeeb1c09 31
timmey9 22:523e316cbe70 32 AngleEncoder angle_encoder(PTD2, PTD3, PTD1, PTD0, 8, 0, 1000000); // mosi, miso, sclk, cs, bit_width, mode, hz
timmey9 22:523e316cbe70 33 DigitalIn AMT20_A(PTC0); // input for quadrature encoding from angle encoder
timmey9 22:523e316cbe70 34 DigitalIn AMT20_B(PTC1); // input for quadrature encoding from angle encoder
timmey9 22:523e316cbe70 35
timmey9 22:523e316cbe70 36 // Analog sampling
timmey9 22:523e316cbe70 37 AnalogIn A0_pin(A0);
timmey9 22:523e316cbe70 38 AnalogIn A2_pin(A2);
timmey9 34:44cc9b76a507 39 Ticker Sampler;
timmey9 22:523e316cbe70 40
timmey9 22:523e316cbe70 41 uint32_t current_sample_index = WAITING_TO_BEGIN;
timmey9 25:abbc19af13f9 42 uint16_t sample_array1[TOTAL_SAMPLES];
timmey9 25:abbc19af13f9 43 uint16_t sample_array2[TOTAL_SAMPLES];
timmey9 22:523e316cbe70 44 uint16_t angle_array[TOTAL_SAMPLES];
timmey9 34:44cc9b76a507 45 float currA0 = 0;
timmey9 34:44cc9b76a507 46 float currA2 = 0;
timmey9 22:523e316cbe70 47
timmey9 22:523e316cbe70 48 // Declaration of functions
timmey9 22:523e316cbe70 49 void analog_initialization(PinName pin);
timmey9 22:523e316cbe70 50 void timed_sampling();
timmey9 22:523e316cbe70 51
timmey9 22:523e316cbe70 52 // Important globabl variables necessary for the sampling every interval
timmey9 22:523e316cbe70 53 int rotary_count = 0;
timmey9 22:523e316cbe70 54 uint32_t last_AMT20_AB_read = 0;
timmey9 23:9e5141647775 55
timmey9 22:523e316cbe70 56 using namespace std;
timmey9 17:2f978f823020 57
emilmont 7:65188f4a8c25 58 int main() {
timmey9 22:523e316cbe70 59 led_blue = 1;
timmey9 35:df40c4566826 60 led_green = 1;
timmey9 18:b17ddeeb1c09 61 led_red = 1;
timmey9 34:44cc9b76a507 62
timmey9 18:b17ddeeb1c09 63 pc.baud(230400);
timmey9 34:44cc9b76a507 64 pc.printf("Starting\r\n");
timmey9 27:8c2b30c855d1 65
timmey9 38:ec3b16c130d7 66
timmey9 38:ec3b16c130d7 67 // Turn on the ADC0 and ADC1 clocks as well as the PDB clocks to test ADC triggered by PDB
timmey9 38:ec3b16c130d7 68 SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
timmey9 38:ec3b16c130d7 69 SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
timmey9 38:ec3b16c130d7 70 SIM_SCGC6 |= SIM_SCGC6_PDB_MASK;
timmey9 38:ec3b16c130d7 71
timmey9 38:ec3b16c130d7 72
timmey9 38:ec3b16c130d7 73
timmey9 38:ec3b16c130d7 74 analog_initialization(A0);
timmey9 38:ec3b16c130d7 75 //analog_initialization(A2);
timmey9 38:ec3b16c130d7 76
timmey9 38:ec3b16c130d7 77 ADC0->CFG1 |= ADC_CFG1_ADLPC_MASK; // high power mode for faster frequencies
timmey9 38:ec3b16c130d7 78 //ADC0->SC2 |= ADC_SC2_ADTRG_MASK; // enable hardware trigger
timmey9 38:ec3b16c130d7 79 SIM_SOPT7 |= 0;
timmey9 38:ec3b16c130d7 80
timmey9 38:ec3b16c130d7 81 // put in continuous conversion mode
timmey9 38:ec3b16c130d7 82 //pc.printf("ADC0_SC3: %08x\r\n", ADC0->SC3);
timmey9 38:ec3b16c130d7 83
timmey9 38:ec3b16c130d7 84 // enable the DMA
timmey9 38:ec3b16c130d7 85 ADC0->SC2 |= ADC_SC2_DMAEN_MASK;
timmey9 38:ec3b16c130d7 86 //ADC1->SC2 |= ADC_SC2_DMAEN_MASK;
timmey9 38:ec3b16c130d7 87 ADC0->SC3 = 0; // Reset SC3
timmey9 38:ec3b16c130d7 88 //ADC1->SC3 = 0; // Reset SC3
timmey9 38:ec3b16c130d7 89
timmey9 38:ec3b16c130d7 90 dma_init(sample_array1, sample_array2, angle_array, TOTAL_SAMPLES);
timmey9 38:ec3b16c130d7 91
timmey9 37:8bdc71f3e874 92 // initialize the Programmable Delay Block
timmey9 38:ec3b16c130d7 93 SIM->SCGC6 |= SIM_SCGC6_PDB_MASK; // turn on the clock to the PDB
timmey9 38:ec3b16c130d7 94
timmey9 38:ec3b16c130d7 95
timmey9 38:ec3b16c130d7 96 // Configure System Integration Module for defaults as far as ADC
timmey9 38:ec3b16c130d7 97 SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK | // selects PDB not ALT trigger
timmey9 38:ec3b16c130d7 98 SIM_SOPT7_ADC1PRETRGSEL_MASK |
timmey9 38:ec3b16c130d7 99 SIM_SOPT7_ADC0ALTTRGEN_MASK | // selects PDB not ALT trigger
timmey9 38:ec3b16c130d7 100 SIM_SOPT7_ADC0ALTTRGEN_MASK) ;
timmey9 38:ec3b16c130d7 101 SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); // applies only in case of ALT trigger, in which case PDB external pin input trigger for ADC
timmey9 38:ec3b16c130d7 102 SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); // same for both ADCs
timmey9 38:ec3b16c130d7 103
timmey9 38:ec3b16c130d7 104
timmey9 38:ec3b16c130d7 105
timmey9 38:ec3b16c130d7 106 // Configure the Peripheral Delay Block (PDB):
timmey9 38:ec3b16c130d7 107 // enable PDB, pdb counter clock = busclock / 20 , continous triggers, sw trigger , and use prescaler too
timmey9 38:ec3b16c130d7 108 PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode
timmey9 38:ec3b16c130d7 109 | PDB_SC_PDBEN_MASK // PDB enabled
timmey9 38:ec3b16c130d7 110 //| PDB_SC_PDBIE_MASK // PDB Interrupt Enable
timmey9 38:ec3b16c130d7 111 | PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing
timmey9 38:ec3b16c130d7 112 | PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file
timmey9 38:ec3b16c130d7 113 | PDB_SC_MULT(2); // Multiplication factor 20 for the prescale divider for the counter clock
timmey9 38:ec3b16c130d7 114 // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
timmey9 38:ec3b16c130d7 115
timmey9 38:ec3b16c130d7 116 PDB0_IDLY = 0x0000; // need to trigger interrupt every counter reset which happens when modulus reached
timmey9 38:ec3b16c130d7 117
timmey9 38:ec3b16c130d7 118 PDB0_MOD = 0xffff; // largest period possible with the slections above, so slow you can see each conversion.
timmey9 38:ec3b16c130d7 119
timmey9 38:ec3b16c130d7 120 // channel 0 pretrigger 0 and 1 enabled and delayed
timmey9 38:ec3b16c130d7 121 PDB0_CH0C1 = PDB_C1_EN(0x01)
timmey9 38:ec3b16c130d7 122 | PDB_C1_TOS(0x01)
timmey9 38:ec3b16c130d7 123 | PDB_C1_EN(0x02)
timmey9 38:ec3b16c130d7 124 | PDB_C1_TOS(0x02) ;
timmey9 38:ec3b16c130d7 125
timmey9 38:ec3b16c130d7 126 PDB0_CH0DLY0 = 100 ;
timmey9 38:ec3b16c130d7 127 PDB0_CH0DLY1 = 300 ;
timmey9 38:ec3b16c130d7 128
timmey9 38:ec3b16c130d7 129 // channel 1 pretrigger 0 and 1 enabled and delayed
timmey9 38:ec3b16c130d7 130 PDB0_CH1C1 = PDB_C1_EN(0x01)
timmey9 38:ec3b16c130d7 131 | PDB_C1_TOS(0x01)
timmey9 38:ec3b16c130d7 132 | PDB_C1_EN(0x02)
timmey9 38:ec3b16c130d7 133 | PDB_C1_TOS(0x02) ;
timmey9 38:ec3b16c130d7 134
timmey9 38:ec3b16c130d7 135 PDB0_CH1DLY0 = 200 ;
timmey9 38:ec3b16c130d7 136 PDB0_CH1DLY1 = 400 ;
timmey9 38:ec3b16c130d7 137
timmey9 38:ec3b16c130d7 138 PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode
timmey9 38:ec3b16c130d7 139 | PDB_SC_PDBEN_MASK // PDB enabled
timmey9 38:ec3b16c130d7 140 | PDB_SC_PDBIE_MASK // PDB Interrupt Enable
timmey9 38:ec3b16c130d7 141 | PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing
timmey9 38:ec3b16c130d7 142 | PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file
timmey9 38:ec3b16c130d7 143 | PDB_SC_MULT(2) // Multiplication factor 20 for the prescale divider for the counter clock
timmey9 38:ec3b16c130d7 144 | PDB_SC_LDOK_MASK; // Need to ok the loading or it will not load certain regsiters!
timmey9 38:ec3b16c130d7 145 // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
timmey9 38:ec3b16c130d7 146
timmey9 38:ec3b16c130d7 147
timmey9 38:ec3b16c130d7 148
timmey9 38:ec3b16c130d7 149 //PDB configured above
timmey9 38:ec3b16c130d7 150 /////////////////////////////////////////////////////////////////////////////////////////
timmey9 38:ec3b16c130d7 151 //ADC configured below
timmey9 38:ec3b16c130d7 152 /*
timmey9 38:ec3b16c130d7 153 // setup the initial ADC default configuration
timmey9 38:ec3b16c130d7 154 Master_Adc_Config.CONFIG1 = ADLPC_NORMAL
timmey9 38:ec3b16c130d7 155 | ADC_CFG1_ADIV(ADIV_4)
timmey9 38:ec3b16c130d7 156 | ADLSMP_LONG
timmey9 38:ec3b16c130d7 157 | ADC_CFG1_MODE(MODE_16)
timmey9 38:ec3b16c130d7 158 | ADC_CFG1_ADICLK(ADICLK_BUS);
timmey9 38:ec3b16c130d7 159 Master_Adc_Config.CONFIG2 = MUXSEL_ADCA
timmey9 38:ec3b16c130d7 160 | ADACKEN_DISABLED
timmey9 38:ec3b16c130d7 161 | ADHSC_HISPEED
timmey9 38:ec3b16c130d7 162 | ADC_CFG2_ADLSTS(ADLSTS_20) ;
timmey9 38:ec3b16c130d7 163 Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything
timmey9 38:ec3b16c130d7 164 Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything
timmey9 38:ec3b16c130d7 165 // since not using
timmey9 38:ec3b16c130d7 166 // compare feature
timmey9 38:ec3b16c130d7 167 Master_Adc_Config.STATUS2 = ADTRG_HW
timmey9 38:ec3b16c130d7 168 | ACFE_DISABLED
timmey9 38:ec3b16c130d7 169 | ACFGT_GREATER
timmey9 38:ec3b16c130d7 170 | ACREN_ENABLED
timmey9 38:ec3b16c130d7 171 | DMAEN_DISABLED
timmey9 38:ec3b16c130d7 172 | ADC_SC2_REFSEL(REFSEL_EXT);
timmey9 38:ec3b16c130d7 173
timmey9 38:ec3b16c130d7 174 Master_Adc_Config.STATUS3 = CAL_OFF
timmey9 38:ec3b16c130d7 175 | ADCO_SINGLE
timmey9 38:ec3b16c130d7 176 | AVGE_ENABLED
timmey9 38:ec3b16c130d7 177 | ADC_SC3_AVGS(AVGS_32);
timmey9 38:ec3b16c130d7 178
timmey9 38:ec3b16c130d7 179 Master_Adc_Config.PGA = PGAEN_DISABLED
timmey9 38:ec3b16c130d7 180 | PGACHP_NOCHOP
timmey9 38:ec3b16c130d7 181 | PGALP_NORMAL
timmey9 38:ec3b16c130d7 182 | ADC_PGA_PGAG(PGAG_64);
timmey9 38:ec3b16c130d7 183 Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
timmey9 38:ec3b16c130d7 184 Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
timmey9 38:ec3b16c130d7 185
timmey9 38:ec3b16c130d7 186
timmey9 38:ec3b16c130d7 187 // Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31,
timmey9 38:ec3b16c130d7 188 // the ADC will be inactive. Channel 31 is just disable function.
timmey9 38:ec3b16c130d7 189 // There really is no channel 31.
timmey9 38:ec3b16c130d7 190
timmey9 38:ec3b16c130d7 191 ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC
timmey9 38:ec3b16c130d7 192
timmey9 38:ec3b16c130d7 193 // Calibrate the ADC in the configuration in which it will be used:
timmey9 38:ec3b16c130d7 194 ADC_Cal(ADC0_BASE_PTR); // do the calibration
timmey9 38:ec3b16c130d7 195
timmey9 38:ec3b16c130d7 196 // The structure still has the desired configuration. So restore it.
timmey9 38:ec3b16c130d7 197 // Why restore it? The calibration makes some adjustments to the
timmey9 38:ec3b16c130d7 198 // configuration of the ADC. The are now undone:
timmey9 38:ec3b16c130d7 199
timmey9 38:ec3b16c130d7 200 // config the ADC again to desired conditions
timmey9 38:ec3b16c130d7 201 ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);
timmey9 38:ec3b16c130d7 202
timmey9 38:ec3b16c130d7 203 // REPEAT for BOTH ADC's. However we will only 'use' the results from
timmey9 38:ec3b16c130d7 204 // the ADC wired to the Potentiometer on the Kinetis Tower Card.
timmey9 38:ec3b16c130d7 205
timmey9 38:ec3b16c130d7 206 // Repeating for ADC1:
timmey9 38:ec3b16c130d7 207 ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC
timmey9 38:ec3b16c130d7 208 ADC_Cal(ADC1_BASE_PTR); // do the calibration
timmey9 38:ec3b16c130d7 209 // ADC_Read_Cal(ADC1_BASE_PTR,&CalibrationStore[0]); // store the cal
timmey9 38:ec3b16c130d7 210
timmey9 38:ec3b16c130d7 211
timmey9 38:ec3b16c130d7 212 // config the ADC again to default conditions
timmey9 38:ec3b16c130d7 213 ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config);
timmey9 38:ec3b16c130d7 214
timmey9 38:ec3b16c130d7 215 // *****************************************************************************
timmey9 38:ec3b16c130d7 216 // ADC0 and ADC1 using the PDB trigger in ping pong
timmey9 38:ec3b16c130d7 217 // *****************************************************************************
timmey9 38:ec3b16c130d7 218
timmey9 38:ec3b16c130d7 219 // use interrupts, single ended mode, and real channel numbers now:
timmey9 38:ec3b16c130d7 220
timmey9 38:ec3b16c130d7 221 Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANA);
timmey9 38:ec3b16c130d7 222 Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANB);
timmey9 38:ec3b16c130d7 223 ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC0
timmey9 38:ec3b16c130d7 224
timmey9 38:ec3b16c130d7 225 Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANA);
timmey9 38:ec3b16c130d7 226 Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANB);
timmey9 38:ec3b16c130d7 227 ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC1
timmey9 38:ec3b16c130d7 228 */
timmey9 37:8bdc71f3e874 229
timmey9 37:8bdc71f3e874 230
timmey9 37:8bdc71f3e874 231
timmey9 37:8bdc71f3e874 232
timmey9 37:8bdc71f3e874 233
timmey9 38:ec3b16c130d7 234 /*
timmey9 38:ec3b16c130d7 235 PDB0->SC = 0x0100; // DMA enable and Load OK
timmey9 38:ec3b16c130d7 236 PDB0->MOD = 1000;// the period of the PDB
timmey9 38:ec3b16c130d7 237 // AOS
timmey9 38:ec3b16c130d7 238 PDB0->SC |= PDB_SC_CONT_MASK; // run PDB in continuous mode
timmey9 38:ec3b16c130d7 239 PDB0->SC |= PDB_SC_TRGSEL(7); // set trigger selection to 7
timmey9 38:ec3b16c130d7 240 PDB0->SC |= PDB_SC_LDOK_MASK; // load values into the register
timmey9 38:ec3b16c130d7 241 PDB0->SC |= PDB_SC_PDBEN_MASK; // enables the PDB
timmey9 38:ec3b16c130d7 242 PDB0->SC |= PDB_SC_SWTRIG_MASK; // enable software trigger (start the PDB)
timmey9 38:ec3b16c130d7 243 */
timmey9 38:ec3b16c130d7 244 PDB0->SC |= PDB_SC_SWTRIG_MASK; // enable software trigger (start the PDB)
timmey9 35:df40c4566826 245
timmey9 38:ec3b16c130d7 246 //pc.printf("SampleArr: %08x\r\n", &sample_array1);
timmey9 38:ec3b16c130d7 247 //uint16_t* dma_csr = (uint16_t*) 0x4000901C;
timmey9 38:ec3b16c130d7 248 //uint32_t* dma_daddr = (uint32_t*) 0x40009010;
timmey9 38:ec3b16c130d7 249 //*dma_csr |= 1;
timmey9 35:df40c4566826 250
timmey9 27:8c2b30c855d1 251 // Start the sampling loop
timmey9 27:8c2b30c855d1 252 current_sample_index = WAITING_TO_BEGIN;
timmey9 34:44cc9b76a507 253 Sampler.attach_us(&timed_sampling, SAMPLING_RATE);
timmey9 27:8c2b30c855d1 254
timmey9 35:df40c4566826 255 pc.printf("\r\n\r\n\r\n");
timmey9 35:df40c4566826 256
timmey9 34:44cc9b76a507 257 while(1) {
timmey9 36:07d8a3143967 258 rotary_count++;
timmey9 34:44cc9b76a507 259 if(pc.readable() > 0) {
timmey9 34:44cc9b76a507 260 char temp = pc.getc();
timmey9 34:44cc9b76a507 261
timmey9 34:44cc9b76a507 262 switch(temp) {
timmey9 34:44cc9b76a507 263 case 's':
timmey9 35:df40c4566826 264 for(int i = 0; i < TOTAL_SAMPLES; i++) pc.printf("%i: %f\t",i,sample_array1[i]*3.3/65535);
timmey9 36:07d8a3143967 265
timmey9 35:df40c4566826 266 pc.printf("\r\n");
timmey9 34:44cc9b76a507 267 break;
timmey9 34:44cc9b76a507 268 case 'f':
timmey9 34:44cc9b76a507 269 for(int i = 0; i < TOTAL_SAMPLES; i++) sample_array1[i] = 0;
timmey9 34:44cc9b76a507 270 break;
timmey9 34:44cc9b76a507 271
timmey9 34:44cc9b76a507 272 }
timmey9 34:44cc9b76a507 273 }
timmey9 36:07d8a3143967 274 for(int i = 0; i < TOTAL_SAMPLES; i++) pc.printf("A%i: %f ",i,sample_array1[i]*3.3/65535);
timmey9 36:07d8a3143967 275 for(int i = 0; i < TOTAL_SAMPLES; i++) pc.printf("B%i: %f ",i,sample_array2[i]*3.3/65535);
timmey9 36:07d8a3143967 276 for(int i = 0; i < TOTAL_SAMPLES; i++) pc.printf("C%i: %i ",i,angle_array[i]);
timmey9 35:df40c4566826 277 pc.printf("\r");
timmey9 35:df40c4566826 278 //pc.printf("DMA_DADDR: %08x \r", *dma_daddr);
timmey9 35:df40c4566826 279 //pc.printf("A1: %f\tA2: %f\r\n", currA0, currA2);
timmey9 34:44cc9b76a507 280 wait(1);
timmey9 17:2f978f823020 281 }
timmey9 22:523e316cbe70 282 }
timmey9 23:9e5141647775 283
timmey9 22:523e316cbe70 284 void timed_sampling() {
timmey9 35:df40c4566826 285
timmey9 35:df40c4566826 286 // Write to SC1A to start conversion with channel 12 PTB2
timmey9 35:df40c4566826 287 //ADC0_SC1A = (ADC_SC1_ADCH(ADC_CHANNEL) | (ADC0_SC1A & (ADC_SC1_AIEN_MASK | ADC_SC1_DIFF_MASK)));
timmey9 35:df40c4566826 288
timmey9 35:df40c4566826 289 //__disable_irq(); // Disable Interrupts
timmey9 34:44cc9b76a507 290
timmey9 34:44cc9b76a507 291
timmey9 22:523e316cbe70 292 // The following performs analog-to-digital conversions - first reading the last conversion - then initiating another
timmey9 35:df40c4566826 293 //uint32_t A0_value = adc_hal_get_conversion_value(0, 0); // ADC0_RA
timmey9 35:df40c4566826 294 //uint32_t A2_value = adc_hal_get_conversion_value(1, 0);
timmey9 35:df40c4566826 295
timmey9 35:df40c4566826 296
timmey9 22:523e316cbe70 297 BW_ADC_SC1n_ADCH(0, 0, kAdcChannel12); // This corresponds to starting an ADC conversion on channel 12 of ADC 0 - which is A0 (PTB2)
timmey9 22:523e316cbe70 298 BW_ADC_SC1n_ADCH(1, 0, kAdcChannel14); // This corresponds to starting an ADC conversion on channel 14 of ADC 1 - which is A2 (PTB10)
timmey9 22:523e316cbe70 299
timmey9 35:df40c4566826 300 /*
timmey9 34:44cc9b76a507 301 currA0 = (float) A0_value*3.3/65535;
timmey9 34:44cc9b76a507 302 currA2 = (float) A2_value*3.3/65535;
timmey9 36:07d8a3143967 303 */
timmey9 35:df40c4566826 304
timmey9 22:523e316cbe70 305 // The following updates the rotary counter for the AMT20 sensor
timmey9 22:523e316cbe70 306 // Put A on PTC0
timmey9 22:523e316cbe70 307 // Put B on PTC1
timmey9 22:523e316cbe70 308 uint32_t AMT20_AB = HW_GPIO_PDIR_RD(HW_PORTC) & 0x03;
timmey9 22:523e316cbe70 309 if (AMT20_AB != last_AMT20_AB_read)
timmey9 22:523e316cbe70 310 {
timmey9 22:523e316cbe70 311 // change "INVERT_ANGLE" to change whether relative angle counts up or down.
timmey9 22:523e316cbe70 312 if ((AMT20_AB >> 1)^(last_AMT20_AB_read) & 1U)
timmey9 22:523e316cbe70 313 #if INVERT_ANGLE == 1
timmey9 22:523e316cbe70 314 {rotary_count--;}
timmey9 22:523e316cbe70 315 else
timmey9 22:523e316cbe70 316 {rotary_count++;}
timmey9 22:523e316cbe70 317 #else
timmey9 22:523e316cbe70 318 {rotary_count++;}
timmey9 22:523e316cbe70 319 else
timmey9 22:523e316cbe70 320 {rotary_count--;}
timmey9 22:523e316cbe70 321 #endif
timmey9 22:523e316cbe70 322
timmey9 22:523e316cbe70 323 last_AMT20_AB_read = AMT20_AB;
timmey9 22:523e316cbe70 324 }
timmey9 36:07d8a3143967 325 /*
timmey9 22:523e316cbe70 326 //current_sample_index = BEGIN_SAMPLING; // Used to force extra time.
timmey9 22:523e316cbe70 327 if (current_sample_index == WAITING_TO_BEGIN) {}
timmey9 22:523e316cbe70 328 else
timmey9 28:4a833d59897b 329 {
timmey9 22:523e316cbe70 330 if (current_sample_index == BEGIN_SAMPLING) {
timmey9 22:523e316cbe70 331 current_sample_index = FIRST_SAMPLE_INDEX;
timmey9 22:523e316cbe70 332 }
timmey9 22:523e316cbe70 333
timmey9 27:8c2b30c855d1 334 sample_array1[current_sample_index] = A0_value;
timmey9 27:8c2b30c855d1 335 sample_array2[current_sample_index] = A2_value;
timmey9 22:523e316cbe70 336 angle_array[current_sample_index] = rotary_count;
timmey9 22:523e316cbe70 337
timmey9 22:523e316cbe70 338 if (current_sample_index == LAST_SAMPLE_INDEX) {
timmey9 22:523e316cbe70 339 current_sample_index = WAITING_TO_BEGIN;
timmey9 22:523e316cbe70 340 }
timmey9 22:523e316cbe70 341 else { current_sample_index++; }
timmey9 28:4a833d59897b 342 }
timmey9 35:df40c4566826 343 */
timmey9 35:df40c4566826 344 //__enable_irq(); // Enable Interrupts
timmey9 22:523e316cbe70 345 }
timmey9 22:523e316cbe70 346
timmey9 22:523e316cbe70 347 void analog_initialization(PinName pin)
timmey9 22:523e316cbe70 348 {
timmey9 22:523e316cbe70 349 ADCName adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
timmey9 22:523e316cbe70 350 // MBED_ASSERT(adc != (ADCName)NC);
timmey9 22:523e316cbe70 351
timmey9 22:523e316cbe70 352 uint32_t instance = adc >> ADC_INSTANCE_SHIFT;
timmey9 22:523e316cbe70 353
timmey9 22:523e316cbe70 354 clock_manager_set_gate(kClockModuleADC, instance, true);
timmey9 22:523e316cbe70 355
timmey9 22:523e316cbe70 356 uint32_t bus_clock;
timmey9 22:523e316cbe70 357 clock_manager_get_frequency(kBusClock, &bus_clock);
timmey9 22:523e316cbe70 358 uint32_t clkdiv;
timmey9 22:523e316cbe70 359 for (clkdiv = 0; clkdiv < 4; clkdiv++) {
timmey9 22:523e316cbe70 360 if ((bus_clock >> clkdiv) <= MAX_FADC)
timmey9 22:523e316cbe70 361 break;
timmey9 22:523e316cbe70 362 }
timmey9 22:523e316cbe70 363 if (clkdiv == 4) {
timmey9 22:523e316cbe70 364 clkdiv = 0x7; //Set max div
timmey9 22:523e316cbe70 365 }
timmey9 22:523e316cbe70 366 // adc is enabled/triggered when reading.
timmey9 22:523e316cbe70 367 adc_hal_set_clock_source_mode(instance, (adc_clock_source_mode_t)(clkdiv >> 2));
timmey9 22:523e316cbe70 368 adc_hal_set_clock_divider_mode(instance, (adc_clock_divider_mode_t)(clkdiv & 0x3));
timmey9 22:523e316cbe70 369 adc_hal_set_reference_voltage_mode(instance, kAdcVoltageVref);
timmey9 22:523e316cbe70 370 adc_hal_set_resolution_mode(instance, kAdcSingleDiff16);
timmey9 37:8bdc71f3e874 371 adc_hal_configure_continuous_conversion(instance, false); // true=continuous conversion mode, false = single conversion mode
timmey9 38:ec3b16c130d7 372 adc_hal_configure_hw_trigger(instance, false); // true=hw trigger, false=sw trigger
timmey9 22:523e316cbe70 373 adc_hal_configure_hw_average(instance, false);
timmey9 22:523e316cbe70 374 adc_hal_set_hw_average_mode(instance, kAdcHwAverageCount4);
timmey9 22:523e316cbe70 375 adc_hal_set_group_mux(instance, kAdcChannelMuxB); // only B channels are avail
timmey9 22:523e316cbe70 376
timmey9 22:523e316cbe70 377 pinmap_pinout(pin, PinMap_ADC);
timmey9 35:df40c4566826 378 }
timmey9 35:df40c4566826 379
timmey9 35:df40c4566826 380
timmey9 35:df40c4566826 381
timmey9 35:df40c4566826 382 /*
timmey9 35:df40c4566826 383 // read some registers for some info.
timmey9 35:df40c4566826 384 uint32_t* dma_cr = (uint32_t*) 0x40008000;
timmey9 35:df40c4566826 385 pc.printf("DMA_CR: %08x\r\n", *dma_cr);
timmey9 35:df40c4566826 386
timmey9 35:df40c4566826 387 uint32_t* dma_eei = (uint32_t*) 0x40008014;
timmey9 35:df40c4566826 388 pc.printf("DMA_EEI: %08x\r\n", *dma_eei);
timmey9 35:df40c4566826 389
timmey9 35:df40c4566826 390 uint32_t* dma_erq = (uint32_t*) 0x4000800C;
timmey9 35:df40c4566826 391 pc.printf("DMA_ERQ: %08x\r\n", *dma_erq);
timmey9 35:df40c4566826 392
timmey9 35:df40c4566826 393 uint16_t* dma_csr = (uint16_t*) 0x4000901C;
timmey9 35:df40c4566826 394 pc.printf("DMA_TD0_CSR: %04x\r\n\n", *dma_csr);
timmey9 35:df40c4566826 395
timmey9 35:df40c4566826 396 uint32_t* dma_saddr = (uint32_t*) 0x40009000;
timmey9 35:df40c4566826 397 pc.printf("DMA_SAADR: %08x\r\n", *dma_saddr);
timmey9 35:df40c4566826 398
timmey9 35:df40c4566826 399 uint16_t* dma_soff = (uint16_t*) 0x40009004;
timmey9 35:df40c4566826 400 pc.printf("DMA_SOFF: %04x\r\n", *dma_soff);
timmey9 35:df40c4566826 401
timmey9 35:df40c4566826 402 uint16_t* dma_attr = (uint16_t*) 0x40009006;
timmey9 35:df40c4566826 403 pc.printf("DMA_ATTR: %04x\r\n", *dma_attr);
timmey9 35:df40c4566826 404
timmey9 35:df40c4566826 405 uint32_t* dma_minor = (uint32_t*) 0x40009008;
timmey9 35:df40c4566826 406 pc.printf("DMA_MINOR: %08x\r\n", *dma_minor);
timmey9 35:df40c4566826 407
timmey9 35:df40c4566826 408 uint32_t* dma_daddr = (uint32_t*) 0x40009010;
timmey9 35:df40c4566826 409 pc.printf("DMA_DADDR: %08x\r\n", *dma_daddr);
timmey9 35:df40c4566826 410
timmey9 35:df40c4566826 411
timmey9 35:df40c4566826 412 // read some registers for some info.
timmey9 35:df40c4566826 413 pc.printf("DMA_CR: %08x\r\n", *dma_cr);
timmey9 35:df40c4566826 414 pc.printf("DMA_EEI: %08x\r\n", *dma_eei);
timmey9 35:df40c4566826 415 pc.printf("DMA_ERQ: %08x\r\n", *dma_erq);
timmey9 35:df40c4566826 416 pc.printf("DMA_TD0_CSR: %04x\r\n\n", *dma_csr);
timmey9 35:df40c4566826 417 pc.printf("DMA_SAADR: %08x\r\n", *dma_saddr);
timmey9 35:df40c4566826 418 pc.printf("DMA_SOFF: %04x\r\n", *dma_soff);
timmey9 35:df40c4566826 419 pc.printf("DMA_ATTR: %04x\r\n", *dma_attr);
timmey9 35:df40c4566826 420 pc.printf("DMA_MINOR: %08x\r\n", *dma_minor);
timmey9 35:df40c4566826 421 pc.printf("DMA_DADDR: %08x\r\n", *dma_daddr);
timmey9 35:df40c4566826 422 pc.printf("SampleArr: %08x\r\n",&sample_array1);
timmey9 35:df40c4566826 423 */