Bavo Van Achte / Mbed 2 deprecated MLX90418_I2C_master

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Dependencies:   mbed libscpi

i2c_mbed_fpga.cpp@10:a8390614edcc, 2021-02-26 (annotated)

Committer:
wuliqunyy
Date:
Fri Feb 26 10:16:32 2021 +0000
Revision:
10:a8390614edcc
Parent:
9:76a0b9f29a2d
Child:
11:b86aea372744
anti cogging works;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 6:019ab407ac3c 3 DigitalOut led3(LED3);
wuliqunyy 0:fe3c7dde9771 4
wuliqunyy 6:019ab407ac3c 5 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 6 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 7 *
wuliqunyy 6:019ab407ac3c 8 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 9 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 10 */
wuliqunyy 6:019ab407ac3c 11 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 6:019ab407ac3c 12 int ack = 0;
wuliqunyy 6:019ab407ac3c 13 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 2, true); //restart
wuliqunyy 6:019ab407ac3c 14 ack += i2c_master.read(I2C_SLAVE_ADDR, word+2, 2, false); //stop bit
wuliqunyy 6:019ab407ac3c 15 wait_us(100);
wuliqunyy 6:019ab407ac3c 16 return (ack == 0) ? 0 : 1;
wuliqunyy 6:019ab407ac3c 17 }
wuliqunyy 0:fe3c7dde9771 18
wuliqunyy 0:fe3c7dde9771 19 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 20 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 21 *
wuliqunyy 0:fe3c7dde9771 22 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 23 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 24 */
wuliqunyy 5:daab0e0e67e2 25 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 26 int ack = 0;
wuliqunyy 6:019ab407ac3c 27 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
wuliqunyy 5:daab0e0e67e2 28 return ack;
wuliqunyy 0:fe3c7dde9771 29 }
wuliqunyy 0:fe3c7dde9771 30
wuliqunyy 0:fe3c7dde9771 31
wuliqunyy 6:019ab407ac3c 32 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 33 * ==> Safe write with 3 times read back check
wuliqunyy 0:fe3c7dde9771 34 *
wuliqunyy 0:fe3c7dde9771 35 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 36 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 37 */
wuliqunyy 6:019ab407ac3c 38 int i2c_mbed_fpga::i2c_word_safe_write(char *word){
wuliqunyy 6:019ab407ac3c 39 int ack = 0;
wuliqunyy 6:019ab407ac3c 40 char readBuff[4];
wuliqunyy 6:019ab407ac3c 41 std::copy(word, word+4, readBuff);
wuliqunyy 6:019ab407ac3c 42 int i = 0;
wuliqunyy 6:019ab407ac3c 43 do{
wuliqunyy 6:019ab407ac3c 44 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
wuliqunyy 6:019ab407ac3c 45 wait_us(100);
wuliqunyy 6:019ab407ac3c 46 ack +=i2c_word_read(readBuff);
wuliqunyy 6:019ab407ac3c 47 wait_us(100);
wuliqunyy 6:019ab407ac3c 48 if( *(readBuff+2) == *(word+2) && *(readBuff+3) == *(word+3) ){
wuliqunyy 6:019ab407ac3c 49 ack++;
wuliqunyy 6:019ab407ac3c 50 }
wuliqunyy 6:019ab407ac3c 51 i++;
wuliqunyy 6:019ab407ac3c 52 }while ( ack!=0 && i<3 );
wuliqunyy 6:019ab407ac3c 53 return ack;
wuliqunyy 0:fe3c7dde9771 54 }
wuliqunyy 0:fe3c7dde9771 55
wuliqunyy 0:fe3c7dde9771 56
wuliqunyy 5:daab0e0e67e2 57 /** i2c enter key to open I2C window
wuliqunyy 0:fe3c7dde9771 58 */
wuliqunyy 5:daab0e0e67e2 59 int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 10:a8390614edcc 60 char i2cMessage[4];
wuliqunyy 10:a8390614edcc 61 *(i2cMessage+0) = (char)(NVADDR_NV_TRACEABILITY_0 >> 8)& 0xff;
wuliqunyy 10:a8390614edcc 62 *(i2cMessage+1) = (char)(NVADDR_NV_TRACEABILITY_0 >> 0)& 0xff;
wuliqunyy 10:a8390614edcc 63 *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 10:a8390614edcc 64 *(i2cMessage+3) = (char)(0xD0)& 0xff;
wuliqunyy 10:a8390614edcc 65 return i2c_word_safe_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 66 }
wuliqunyy 0:fe3c7dde9771 67
wuliqunyy 5:daab0e0e67e2 68 /** i2c enter key to Start the motor
wuliqunyy 0:fe3c7dde9771 69 */
wuliqunyy 5:daab0e0e67e2 70 int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 10:a8390614edcc 71 char i2cMessage[4];
wuliqunyy 10:a8390614edcc 72 *(i2cMessage+0) = (char)(NVADDR_NV_TRACEABILITY_0 >> 8)& 0xff;
wuliqunyy 10:a8390614edcc 73 *(i2cMessage+1) = (char)(NVADDR_NV_TRACEABILITY_0 >> 0)& 0xff;
wuliqunyy 10:a8390614edcc 74 *(i2cMessage+2) = (char)(0xCA)& 0xff;
wuliqunyy 10:a8390614edcc 75 *(i2cMessage+3) = (char)(0xFE)& 0xff;
wuliqunyy 10:a8390614edcc 76 return i2c_word_safe_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 77 }
wuliqunyy 6:019ab407ac3c 78
wuliqunyy 6:019ab407ac3c 79 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 80 */
wuliqunyy 6:019ab407ac3c 81 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 82 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 83 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 84 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 85 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 86 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 87 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 88 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 89 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 90 }
wuliqunyy 6:019ab407ac3c 91
wuliqunyy 6:019ab407ac3c 92 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 93 */
wuliqunyy 6:019ab407ac3c 94 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 95 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 96 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 6:019ab407ac3c 97 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 98 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 99 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 100 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 101 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 102 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 103 }
wuliqunyy 6:019ab407ac3c 104
wuliqunyy 6:019ab407ac3c 105 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 106 */
wuliqunyy 6:019ab407ac3c 107 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 108 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 109 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 6:019ab407ac3c 110 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 111 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 112 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 113 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 114 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 115 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 116 }
wuliqunyy 6:019ab407ac3c 117
wuliqunyy 6:019ab407ac3c 118 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 119 */
wuliqunyy 6:019ab407ac3c 120 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 121 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 122 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 6:019ab407ac3c 123 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 124 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 125 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 126 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 127 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 128 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 129 }
wuliqunyy 6:019ab407ac3c 130
wuliqunyy 6:019ab407ac3c 131
wuliqunyy 6:019ab407ac3c 132 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 133 */
wuliqunyy 6:019ab407ac3c 134 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 135 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 136 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 137 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 138 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 139 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 140 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 141 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 142 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 143 }
wuliqunyy 6:019ab407ac3c 144
wuliqunyy 6:019ab407ac3c 145 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 146 */
wuliqunyy 6:019ab407ac3c 147 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 148 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 149 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 6:019ab407ac3c 150 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 151 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 152 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 153 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 154 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 155 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 156 }
wuliqunyy 6:019ab407ac3c 157
wuliqunyy 6:019ab407ac3c 158 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 159 */
wuliqunyy 6:019ab407ac3c 160 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 161 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 162 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 6:019ab407ac3c 163 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 164 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 165 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 166 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 167 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 168 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 169 }
wuliqunyy 6:019ab407ac3c 170
wuliqunyy 6:019ab407ac3c 171 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 172 */
wuliqunyy 6:019ab407ac3c 173 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 174 int ack = 0;
wuliqunyy 6:019ab407ac3c 175 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 176 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 177 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 178 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 179 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 180 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 181 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 182 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 6:019ab407ac3c 183 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 184 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 185 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 186 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 187 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 188 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 189
wuliqunyy 9:76a0b9f29a2d 190 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 191 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 192 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 193 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 194 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 195
wuliqunyy 9:76a0b9f29a2d 196 *(i2cMessage+0) = (char)(NVADDR_NV_WIND_BRAKE >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 197 *(i2cMessage+1) = (char)(NVADDR_NV_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 198 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 199 *(i2cMessage+3) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 200 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 201
wuliqunyy 6:019ab407ac3c 202 return ack;
wuliqunyy 6:019ab407ac3c 203 }
wuliqunyy 6:019ab407ac3c 204
wuliqunyy 6:019ab407ac3c 205 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 206 */
wuliqunyy 6:019ab407ac3c 207 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 208 int ack = 0;
wuliqunyy 6:019ab407ac3c 209 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 210 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 211 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 212 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 213 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 214 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 215 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 216 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 217 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 218 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 219
wuliqunyy 9:76a0b9f29a2d 220 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 221 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 222 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 223 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 224 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 225
wuliqunyy 6:019ab407ac3c 226 return ack;
wuliqunyy 6:019ab407ac3c 227 }
wuliqunyy 6:019ab407ac3c 228
wuliqunyy 6:019ab407ac3c 229 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 230 */
wuliqunyy 6:019ab407ac3c 231 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 232 int ack = 0;
wuliqunyy 6:019ab407ac3c 233 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 234 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 235 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 236 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 237 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 238 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 239 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 240 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 241 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 242 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 243
wuliqunyy 9:76a0b9f29a2d 244 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 245 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 246 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 247 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 248 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 249
wuliqunyy 6:019ab407ac3c 250 return ack;
wuliqunyy 9:76a0b9f29a2d 251 }
wuliqunyy 9:76a0b9f29a2d 252
wuliqunyy 9:76a0b9f29a2d 253 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 254 */
wuliqunyy 9:76a0b9f29a2d 255 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 256 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 257 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 258 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 9:76a0b9f29a2d 259 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 260 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_1 >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 261 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 262 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 263 *(i2cMessage+3) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 264 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 265
wuliqunyy 9:76a0b9f29a2d 266 return ack;
wuliqunyy 9:76a0b9f29a2d 267 }
wuliqunyy 9:76a0b9f29a2d 268
wuliqunyy 9:76a0b9f29a2d 269 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 9:76a0b9f29a2d 270 */
wuliqunyy 9:76a0b9f29a2d 271 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 9:76a0b9f29a2d 272 int ack = 0;
wuliqunyy 10:a8390614edcc 273 ram_open_duty_val = duty;
wuliqunyy 9:76a0b9f29a2d 274 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 275 *(i2cMessage+0) = (char)(0x10)& 0xff;
wuliqunyy 9:76a0b9f29a2d 276 *(i2cMessage+1) = (char)(0x3e)& 0xff;
wuliqunyy 10:a8390614edcc 277 *(i2cMessage+2) = (char)(ram_open_duty_val >> 8)& 0xff;
wuliqunyy 10:a8390614edcc 278 *(i2cMessage+3) = (char)(ram_open_duty_val >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 279 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 280
wuliqunyy 9:76a0b9f29a2d 281 return ack;
wuliqunyy 9:76a0b9f29a2d 282 }