aurelio carella / Mbed OS mbed-os-example-ble-GattServer_ECG

20200716 read Status Register each second

Dependencies:   SDFileSystem mbed-os-example-ble-GattServer max32630fthr

HSP/Interfaces/QuadSpiInterface.cpp@21:51e162c130a9, 2020-07-16 (annotated)

Committer:
aureliocarella
Date:
Thu Jul 16 14:59:04 2020 +0000
Revision:
21:51e162c130a9
20200716

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aureliocarella 21:51e162c130a9 1 /*******************************************************************************
aureliocarella 21:51e162c130a9 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
aureliocarella 21:51e162c130a9 3 *
aureliocarella 21:51e162c130a9 4 * Permission is hereby granted, free of charge, to any person obtaining a
aureliocarella 21:51e162c130a9 5 * copy of this software and associated documentation files (the "Software"),
aureliocarella 21:51e162c130a9 6 * to deal in the Software without restriction, including without limitation
aureliocarella 21:51e162c130a9 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
aureliocarella 21:51e162c130a9 8 * and/or sell copies of the Software, and to permit persons to whom the
aureliocarella 21:51e162c130a9 9 * Software is furnished to do so, subject to the following conditions:
aureliocarella 21:51e162c130a9 10 *
aureliocarella 21:51e162c130a9 11 * The above copyright notice and this permission notice shall be included
aureliocarella 21:51e162c130a9 12 * in all copies or substantial portions of the Software.
aureliocarella 21:51e162c130a9 13 *
aureliocarella 21:51e162c130a9 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
aureliocarella 21:51e162c130a9 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
aureliocarella 21:51e162c130a9 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
aureliocarella 21:51e162c130a9 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
aureliocarella 21:51e162c130a9 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
aureliocarella 21:51e162c130a9 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
aureliocarella 21:51e162c130a9 20 * OTHER DEALINGS IN THE SOFTWARE.
aureliocarella 21:51e162c130a9 21 *
aureliocarella 21:51e162c130a9 22 * Except as contained in this notice, the name of Maxim Integrated
aureliocarella 21:51e162c130a9 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
aureliocarella 21:51e162c130a9 24 * Products, Inc. Branding Policy.
aureliocarella 21:51e162c130a9 25 *
aureliocarella 21:51e162c130a9 26 * The mere transfer of this software does not imply any licenses
aureliocarella 21:51e162c130a9 27 * of trade secrets, proprietary technology, copyrights, patents,
aureliocarella 21:51e162c130a9 28 * trademarks, maskwork rights, or any other form of intellectual
aureliocarella 21:51e162c130a9 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
aureliocarella 21:51e162c130a9 30 * ownership rights.
aureliocarella 21:51e162c130a9 31 *******************************************************************************
aureliocarella 21:51e162c130a9 32 */
aureliocarella 21:51e162c130a9 33 #include "QuadSpiInterface.h"
aureliocarella 21:51e162c130a9 34
aureliocarella 21:51e162c130a9 35 /**
aureliocarella 21:51e162c130a9 36 * @brief Constructor that accepts pin names for the QUAD SPI interface
aureliocarella 21:51e162c130a9 37 * @param mosi master out slave in pin name
aureliocarella 21:51e162c130a9 38 * @param miso master in slave out pin name
aureliocarella 21:51e162c130a9 39 * @param sclk serial clock pin name
aureliocarella 21:51e162c130a9 40 * @param cs chip select pin name
aureliocarella 21:51e162c130a9 41 */
aureliocarella 21:51e162c130a9 42 QuadSpiInterface::QuadSpiInterface(PinName mosi, PinName miso, PinName sclk,
aureliocarella 21:51e162c130a9 43 PinName cs)
aureliocarella 21:51e162c130a9 44 : spi(mosi, miso, sclk), csPin(cs) {
aureliocarella 21:51e162c130a9 45
aureliocarella 21:51e162c130a9 46 }
aureliocarella 21:51e162c130a9 47
aureliocarella 21:51e162c130a9 48 /**
aureliocarella 21:51e162c130a9 49 * @brief Transmit and recieve QUAD SPI data
aureliocarella 21:51e162c130a9 50 * @param tx_buf pointer to transmit byte buffer
aureliocarella 21:51e162c130a9 51 * @param tx_size number of bytes to transmit
aureliocarella 21:51e162c130a9 52 * @param rx_buf pointer to the recieve buffer
aureliocarella 21:51e162c130a9 53 * @param rx_size number of bytes to recieve
aureliocarella 21:51e162c130a9 54 * @param last flag to indicate if this is the last QUAD SPI transaction for the
aureliocarella 21:51e162c130a9 55 * current chip select cycle
aureliocarella 21:51e162c130a9 56 */
aureliocarella 21:51e162c130a9 57 int QuadSpiInterface::SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size,
aureliocarella 21:51e162c130a9 58 uint8_t *rx_buf, uint32_t rx_size,
aureliocarella 21:51e162c130a9 59 int last) {
aureliocarella 21:51e162c130a9 60 uint32_t i;
aureliocarella 21:51e162c130a9 61 int result = 0;
aureliocarella 21:51e162c130a9 62 int index = 0;
aureliocarella 21:51e162c130a9 63 // lower chip select
aureliocarella 21:51e162c130a9 64 csPin = 0;
aureliocarella 21:51e162c130a9 65 // write bytes out QUAD SPI
aureliocarella 21:51e162c130a9 66 spi.setQuadMode();
aureliocarella 21:51e162c130a9 67 for (i = 0; i < tx_size; i++) {
aureliocarella 21:51e162c130a9 68 rx_buf[index] = spi.write((int)tx_buf[i]);
aureliocarella 21:51e162c130a9 69 index++;
aureliocarella 21:51e162c130a9 70 }
aureliocarella 21:51e162c130a9 71 // read in bytes from QUAD SPI
aureliocarella 21:51e162c130a9 72 for (i = 0; i < rx_size; i++) {
aureliocarella 21:51e162c130a9 73 rx_buf[index] = (uint8_t)spi.read();
aureliocarella 21:51e162c130a9 74 index++;
aureliocarella 21:51e162c130a9 75 }
aureliocarella 21:51e162c130a9 76 // raise chip select if this is the last transaction
aureliocarella 21:51e162c130a9 77 if (last) csPin = 1;
aureliocarella 21:51e162c130a9 78 return result;
aureliocarella 21:51e162c130a9 79 }
aureliocarella 21:51e162c130a9 80
aureliocarella 21:51e162c130a9 81 /**
aureliocarella 21:51e162c130a9 82 * @brief Transmit and recieve QUAD SPI data
aureliocarella 21:51e162c130a9 83 * @param tx_buf pointer to transmit byte buffer
aureliocarella 21:51e162c130a9 84 * @param tx_size number of bytes to transmit
aureliocarella 21:51e162c130a9 85 * @param rx_buf pointer to the recieve buffer
aureliocarella 21:51e162c130a9 86 * @param rx_size number of bytes to recieve
aureliocarella 21:51e162c130a9 87 * @param last flag to indicate if this is the last QUAD SPI transaction for the
aureliocarella 21:51e162c130a9 88 * current chip select cycle
aureliocarella 21:51e162c130a9 89 */
aureliocarella 21:51e162c130a9 90 int QuadSpiInterface::SPI_Transmit4Wire(const uint8_t *tx_buf, uint32_t tx_size,
aureliocarella 21:51e162c130a9 91 uint8_t *rx_buf, uint32_t rx_size,
aureliocarella 21:51e162c130a9 92 int last) {
aureliocarella 21:51e162c130a9 93 uint32_t i;
aureliocarella 21:51e162c130a9 94 int result = 0;
aureliocarella 21:51e162c130a9 95 int index = 0;
aureliocarella 21:51e162c130a9 96 // lower chip select
aureliocarella 21:51e162c130a9 97 csPin = 0;
aureliocarella 21:51e162c130a9 98 // write bytes out Single SPI
aureliocarella 21:51e162c130a9 99 spi.setSingleMode();
aureliocarella 21:51e162c130a9 100 for (i = 0; i < tx_size; i++) {
aureliocarella 21:51e162c130a9 101 rx_buf[index] = spi.write((int)tx_buf[i]);
aureliocarella 21:51e162c130a9 102 index++;
aureliocarella 21:51e162c130a9 103 }
aureliocarella 21:51e162c130a9 104 // raise chip select if this is the last transaction
aureliocarella 21:51e162c130a9 105 if (last) csPin = 1;
aureliocarella 21:51e162c130a9 106 return result;
aureliocarella 21:51e162c130a9 107 }
aureliocarella 21:51e162c130a9 108