GA-Test_copy

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decadriver/deca_regs.h@0:a3b83d366423, 2017-12-06 (annotated)

Committer:: aungriah
Date:: Wed Dec 06 21:35:45 2017 +0000
Revision:: 0:a3b83d366423

test

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User	Revision	Line number	New contents of line
aungriah	0:a3b83d366423	1	/*! ------------------------------------------------------------------------------------------------------------------
aungriah	0:a3b83d366423	2	* @file deca_regs.h
aungriah	0:a3b83d366423	3	* @brief DW1000 Register Definitions
aungriah	0:a3b83d366423	4	* This file supports assembler and C development for DW1000 enabled devices
aungriah	0:a3b83d366423	5	*
aungriah	0:a3b83d366423	6	* @attention
aungriah	0:a3b83d366423	7	*
aungriah	0:a3b83d366423	8	* Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
aungriah	0:a3b83d366423	9	*
aungriah	0:a3b83d366423	10	* All rights reserved.
aungriah	0:a3b83d366423	11	*
aungriah	0:a3b83d366423	12	*/
aungriah	0:a3b83d366423	13
aungriah	0:a3b83d366423	14	#ifndef _DECA_REGS_H_
aungriah	0:a3b83d366423	15	#define _DECA_REGS_H_
aungriah	0:a3b83d366423	16
aungriah	0:a3b83d366423	17	#ifdef __cplusplus
aungriah	0:a3b83d366423	18	extern "C" {
aungriah	0:a3b83d366423	19	#endif
aungriah	0:a3b83d366423	20
aungriah	0:a3b83d366423	21	#include "deca_version.h"
aungriah	0:a3b83d366423	22
aungriah	0:a3b83d366423	23
aungriah	0:a3b83d366423	24	/**************************************************************************//
aungriah	0:a3b83d366423	25	* @brief Bit definitions for register DEV_ID
aungriah	0:a3b83d366423	26	**/
aungriah	0:a3b83d366423	27	#define DEV_ID_ID 0x00 /* Device ID register, includes revision info (0xDECA0130) */
aungriah	0:a3b83d366423	28	#define DEV_ID_LEN (4)
aungriah	0:a3b83d366423	29	/* mask and shift */
aungriah	0:a3b83d366423	30	#define DEV_ID_REV_MASK 0x0000000FUL /* Revision */
aungriah	0:a3b83d366423	31	#define DEV_ID_VER_MASK 0x000000F0UL /* Version */
aungriah	0:a3b83d366423	32	#define DEV_ID_MODEL_MASK 0x0000FF00UL /* The MODEL identifies the device. The DW1000 is device type 0x01 */
aungriah	0:a3b83d366423	33	#define DEV_ID_RIDTAG_MASK 0xFFFF0000UL /* Register Identification Tag 0XDECA */
aungriah	0:a3b83d366423	34
aungriah	0:a3b83d366423	35	/**************************************************************************//
aungriah	0:a3b83d366423	36	* @brief Bit definitions for register EUI_64
aungriah	0:a3b83d366423	37	**/
aungriah	0:a3b83d366423	38	#define EUI_64_ID 0x01 /* IEEE Extended Unique Identifier (63:0) */
aungriah	0:a3b83d366423	39	#define EUI_64_OFFSET 0x00
aungriah	0:a3b83d366423	40	#define EUI_64_LEN (8)
aungriah	0:a3b83d366423	41
aungriah	0:a3b83d366423	42	/**************************************************************************//
aungriah	0:a3b83d366423	43	* @brief Bit definitions for register PANADR
aungriah	0:a3b83d366423	44	**/
aungriah	0:a3b83d366423	45	#define PANADR_ID 0x03 /* PAN ID (31:16) and Short Address (15:0) */
aungriah	0:a3b83d366423	46	#define PANADR_LEN (4)
aungriah	0:a3b83d366423	47	/mask and shift /
aungriah	0:a3b83d366423	48	#define PANADR_SHORT_ADDR_OFFSET 0 /* In bytes */
aungriah	0:a3b83d366423	49	#define PANADR_SHORT_ADDR_MASK 0x0000FFFFUL /* Short Address */
aungriah	0:a3b83d366423	50	#define PANADR_PAN_ID_OFFSET 2 /* In bytes */
aungriah	0:a3b83d366423	51	#define PANADR_PAN_ID_MASK 0xFFFF00F0UL /* PAN Identifier */
aungriah	0:a3b83d366423	52
aungriah	0:a3b83d366423	53	/**************************************************************************//
aungriah	0:a3b83d366423	54	* @brief Bit definitions for register 0x05
aungriah	0:a3b83d366423	55	**/
aungriah	0:a3b83d366423	56	#define REG_05_ID_RESERVED 0x05
aungriah	0:a3b83d366423	57
aungriah	0:a3b83d366423	58	/**************************************************************************//
aungriah	0:a3b83d366423	59	* @brief Bit definitions for register SYS_CFG
aungriah	0:a3b83d366423	60	**/
aungriah	0:a3b83d366423	61	#define SYS_CFG_ID 0x04 /* System Configuration (31:0) */
aungriah	0:a3b83d366423	62	#define SYS_CFG_LEN (4)
aungriah	0:a3b83d366423	63	/mask and shift /
aungriah	0:a3b83d366423	64	#define SYS_CFG_MASK 0xF047FFFFUL /* access mask to SYS_CFG_ID */
aungriah	0:a3b83d366423	65	#define SYS_CFG_FF_ALL_EN 0x000001FEUL /* Frame filtering options all frames allowed */
aungriah	0:a3b83d366423	66	/offset 0 /
aungriah	0:a3b83d366423	67	#define SYS_CFG_FFE 0x00000001UL /* Frame Filtering Enable. This bit enables the frame filtering functionality */
aungriah	0:a3b83d366423	68	#define SYS_CFG_FFBC 0x00000002UL /* Frame Filtering Behave as a Co-ordinator */
aungriah	0:a3b83d366423	69	#define SYS_CFG_FFAB 0x00000004UL /* Frame Filtering Allow Beacon frame reception */
aungriah	0:a3b83d366423	70	#define SYS_CFG_FFAD 0x00000008UL /* Frame Filtering Allow Data frame reception */
aungriah	0:a3b83d366423	71	#define SYS_CFG_FFAA 0x00000010UL /* Frame Filtering Allow Acknowledgment frame reception */
aungriah	0:a3b83d366423	72	#define SYS_CFG_FFAM 0x00000020UL /* Frame Filtering Allow MAC command frame reception */
aungriah	0:a3b83d366423	73	#define SYS_CFG_FFAR 0x00000040UL /* Frame Filtering Allow Reserved frame types */
aungriah	0:a3b83d366423	74	#define SYS_CFG_FFA4 0x00000080UL /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */
aungriah	0:a3b83d366423	75	/offset 8 /
aungriah	0:a3b83d366423	76	#define SYS_CFG_FFA5 0x00000100UL /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */
aungriah	0:a3b83d366423	77	#define SYS_CFG_HIRQ_POL 0x00000200UL /* Host interrupt polarity */
aungriah	0:a3b83d366423	78	#define SYS_CFG_SPI_EDGE 0x00000400UL /* SPI data launch edge */
aungriah	0:a3b83d366423	79	#define SYS_CFG_DIS_FCE 0x00000800UL /* Disable frame check error handling */
aungriah	0:a3b83d366423	80	#define SYS_CFG_DIS_DRXB 0x00001000UL /* Disable Double RX Buffer */
aungriah	0:a3b83d366423	81	#define SYS_CFG_DIS_PHE 0x00002000UL /* Disable receiver abort on PHR error */
aungriah	0:a3b83d366423	82	#define SYS_CFG_DIS_RSDE 0x00004000UL /* Disable Receiver Abort on RSD error */
aungriah	0:a3b83d366423	83	#define SYS_CFG_FCS_INIT2F 0x00008000UL /* initial seed value for the FCS generation and checking function */
aungriah	0:a3b83d366423	84	/offset 16 /
aungriah	0:a3b83d366423	85	#define SYS_CFG_PHR_MODE_SHFT 16
aungriah	0:a3b83d366423	86	#define SYS_CFG_PHR_MODE_00 0x00000000UL /* Standard Frame mode */
aungriah	0:a3b83d366423	87	#define SYS_CFG_PHR_MODE_11 0x00030000UL /* Long Frames mode */
aungriah	0:a3b83d366423	88	#define SYS_CFG_DIS_STXP 0x00040000UL /* Disable Smart TX Power control */
aungriah	0:a3b83d366423	89	#define SYS_CFG_RXM110K 0x00400000UL /* Receiver Mode 110 kbps data rate */
aungriah	0:a3b83d366423	90	/offset 24 /
aungriah	0:a3b83d366423	91	#define SYS_CFG_RXWTOE 0x10000000UL /* Receive Wait Timeout Enable. */
aungriah	0:a3b83d366423	92	#define SYS_CFG_RXAUTR 0x20000000UL /* Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically */
aungriah	0:a3b83d366423	93	#define SYS_CFG_AUTOACK 0x40000000UL /* Automatic Acknowledgement Enable */
aungriah	0:a3b83d366423	94	#define SYS_CFG_AACKPEND 0x80000000UL /* Automatic Acknowledgement Pending bit control */
aungriah	0:a3b83d366423	95
aungriah	0:a3b83d366423	96
aungriah	0:a3b83d366423	97	/**************************************************************************//
aungriah	0:a3b83d366423	98	* @brief Bit definitions for register SYS_TIME
aungriah	0:a3b83d366423	99	**/
aungriah	0:a3b83d366423	100	#define SYS_TIME_ID 0x06 /* System Time Counter (40-bit) */
aungriah	0:a3b83d366423	101	#define SYS_TIME_OFFSET 0x00
aungriah	0:a3b83d366423	102	#define SYS_TIME_LEN (5) /* Note 40 bit register */
aungriah	0:a3b83d366423	103
aungriah	0:a3b83d366423	104
aungriah	0:a3b83d366423	105	/**************************************************************************//
aungriah	0:a3b83d366423	106	* @brief Bit definitions for register 0x07
aungriah	0:a3b83d366423	107	**/
aungriah	0:a3b83d366423	108	#define REG_07_ID_RESERVED 0x07
aungriah	0:a3b83d366423	109
aungriah	0:a3b83d366423	110	/**************************************************************************//
aungriah	0:a3b83d366423	111	* @brief Bit definitions for register TX_FCTRL
aungriah	0:a3b83d366423	112	**/
aungriah	0:a3b83d366423	113	#define TX_FCTRL_ID 0x08 /* Transmit Frame Control */
aungriah	0:a3b83d366423	114	#define TX_FCTRL_LEN (5) /* Note 40 bit register */
aungriah	0:a3b83d366423	115	/masks (low 32 bit) /
aungriah	0:a3b83d366423	116	#define TX_FCTRL_TFLEN_MASK 0x0000007FUL /* bit mask to access Transmit Frame Length */
aungriah	0:a3b83d366423	117	#define TX_FCTRL_TFLE_MASK 0x00000380UL /* bit mask to access Transmit Frame Length Extension */
aungriah	0:a3b83d366423	118	#define TX_FCTRL_FLE_MASK 0x000003FFUL /* bit mask to access Frame Length field */
aungriah	0:a3b83d366423	119	#define TX_FCTRL_TXBR_MASK 0x00006000UL /* bit mask to access Transmit Bit Rate */
aungriah	0:a3b83d366423	120	#define TX_FCTRL_TXPRF_MASK 0x00030000UL /* bit mask to access Transmit Pulse Repetition Frequency */
aungriah	0:a3b83d366423	121	#define TX_FCTRL_TXPSR_MASK 0x000C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
aungriah	0:a3b83d366423	122	#define TX_FCTRL_PE_MASK 0x00300000UL /* bit mask to access Preamble Extension */
aungriah	0:a3b83d366423	123	#define TX_FCTRL_TXPSR_PE_MASK 0x003C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
aungriah	0:a3b83d366423	124	#define TX_FCTRL_SAFE_MASK_32 0xFFFFE3FFUL /* FSCTRL has fields which should always be writen zero */
aungriah	0:a3b83d366423	125	/offset 0 /
aungriah	0:a3b83d366423	126	/offset 8 /
aungriah	0:a3b83d366423	127	#define TX_FCTRL_TXBR_110k 0x00000000UL /* Transmit Bit Rate = 110k */
aungriah	0:a3b83d366423	128	#define TX_FCTRL_TXBR_850k 0x00002000UL /* Transmit Bit Rate = 850k */
aungriah	0:a3b83d366423	129	#define TX_FCTRL_TXBR_6M 0x00004000UL /* Transmit Bit Rate = 6.8M */
aungriah	0:a3b83d366423	130	#define TX_FCTRL_TXBR_SHFT (13) /* shift to access Data Rate field */
aungriah	0:a3b83d366423	131	#define TX_FCTRL_TR 0x00008000UL /* Transmit Ranging enable */
aungriah	0:a3b83d366423	132	#define TX_FCTRL_TR_SHFT (15) /* shift to access Ranging bit */
aungriah	0:a3b83d366423	133	/offset 16 /
aungriah	0:a3b83d366423	134	#define TX_FCTRL_TXPRF_SHFT (16) /* shift to access Pulse Repetition Frequency field */
aungriah	0:a3b83d366423	135	#define TX_FCTRL_TXPRF_4M 0x00000000UL /* Transmit Pulse Repetition Frequency = 4 Mhz */
aungriah	0:a3b83d366423	136	#define TX_FCTRL_TXPRF_16M 0x00010000UL /* Transmit Pulse Repetition Frequency = 16 Mhz */
aungriah	0:a3b83d366423	137	#define TX_FCTRL_TXPRF_64M 0x00020000UL /* Transmit Pulse Repetition Frequency = 64 Mhz */
aungriah	0:a3b83d366423	138	#define TX_FCTRL_TXPSR_SHFT (18) /* shift to access Preamble Symbol Repetitions field */
aungriah	0:a3b83d366423	139	#define TX_FCTRL_PE_SHFT (20) /* shift to access Preamble length Extension to allow specification of non-standard values */
aungriah	0:a3b83d366423	140	#define TX_FCTRL_TXPSR_PE_16 0x00000000UL /* bit mask to access Preamble Extension = 16 */
aungriah	0:a3b83d366423	141	#define TX_FCTRL_TXPSR_PE_64 0x00040000UL /* bit mask to access Preamble Extension = 64 */
aungriah	0:a3b83d366423	142	#define TX_FCTRL_TXPSR_PE_128 0x00140000UL /* bit mask to access Preamble Extension = 128 */
aungriah	0:a3b83d366423	143	#define TX_FCTRL_TXPSR_PE_256 0x00240000UL /* bit mask to access Preamble Extension = 256 */
aungriah	0:a3b83d366423	144	#define TX_FCTRL_TXPSR_PE_512 0x00340000UL /* bit mask to access Preamble Extension = 512 */
aungriah	0:a3b83d366423	145	#define TX_FCTRL_TXPSR_PE_1024 0x00080000UL /* bit mask to access Preamble Extension = 1024 */
aungriah	0:a3b83d366423	146	#define TX_FCTRL_TXPSR_PE_1536 0x00180000UL /* bit mask to access Preamble Extension = 1536 */
aungriah	0:a3b83d366423	147	#define TX_FCTRL_TXPSR_PE_2048 0x00280000UL /* bit mask to access Preamble Extension = 2048 */
aungriah	0:a3b83d366423	148	#define TX_FCTRL_TXPSR_PE_4096 0x000C0000UL /* bit mask to access Preamble Extension = 4096 */
aungriah	0:a3b83d366423	149	/offset 22 /
aungriah	0:a3b83d366423	150	#define TX_FCTRL_TXBOFFS_SHFT (22) /* Shift to access transmit buffer index offset */
aungriah	0:a3b83d366423	151	#define TX_FCTRL_TXBOFFS_MASK 0xFFC00000UL /* bit mask to access Transmit buffer index offset 10-bit field */
aungriah	0:a3b83d366423	152	/offset 32 /
aungriah	0:a3b83d366423	153	#define TX_FCTRL_IFSDELAY_MASK 0xFF00000000ULL /* bit mask to access Inter-Frame Spacing field */
aungriah	0:a3b83d366423	154
aungriah	0:a3b83d366423	155	/**************************************************************************//
aungriah	0:a3b83d366423	156	* @brief Bit definitions for register TX_BUFFER
aungriah	0:a3b83d366423	157	**/
aungriah	0:a3b83d366423	158	#define TX_BUFFER_ID 0x09 /* Transmit Data Buffer */
aungriah	0:a3b83d366423	159	#define TX_BUFFER_LEN (1024)
aungriah	0:a3b83d366423	160
aungriah	0:a3b83d366423	161	/**************************************************************************//
aungriah	0:a3b83d366423	162	* @brief Bit definitions for register DX_TIME
aungriah	0:a3b83d366423	163	**/
aungriah	0:a3b83d366423	164	#define DX_TIME_ID 0x0A /* Delayed Send or Receive Time (40-bit) */
aungriah	0:a3b83d366423	165	#define DX_TIME_LEN (5)
aungriah	0:a3b83d366423	166
aungriah	0:a3b83d366423	167	/**************************************************************************//
aungriah	0:a3b83d366423	168	* @brief Bit definitions for register 0x08
aungriah	0:a3b83d366423	169	**/
aungriah	0:a3b83d366423	170	#define REG_0B_ID_RESERVED 0x0B
aungriah	0:a3b83d366423	171
aungriah	0:a3b83d366423	172	/**************************************************************************//
aungriah	0:a3b83d366423	173	* @brief Bit definitions for register RX_FWTO
aungriah	0:a3b83d366423	174	**/
aungriah	0:a3b83d366423	175	#define RX_FWTO_ID 0x0C /* Receive Frame Wait Timeout Period */
aungriah	0:a3b83d366423	176	#define RX_FWTO_OFFSET 0x00
aungriah	0:a3b83d366423	177	#define RX_FWTO_LEN (2) /* doc bug*/
aungriah	0:a3b83d366423	178	/mask and shift /
aungriah	0:a3b83d366423	179	#define RX_FWTO_MASK 0xFFFF
aungriah	0:a3b83d366423	180
aungriah	0:a3b83d366423	181	/**************************************************************************//
aungriah	0:a3b83d366423	182	* @brief Bit definitions for register SYS_CTRL
aungriah	0:a3b83d366423	183	**/
aungriah	0:a3b83d366423	184	#define SYS_CTRL_ID 0x0D /* System Control Register */
aungriah	0:a3b83d366423	185	#define SYS_CTRL_OFFSET 0x00
aungriah	0:a3b83d366423	186	#define SYS_CTRL_LEN (4)
aungriah	0:a3b83d366423	187	/masks /
aungriah	0:a3b83d366423	188	#define SYS_CTRL_MASK_32 0x010003CFUL /* System Control Register access mask (all unused fields should always be writen as zero) */
aungriah	0:a3b83d366423	189	/offset 0 /
aungriah	0:a3b83d366423	190	#define SYS_CTRL_SFCST 0x00000001UL /* Suppress Auto-FCS Transmission (on this frame) */
aungriah	0:a3b83d366423	191	#define SYS_CTRL_TXSTRT 0x00000002UL /* Start Transmitting Now */
aungriah	0:a3b83d366423	192	#define SYS_CTRL_TXDLYS 0x00000004UL /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */
aungriah	0:a3b83d366423	193	#define SYS_CTRL_CANSFCS 0x00000008UL /* Cancel Suppression of auto-FCS transmission (on the current frame) */
aungriah	0:a3b83d366423	194	#define SYS_CTRL_TRXOFF 0x00000040UL /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */
aungriah	0:a3b83d366423	195	#define SYS_CTRL_WAIT4RESP 0x00000080UL /* Wait for Response */
aungriah	0:a3b83d366423	196	/offset 8 /
aungriah	0:a3b83d366423	197	#define SYS_CTRL_RXENAB 0x00000100UL /* Enable Receiver Now */
aungriah	0:a3b83d366423	198	#define SYS_CTRL_RXDLYE 0x00000200UL /* Receiver Delayed Enable (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment*/
aungriah	0:a3b83d366423	199	/offset 16 /
aungriah	0:a3b83d366423	200	/offset 24 /
aungriah	0:a3b83d366423	201	#define SYS_CTRL_HSRBTOGGLE 0x01000000UL /* Host side receiver buffer pointer toggle - toggles 0/1 host side data set pointer */
aungriah	0:a3b83d366423	202	#define SYS_CTRL_HRBT (SYS_CTRL_HSRBTOGGLE)
aungriah	0:a3b83d366423	203	#define SYS_CTRL_HRBT_OFFSET (3)
aungriah	0:a3b83d366423	204
aungriah	0:a3b83d366423	205	/**************************************************************************//
aungriah	0:a3b83d366423	206	* @brief Bit definitions for register SYS_MASK
aungriah	0:a3b83d366423	207	**/
aungriah	0:a3b83d366423	208	#define SYS_MASK_ID 0x0E /* System Event Mask Register */
aungriah	0:a3b83d366423	209	#define SYS_MASK_LEN (4)
aungriah	0:a3b83d366423	210	/masks /
aungriah	0:a3b83d366423	211	#define SYS_MASK_MASK_32 0x3FF7FFFEUL /* System Event Mask Register access mask (all unused fields should always be writen as zero) */
aungriah	0:a3b83d366423	212	/offset 0 /
aungriah	0:a3b83d366423	213	#define SYS_MASK_MCPLOCK 0x00000002UL /* Mask clock PLL lock event */
aungriah	0:a3b83d366423	214	#define SYS_MASK_MESYNCR 0x00000004UL /* Mask clock PLL lock event */
aungriah	0:a3b83d366423	215	#define SYS_MASK_MAAT 0x00000008UL /* Mask automatic acknowledge trigger event */
aungriah	0:a3b83d366423	216	#define SYS_MASK_MTXFRB 0x00000010UL /* Mask transmit frame begins event */
aungriah	0:a3b83d366423	217	#define SYS_MASK_MTXPRS 0x00000020UL /* Mask transmit preamble sent event */
aungriah	0:a3b83d366423	218	#define SYS_MASK_MTXPHS 0x00000040UL /* Mask transmit PHY Header Sent event */
aungriah	0:a3b83d366423	219	#define SYS_MASK_MTXFRS 0x00000080UL /* Mask transmit frame sent event */
aungriah	0:a3b83d366423	220	/offset 8 /
aungriah	0:a3b83d366423	221	#define SYS_MASK_MRXPRD 0x00000100UL /* Mask receiver preamble detected event */
aungriah	0:a3b83d366423	222	#define SYS_MASK_MRXSFDD 0x00000200UL /* Mask receiver SFD detected event */
aungriah	0:a3b83d366423	223	#define SYS_MASK_MLDEDONE 0x00000400UL /* Mask LDE processing done event */
aungriah	0:a3b83d366423	224	#define SYS_MASK_MRXPHD 0x00000800UL /* Mask receiver PHY header detect event */
aungriah	0:a3b83d366423	225	#define SYS_MASK_MRXPHE 0x00001000UL /* Mask receiver PHY header error event */
aungriah	0:a3b83d366423	226	#define SYS_MASK_MRXDFR 0x00002000UL /* Mask receiver data frame ready event */
aungriah	0:a3b83d366423	227	#define SYS_MASK_MRXFCG 0x00004000UL /* Mask receiver FCS good event */
aungriah	0:a3b83d366423	228	#define SYS_MASK_MRXFCE 0x00008000UL /* Mask receiver FCS error event */
aungriah	0:a3b83d366423	229	/offset 16 /
aungriah	0:a3b83d366423	230	#define SYS_MASK_MRXRFSL 0x00010000UL /* Mask receiver Reed Solomon Frame Sync Loss event */
aungriah	0:a3b83d366423	231	#define SYS_MASK_MRXRFTO 0x00020000UL /* Mask Receive Frame Wait Timeout event */
aungriah	0:a3b83d366423	232	#define SYS_MASK_MLDEERR 0x00040000UL /* Mask leading edge detection processing error event */
aungriah	0:a3b83d366423	233	#define SYS_MASK_MRXOVRR 0x00100000UL /* Mask Receiver Overrun event */
aungriah	0:a3b83d366423	234	#define SYS_MASK_MRXPTO 0x00200000UL /* Mask Preamble detection timeout event */
aungriah	0:a3b83d366423	235	#define SYS_MASK_MGPIOIRQ 0x00400000UL /* Mask GPIO interrupt event */
aungriah	0:a3b83d366423	236	#define SYS_MASK_MSLP2INIT 0x00800000UL /* Mask SLEEP to INIT event */
aungriah	0:a3b83d366423	237	/offset 24/
aungriah	0:a3b83d366423	238	#define SYS_MASK_MRFPLLLL 0x01000000UL /* Mask RF PLL Loosing Lock warning event */
aungriah	0:a3b83d366423	239	#define SYS_MASK_MCPLLLL 0x02000000UL /* Mask Clock PLL Loosing Lock warning event */
aungriah	0:a3b83d366423	240	#define SYS_MASK_MRXSFDTO 0x04000000UL /* Mask Receive SFD timeout event */
aungriah	0:a3b83d366423	241	#define SYS_MASK_MHPDWARN 0x08000000UL /* Mask Half Period Delay Warning event */
aungriah	0:a3b83d366423	242	#define SYS_MASK_MTXBERR 0x10000000UL /* Mask Transmit Buffer Error event */
aungriah	0:a3b83d366423	243	#define SYS_MASK_MAFFREJ 0x20000000UL /* Mask Automatic Frame Filtering rejection event */
aungriah	0:a3b83d366423	244
aungriah	0:a3b83d366423	245	/**************************************************************************//
aungriah	0:a3b83d366423	246	* @brief Bit definitions for register SYS_STATUS
aungriah	0:a3b83d366423	247	**/
aungriah	0:a3b83d366423	248	#define SYS_STATUS_ID 0x0F /* System event Status Register */
aungriah	0:a3b83d366423	249	#define SYS_STATUS_OFFSET 0x00
aungriah	0:a3b83d366423	250	#define SYS_STATUS_LEN (5) /* Note 40 bit register */
aungriah	0:a3b83d366423	251	/masks /
aungriah	0:a3b83d366423	252	#define SYS_STATUS_MASK_32 0xFFF7FFFFUL /* System event Status Register access mask (all unused fields should always be writen as zero) */
aungriah	0:a3b83d366423	253	/offset 0 /
aungriah	0:a3b83d366423	254	#define SYS_STATUS_IRQS 0x00000001UL /* Interrupt Request Status READ ONLY */
aungriah	0:a3b83d366423	255	#define SYS_STATUS_CPLOCK 0x00000002UL /* Clock PLL Lock */
aungriah	0:a3b83d366423	256	#define SYS_STATUS_ESYNCR 0x00000004UL /* External Sync Clock Reset */
aungriah	0:a3b83d366423	257	#define SYS_STATUS_AAT 0x00000008UL /* Automatic Acknowledge Trigger */
aungriah	0:a3b83d366423	258	#define SYS_STATUS_TXFRB 0x00000010UL /* Transmit Frame Begins */
aungriah	0:a3b83d366423	259	#define SYS_STATUS_TXPRS 0x00000020UL /* Transmit Preamble Sent */
aungriah	0:a3b83d366423	260	#define SYS_STATUS_TXPHS 0x00000040UL /* Transmit PHY Header Sent */
aungriah	0:a3b83d366423	261	#define SYS_STATUS_TXFRS 0x00000080UL /* Transmit Frame Sent: This is set when the transmitter has completed the sending of a frame */
aungriah	0:a3b83d366423	262	/offset 8 /
aungriah	0:a3b83d366423	263	#define SYS_STATUS_RXPRD 0x00000100UL /* Receiver Preamble Detected status */
aungriah	0:a3b83d366423	264	#define SYS_STATUS_RXSFDD 0x00000200UL /* Receiver Start Frame Delimiter Detected. */
aungriah	0:a3b83d366423	265	#define SYS_STATUS_LDEDONE 0x00000400UL /* LDE processing done */
aungriah	0:a3b83d366423	266	#define SYS_STATUS_RXPHD 0x00000800UL /* Receiver PHY Header Detect */
aungriah	0:a3b83d366423	267	#define SYS_STATUS_RXPHE 0x00001000UL /* Receiver PHY Header Error */
aungriah	0:a3b83d366423	268	#define SYS_STATUS_RXDFR 0x00002000UL /* Receiver Data Frame Ready */
aungriah	0:a3b83d366423	269	#define SYS_STATUS_RXFCG 0x00004000UL /* Receiver FCS Good */
aungriah	0:a3b83d366423	270	#define SYS_STATUS_RXFCE 0x00008000UL /* Receiver FCS Error */
aungriah	0:a3b83d366423	271	/offset 16 /
aungriah	0:a3b83d366423	272	#define SYS_STATUS_RXRFSL 0x00010000UL /* Receiver Reed Solomon Frame Sync Loss */
aungriah	0:a3b83d366423	273	#define SYS_STATUS_RXRFTO 0x00020000UL /* Receive Frame Wait Timeout */
aungriah	0:a3b83d366423	274	#define SYS_STATUS_LDEERR 0x00040000UL /* Leading edge detection processing error */
aungriah	0:a3b83d366423	275	#define SYS_STATUS_reserved 0x00080000UL /* bit19 reserved */
aungriah	0:a3b83d366423	276	#define SYS_STATUS_RXOVRR 0x00100000UL /* Receiver Overrun */
aungriah	0:a3b83d366423	277	#define SYS_STATUS_RXPTO 0x00200000UL /* Preamble detection timeout */
aungriah	0:a3b83d366423	278	#define SYS_STATUS_GPIOIRQ 0x00400000UL /* GPIO interrupt */
aungriah	0:a3b83d366423	279	#define SYS_STATUS_SLP2INIT 0x00800000UL /* SLEEP to INIT */
aungriah	0:a3b83d366423	280	/offset 24 /
aungriah	0:a3b83d366423	281	#define SYS_STATUS_RFPLL_LL 0x01000000UL /* RF PLL Losing Lock */
aungriah	0:a3b83d366423	282	#define SYS_STATUS_CLKPLL_LL 0x02000000UL /* Clock PLL Losing Lock */
aungriah	0:a3b83d366423	283	#define SYS_STATUS_RXSFDTO 0x04000000UL /* Receive SFD timeout */
aungriah	0:a3b83d366423	284	#define SYS_STATUS_HPDWARN 0x08000000UL /* Half Period Delay Warning */
aungriah	0:a3b83d366423	285	#define SYS_STATUS_TXBERR 0x10000000UL /* Transmit Buffer Error */
aungriah	0:a3b83d366423	286	#define SYS_STATUS_AFFREJ 0x20000000UL /* Automatic Frame Filtering rejection */
aungriah	0:a3b83d366423	287	#define SYS_STATUS_HSRBP 0x40000000UL /* Host Side Receive Buffer Pointer */
aungriah	0:a3b83d366423	288	#define SYS_STATUS_ICRBP 0x80000000UL /* IC side Receive Buffer Pointer READ ONLY */
aungriah	0:a3b83d366423	289	/offset 32 /
aungriah	0:a3b83d366423	290	#define SYS_STATUS_RXRSCS 0x0100000000ULL /* Receiver Reed-Solomon Correction Status */
aungriah	0:a3b83d366423	291	#define SYS_STATUS_RXPREJ 0x0200000000ULL /* Receiver Preamble Rejection */
aungriah	0:a3b83d366423	292	#define SYS_STATUS_TXPUTE 0x0400000000ULL /* Transmit power up time error */
aungriah	0:a3b83d366423	293
aungriah	0:a3b83d366423	294	#define SYS_STATUS_TXERR (0x0408) /* These bits are the 16 high bits of status register TXPUTE and HPDWARN flags */
aungriah	0:a3b83d366423	295
aungriah	0:a3b83d366423	296	/* All RX events after a correct packet reception mask. */
aungriah	0:a3b83d366423	297	#define SYS_STATUS_ALL_RX_GOOD (SYS_STATUS_RXDFR \| SYS_STATUS_RXFCG \| SYS_STATUS_RXPRD \| \
aungriah	0:a3b83d366423	298	SYS_STATUS_RXSFDD \| SYS_STATUS_RXPHD \| SYS_STATUS_LDEDONE)
aungriah	0:a3b83d366423	299
aungriah	0:a3b83d366423	300	/* All double buffer events mask. */
aungriah	0:a3b83d366423	301	#define SYS_STATUS_ALL_DBLBUFF (SYS_STATUS_RXDFR \| SYS_STATUS_RXFCG)
aungriah	0:a3b83d366423	302
aungriah	0:a3b83d366423	303	/* All RX errors mask. */
aungriah	0:a3b83d366423	304	#define SYS_STATUS_ALL_RX_ERR (SYS_STATUS_RXPHE \| SYS_STATUS_RXFCE \| SYS_STATUS_RXRFSL \| SYS_STATUS_RXSFDTO \
aungriah	0:a3b83d366423	305	\| SYS_STATUS_AFFREJ \| SYS_STATUS_LDEERR)
aungriah	0:a3b83d366423	306
aungriah	0:a3b83d366423	307	/* User defined RX timeouts (frame wait timeout and preamble detect timeout) mask. */
aungriah	0:a3b83d366423	308	#define SYS_STATUS_ALL_RX_TO (SYS_STATUS_RXRFTO \| SYS_STATUS_RXPTO)
aungriah	0:a3b83d366423	309
aungriah	0:a3b83d366423	310	/* All TX events mask. */
aungriah	0:a3b83d366423	311	#define SYS_STATUS_ALL_TX (SYS_STATUS_AAT \| SYS_STATUS_TXFRB \| SYS_STATUS_TXPRS \| \
aungriah	0:a3b83d366423	312	SYS_STATUS_TXPHS \| SYS_STATUS_TXFRS )
aungriah	0:a3b83d366423	313
aungriah	0:a3b83d366423	314
aungriah	0:a3b83d366423	315	/**************************************************************************//
aungriah	0:a3b83d366423	316	* @brief Bit definitions for register RX_FINFO
aungriah	0:a3b83d366423	317	**/
aungriah	0:a3b83d366423	318	#define RX_FINFO_ID 0x10 /* RX Frame Information (in double buffer set) */
aungriah	0:a3b83d366423	319	#define RX_FINFO_OFFSET 0x00
aungriah	0:a3b83d366423	320	#define RX_FINFO_LEN (4)
aungriah	0:a3b83d366423	321	/mask and shift /
aungriah	0:a3b83d366423	322	#define RX_FINFO_MASK_32 0xFFFFFBFFUL /* System event Status Register access mask (all unused fields should always be writen as zero) */
aungriah	0:a3b83d366423	323	#define RX_FINFO_RXFLEN_MASK 0x0000007FUL /* Receive Frame Length (0 to 127) */
aungriah	0:a3b83d366423	324	#define RX_FINFO_RXFLE_MASK 0x00000380UL /* Receive Frame Length Extension (0 to 7)<<7 */
aungriah	0:a3b83d366423	325	#define RX_FINFO_RXFL_MASK_1023 0x000003FFUL /* Receive Frame Length Extension (0 to 1023) */
aungriah	0:a3b83d366423	326
aungriah	0:a3b83d366423	327	#define RX_FINFO_RXNSPL_MASK 0x00001800UL /* Receive Non-Standard Preamble Length */
aungriah	0:a3b83d366423	328	#define RX_FINFO_RXPSR_MASK 0x000C0000UL /* RX Preamble Repetition. 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols */
aungriah	0:a3b83d366423	329
aungriah	0:a3b83d366423	330	#define RX_FINFO_RXPEL_MASK 0x000C1800UL /* Receive Preamble Length = RXPSR+RXNSPL */
aungriah	0:a3b83d366423	331	#define RX_FINFO_RXPEL_64 0x00040000UL /* Receive Preamble length = 64 */
aungriah	0:a3b83d366423	332	#define RX_FINFO_RXPEL_128 0x00040800UL /* Receive Preamble length = 128 */
aungriah	0:a3b83d366423	333	#define RX_FINFO_RXPEL_256 0x00041000UL /* Receive Preamble length = 256 */
aungriah	0:a3b83d366423	334	#define RX_FINFO_RXPEL_512 0x00041800UL /* Receive Preamble length = 512 */
aungriah	0:a3b83d366423	335	#define RX_FINFO_RXPEL_1024 0x00080000UL /* Receive Preamble length = 1024 */
aungriah	0:a3b83d366423	336	#define RX_FINFO_RXPEL_1536 0x00080800UL /* Receive Preamble length = 1536 */
aungriah	0:a3b83d366423	337	#define RX_FINFO_RXPEL_2048 0x00081000UL /* Receive Preamble length = 2048 */
aungriah	0:a3b83d366423	338	#define RX_FINFO_RXPEL_4096 0x000C0000UL /* Receive Preamble length = 4096 */
aungriah	0:a3b83d366423	339
aungriah	0:a3b83d366423	340	#define RX_FINFO_RXBR_MASK 0x00006000UL /* Receive Bit Rate report. This field reports the received bit rate */
aungriah	0:a3b83d366423	341	#define RX_FINFO_RXBR_110k 0x00000000UL /* Received bit rate = 110 kbps */
aungriah	0:a3b83d366423	342	#define RX_FINFO_RXBR_850k 0x00002000UL /* Received bit rate = 850 kbps */
aungriah	0:a3b83d366423	343	#define RX_FINFO_RXBR_6M 0x00004000UL /* Received bit rate = 6.8 Mbps */
aungriah	0:a3b83d366423	344	#define RX_FINFO_RXBR_SHIFT (13)
aungriah	0:a3b83d366423	345
aungriah	0:a3b83d366423	346	#define RX_FINFO_RNG 0x00008000UL /* Receiver Ranging. Ranging bit in the received PHY header identifying the frame as a ranging packet. */
aungriah	0:a3b83d366423	347	#define RX_FINFO_RNG_SHIFT (15)
aungriah	0:a3b83d366423	348
aungriah	0:a3b83d366423	349	#define RX_FINFO_RXPRF_MASK 0x00030000UL /* RX Pulse Repetition Rate report */
aungriah	0:a3b83d366423	350	#define RX_FINFO_RXPRF_16M 0x00010000UL /* PRF being employed in the receiver = 16M */
aungriah	0:a3b83d366423	351	#define RX_FINFO_RXPRF_64M 0x00020000UL /* PRF being employed in the receiver = 64M */
aungriah	0:a3b83d366423	352	#define RX_FINFO_RXPRF_SHIFT (16)
aungriah	0:a3b83d366423	353
aungriah	0:a3b83d366423	354	#define RX_FINFO_RXPACC_MASK 0xFFF00000UL /* Preamble Accumulation Count */
aungriah	0:a3b83d366423	355	#define RX_FINFO_RXPACC_SHIFT (20)
aungriah	0:a3b83d366423	356
aungriah	0:a3b83d366423	357
aungriah	0:a3b83d366423	358	/**************************************************************************//
aungriah	0:a3b83d366423	359	* @brief Bit definitions for register RX_BUFFER
aungriah	0:a3b83d366423	360	**/
aungriah	0:a3b83d366423	361	#define RX_BUFFER_ID 0x11 /* Receive Data Buffer (in double buffer set) */
aungriah	0:a3b83d366423	362	#define RX_BUFFER_LEN (1024)
aungriah	0:a3b83d366423	363
aungriah	0:a3b83d366423	364
aungriah	0:a3b83d366423	365	/**************************************************************************//
aungriah	0:a3b83d366423	366	* @brief Bit definitions for register RX_FQUAL
aungriah	0:a3b83d366423	367	**/
aungriah	0:a3b83d366423	368	#define RX_FQUAL_ID 0x12 /* Rx Frame Quality information (in double buffer set) */
aungriah	0:a3b83d366423	369	#define RX_FQUAL_LEN (8) /* note 64 bit register*/
aungriah	0:a3b83d366423	370	/mask and shift /
aungriah	0:a3b83d366423	371	/offset 0 /
aungriah	0:a3b83d366423	372	#define RX_EQUAL_STD_NOISE_MASK 0x0000FFFFULL /* Standard Deviation of Noise */
aungriah	0:a3b83d366423	373	#define RX_EQUAL_STD_NOISE_SHIFT (0)
aungriah	0:a3b83d366423	374	#define STD_NOISE_MASK RX_EQUAL_STD_NOISE_MASK
aungriah	0:a3b83d366423	375	#define STD_NOISE_SHIFT RX_EQUAL_STD_NOISE_SHIFT
aungriah	0:a3b83d366423	376	/offset 16 /
aungriah	0:a3b83d366423	377	#define RX_EQUAL_FP_AMPL2_MASK 0xFFFF0000ULL /* First Path Amplitude point 2 */
aungriah	0:a3b83d366423	378	#define RX_EQUAL_FP_AMPL2_SHIFT (16)
aungriah	0:a3b83d366423	379	#define FP_AMPL2_MASK RX_EQUAL_FP_AMPL2_MASK
aungriah	0:a3b83d366423	380	#define FP_AMPL2_SHIFT RX_EQUAL_FP_AMPL2_SHIFT
aungriah	0:a3b83d366423	381	/offset 32/
aungriah	0:a3b83d366423	382	#define RX_EQUAL_PP_AMPL3_MASK 0x0000FFFF00000000ULL /* First Path Amplitude point 3 */
aungriah	0:a3b83d366423	383	#define RX_EQUAL_PP_AMPL3_SHIFT (32)
aungriah	0:a3b83d366423	384	#define PP_AMPL3_MASK RX_EQUAL_PP_AMPL3_MASK
aungriah	0:a3b83d366423	385	#define PP_AMPL3_SHIFT RX_EQUAL_PP_AMPL3_SHIFT
aungriah	0:a3b83d366423	386	/offset 48/
aungriah	0:a3b83d366423	387	#define RX_EQUAL_CIR_MXG_MASK 0xFFFF000000000000ULL /* Channel Impulse Response Max Growth */
aungriah	0:a3b83d366423	388	#define RX_EQUAL_CIR_MXG_SHIFT (48)
aungriah	0:a3b83d366423	389	#define CIR_MXG_MASK RX_EQUAL_CIR_MXG_MASK
aungriah	0:a3b83d366423	390	#define CIR_MXG_SHIFT RX_EQUAL_CIR_MXG_SHIFT
aungriah	0:a3b83d366423	391
aungriah	0:a3b83d366423	392
aungriah	0:a3b83d366423	393
aungriah	0:a3b83d366423	394	/**************************************************************************//
aungriah	0:a3b83d366423	395	* @brief Bit definitions for register RX_TTCKI
aungriah	0:a3b83d366423	396	* The value here is the interval over which the timing offset reported
aungriah	0:a3b83d366423	397	* in the RXTOFS field of Register file: 0x14 RX_TTCKO is measured.
aungriah	0:a3b83d366423	398	* The clock offset is calculated by dividing RXTTCKI by RXTOFS.
aungriah	0:a3b83d366423	399	* The value in RXTTCKI will take just one of two values depending on the PRF: 0x01F00000 @ 16 MHz PRF,
aungriah	0:a3b83d366423	400	* and 0x01FC0000 @ 64 MHz PRF.
aungriah	0:a3b83d366423	401	**/
aungriah	0:a3b83d366423	402	#define RX_TTCKI_ID 0x13 /* Receiver Time Tracking Interval (in double buffer set) */
aungriah	0:a3b83d366423	403	#define RX_TTCKI_LEN (4)
aungriah	0:a3b83d366423	404
aungriah	0:a3b83d366423	405	/**************************************************************************//
aungriah	0:a3b83d366423	406	* @brief Bit definitions for register RX_TTCKO
aungriah	0:a3b83d366423	407	**/
aungriah	0:a3b83d366423	408	#define RX_TTCKO_ID 0x14 /* Receiver Time Tracking Offset (in double buffer set) */
aungriah	0:a3b83d366423	409	#define RX_TTCKO_LEN (5) /* Note 40 bit register */
aungriah	0:a3b83d366423	410	/mask and shift /
aungriah	0:a3b83d366423	411	#define RX_TTCKO_MASK_32 0xFF07FFFFUL /* Receiver Time Tracking Offset access mask (all unused fields should always be writen as zero) */
aungriah	0:a3b83d366423	412	/offset 0 /
aungriah	0:a3b83d366423	413	#define RX_TTCKO_RXTOFS_MASK 0x0007FFFFUL /* RX time tracking offset. This RXTOFS value is a 19-bit signed quantity*/
aungriah	0:a3b83d366423	414	/offset 24 /
aungriah	0:a3b83d366423	415	#define RX_TTCKO_RSMPDEL_MASK 0xFF000000UL /* This 8-bit field reports an internal re-sampler delay value */
aungriah	0:a3b83d366423	416	/offset 32 /
aungriah	0:a3b83d366423	417	#define RX_TTCKO_RCPHASE_MASK 0x7F0000000000ULL /* This 7-bit field reports the receive carrier phase adjustment at time the ranging timestamp is made. */
aungriah	0:a3b83d366423	418
aungriah	0:a3b83d366423	419
aungriah	0:a3b83d366423	420	/**************************************************************************//
aungriah	0:a3b83d366423	421	* @brief Bit definitions for register RX_TIME
aungriah	0:a3b83d366423	422	**/
aungriah	0:a3b83d366423	423	#define RX_TIME_ID 0x15 /* Receive Message Time of Arrival (in double buffer set) */
aungriah	0:a3b83d366423	424	#define RX_TIME_LLEN (14)
aungriah	0:a3b83d366423	425	#define RX_TIME_RX_STAMP_LEN (5) /* read only 5 bytes (the adjusted timestamp (40:0)) */
aungriah	0:a3b83d366423	426	#define RX_STAMP_LEN RX_TIME_RX_STAMP_LEN
aungriah	0:a3b83d366423	427	/mask and shift /
aungriah	0:a3b83d366423	428	#define RX_TIME_RX_STAMP_OFFSET (0) /* byte 0..4 40 bit Reports the fully adjusted time of reception. */
aungriah	0:a3b83d366423	429	#define RX_TIME_FP_INDEX_OFFSET (5) /* byte 5..6 16 bit First path index. */
aungriah	0:a3b83d366423	430	#define RX_TIME_FP_AMPL1_OFFSET (7) /* byte 7..8 16 bit First Path Amplitude point 1 / / doc bug */
aungriah	0:a3b83d366423	431	#define RX_TIME_FP_RAWST_OFFSET (9) /* byte 9..13 40 bit Raw Timestamp for the frame */
aungriah	0:a3b83d366423	432
aungriah	0:a3b83d366423	433
aungriah	0:a3b83d366423	434	/**************************************************************************//
aungriah	0:a3b83d366423	435	* @brief Bit definitions for register
aungriah	0:a3b83d366423	436	**/
aungriah	0:a3b83d366423	437	#define REG_16_ID_RESERVED 0x16
aungriah	0:a3b83d366423	438
aungriah	0:a3b83d366423	439
aungriah	0:a3b83d366423	440	/**************************************************************************//
aungriah	0:a3b83d366423	441	* @brief Bit definitions for register
aungriah	0:a3b83d366423	442	**/
aungriah	0:a3b83d366423	443	#define TX_TIME_ID 0x17 /* Transmit Message Time of Sending */
aungriah	0:a3b83d366423	444	#define TX_TIME_LLEN (10)
aungriah	0:a3b83d366423	445	#define TX_TIME_TX_STAMP_LEN (5) /* 40-bits = 5 bytes */
aungriah	0:a3b83d366423	446	#define TX_STAMP_LEN TX_TIME_TX_STAMP_LEN
aungriah	0:a3b83d366423	447	/mask and shift /
aungriah	0:a3b83d366423	448	#define TX_TIME_TX_STAMP_OFFSET (0) /* byte 0..4 40 bit Reports the fully adjusted time of transmission */
aungriah	0:a3b83d366423	449	#define TX_TIME_TX_RAWST_OFFSET (5) /* byte 5..9 40 bit Raw Timestamp for the frame */
aungriah	0:a3b83d366423	450
aungriah	0:a3b83d366423	451
aungriah	0:a3b83d366423	452
aungriah	0:a3b83d366423	453
aungriah	0:a3b83d366423	454	/**************************************************************************//
aungriah	0:a3b83d366423	455	* @brief Bit definitions for register TX_ANTD
aungriah	0:a3b83d366423	456	**/
aungriah	0:a3b83d366423	457	#define TX_ANTD_ID 0x18 /* 16-bit Delay from Transmit to Antenna */
aungriah	0:a3b83d366423	458	#define TX_ANTD_OFFSET 0x00
aungriah	0:a3b83d366423	459	#define TX_ANTD_LEN (2)
aungriah	0:a3b83d366423	460
aungriah	0:a3b83d366423	461
aungriah	0:a3b83d366423	462
aungriah	0:a3b83d366423	463
aungriah	0:a3b83d366423	464	/**************************************************************************//
aungriah	0:a3b83d366423	465	* @brief Bit definitions for register SYS_STATES
aungriah	0:a3b83d366423	466	* Register map register file 0x19 is reserved
aungriah	0:a3b83d366423	467	*
aungriah	0:a3b83d366423	468	**/
aungriah	0:a3b83d366423	469	#define SYS_STATE_ID 0x19 /* System State information READ ONLY */
aungriah	0:a3b83d366423	470	#define SYS_STATE_LEN (5)
aungriah	0:a3b83d366423	471
aungriah	0:a3b83d366423	472	/**************************************************************************//
aungriah	0:a3b83d366423	473	* @brief Bit definitions for register ACK_RESP_T
aungriah	0:a3b83d366423	474	**/
aungriah	0:a3b83d366423	475	/* Acknowledge (31:24 preamble symbol delay before auto ACK is sent) and respose (19:0 - unit 1us) timer */
aungriah	0:a3b83d366423	476	#define ACK_RESP_T_ID 0x1A /* Acknowledgement Time and Response Time */
aungriah	0:a3b83d366423	477	#define ACK_RESP_T_LEN (4)
aungriah	0:a3b83d366423	478	/mask and shift /
aungriah	0:a3b83d366423	479	#define ACK_RESP_T_MASK 0xFF0FFFFFUL /* Acknowledgement Time and Response access mask */
aungriah	0:a3b83d366423	480	#define ACK_RESP_T_W4R_TIM_OFFSET 0 /* In bytes */
aungriah	0:a3b83d366423	481	#define ACK_RESP_T_W4R_TIM_MASK 0x000FFFFFUL /* Wait-for-Response turn-around Time 20 bit field */
aungriah	0:a3b83d366423	482	#define W4R_TIM_MASK ACK_RESP_T_W4R_TIM_MASK
aungriah	0:a3b83d366423	483	#define ACK_RESP_T_ACK_TIM_OFFSET 3 /* In bytes */
aungriah	0:a3b83d366423	484	#define ACK_RESP_T_ACK_TIM_MASK 0xFF000000UL /* Auto-Acknowledgement turn-around Time */
aungriah	0:a3b83d366423	485	#define ACK_TIM_MASK ACK_RESP_T_ACK_TIM_MASK
aungriah	0:a3b83d366423	486
aungriah	0:a3b83d366423	487
aungriah	0:a3b83d366423	488
aungriah	0:a3b83d366423	489	/**************************************************************************//
aungriah	0:a3b83d366423	490	* @brief Bit definitions for register 0x1B 0x1C
aungriah	0:a3b83d366423	491	**/
aungriah	0:a3b83d366423	492	#define REG_1B_ID_RESERVED 0x1B
aungriah	0:a3b83d366423	493	#define REG_1C_ID_RESERVED 0x1C
aungriah	0:a3b83d366423	494
aungriah	0:a3b83d366423	495	/**************************************************************************//
aungriah	0:a3b83d366423	496	* @brief Bit definitions for register RX_SNIFF
aungriah	0:a3b83d366423	497	* Sniff Mode Configuration or Pulsed Preamble Reception Configuration
aungriah	0:a3b83d366423	498	**/
aungriah	0:a3b83d366423	499	#define RX_SNIFF_ID 0x1D /* Sniff Mode Configuration */
aungriah	0:a3b83d366423	500	#define RX_SNIFF_OFFSET 0x00
aungriah	0:a3b83d366423	501	#define RX_SNIFF_LEN (4)
aungriah	0:a3b83d366423	502	/mask and shift /
aungriah	0:a3b83d366423	503	#define RX_SNIFF_MASK 0x0000FF0FUL /* */
aungriah	0:a3b83d366423	504	#define RX_SNIFF_SNIFF_ONT_MASK 0x0000000FUL /* SNIFF Mode ON time. Specified in units of PAC */
aungriah	0:a3b83d366423	505	#define SNIFF_ONT_MASK RX_SNIFF_SNIFF_ONT_MASK
aungriah	0:a3b83d366423	506	#define RX_SNIFF_SNIFF_OFFT_MASK 0x0000FF00UL /* SNIFF Mode OFF time specified in units of approximately 1mkS, or 128 system clock cycles.*/
aungriah	0:a3b83d366423	507	#define SNIFF_OFFT_MASK RX_SNIFF_SNIFF_OFFT_MASK
aungriah	0:a3b83d366423	508
aungriah	0:a3b83d366423	509
aungriah	0:a3b83d366423	510
aungriah	0:a3b83d366423	511	/**************************************************************************//
aungriah	0:a3b83d366423	512	* @brief Bit definitions for register TX_POWER
aungriah	0:a3b83d366423	513	**/
aungriah	0:a3b83d366423	514	#define TX_POWER_ID 0x1E /* TX Power Control */
aungriah	0:a3b83d366423	515	#define TX_POWER_LEN (4)
aungriah	0:a3b83d366423	516	/mask and shift definition for Smart Transmit Power Control/
aungriah	0:a3b83d366423	517	#define TX_POWER_BOOSTNORM_MASK 0x00000000UL /* This is the normal power setting used for frames that do not fall */
aungriah	0:a3b83d366423	518	#define BOOSTNORM_MASK TX_POWER_BOOSTNORM_MASK
aungriah	0:a3b83d366423	519	#define TX_POWER_BOOSTNORM_SHIFT (0)
aungriah	0:a3b83d366423	520	#define TX_POWER_BOOSTP500_MASK 0x00000000UL /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.5 ms duration */
aungriah	0:a3b83d366423	521	#define BOOSTP500_MASK TX_POWER_BOOSTP500_MASK
aungriah	0:a3b83d366423	522	#define TX_POWER_BOOSTP500_SHIFT (8)
aungriah	0:a3b83d366423	523	#define TX_POWER_BOOSTP250_MASK 0x00000000UL /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.25 ms duration */
aungriah	0:a3b83d366423	524	#define BOOSTP250_MASK TX_POWER_BOOSTP250_MASK
aungriah	0:a3b83d366423	525	#define TX_POWER_BOOSTP250_SHIFT (16)
aungriah	0:a3b83d366423	526	#define TX_POWER_BOOSTP125_MASK 0x00000000UL /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.125 ms */
aungriah	0:a3b83d366423	527	#define BOOSTP125_MASK TX_POWER_BOOSTP125_MASK
aungriah	0:a3b83d366423	528	#define TX_POWER_BOOSTP125_SHIFT (24)
aungriah	0:a3b83d366423	529	/mask and shift definition for Manual Transmit Power Control (DIS_STXP=1 in SYS_CFG)/
aungriah	0:a3b83d366423	530	#define TX_POWER_MAN_DEFAULT 0x0E080222UL
aungriah	0:a3b83d366423	531	#define TX_POWER_TXPOWPHR_MASK 0x0000FF00UL /* This power setting is applied during the transmission of the PHY header (PHR) portion of the frame. */
aungriah	0:a3b83d366423	532	#define TX_POWER_TXPOWSD_MASK 0x00FF0000UL /* This power setting is applied during the transmission of the synchronisation header (SHR) and data portions of the frame. */
aungriah	0:a3b83d366423	533
aungriah	0:a3b83d366423	534
aungriah	0:a3b83d366423	535	/**************************************************************************//
aungriah	0:a3b83d366423	536	* @brief Bit definitions for register CHAN_CTRL
aungriah	0:a3b83d366423	537	**/
aungriah	0:a3b83d366423	538	#define CHAN_CTRL_ID 0x1F /* Channel Control */
aungriah	0:a3b83d366423	539	#define CHAN_CTRL_LEN (4)
aungriah	0:a3b83d366423	540	/mask and shift /
aungriah	0:a3b83d366423	541	#define CHAN_CTRL_MASK 0xFFFF00FFUL /* Channel Control Register access mask */
aungriah	0:a3b83d366423	542	#define CHAN_CTRL_TX_CHAN_MASK 0x0000000FUL /* Supported channels are 1, 2, 3, 4, 5, and 7.*/
aungriah	0:a3b83d366423	543	#define CHAN_CTRL_TX_CHAN_SHIFT (0) /* Bits 0..3 TX channel number 0-15 selection */
aungriah	0:a3b83d366423	544
aungriah	0:a3b83d366423	545	#define CHAN_CTRL_RX_CHAN_MASK 0x000000F0UL
aungriah	0:a3b83d366423	546	#define CHAN_CTRL_RX_CHAN_SHIFT (4) /* Bits 4..7 RX channel number 0-15 selection */
aungriah	0:a3b83d366423	547
aungriah	0:a3b83d366423	548	#define CHAN_CTRL_RXFPRF_MASK 0x000C0000UL /* Bits 18..19 Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
aungriah	0:a3b83d366423	549	#define CHAN_CTRL_RXFPRF_SHIFT (18)
aungriah	0:a3b83d366423	550	/* Specific RXFPRF configuration */
aungriah	0:a3b83d366423	551	#define CHAN_CTRL_RXFPRF_4 0x00000000UL /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
aungriah	0:a3b83d366423	552	#define CHAN_CTRL_RXFPRF_16 0x00040000UL /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
aungriah	0:a3b83d366423	553	#define CHAN_CTRL_RXFPRF_64 0x00080000UL /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
aungriah	0:a3b83d366423	554	#define CHAN_CTRL_TX_PCOD_MASK 0x07C00000UL /* Bits 22..26 TX Preamble Code selection, 1 to 24. */
aungriah	0:a3b83d366423	555	#define CHAN_CTRL_TX_PCOD_SHIFT (22)
aungriah	0:a3b83d366423	556	#define CHAN_CTRL_RX_PCOD_MASK 0xF8000000UL /* Bits 27..31 RX Preamble Code selection, 1 to 24. */
aungriah	0:a3b83d366423	557	#define CHAN_CTRL_RX_PCOD_SHIFT (27)
aungriah	0:a3b83d366423	558	/offset 16 /
aungriah	0:a3b83d366423	559	#define CHAN_CTRL_DWSFD 0x00020000UL /* Bit 17 This bit enables a non-standard DecaWave proprietary SFD sequence. */
aungriah	0:a3b83d366423	560	#define CHAN_CTRL_DWSFD_SHIFT (17)
aungriah	0:a3b83d366423	561	#define CHAN_CTRL_TNSSFD 0x00100000UL /* Bit 20 This bit enables the use of user-defined SFD when transmitting */
aungriah	0:a3b83d366423	562	#define CHAN_CTRL_TNSSFD_SHIFT (20)
aungriah	0:a3b83d366423	563	#define CHAN_CTRL_RNSSFD 0x00200000UL /* Bit 21 This bit enables the use of user-defined SFD when receiving */
aungriah	0:a3b83d366423	564	#define CHAN_CTRL_RNSSFD_SHIFT (21)
aungriah	0:a3b83d366423	565
aungriah	0:a3b83d366423	566
aungriah	0:a3b83d366423	567
aungriah	0:a3b83d366423	568
aungriah	0:a3b83d366423	569	/**************************************************************************//
aungriah	0:a3b83d366423	570	* @brief Bit definitions for register 0x20
aungriah	0:a3b83d366423	571	**/
aungriah	0:a3b83d366423	572	#define REG_20_ID_RESERVED 0x20
aungriah	0:a3b83d366423	573
aungriah	0:a3b83d366423	574	/**************************************************************************//
aungriah	0:a3b83d366423	575	* @brief Bit definitions for register USR_SFD
aungriah	0:a3b83d366423	576	* Please read User Manual : User defined SFD sequence
aungriah	0:a3b83d366423	577	**/
aungriah	0:a3b83d366423	578	#define USR_SFD_ID 0x21 /* User-specified short/long TX/RX SFD sequences */
aungriah	0:a3b83d366423	579	#define USR_SFD_LEN (41)
aungriah	0:a3b83d366423	580	#define DW_NS_SFD_LEN_110K 64 /* Decawave non-standard SFD length for 110 kbps */
aungriah	0:a3b83d366423	581	#define DW_NS_SFD_LEN_850K 16 /* Decawave non-standard SFD length for 850 kbps */
aungriah	0:a3b83d366423	582	#define DW_NS_SFD_LEN_6M8 8 /* Decawave non-standard SFD length for 6.8 Mbps */
aungriah	0:a3b83d366423	583
aungriah	0:a3b83d366423	584
aungriah	0:a3b83d366423	585	/**************************************************************************//
aungriah	0:a3b83d366423	586	* @brief Bit definitions for register
aungriah	0:a3b83d366423	587	**/
aungriah	0:a3b83d366423	588	#define REG_22_ID_RESERVED 0x22
aungriah	0:a3b83d366423	589
aungriah	0:a3b83d366423	590	/**************************************************************************//
aungriah	0:a3b83d366423	591	* @brief Bit definitions for register AGC_CTRL
aungriah	0:a3b83d366423	592	* Please take care to write to this register as doing so may cause the DW1000 to malfunction
aungriah	0:a3b83d366423	593	**/
aungriah	0:a3b83d366423	594	#define AGC_CTRL_ID 0x23 /* Automatic Gain Control configuration */
aungriah	0:a3b83d366423	595	#define AGC_CTRL_LEN (32)
aungriah	0:a3b83d366423	596	#define AGC_CFG_STS_ID AGC_CTRL_ID
aungriah	0:a3b83d366423	597	/* offset from AGC_CTRL_ID in bytes */
aungriah	0:a3b83d366423	598	#define AGC_CTRL1_OFFSET (0x02)
aungriah	0:a3b83d366423	599	#define AGC_CTRL1_LEN (2)
aungriah	0:a3b83d366423	600	#define AGC_CTRL1_MASK 0x0001 /* access mask to AGC configuration and control register */
aungriah	0:a3b83d366423	601	#define AGC_CTRL1_DIS_AM 0x0001 /* Disable AGC Measurement. The DIS_AM bit is set by default. */
aungriah	0:a3b83d366423	602	/* offset from AGC_CTRL_ID in bytes */
aungriah	0:a3b83d366423	603	/* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
aungriah	0:a3b83d366423	604	#define AGC_TUNE1_OFFSET (0x04)
aungriah	0:a3b83d366423	605	#define AGC_TUNE1_LEN (2)
aungriah	0:a3b83d366423	606	#define AGC_TUNE1_MASK 0xFFFF /* It is a 16-bit tuning register for the AGC. */
aungriah	0:a3b83d366423	607	#define AGC_TUNE1_16M 0x8870
aungriah	0:a3b83d366423	608	#define AGC_TUNE1_64M 0x889B
aungriah	0:a3b83d366423	609	/* offset from AGC_CTRL_ID in bytes */
aungriah	0:a3b83d366423	610	/* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
aungriah	0:a3b83d366423	611	#define AGC_TUNE2_OFFSET (0x0C)
aungriah	0:a3b83d366423	612	#define AGC_TUNE2_LEN (4)
aungriah	0:a3b83d366423	613	#define AGC_TUNE2_MASK 0xFFFFFFFFUL
aungriah	0:a3b83d366423	614	#define AGC_TUNE2_VAL 0X2502A907UL
aungriah	0:a3b83d366423	615	/* offset from AGC_CTRL_ID in bytes */
aungriah	0:a3b83d366423	616	/* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
aungriah	0:a3b83d366423	617	#define AGC_TUNE3_OFFSET (0x12)
aungriah	0:a3b83d366423	618	#define AGC_TUNE3_LEN (2)
aungriah	0:a3b83d366423	619	#define AGC_TUNE3_MASK 0xFFFF
aungriah	0:a3b83d366423	620	#define AGC_TUNE3_VAL 0X0055
aungriah	0:a3b83d366423	621	/* offset from AGC_CTRL_ID in bytes */
aungriah	0:a3b83d366423	622	#define AGC_STAT1_OFFSET (0x1E)
aungriah	0:a3b83d366423	623	#define AGC_STAT1_LEN (3)
aungriah	0:a3b83d366423	624	#define AGC_STAT1_MASK 0x0FFFFF
aungriah	0:a3b83d366423	625	#define AGC_STAT1_EDG1_MASK 0x0007C0 /* This 5-bit gain value relates to input noise power measurement. */
aungriah	0:a3b83d366423	626	#define AGC_STAT1_EDG2_MASK 0x0FF800 /* This 9-bit value relates to the input noise power measurement. */
aungriah	0:a3b83d366423	627
aungriah	0:a3b83d366423	628	/**************************************************************************//
aungriah	0:a3b83d366423	629	* @brief Bit definitions for register EXT_SYNC
aungriah	0:a3b83d366423	630	**/
aungriah	0:a3b83d366423	631	#define EXT_SYNC_ID 0x24 /* External synchronisation control */
aungriah	0:a3b83d366423	632	#define EXT_SYNC_LEN (12)
aungriah	0:a3b83d366423	633	/* offset from EXT_SYNC_ID in bytes */
aungriah	0:a3b83d366423	634	#define EC_CTRL_OFFSET (0x00)
aungriah	0:a3b83d366423	635	#define EC_CTRL_LEN (4)
aungriah	0:a3b83d366423	636	#define EC_CTRL_MASK 0x00000FFBUL /* sub-register 0x00 is the External clock synchronisation counter configuration register */
aungriah	0:a3b83d366423	637	#define EC_CTRL_OSTSM 0x00000001UL /* External transmit synchronisation mode enable */
aungriah	0:a3b83d366423	638	#define EC_CTRL_OSRSM 0x00000002UL /* External receive synchronisation mode enable */
aungriah	0:a3b83d366423	639	#define EC_CTRL_PLLLCK 0x04 /* PLL lock detect enable */
aungriah	0:a3b83d366423	640	#define EC_CTRL_OSTRM 0x00000800UL /* External timebase reset mode enable */
aungriah	0:a3b83d366423	641	#define EC_CTRL_WAIT_MASK 0x000007F8UL /* Wait counter used for external transmit synchronisation and external timebase reset */
aungriah	0:a3b83d366423	642	/* offset from EXT_SYNC_ID in bytes */
aungriah	0:a3b83d366423	643	#define EC_RXTC_OFFSET (0x04)
aungriah	0:a3b83d366423	644	#define EC_RXTC_LEN (4)
aungriah	0:a3b83d366423	645	#define EC_RXTC_MASK 0xFFFFFFFFUL /* External clock synchronisation counter captured on RMARKER */
aungriah	0:a3b83d366423	646	/* offset from EXT_SYNC_ID in bytes */
aungriah	0:a3b83d366423	647	#define EC_GOLP (0x08)
aungriah	0:a3b83d366423	648	#define EC_GOLP_LEN (4)
aungriah	0:a3b83d366423	649	#define EC_GOLP_MASK 0x0000003FUL /* sub-register 0x08 is the External clock offset to first path 1 GHz counter, EC_GOLP */
aungriah	0:a3b83d366423	650	#define EC_GOLP_OFFSET_EXT_MASK 0x0000003FUL /* This register contains the 1 GHz count from the arrival of the RMARKER and the next edge of the external clock. */
aungriah	0:a3b83d366423	651
aungriah	0:a3b83d366423	652
aungriah	0:a3b83d366423	653	/**************************************************************************//
aungriah	0:a3b83d366423	654	* @brief Bit definitions for register ACC_MEM
aungriah	0:a3b83d366423	655	**/
aungriah	0:a3b83d366423	656	#define ACC_MEM_ID 0x25 /* Read access to accumulator data */
aungriah	0:a3b83d366423	657	#define ACC_MEM_LEN (4064)
aungriah	0:a3b83d366423	658
aungriah	0:a3b83d366423	659
aungriah	0:a3b83d366423	660	/**************************************************************************//
aungriah	0:a3b83d366423	661	* @brief Bit definitions for register GPIO_CTRL
aungriah	0:a3b83d366423	662	**/
aungriah	0:a3b83d366423	663	#define GPIO_CTRL_ID 0x26 /* Peripheral register bus 1 access - GPIO control */
aungriah	0:a3b83d366423	664	#define GPIO_CTRL_LEN (44)
aungriah	0:a3b83d366423	665
aungriah	0:a3b83d366423	666	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	667	#define GPIO_MODE_OFFSET 0x00 /* sub-register 0x00 is the GPIO Mode Control Register */
aungriah	0:a3b83d366423	668	#define GPIO_MODE_LEN (4)
aungriah	0:a3b83d366423	669	#define GPIO_MODE_MASK 0x00FFFFC0UL
aungriah	0:a3b83d366423	670
aungriah	0:a3b83d366423	671	#define GPIO_MSGP0_MASK 0x000000C0UL /* Mode Selection for GPIO0/RXOKLED */
aungriah	0:a3b83d366423	672	#define GPIO_MSGP1_MASK 0x00000300UL /* Mode Selection for GPIO1/SFDLED */
aungriah	0:a3b83d366423	673	#define GPIO_MSGP2_MASK 0x00000C00UL /* Mode Selection for GPIO2/RXLED */
aungriah	0:a3b83d366423	674	#define GPIO_MSGP3_MASK 0x00003000UL /* Mode Selection for GPIO3/TXLED */
aungriah	0:a3b83d366423	675	#define GPIO_MSGP4_MASK 0x0000C000UL /* Mode Selection for GPIO4/EXTPA */
aungriah	0:a3b83d366423	676	#define GPIO_MSGP5_MASK 0x00030000UL /* Mode Selection for GPIO5/EXTTXE */
aungriah	0:a3b83d366423	677	#define GPIO_MSGP6_MASK 0x000C0000UL /* Mode Selection for GPIO6/EXTRXE */
aungriah	0:a3b83d366423	678	#define GPIO_MSGP7_MASK 0x00300000UL /* Mode Selection for SYNC/GPIO7 */
aungriah	0:a3b83d366423	679	#define GPIO_MSGP8_MASK 0x00C00000UL /* Mode Selection for IRQ/GPIO8 */
aungriah	0:a3b83d366423	680
aungriah	0:a3b83d366423	681	#define GPIO_PIN2_RXLED 0x00000400UL /* The pin operates as the RXLED output */
aungriah	0:a3b83d366423	682	#define GPIO_PIN3_TXLED 0x00001000UL /* The pin operates as the TXLED output */
aungriah	0:a3b83d366423	683	#define GPIO_PIN4_EXTPA 0x00004000UL /* The pin operates as the EXTPA output */
aungriah	0:a3b83d366423	684	#define GPIO_PIN5_EXTTXE 0x00010000UL /* The pin operates as the EXTTXE output */
aungriah	0:a3b83d366423	685	#define GPIO_PIN6_EXTRXE 0x00040000UL /* The pin operates as the EXTRXE output */
aungriah	0:a3b83d366423	686
aungriah	0:a3b83d366423	687	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	688	#define GPIO_DIR_OFFSET 0x08 /* sub-register 0x08 is the GPIO Direction Control Register */
aungriah	0:a3b83d366423	689	#define GPIO_DIR_LEN (3)
aungriah	0:a3b83d366423	690	#define GPIO_DIR_MASK 0x0011FFFFUL
aungriah	0:a3b83d366423	691
aungriah	0:a3b83d366423	692	#define GxP0 0x00000001UL /* GPIO0 Only changed if the GxM0 mask bit has a value of 1 for the write operation*/
aungriah	0:a3b83d366423	693	#define GxP1 0x00000002UL /* GPIO1. (See GDP0). */
aungriah	0:a3b83d366423	694	#define GxP2 0x00000004UL /* GPIO2. (See GDP0). */
aungriah	0:a3b83d366423	695	#define GxP3 0x00000008UL /* GPIO3. (See GDP0). */
aungriah	0:a3b83d366423	696	#define GxP4 0x00000100UL /* GPIO4. (See GDP0). */
aungriah	0:a3b83d366423	697	#define GxP5 0x00000200UL /* GPIO5. (See GDP0). */
aungriah	0:a3b83d366423	698	#define GxP6 0x00000400UL /* GPIO6. (See GDP0). */
aungriah	0:a3b83d366423	699	#define GxP7 0x00000800UL /* GPIO7. (See GDP0). */
aungriah	0:a3b83d366423	700	#define GxP8 0x00010000UL /* GPIO8 */
aungriah	0:a3b83d366423	701
aungriah	0:a3b83d366423	702	#define GxM0 0x00000010UL /* Mask for GPIO0 */
aungriah	0:a3b83d366423	703	#define GxM1 0x00000020UL /* Mask for GPIO1. (See GDM0). */
aungriah	0:a3b83d366423	704	#define GxM2 0x00000040UL /* Mask for GPIO2. (See GDM0). */
aungriah	0:a3b83d366423	705	#define GxM3 0x00000080UL /* Mask for GPIO3. (See GDM0). */
aungriah	0:a3b83d366423	706	#define GxM4 0x00001000UL /* Mask for GPIO4. (See GDM0). */
aungriah	0:a3b83d366423	707	#define GxM5 0x00002000UL /* Mask for GPIO5. (See GDM0). */
aungriah	0:a3b83d366423	708	#define GxM6 0x00004000UL /* Mask for GPIO6. (See GDM0). */
aungriah	0:a3b83d366423	709	#define GxM7 0x00008000UL /* Mask for GPIO7. (See GDM0). */
aungriah	0:a3b83d366423	710	#define GxM8 0x00100000UL /* Mask for GPIO8. (See GDM0). */
aungriah	0:a3b83d366423	711
aungriah	0:a3b83d366423	712	#define GDP0 GxP0 /* Direction Selection for GPIO0. 1 = input, 0 = output. Only changed if the GDM0 mask bit has a value of 1 for the write operation*/
aungriah	0:a3b83d366423	713	#define GDP1 GxP1 /* Direction Selection for GPIO1. (See GDP0). */
aungriah	0:a3b83d366423	714	#define GDP2 GxP2 /* Direction Selection for GPIO2. (See GDP0). */
aungriah	0:a3b83d366423	715	#define GDP3 GxP3 /* Direction Selection for GPIO3. (See GDP0). */
aungriah	0:a3b83d366423	716	#define GDP4 GxP4 /* Direction Selection for GPIO4. (See GDP0). */
aungriah	0:a3b83d366423	717	#define GDP5 GxP5 /* Direction Selection for GPIO5. (See GDP0). */
aungriah	0:a3b83d366423	718	#define GDP6 GxP6 /* Direction Selection for GPIO6. (See GDP0). */
aungriah	0:a3b83d366423	719	#define GDP7 GxP7 /* Direction Selection for GPIO7. (See GDP0). */
aungriah	0:a3b83d366423	720	#define GDP8 GxP8 /* Direction Selection for GPIO8 */
aungriah	0:a3b83d366423	721
aungriah	0:a3b83d366423	722	#define GDM0 GxM0 /* Mask for setting the direction of GPIO0 */
aungriah	0:a3b83d366423	723	#define GDM1 GxM1 /* Mask for setting the direction of GPIO1. (See GDM0). */
aungriah	0:a3b83d366423	724	#define GDM2 GxM2 /* Mask for setting the direction of GPIO2. (See GDM0). */
aungriah	0:a3b83d366423	725	#define GDM3 GxM3 /* Mask for setting the direction of GPIO3. (See GDM0). */
aungriah	0:a3b83d366423	726	#define GDM4 GxM4 /* Mask for setting the direction of GPIO4. (See GDM0). */
aungriah	0:a3b83d366423	727	#define GDM5 GxM5 /* Mask for setting the direction of GPIO5. (See GDM0). */
aungriah	0:a3b83d366423	728	#define GDM6 GxM6 /* Mask for setting the direction of GPIO6. (See GDM0). */
aungriah	0:a3b83d366423	729	#define GDM7 GxM7 /* Mask for setting the direction of GPIO7. (See GDM0). */
aungriah	0:a3b83d366423	730	#define GDM8 GxM8 /* Mask for setting the direction of GPIO8. (See GDM0). */
aungriah	0:a3b83d366423	731
aungriah	0:a3b83d366423	732	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	733	#define GPIO_DOUT_OFFSET 0x0C /* sub-register 0x0C is the GPIO data output register. */
aungriah	0:a3b83d366423	734	#define GPIO_DOUT_LEN (3)
aungriah	0:a3b83d366423	735	#define GPIO_DOUT_MASK GPIO_DIR_MASK
aungriah	0:a3b83d366423	736
aungriah	0:a3b83d366423	737	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	738	#define GPIO_IRQE_OFFSET 0x10 /* sub-register 0x10 is the GPIO interrupt enable register */
aungriah	0:a3b83d366423	739	#define GPIO_IRQE_LEN (4)
aungriah	0:a3b83d366423	740	#define GPIO_IRQE_MASK 0x000001FFUL
aungriah	0:a3b83d366423	741	#define GIRQx0 0x00000001UL /* IRQ bit0 */
aungriah	0:a3b83d366423	742	#define GIRQx1 0x00000002UL /* IRQ bit1 */
aungriah	0:a3b83d366423	743	#define GIRQx2 0x00000004UL /* IRQ bit2 */
aungriah	0:a3b83d366423	744	#define GIRQx3 0x00000008UL /* IRQ bit3 */
aungriah	0:a3b83d366423	745	#define GIRQx4 0x00000010UL /* IRQ bit4 */
aungriah	0:a3b83d366423	746	#define GIRQx5 0x00000020UL /* IRQ bit5 */
aungriah	0:a3b83d366423	747	#define GIRQx6 0x00000040UL /* IRQ bit6 */
aungriah	0:a3b83d366423	748	#define GIRQx7 0x00000080UL /* IRQ bit7 */
aungriah	0:a3b83d366423	749	#define GIRQx8 0x00000100UL /* IRQ bit8 */
aungriah	0:a3b83d366423	750	#define GIRQE0 GIRQx0 /* GPIO IRQ Enable for GPIO0 input. Value 1 = enable, 0 = disable*/
aungriah	0:a3b83d366423	751	#define GIRQE1 GIRQx1 /* */
aungriah	0:a3b83d366423	752	#define GIRQE2 GIRQx2 /* */
aungriah	0:a3b83d366423	753	#define GIRQE3 GIRQx3 /* */
aungriah	0:a3b83d366423	754	#define GIRQE4 GIRQx4 /* */
aungriah	0:a3b83d366423	755	#define GIRQE5 GIRQx5 /* */
aungriah	0:a3b83d366423	756	#define GIRQE6 GIRQx6 /* */
aungriah	0:a3b83d366423	757	#define GIRQE7 GIRQx7 /* */
aungriah	0:a3b83d366423	758	#define GIRQE8 GIRQx8 /* Value 1 = enable, 0 = disable */
aungriah	0:a3b83d366423	759
aungriah	0:a3b83d366423	760	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	761	#define GPIO_ISEN_OFFSET 0x14 /* sub-register 0x14 is the GPIO interrupt sense selection register */
aungriah	0:a3b83d366423	762	#define GPIO_ISEN_LEN (4)
aungriah	0:a3b83d366423	763	#define GPIO_ISEN_MASK GPIO_IRQE_MASK
aungriah	0:a3b83d366423	764	#define GISEN0 GIRQx0 /* GPIO IRQ Sense selection GPIO0 input. Value 0 = High or Rising-Edge, 1 = Low or falling-edge.*/
aungriah	0:a3b83d366423	765	#define GISEN1 GIRQx1 /* */
aungriah	0:a3b83d366423	766	#define GISEN2 GIRQx2 /* */
aungriah	0:a3b83d366423	767	#define GISEN3 GIRQx3 /* */
aungriah	0:a3b83d366423	768	#define GISEN4 GIRQx4 /* */
aungriah	0:a3b83d366423	769	#define GISEN5 GIRQx5 /* */
aungriah	0:a3b83d366423	770	#define GISEN6 GIRQx6 /* */
aungriah	0:a3b83d366423	771	#define GISEN7 GIRQx7 /* */
aungriah	0:a3b83d366423	772	#define GISEN8 GIRQx8 /* Value 0 = High or Rising-Edge, 1 = Low or falling-edge */
aungriah	0:a3b83d366423	773
aungriah	0:a3b83d366423	774	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	775	#define GPIO_IMODE_OFFSET 0x18 /* sub-register 0x18 is the GPIO interrupt mode selection register */
aungriah	0:a3b83d366423	776	#define GPIO_IMODE_LEN (4)
aungriah	0:a3b83d366423	777	#define GPIO_IMODE_MASK GPIO_IRQE_MASK
aungriah	0:a3b83d366423	778	#define GIMOD0 GIRQx0 /* GPIO IRQ Mode selection for GPIO0 input. Value 0 = Level sensitive interrupt. Value 1 = Edge triggered interrupt */
aungriah	0:a3b83d366423	779	#define GIMOD1 GIRQx1 /* */
aungriah	0:a3b83d366423	780	#define GIMOD2 GIRQx2 /* */
aungriah	0:a3b83d366423	781	#define GIMOD3 GIRQx3 /* */
aungriah	0:a3b83d366423	782	#define GIMOD4 GIRQx4 /* */
aungriah	0:a3b83d366423	783	#define GIMOD5 GIRQx5 /* */
aungriah	0:a3b83d366423	784	#define GIMOD6 GIRQx6 /* */
aungriah	0:a3b83d366423	785	#define GIMOD7 GIRQx7 /* */
aungriah	0:a3b83d366423	786	#define GIMOD8 GIRQx8 /* Value 0 = Level, 1 = Edge. */
aungriah	0:a3b83d366423	787
aungriah	0:a3b83d366423	788	/* offset from EXT_SYNC_ID in bytes */
aungriah	0:a3b83d366423	789	#define GPIO_IBES_OFFSET 0x1C /* sub-register 0x1C is the GPIO interrupt Both Edge selection register */
aungriah	0:a3b83d366423	790	#define GPIO_IBES_LEN (4)
aungriah	0:a3b83d366423	791	#define GPIO_IBES_MASK GPIO_IRQE_MASK /* */
aungriah	0:a3b83d366423	792	#define GIBES0 GIRQx0 /* GPIO IRQ Both Edge selection for GPIO0 input. Value 0 = GPIO_IMODE register selects the edge. Value 1 = Both edges trigger the interrupt. */
aungriah	0:a3b83d366423	793	#define GIBES1 GIRQx1 /* */
aungriah	0:a3b83d366423	794	#define GIBES2 GIRQx2 /* */
aungriah	0:a3b83d366423	795	#define GIBES3 GIRQx3 /* */
aungriah	0:a3b83d366423	796	#define GIBES4 GIRQx4 /* */
aungriah	0:a3b83d366423	797	#define GIBES5 GIRQx5 /* */
aungriah	0:a3b83d366423	798	#define GIBES6 GIRQx6 /* */
aungriah	0:a3b83d366423	799	#define GIBES7 GIRQx7 /* */
aungriah	0:a3b83d366423	800	#define GIBES8 GIRQx8 /* Value 0 = use GPIO_IMODE, 1 = Both Edges */
aungriah	0:a3b83d366423	801
aungriah	0:a3b83d366423	802	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	803	#define GPIO_ICLR_OFFSET 0x20 /* sub-register 0x20 is the GPIO interrupt clear register */
aungriah	0:a3b83d366423	804	#define GPIO_ICLR_LEN (4)
aungriah	0:a3b83d366423	805	#define GPIO_ICLR_MASK GPIO_IRQE_MASK /* */
aungriah	0:a3b83d366423	806	#define GICLR0 GIRQx0 /* GPIO IRQ latch clear for GPIO0 input. Write 1 to clear the GPIO0 interrupt latch. Writing 0 has no effect. Reading returns zero */
aungriah	0:a3b83d366423	807	#define GICLR1 GIRQx1 /* */
aungriah	0:a3b83d366423	808	#define GICLR2 GIRQx2 /* */
aungriah	0:a3b83d366423	809	#define GICLR3 GIRQx3 /* */
aungriah	0:a3b83d366423	810	#define GICLR4 GIRQx4 /* */
aungriah	0:a3b83d366423	811	#define GICLR5 GIRQx5 /* */
aungriah	0:a3b83d366423	812	#define GICLR6 GIRQx6 /* */
aungriah	0:a3b83d366423	813	#define GICLR7 GIRQx7 /* */
aungriah	0:a3b83d366423	814	#define GICLR8 GIRQx8 /* Write 1 to clear the interrupt latch */
aungriah	0:a3b83d366423	815
aungriah	0:a3b83d366423	816	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	817	#define GPIO_IDBE_OFFSET 0x24 /* sub-register 0x24 is the GPIO interrupt de-bounce enable register */
aungriah	0:a3b83d366423	818	#define GPIO_IDBE_LEN (4)
aungriah	0:a3b83d366423	819	#define GPIO_IDBE_MASK GPIO_IRQE_MASK
aungriah	0:a3b83d366423	820	#define GIDBE0 GIRQx0 /* GPIO IRQ de-bounce enable for GPIO0. Value 1 = de-bounce enabled. Value 0 = de-bounce disabled */
aungriah	0:a3b83d366423	821	#define GIDBE1 GIRQx1 /* */
aungriah	0:a3b83d366423	822	#define GIDBE2 GIRQx2 /* */
aungriah	0:a3b83d366423	823	#define GIDBE3 GIRQx3 /* */
aungriah	0:a3b83d366423	824	#define GIDBE4 GIRQx4 /* */
aungriah	0:a3b83d366423	825	#define GIDBE5 GIRQx5 /* */
aungriah	0:a3b83d366423	826	#define GIDBE6 GIRQx6 /* */
aungriah	0:a3b83d366423	827	#define GIDBE7 GIRQx7 /* */
aungriah	0:a3b83d366423	828	#define GIDBE8 GIRQx8 /* Value 1 = de-bounce enabled, 0 = de-bounce disabled */
aungriah	0:a3b83d366423	829
aungriah	0:a3b83d366423	830	/* offset from GPIO_CTRL in bytes */
aungriah	0:a3b83d366423	831	#define GPIO_RAW_OFFSET 0x28 /* sub-register 0x28 allows the raw state of the GPIO pin to be read. */
aungriah	0:a3b83d366423	832	#define GPIO_RAW_LEN (4)
aungriah	0:a3b83d366423	833	#define GPIO_RAW_MASK GPIO_IRQE_MASK
aungriah	0:a3b83d366423	834	#define GRAWP0 GIRQx0 /* This bit reflects the raw state of GPIO0 */
aungriah	0:a3b83d366423	835	#define GRAWP1 GIRQx1 /* */
aungriah	0:a3b83d366423	836	#define GRAWP2 GIRQx2 /* */
aungriah	0:a3b83d366423	837	#define GRAWP3 GIRQx3 /* */
aungriah	0:a3b83d366423	838	#define GRAWP4 GIRQx4 /* */
aungriah	0:a3b83d366423	839	#define GRAWP5 GIRQx5 /* */
aungriah	0:a3b83d366423	840	#define GRAWP6 GIRQx6 /* */
aungriah	0:a3b83d366423	841	#define GRAWP7 GIRQx7 /* */
aungriah	0:a3b83d366423	842	#define GRAWP8 GIRQx8 /* This bit reflects the raw state of GPIO8 */
aungriah	0:a3b83d366423	843
aungriah	0:a3b83d366423	844	/**************************************************************************//
aungriah	0:a3b83d366423	845	* @brief Bit definitions for register DRX_CONF
aungriah	0:a3b83d366423	846	* Digital Receiver configuration block
aungriah	0:a3b83d366423	847	**/
aungriah	0:a3b83d366423	848	#define DRX_CONF_ID 0x27 /* Digital Receiver configuration */
aungriah	0:a3b83d366423	849	#define DRX_CONF_LEN (44)
aungriah	0:a3b83d366423	850	/* offset from DRX_CONF_ID in bytes */
aungriah	0:a3b83d366423	851	#define DRX_TUNE0b_OFFSET (0x02) /* sub-register 0x02 is a 16-bit tuning register. */
aungriah	0:a3b83d366423	852	#define DRX_TUNE0b_LEN (2)
aungriah	0:a3b83d366423	853	#define DRX_TUNE0b_MASK 0xFFFF /* 7.2.40.2 Sub-Register 0x27:02 DRX_TUNE0b */
aungriah	0:a3b83d366423	854	#define DRX_TUNE0b_110K_STD 0x000A
aungriah	0:a3b83d366423	855	#define DRX_TUNE0b_110K_NSTD 0x0016
aungriah	0:a3b83d366423	856	#define DRX_TUNE0b_850K_STD 0x0001
aungriah	0:a3b83d366423	857	#define DRX_TUNE0b_850K_NSTD 0x0006
aungriah	0:a3b83d366423	858	#define DRX_TUNE0b_6M8_STD 0x0001
aungriah	0:a3b83d366423	859	#define DRX_TUNE0b_6M8_NSTD 0x0002
aungriah	0:a3b83d366423	860
aungriah	0:a3b83d366423	861	/* offset from DRX_CONF_ID in bytes */
aungriah	0:a3b83d366423	862	#define DRX_TUNE1a_OFFSET 0x04 /* 7.2.40.3 Sub-Register 0x27:04 DRX_TUNE1a */
aungriah	0:a3b83d366423	863	#define DRX_TUNE1a_LEN (2)
aungriah	0:a3b83d366423	864	#define DRX_TUNE1a_MASK 0xFFFF
aungriah	0:a3b83d366423	865	#define DRX_TUNE1a_PRF16 0x0087
aungriah	0:a3b83d366423	866	#define DRX_TUNE1a_PRF64 0x008D
aungriah	0:a3b83d366423	867
aungriah	0:a3b83d366423	868	/* offset from DRX_CONF_ID in bytes */
aungriah	0:a3b83d366423	869	#define DRX_TUNE1b_OFFSET 0x06 /* 7.2.40.4 Sub-Register 0x27:06 DRX_TUNE1b */
aungriah	0:a3b83d366423	870	#define DRX_TUNE1b_LEN (2)
aungriah	0:a3b83d366423	871	#define DRX_TUNE1b_MASK 0xFFFF
aungriah	0:a3b83d366423	872	#define DRX_TUNE1b_110K 0x0064
aungriah	0:a3b83d366423	873	#define DRX_TUNE1b_850K_6M8 0x0020
aungriah	0:a3b83d366423	874	#define DRX_TUNE1b_6M8_PRE64 0x0010
aungriah	0:a3b83d366423	875
aungriah	0:a3b83d366423	876	/* offset from DRX_CONF_ID in bytes */
aungriah	0:a3b83d366423	877	#define DRX_TUNE2_OFFSET 0x08 /* 7.2.40.5 Sub-Register 0x27:08 DRX_TUNE2 */
aungriah	0:a3b83d366423	878	#define DRX_TUNE2_LEN (4)
aungriah	0:a3b83d366423	879	#define DRX_TUNE2_MASK 0xFFFFFFFFUL
aungriah	0:a3b83d366423	880	#define DRX_TUNE2_PRF16_PAC8 0x311A002DUL
aungriah	0:a3b83d366423	881	#define DRX_TUNE2_PRF16_PAC16 0x331A0052UL
aungriah	0:a3b83d366423	882	#define DRX_TUNE2_PRF16_PAC32 0x351A009AUL
aungriah	0:a3b83d366423	883	#define DRX_TUNE2_PRF16_PAC64 0x371A011DUL
aungriah	0:a3b83d366423	884	#define DRX_TUNE2_PRF64_PAC8 0x313B006BUL
aungriah	0:a3b83d366423	885	#define DRX_TUNE2_PRF64_PAC16 0x333B00BEUL
aungriah	0:a3b83d366423	886	#define DRX_TUNE2_PRF64_PAC32 0x353B015EUL
aungriah	0:a3b83d366423	887	#define DRX_TUNE2_PRF64_PAC64 0x373B0296UL
aungriah	0:a3b83d366423	888
aungriah	0:a3b83d366423	889	/* offset from DRX_CONF_ID in bytes */
aungriah	0:a3b83d366423	890	/* WARNING: Please do NOT set DRX_SFDTOC to zero (disabling SFD detection timeout)
aungriah	0:a3b83d366423	891	* since this risks IC malfunction due to prolonged receiver activity in the event of false preamble detection.
aungriah	0:a3b83d366423	892	*/
aungriah	0:a3b83d366423	893	#define DRX_SFDTOC_OFFSET 0x20 /* 7.2.40.7 Sub-Register 0x27:20 DRX_SFDTOC */
aungriah	0:a3b83d366423	894	#define DRX_SFDTOC_LEN (2)
aungriah	0:a3b83d366423	895	#define DRX_SFDTOC_MASK 0xFFFF
aungriah	0:a3b83d366423	896
aungriah	0:a3b83d366423	897	/* offset from DRX_CONF_ID in bytes */
aungriah	0:a3b83d366423	898	#define DRX_PRETOC_OFFSET 0x24 /* 7.2.40.9 Sub-Register 0x27:24 DRX_PRETOC */
aungriah	0:a3b83d366423	899	#define DRX_PRETOC_LEN (2)
aungriah	0:a3b83d366423	900	#define DRX_PRETOC_MASK 0xFFFF
aungriah	0:a3b83d366423	901
aungriah	0:a3b83d366423	902	/* offset from DRX_CONF_ID in bytes */
aungriah	0:a3b83d366423	903	#define DRX_TUNE4H_OFFSET 0x26 /* 7.2.40.10 Sub-Register 0x27:26 DRX_TUNE4H */
aungriah	0:a3b83d366423	904	#define DRX_TUNE4H_LEN (2)
aungriah	0:a3b83d366423	905	#define DRX_TUNE4H_MASK 0xFFFF
aungriah	0:a3b83d366423	906	#define DRX_TUNE4H_PRE64 0x0010
aungriah	0:a3b83d366423	907	#define DRX_TUNE4H_PRE128PLUS 0x0028
aungriah	0:a3b83d366423	908
aungriah	0:a3b83d366423	909
aungriah	0:a3b83d366423	910	/**************************************************************************//
aungriah	0:a3b83d366423	911	* @brief Bit definitions for register RF_CONF
aungriah	0:a3b83d366423	912	* Analog RF Configuration block
aungriah	0:a3b83d366423	913	* Refer to section 7.2.41 Register file: 0x28 Analog RF configuration block
aungriah	0:a3b83d366423	914	**/
aungriah	0:a3b83d366423	915	#define RF_CONF_ID 0x28 /* Analog RF Configuration */
aungriah	0:a3b83d366423	916	#define RF_CONF_LEN (58)
aungriah	0:a3b83d366423	917	#define RF_CONF_TXEN_MASK 0x00400000UL /* TX enable */
aungriah	0:a3b83d366423	918	#define RF_CONF_RXEN_MASK 0x00200000UL /* RX enable */
aungriah	0:a3b83d366423	919	#define RF_CONF_TXPOW_MASK 0x001F0000UL /* turn on power all LDOs */
aungriah	0:a3b83d366423	920	#define RF_CONF_PLLEN_MASK 0x0000E000UL /* enable PLLs */
aungriah	0:a3b83d366423	921	#define RF_CONF_TXBLOCKSEN_MASK 0x00001F00UL /* enable TX blocks */
aungriah	0:a3b83d366423	922	#define RF_CONF_TXPLLPOWEN_MASK (RF_CONF_PLLEN_MASK \| RF_CONF_TXPOW_MASK)
aungriah	0:a3b83d366423	923	#define RF_CONF_TXALLEN_MASK (RF_CONF_TXEN_MASK \| RF_CONF_TXPOW_MASK \| RF_CONF_PLLEN_MASK \| RF_CONF_TXBLOCKSEN_MASK)
aungriah	0:a3b83d366423	924	/* offset from TX_CAL_ID in bytes */
aungriah	0:a3b83d366423	925	#define RF_RXCTRLH_OFFSET 0x0B /* Analog RX Control Register */
aungriah	0:a3b83d366423	926	#define RF_RXCTRLH_LEN (1)
aungriah	0:a3b83d366423	927	#define RF_RXCTRLH_NBW 0xD8 /* RXCTRLH value for narrow bandwidth channels */
aungriah	0:a3b83d366423	928	#define RF_RXCTRLH_WBW 0xBC /* RXCTRLH value for wide bandwidth channels */
aungriah	0:a3b83d366423	929	/* offset from TX_CAL_ID in bytes */
aungriah	0:a3b83d366423	930	#define RF_TXCTRL_OFFSET 0x0C /* Analog TX Control Register */
aungriah	0:a3b83d366423	931	#define RF_TXCTRL_LEN (4)
aungriah	0:a3b83d366423	932	#define RF_TXCTRL_TXMTUNE_MASK 0x000001E0UL /* Transmit mixer tuning register */
aungriah	0:a3b83d366423	933	#define RF_TXCTRL_TXTXMQ_MASK 0x00000E00UL /* Transmit mixer Q-factor tuning register */
aungriah	0:a3b83d366423	934	#define RF_TXCTRL_CH1 0x00005C40UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
aungriah	0:a3b83d366423	935	#define RF_TXCTRL_CH2 0x00045CA0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
aungriah	0:a3b83d366423	936	#define RF_TXCTRL_CH3 0x00086CC0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
aungriah	0:a3b83d366423	937	#define RF_TXCTRL_CH4 0x00045C80UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
aungriah	0:a3b83d366423	938	#define RF_TXCTRL_CH5 0x001E3FE0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
aungriah	0:a3b83d366423	939	#define RF_TXCTRL_CH7 0x001E7DE0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
aungriah	0:a3b83d366423	940
aungriah	0:a3b83d366423	941	/* offset from TX_CAL_ID in bytes */
aungriah	0:a3b83d366423	942	#define RF_STATUS_OFFSET 0x2C
aungriah	0:a3b83d366423	943
aungriah	0:a3b83d366423	944	/**************************************************************************//
aungriah	0:a3b83d366423	945	* @brief Bit definitions for register
aungriah	0:a3b83d366423	946	**/
aungriah	0:a3b83d366423	947	#define REG_29_ID_RESERVED 0x29
aungriah	0:a3b83d366423	948
aungriah	0:a3b83d366423	949	/**************************************************************************//
aungriah	0:a3b83d366423	950	* @brief Bit definitions for register TX_CAL
aungriah	0:a3b83d366423	951	* Refer to section 7.2.43 Register file: 0x2A Transmitter Calibration block
aungriah	0:a3b83d366423	952	**/
aungriah	0:a3b83d366423	953	#define TX_CAL_ID 0x2A /* Transmitter calibration block */
aungriah	0:a3b83d366423	954	#define TX_CAL_LEN (52)
aungriah	0:a3b83d366423	955	/* offset from TX_CAL_ID in bytes */
aungriah	0:a3b83d366423	956	#define TC_SARL_SAR_C (0) /* SAR control */
aungriah	0:a3b83d366423	957	/cause bug in register block TX_CAL, we need to read 1 byte in a time/
aungriah	0:a3b83d366423	958	#define TC_SARL_SAR_LVBAT_OFFSET (3) /* Latest SAR reading for Voltage level */
aungriah	0:a3b83d366423	959	#define TC_SARL_SAR_LTEMP_OFFSET (4) /* Latest SAR reading for Temperature level */
aungriah	0:a3b83d366423	960	#define TC_SARW_SAR_WTEMP_OFFSET 0x06 /* SAR reading of Temperature level taken at last wakeup event */
aungriah	0:a3b83d366423	961	#define TC_SARW_SAR_WVBAT_OFFSET 0x07 /* SAR reading of Voltage level taken at last wakeup event */
aungriah	0:a3b83d366423	962	/* offset from TX_CAL_ID in bytes */
aungriah	0:a3b83d366423	963	#define TC_PGDELAY_OFFSET 0x0B /* Transmitter Calibration Pulse Generator Delay */
aungriah	0:a3b83d366423	964	#define TC_PGDELAY_LEN (1)
aungriah	0:a3b83d366423	965	#define TC_PGDELAY_CH1 0xC9 /* Recommended value for channel 1 */
aungriah	0:a3b83d366423	966	#define TC_PGDELAY_CH2 0xC2 /* Recommended value for channel 2 */
aungriah	0:a3b83d366423	967	#define TC_PGDELAY_CH3 0xC5 /* Recommended value for channel 3 */
aungriah	0:a3b83d366423	968	#define TC_PGDELAY_CH4 0x95 /* Recommended value for channel 4 */
aungriah	0:a3b83d366423	969	#define TC_PGDELAY_CH5 0xC0 /* Recommended value for channel 5 */
aungriah	0:a3b83d366423	970	#define TC_PGDELAY_CH7 0x93 /* Recommended value for channel 7 */
aungriah	0:a3b83d366423	971	/* offset from TX_CAL_ID in bytes */
aungriah	0:a3b83d366423	972	#define TC_PGTEST_OFFSET 0x0C /* Transmitter Calibration Pulse Generator Test */
aungriah	0:a3b83d366423	973	#define TC_PGTEST_LEN (1)
aungriah	0:a3b83d366423	974	#define TC_PGTEST_NORMAL 0x00 /* Normal operation */
aungriah	0:a3b83d366423	975	#define TC_PGTEST_CW 0x13 /* Continuous Wave (CW) Test Mode */
aungriah	0:a3b83d366423	976
aungriah	0:a3b83d366423	977	/**************************************************************************//
aungriah	0:a3b83d366423	978	* @brief Bit definitions for register
aungriah	0:a3b83d366423	979	* Refer to section 7.2.44 Register file: 0x2B Frequency synthesiser control block
aungriah	0:a3b83d366423	980	**/
aungriah	0:a3b83d366423	981	#define FS_CTRL_ID 0x2B /* Frequency synthesiser control block */
aungriah	0:a3b83d366423	982	#define FS_CTRL_LEN (21)
aungriah	0:a3b83d366423	983	/* offset from FS_CTRL_ID in bytes */
aungriah	0:a3b83d366423	984	#define FS_RES1_OFFSET 0x00 /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */
aungriah	0:a3b83d366423	985	#define FS_RES1_LEN (7)
aungriah	0:a3b83d366423	986	/* offset from FS_CTRL_ID in bytes */
aungriah	0:a3b83d366423	987	#define FS_PLLCFG_OFFSET 0x07 /* Frequency synthesiser PLL configuration */
aungriah	0:a3b83d366423	988	#define FS_PLLCFG_LEN (5)
aungriah	0:a3b83d366423	989	#define FS_PLLCFG_CH1 0x09000407UL /* Operating Channel 1 */
aungriah	0:a3b83d366423	990	#define FS_PLLCFG_CH2 0x08400508UL /* Operating Channel 2 */
aungriah	0:a3b83d366423	991	#define FS_PLLCFG_CH3 0x08401009UL /* Operating Channel 3 */
aungriah	0:a3b83d366423	992	#define FS_PLLCFG_CH4 FS_PLLCFG_CH2 /* Operating Channel 4 (same as 2) */
aungriah	0:a3b83d366423	993	#define FS_PLLCFG_CH5 0x0800041DUL /* Operating Channel 5 */
aungriah	0:a3b83d366423	994	#define FS_PLLCFG_CH7 FS_PLLCFG_CH5 /* Operating Channel 7 (same as 5) */
aungriah	0:a3b83d366423	995	/* offset from FS_CTRL_ID in bytes */
aungriah	0:a3b83d366423	996	#define FS_PLLTUNE_OFFSET 0x0B /* Frequency synthesiser PLL Tuning */
aungriah	0:a3b83d366423	997	#define FS_PLLTUNE_LEN (1)
aungriah	0:a3b83d366423	998	#define FS_PLLTUNE_CH1 0x1E /* Operating Channel 1 */
aungriah	0:a3b83d366423	999	#define FS_PLLTUNE_CH2 0x26 /* Operating Channel 2 */
aungriah	0:a3b83d366423	1000	#define FS_PLLTUNE_CH3 0x56 /* Operating Channel 3 */
aungriah	0:a3b83d366423	1001	#define FS_PLLTUNE_CH4 FS_PLLTUNE_CH2 /* Operating Channel 4 (same as 2) */
aungriah	0:a3b83d366423	1002	#define FS_PLLTUNE_CH5 0xBE /* Operating Channel 5 */
aungriah	0:a3b83d366423	1003	#define FS_PLLTUNE_CH7 FS_PLLTUNE_CH5 /* Operating Channel 7 (same as 5) */
aungriah	0:a3b83d366423	1004	/* offset from FS_CTRL_ID in bytes */
aungriah	0:a3b83d366423	1005	#define FS_RES2_OFFSET 0x0C /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */
aungriah	0:a3b83d366423	1006	#define FS_RES2_LEN (2)
aungriah	0:a3b83d366423	1007	/* offset from FS_CTRL_ID in bytes */
aungriah	0:a3b83d366423	1008	#define FS_XTALT_OFFSET 0x0E /* Frequency synthesiser Crystal trim */
aungriah	0:a3b83d366423	1009	#define FS_XTALT_LEN (1)
aungriah	0:a3b83d366423	1010	#define FS_XTALT_MASK 0x1F /* Crystal Trim. Crystals may be trimmed using this register setting to tune out errors, see 8.1 IC Calibration Crystal Oscillator Trim. */
aungriah	0:a3b83d366423	1011	#define FS_XTALT_MIDRANGE 0x10
aungriah	0:a3b83d366423	1012	/* offset from FS_CTRL_ID in bytes */
aungriah	0:a3b83d366423	1013	#define FS_RES3_OFFSET 0x0F /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */
aungriah	0:a3b83d366423	1014	#define FS_RES3_LEN (6)
aungriah	0:a3b83d366423	1015
aungriah	0:a3b83d366423	1016	/**************************************************************************//
aungriah	0:a3b83d366423	1017	* @brief Bit definitions for register
aungriah	0:a3b83d366423	1018	**/
aungriah	0:a3b83d366423	1019	#define AON_ID 0x2C /* Always-On register set */
aungriah	0:a3b83d366423	1020	#define AON_LEN (12)
aungriah	0:a3b83d366423	1021	/* offset from AON_ID in bytes */
aungriah	0:a3b83d366423	1022	#define AON_WCFG_OFFSET 0x00 /* used to control what the DW1000 IC does as it wakes up from low-power SLEEP or DEEPSLEEPstates. */
aungriah	0:a3b83d366423	1023	#define AON_WCFG_LEN (2)
aungriah	0:a3b83d366423	1024	#define AON_WCFG_MASK 0x09CB /* access mask to AON_WCFG register*/
aungriah	0:a3b83d366423	1025	#define AON_WCFG_ONW_RADC 0x0001 /* On Wake-up Run the (temperature and voltage) Analog-to-Digital Convertors */
aungriah	0:a3b83d366423	1026	#define AON_WCFG_ONW_RX 0x0002 /* On Wake-up turn on the Receiver */
aungriah	0:a3b83d366423	1027	#define AON_WCFG_ONW_LEUI 0x0008 /* On Wake-up load the EUI from OTP memory into Register file: 0x01 Extended Unique Identifier. */
aungriah	0:a3b83d366423	1028	#define AON_WCFG_ONW_LDC 0x0040 /* On Wake-up load configurations from the AON memory into the host interface register set */
aungriah	0:a3b83d366423	1029	#define AON_WCFG_ONW_L64P 0x0080 /* On Wake-up load the Length64 receiver operating parameter set */
aungriah	0:a3b83d366423	1030	#define AON_WCFG_PRES_SLEEP 0x0100 /* Preserve Sleep. This bit determines what the DW1000 does with respect to the ARXSLP and ATXSLP sleep controls */
aungriah	0:a3b83d366423	1031	#define AON_WCFG_ONW_LLDE 0x0800 /* On Wake-up load the LDE microcode. */
aungriah	0:a3b83d366423	1032	#define AON_WCFG_ONW_LLDO 0x1000 /* On Wake-up load the LDO tune value. */
aungriah	0:a3b83d366423	1033	/* offset from AON_ID in bytes */
aungriah	0:a3b83d366423	1034	#define AON_CTRL_OFFSET 0x02 /* The bits in this register in general cause direct activity within the AON block with respect to the stored AON memory */
aungriah	0:a3b83d366423	1035	#define AON_CTRL_LEN (1)
aungriah	0:a3b83d366423	1036	#define AON_CTRL_MASK 0x8F /* access mask to AON_CTRL register */
aungriah	0:a3b83d366423	1037	#define AON_CTRL_RESTORE 0x01 /* When this bit is set the DW1000 will copy the user configurations from the AON memory to the host interface register set. */
aungriah	0:a3b83d366423	1038	#define AON_CTRL_SAVE 0x02 /* When this bit is set the DW1000 will copy the user configurations from the host interface register set into the AON memory */
aungriah	0:a3b83d366423	1039	#define AON_CTRL_UPL_CFG 0x04 /* Upload the AON block configurations to the AON */
aungriah	0:a3b83d366423	1040	#define AON_CTRL_DCA_READ 0x08 /* Direct AON memory access read */
aungriah	0:a3b83d366423	1041	#define AON_CTRL_DCA_ENAB 0x80 /* Direct AON memory access enable bit */
aungriah	0:a3b83d366423	1042	/* offset from AON_ID in bytes */
aungriah	0:a3b83d366423	1043	#define AON_RDAT_OFFSET 0x03 /* AON Direct Access Read Data Result */
aungriah	0:a3b83d366423	1044	#define AON_RDAT_LEN (1)
aungriah	0:a3b83d366423	1045	/* offset from AON_ID in bytes */
aungriah	0:a3b83d366423	1046	#define AON_ADDR_OFFSET 0x04 /* AON Direct Access Address */
aungriah	0:a3b83d366423	1047	#define AON_ADDR_LEN (1)
aungriah	0:a3b83d366423	1048	#define AON_ADDR_LPOSC_CAL_0 117 /* Address of low-power oscillator calibration value (lower byte) */
aungriah	0:a3b83d366423	1049	#define AON_ADDR_LPOSC_CAL_1 118 /* Address of low-power oscillator calibration value (lower byte) */
aungriah	0:a3b83d366423	1050
aungriah	0:a3b83d366423	1051	/* offset from AON_ID in bytes */
aungriah	0:a3b83d366423	1052	#define AON_CFG0_OFFSET 0x06 /* 32-bit configuration register for the always on block. */
aungriah	0:a3b83d366423	1053	#define AON_CFG0_LEN (4)
aungriah	0:a3b83d366423	1054	#define AON_CFG0_SLEEP_EN 0x00000001UL /* This is the sleep enable configuration bit */
aungriah	0:a3b83d366423	1055	#define AON_CFG0_WAKE_PIN 0x00000002UL /* Wake using WAKEUP pin */
aungriah	0:a3b83d366423	1056	#define AON_CFG0_WAKE_SPI 0x00000004UL /* Wake using SPI access SPICSn */
aungriah	0:a3b83d366423	1057	#define AON_CFG0_WAKE_CNT 0x00000008UL /* Wake when sleep counter elapses */
aungriah	0:a3b83d366423	1058	#define AON_CFG0_LPDIV_EN 0x00000010UL /* Low power divider enable configuration */
aungriah	0:a3b83d366423	1059	#define AON_CFG0_LPCLKDIVA_MASK 0x0000FFE0UL /* divider count for dividing the raw DW1000 XTAL oscillator frequency to set an LP clock frequency */
aungriah	0:a3b83d366423	1060	#define AON_CFG0_LPCLKDIVA_SHIFT (5)
aungriah	0:a3b83d366423	1061	#define AON_CFG0_SLEEP_TIM 0xFFFF0000UL /* Sleep time. This field configures the sleep time count elapse value */
aungriah	0:a3b83d366423	1062	#define AON_CFG0_SLEEP_SHIFT (16)
aungriah	0:a3b83d366423	1063	#define AON_CFG0_SLEEP_TIM_OFFSET 2 /* In bytes */
aungriah	0:a3b83d366423	1064	/* offset from AON_ID in bytes */
aungriah	0:a3b83d366423	1065	#define AON_CFG1_OFFSET 0x0A
aungriah	0:a3b83d366423	1066	#define AON_CFG1_LEN (2)
aungriah	0:a3b83d366423	1067	#define AON_CFG1_MASK 0x0007 /* aceess mask to AON_CFG1 */
aungriah	0:a3b83d366423	1068	#define AON_CFG1_SLEEP_CEN 0x0001 /* This bit enables the sleep counter */
aungriah	0:a3b83d366423	1069	#define AON_CFG1_SMXX 0x0002 /* This bit needs to be set to 0 for correct operation in the SLEEP state within the DW1000 */
aungriah	0:a3b83d366423	1070	#define AON_CFG1_LPOSC_CAL 0x0004 /* This bit enables the calibration function that measures the period of the ICs internal low powered oscillator */
aungriah	0:a3b83d366423	1071
aungriah	0:a3b83d366423	1072	/**************************************************************************//
aungriah	0:a3b83d366423	1073	* @brief Bit definitions for register OTP_IF
aungriah	0:a3b83d366423	1074	* Refer to section 7.2.46 Register file: 0x2D OTP Memory Interface
aungriah	0:a3b83d366423	1075	**/
aungriah	0:a3b83d366423	1076	#define OTP_IF_ID 0x2D /* One Time Programmable Memory Interface */
aungriah	0:a3b83d366423	1077	#define OTP_IF_LEN (18)
aungriah	0:a3b83d366423	1078	/* offset from OTP_IF_ID in bytes */
aungriah	0:a3b83d366423	1079	#define OTP_WDAT 0x00 /* 32-bit register. The data value to be programmed into an OTP location */
aungriah	0:a3b83d366423	1080	#define OTP_WDAT_LEN (4)
aungriah	0:a3b83d366423	1081	/* offset from OTP_IF_ID in bytes */
aungriah	0:a3b83d366423	1082	#define OTP_ADDR 0x04 /* 16-bit register used to select the address within the OTP memory block */
aungriah	0:a3b83d366423	1083	#define OTP_ADDR_LEN (2)
aungriah	0:a3b83d366423	1084	#define OTP_ADDR_MASK 0x07FF /* This 11-bit field specifies the address within OTP memory that will be accessed read or written. */
aungriah	0:a3b83d366423	1085	/* offset from OTP_IF_ID in bytes */
aungriah	0:a3b83d366423	1086	#define OTP_CTRL 0x06 /* used to control the operation of the OTP memory */
aungriah	0:a3b83d366423	1087	#define OTP_CTRL_LEN (2)
aungriah	0:a3b83d366423	1088	#define OTP_CTRL_MASK 0x8002
aungriah	0:a3b83d366423	1089	#define OTP_CTRL_OTPRDEN 0x0001 /* This bit forces the OTP into manual read mode */
aungriah	0:a3b83d366423	1090	#define OTP_CTRL_OTPREAD 0x0002 /* This bit commands a read operation from the address specified in the OTP_ADDR register */
aungriah	0:a3b83d366423	1091	#define OTP_CTRL_LDELOAD 0x8000 /* This bit forces a load of LDE microcode */
aungriah	0:a3b83d366423	1092	#define OTP_CTRL_OTPPROG 0x0040 /* Setting this bit will cause the contents of OTP_WDAT to be written to OTP_ADDR. */
aungriah	0:a3b83d366423	1093	/* offset from OTP_IF_ID in bytes */
aungriah	0:a3b83d366423	1094	#define OTP_STAT 0x08
aungriah	0:a3b83d366423	1095	#define OTP_STAT_LEN (2)
aungriah	0:a3b83d366423	1096	#define OTP_STAT_MASK 0x0003
aungriah	0:a3b83d366423	1097	#define OTP_STAT_OTPPRGD 0x0001 /* OTP Programming Done */
aungriah	0:a3b83d366423	1098	#define OTP_STAT_OTPVPOK 0x0002 /* OTP Programming Voltage OK */
aungriah	0:a3b83d366423	1099	/* offset from OTP_IF_ID in bytes */
aungriah	0:a3b83d366423	1100	#define OTP_RDAT 0x0A /* 32-bit register. The data value read from an OTP location will appear here */
aungriah	0:a3b83d366423	1101	#define OTP_RDAT_LEN (4)
aungriah	0:a3b83d366423	1102	/* offset from OTP_IF_ID in bytes */
aungriah	0:a3b83d366423	1103	#define OTP_SRDAT 0x0E /* 32-bit register. The data value stored in the OTP SR (0x400) location will appear here after power up */
aungriah	0:a3b83d366423	1104	#define OTP_SRDAT_LEN (4)
aungriah	0:a3b83d366423	1105	/* offset from OTP_IF_ID in bytes */
aungriah	0:a3b83d366423	1106	#define OTP_SF 0x12 /8-bit special function register used to select and load special receiver operational parameter /
aungriah	0:a3b83d366423	1107	#define OTP_SF_LEN (1)
aungriah	0:a3b83d366423	1108	#define OTP_SF_MASK 0x63
aungriah	0:a3b83d366423	1109	#define OTP_SF_OPS_KICK 0x01 /* This bit when set initiates a load of the operating parameter set selected by the OPS_SEL */
aungriah	0:a3b83d366423	1110	#define OTP_SF_LDO_KICK 0x02 /* This bit when set initiates a load of the LDO tune code */
aungriah	0:a3b83d366423	1111	#define OTP_SF_OPS_SEL_SHFT 5
aungriah	0:a3b83d366423	1112	#define OTP_SF_OPS_SEL_MASK 0x60
aungriah	0:a3b83d366423	1113	#define OTP_SF_OPS_SEL_L64 0x00 /* Operating parameter set selection: Length64 */
aungriah	0:a3b83d366423	1114	#define OTP_SF_OPS_SEL_TIGHT 0x40 /* Operating parameter set selection: Tight */
aungriah	0:a3b83d366423	1115
aungriah	0:a3b83d366423	1116	/**************************************************************************//
aungriah	0:a3b83d366423	1117	* @brief Bit definitions for register LDE_IF
aungriah	0:a3b83d366423	1118	* Refer to section 7.2.47 Register file: 0x2E Leading Edge Detection Interface
aungriah	0:a3b83d366423	1119	* PLEASE NOTE: Other areas within the address space of Register file: 0x2E Leading Edge Detection Interface
aungriah	0:a3b83d366423	1120	* are reserved. To ensure proper operation of the LDE algorithm (i.e. to avoid loss of performance or a malfunction),
aungriah	0:a3b83d366423	1121	* care must be taken not to write to any byte locations other than those defined in the sub-sections below.
aungriah	0:a3b83d366423	1122	**/
aungriah	0:a3b83d366423	1123	#define LDE_IF_ID 0x2E /* Leading edge detection control block */
aungriah	0:a3b83d366423	1124	#define LDE_IF_LEN (0)
aungriah	0:a3b83d366423	1125	/* offset from LDE_IF_ID in bytes */
aungriah	0:a3b83d366423	1126	#define LDE_THRESH_OFFSET 0x0000 /* 16-bit status register reporting the threshold that was used to find the first path */
aungriah	0:a3b83d366423	1127	#define LDE_THRESH_LEN (2)
aungriah	0:a3b83d366423	1128	/* offset from LDE_IF_ID in bytes */
aungriah	0:a3b83d366423	1129	#define LDE_CFG1_OFFSET 0x0806 /8-bit configuration register/
aungriah	0:a3b83d366423	1130	#define LDE_CFG1_LEN (1)
aungriah	0:a3b83d366423	1131	#define LDE_CFG1_NSTDEV_MASK 0x1F /* Number of Standard Deviations mask. */
aungriah	0:a3b83d366423	1132	#define LDE_CFG1_PMULT_MASK 0xE0 /* Peak Multiplier mask. */
aungriah	0:a3b83d366423	1133	/* offset from LDE_IF_ID in bytes */
aungriah	0:a3b83d366423	1134	#define LDE_PPINDX_OFFSET 0x1000 /* reporting the position within the accumulator that the LDE algorithm has determined to contain the maximum */
aungriah	0:a3b83d366423	1135	#define LDE_PPINDX_LEN (2)
aungriah	0:a3b83d366423	1136	/* offset from LDE_IF_ID in bytes */
aungriah	0:a3b83d366423	1137	#define LDE_PPAMPL_OFFSET 0x1002 /* reporting the magnitude of the peak signal seen in the accumulator data memory */
aungriah	0:a3b83d366423	1138	#define LDE_PPAMPL_LEN (2)
aungriah	0:a3b83d366423	1139	/* offset from LDE_IF_ID in bytes */
aungriah	0:a3b83d366423	1140	#define LDE_RXANTD_OFFSET 0x1804 /* 16-bit configuration register for setting the receive antenna delay */
aungriah	0:a3b83d366423	1141	#define LDE_RXANTD_LEN (2)
aungriah	0:a3b83d366423	1142	/* offset from LDE_IF_ID in bytes */
aungriah	0:a3b83d366423	1143	#define LDE_CFG2_OFFSET 0x1806 /* 16-bit LDE configuration tuning register */
aungriah	0:a3b83d366423	1144	#define LDE_CFG2_LEN (2)
aungriah	0:a3b83d366423	1145	/* offset from LDE_IF_ID in bytes */
aungriah	0:a3b83d366423	1146	#define LDE_REPC_OFFSET 0x2804 /* 16-bit configuration register for setting the replica avoidance coefficient */
aungriah	0:a3b83d366423	1147	#define LDE_REPC_LEN (2)
aungriah	0:a3b83d366423	1148	#define LDE_REPC_PCODE_1 0x5998
aungriah	0:a3b83d366423	1149	#define LDE_REPC_PCODE_2 0x5998
aungriah	0:a3b83d366423	1150	#define LDE_REPC_PCODE_3 0x51EA
aungriah	0:a3b83d366423	1151	#define LDE_REPC_PCODE_4 0x428E
aungriah	0:a3b83d366423	1152	#define LDE_REPC_PCODE_5 0x451E
aungriah	0:a3b83d366423	1153	#define LDE_REPC_PCODE_6 0x2E14
aungriah	0:a3b83d366423	1154	#define LDE_REPC_PCODE_7 0x8000
aungriah	0:a3b83d366423	1155	#define LDE_REPC_PCODE_8 0x51EA
aungriah	0:a3b83d366423	1156	#define LDE_REPC_PCODE_9 0x28F4
aungriah	0:a3b83d366423	1157	#define LDE_REPC_PCODE_10 0x3332
aungriah	0:a3b83d366423	1158	#define LDE_REPC_PCODE_11 0x3AE0
aungriah	0:a3b83d366423	1159	#define LDE_REPC_PCODE_12 0x3D70
aungriah	0:a3b83d366423	1160	#define LDE_REPC_PCODE_13 0x3AE0
aungriah	0:a3b83d366423	1161	#define LDE_REPC_PCODE_14 0x35C2
aungriah	0:a3b83d366423	1162	#define LDE_REPC_PCODE_15 0x2B84
aungriah	0:a3b83d366423	1163	#define LDE_REPC_PCODE_16 0x35C2
aungriah	0:a3b83d366423	1164	#define LDE_REPC_PCODE_17 0x3332
aungriah	0:a3b83d366423	1165	#define LDE_REPC_PCODE_18 0x35C2
aungriah	0:a3b83d366423	1166	#define LDE_REPC_PCODE_19 0x35C2
aungriah	0:a3b83d366423	1167	#define LDE_REPC_PCODE_20 0x47AE
aungriah	0:a3b83d366423	1168	#define LDE_REPC_PCODE_21 0x3AE0
aungriah	0:a3b83d366423	1169	#define LDE_REPC_PCODE_22 0x3850
aungriah	0:a3b83d366423	1170	#define LDE_REPC_PCODE_23 0x30A2
aungriah	0:a3b83d366423	1171	#define LDE_REPC_PCODE_24 0x3850
aungriah	0:a3b83d366423	1172
aungriah	0:a3b83d366423	1173	/**************************************************************************//
aungriah	0:a3b83d366423	1174	* @brief Bit definitions for register DIG_DIAG
aungriah	0:a3b83d366423	1175	* Digital Diagnostics interface.
aungriah	0:a3b83d366423	1176	* It contains a number of sub-registers that give diagnostics information.
aungriah	0:a3b83d366423	1177	**/
aungriah	0:a3b83d366423	1178	#define DIG_DIAG_ID 0x2F /* Digital Diagnostics Interface */
aungriah	0:a3b83d366423	1179	#define DIG_DIAG_LEN (41)
aungriah	0:a3b83d366423	1180
aungriah	0:a3b83d366423	1181	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1182	#define EVC_CTRL_OFFSET 0x00 /* Event Counter Control */
aungriah	0:a3b83d366423	1183	#define EVC_CTRL_LEN (4)
aungriah	0:a3b83d366423	1184	#define EVC_CTRL_MASK 0x00000003UL/* access mask to Register for bits should always be set to zero to avoid any malfunction of the device. */
aungriah	0:a3b83d366423	1185	#define EVC_EN 0x00000001UL/* Event Counters Enable bit */
aungriah	0:a3b83d366423	1186	#define EVC_CLR 0x00000002UL
aungriah	0:a3b83d366423	1187
aungriah	0:a3b83d366423	1188	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1189	#define EVC_PHE_OFFSET 0x04 /* PHR Error Event Counter */
aungriah	0:a3b83d366423	1190	#define EVC_PHE_LEN (2)
aungriah	0:a3b83d366423	1191	#define EVC_PHE_MASK 0x0FFF
aungriah	0:a3b83d366423	1192	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1193	#define EVC_RSE_OFFSET 0x06 /* Reed Solomon decoder (Frame Sync Loss) Error Event Counter */
aungriah	0:a3b83d366423	1194	#define EVC_RSE_LEN (2)
aungriah	0:a3b83d366423	1195	#define EVC_RSE_MASK 0x0FFF
aungriah	0:a3b83d366423	1196
aungriah	0:a3b83d366423	1197	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1198	#define EVC_FCG_OFFSET 0x08 /* The EVC_FCG field is a 12-bit counter of the frames received with good CRC/FCS sequence. */
aungriah	0:a3b83d366423	1199	#define EVC_FCG_LEN (2)
aungriah	0:a3b83d366423	1200	#define EVC_FCG_MASK 0x0FFF
aungriah	0:a3b83d366423	1201	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1202	#define EVC_FCE_OFFSET 0x0A /* The EVC_FCE field is a 12-bit counter of the frames received with bad CRC/FCS sequence. */
aungriah	0:a3b83d366423	1203	#define EVC_FCE_LEN (2)
aungriah	0:a3b83d366423	1204	#define EVC_FCE_MASK 0x0FFF
aungriah	0:a3b83d366423	1205
aungriah	0:a3b83d366423	1206	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1207	#define EVC_FFR_OFFSET 0x0C /* The EVC_FFR field is a 12-bit counter of the frames rejected by the receive frame filtering function. */
aungriah	0:a3b83d366423	1208	#define EVC_FFR_LEN (2)
aungriah	0:a3b83d366423	1209	#define EVC_FFR_MASK 0x0FFF
aungriah	0:a3b83d366423	1210	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1211	#define EVC_OVR_OFFSET 0x0E /* The EVC_OVR field is a 12-bit counter of receive overrun events */
aungriah	0:a3b83d366423	1212	#define EVC_OVR_LEN (2)
aungriah	0:a3b83d366423	1213	#define EVC_OVR_MASK 0x0FFF
aungriah	0:a3b83d366423	1214
aungriah	0:a3b83d366423	1215	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1216	#define EVC_STO_OFFSET 0x10 /* The EVC_STO field is a 12-bit counter of SFD Timeout Error events */
aungriah	0:a3b83d366423	1217	#define EVC_OVR_LEN (2)
aungriah	0:a3b83d366423	1218	#define EVC_OVR_MASK 0x0FFF
aungriah	0:a3b83d366423	1219	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1220	#define EVC_PTO_OFFSET 0x12 /* The EVC_PTO field is a 12-bit counter of Preamble detection Timeout events */
aungriah	0:a3b83d366423	1221	#define EVC_PTO_LEN (2)
aungriah	0:a3b83d366423	1222	#define EVC_PTO_MASK 0x0FFF
aungriah	0:a3b83d366423	1223
aungriah	0:a3b83d366423	1224	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1225	#define EVC_FWTO_OFFSET 0x14 /* The EVC_FWTO field is a 12-bit counter of receive frame wait timeout events */
aungriah	0:a3b83d366423	1226	#define EVC_FWTO_LEN (2)
aungriah	0:a3b83d366423	1227	#define EVC_FWTO_MASK 0x0FFF
aungriah	0:a3b83d366423	1228	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1229	#define EVC_TXFS_OFFSET 0x16 /* The EVC_TXFS field is a 12-bit counter of transmit frames sent. This is incremented every time a frame is sent */
aungriah	0:a3b83d366423	1230	#define EVC_TXFS_LEN (2)
aungriah	0:a3b83d366423	1231	#define EVC_TXFS_MASK 0x0FFF
aungriah	0:a3b83d366423	1232
aungriah	0:a3b83d366423	1233	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1234	#define EVC_HPW_OFFSET 0x18 /* The EVC_HPW field is a 12-bit counter of Half Period Warnings. */
aungriah	0:a3b83d366423	1235	#define EVC_HPW_LEN (2)
aungriah	0:a3b83d366423	1236	#define EVC_HPW_MASK 0x0FFF
aungriah	0:a3b83d366423	1237	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1238	#define EVC_TPW_OFFSET 0x1A /* The EVC_TPW field is a 12-bit counter of Transmitter Power-Up Warnings. */
aungriah	0:a3b83d366423	1239	#define EVC_TPW_LEN (2)
aungriah	0:a3b83d366423	1240	#define EVC_TPW_MASK 0x0FFF
aungriah	0:a3b83d366423	1241
aungriah	0:a3b83d366423	1242	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1243	#define EVC_RES1_OFFSET 0x1C /* Please take care not to write to this register as doing so may cause the DW1000 to malfunction. */
aungriah	0:a3b83d366423	1244
aungriah	0:a3b83d366423	1245	/* offset from DIG_DIAG_ID in bytes */
aungriah	0:a3b83d366423	1246	#define DIAG_TMC_OFFSET 0x24
aungriah	0:a3b83d366423	1247	#define DIAG_TMC_LEN (2)
aungriah	0:a3b83d366423	1248	#define DIAG_TMC_MASK 0x0010
aungriah	0:a3b83d366423	1249	#define DIAG_TMC_TX_PSTM 0x0010 /* This test mode is provided to help support regulatory approvals spectral testing. When the TX_PSTM bit is set it enables a repeating transmission of the data from the TX_BUFFER */
aungriah	0:a3b83d366423	1250
aungriah	0:a3b83d366423	1251
aungriah	0:a3b83d366423	1252	/**************************************************************************//
aungriah	0:a3b83d366423	1253	* @brief Bit definitions for register 0x30-0x35
aungriah	0:a3b83d366423	1254	* Please take care not to write to these registers as doing so may cause the DW1000 to malfunction.
aungriah	0:a3b83d366423	1255	**/
aungriah	0:a3b83d366423	1256	#define REG_30_ID_RESERVED 0x30
aungriah	0:a3b83d366423	1257	#define REG_31_ID_RESERVED 0x31
aungriah	0:a3b83d366423	1258	#define REG_32_ID_RESERVED 0x32
aungriah	0:a3b83d366423	1259	#define REG_33_ID_RESERVED 0x33
aungriah	0:a3b83d366423	1260	#define REG_34_ID_RESERVED 0x34
aungriah	0:a3b83d366423	1261	#define REG_35_ID_RESERVED 0x35
aungriah	0:a3b83d366423	1262
aungriah	0:a3b83d366423	1263	/**************************************************************************//
aungriah	0:a3b83d366423	1264	* @brief Bit definitions for register PMSC
aungriah	0:a3b83d366423	1265	**/
aungriah	0:a3b83d366423	1266	#define PMSC_ID 0x36 /* Power Management System Control Block */
aungriah	0:a3b83d366423	1267	#define PMSC_LEN (48)
aungriah	0:a3b83d366423	1268	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1269	#define PMSC_CTRL0_OFFSET 0x00
aungriah	0:a3b83d366423	1270	#define PMSC_CTRL0_LEN (4)
aungriah	0:a3b83d366423	1271	#define PMSC_CTRL0_MASK 0xF18F847FUL /* access mask to register PMSC_CTRL0 */
aungriah	0:a3b83d366423	1272	#define PMSC_CTRL0_SYSCLKS_AUTO 0x00000000UL /* The system clock will run off the 19.2 MHz XTI clock until the PLL is calibrated and locked, then it will switch over the 125 MHz PLL clock */
aungriah	0:a3b83d366423	1273	#define PMSC_CTRL0_SYSCLKS_19M 0x00000001UL /* Force system clock to be the 19.2 MHz XTI clock. */
aungriah	0:a3b83d366423	1274	#define PMSC_CTRL0_SYSCLKS_125M 0x00000002UL /* Force system clock to the 125 MHz PLL clock. */
aungriah	0:a3b83d366423	1275	#define PMSC_CTRL0_RXCLKS_AUTO 0x00000000UL /* The RX clock will be disabled until it is required for an RX operation */
aungriah	0:a3b83d366423	1276	#define PMSC_CTRL0_RXCLKS_19M 0x00000004UL /* Force RX clock enable and sourced clock from the 19.2 MHz XTI clock */
aungriah	0:a3b83d366423	1277	#define PMSC_CTRL0_RXCLKS_125M 0x00000008UL /* Force RX clock enable and sourced from the 125 MHz PLL clock */
aungriah	0:a3b83d366423	1278	#define PMSC_CTRL0_RXCLKS_OFF 0x0000000CUL /* Force RX clock off. */
aungriah	0:a3b83d366423	1279	#define PMSC_CTRL0_TXCLKS_AUTO 0x00000000UL /* The TX clock will be disabled until it is required for a TX operation */
aungriah	0:a3b83d366423	1280	#define PMSC_CTRL0_TXCLKS_19M 0x00000010UL /* Force TX clock enable and sourced clock from the 19.2 MHz XTI clock */
aungriah	0:a3b83d366423	1281	#define PMSC_CTRL0_TXCLKS_125M 0x00000020UL /* Force TX clock enable and sourced from the 125 MHz PLL clock */
aungriah	0:a3b83d366423	1282	#define PMSC_CTRL0_TXCLKS_OFF 0x00000030UL /* Force TX clock off */
aungriah	0:a3b83d366423	1283	#define PMSC_CTRL0_FACE 0x00000040UL /* Force Accumulator Clock Enable */
aungriah	0:a3b83d366423	1284	#define PMSC_CTRL0_GPDCE 0x00040000UL /* GPIO De-bounce Clock Enable */
aungriah	0:a3b83d366423	1285	#define PMSC_CTRL0_KHZCLEN 0x00800000UL /* Kilohertz Clock Enable */
aungriah	0:a3b83d366423	1286	#define PMSC_CTRL0_PLL2_SEQ_EN 0x01000000UL /* Enable PLL2 on/off sequencing by SNIFF mode */
aungriah	0:a3b83d366423	1287	#define PMSC_CTRL0_SOFTRESET_OFFSET 3 /* In bytes */
aungriah	0:a3b83d366423	1288	#define PMSC_CTRL0_RESET_ALL 0x00 /* Assuming only 4th byte of the register is read */
aungriah	0:a3b83d366423	1289	#define PMSC_CTRL0_RESET_RX 0xE0 /* Assuming only 4th byte of the register is read */
aungriah	0:a3b83d366423	1290	#define PMSC_CTRL0_RESET_CLEAR 0xF0 /* Assuming only 4th byte of the register is read */
aungriah	0:a3b83d366423	1291	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1292	#define PMSC_CTRL1_OFFSET 0x04
aungriah	0:a3b83d366423	1293	#define PMSC_CTRL1_LEN (4)
aungriah	0:a3b83d366423	1294	#define PMSC_CTRL1_MASK 0xFC02F802UL /* access mask to register PMSC_CTRL1 */
aungriah	0:a3b83d366423	1295	#define PMSC_CTRL1_ARX2INIT 0x00000002UL /* Automatic transition from receive mode into the INIT state */
aungriah	0:a3b83d366423	1296	#define PMSC_CTRL1_ATXSLP 0x00000800UL /* If this bit is set then the DW1000 will automatically transition into SLEEP or DEEPSLEEP mode after transmission of a frame */
aungriah	0:a3b83d366423	1297	#define PMSC_CTRL1_ARXSLP 0x00001000UL /* this bit is set then the DW1000 will automatically transition into SLEEP mode after a receive attempt */
aungriah	0:a3b83d366423	1298	#define PMSC_CTRL1_SNOZE 0x00002000UL /* Snooze Enable */
aungriah	0:a3b83d366423	1299	#define PMSC_CTRL1_SNOZR 0x00004000UL /* The SNOZR bit is set to allow the snooze timer to repeat twice */
aungriah	0:a3b83d366423	1300	#define PMSC_CTRL1_PLLSYN 0x00008000UL /* This enables a special 1 GHz clock used for some external SYNC modes */
aungriah	0:a3b83d366423	1301	#define PMSC_CTRL1_LDERUNE 0x00020000UL /* This bit enables the running of the LDE algorithm */
aungriah	0:a3b83d366423	1302	#define PMSC_CTRL1_KHZCLKDIV_MASK 0xFC000000UL /* Kilohertz clock divisor */
aungriah	0:a3b83d366423	1303	#define PMSC_CTRL1_PKTSEQ_DISABLE 0x00 /* writing this to PMSC CONTROL 1 register (bits 10-3) disables PMSC control of analog RF subsystems */
aungriah	0:a3b83d366423	1304	#define PMSC_CTRL1_PKTSEQ_ENABLE 0xE7 /* writing this to PMSC CONTROL 1 register (bits 10-3) enables PMSC control of analog RF subsystems */
aungriah	0:a3b83d366423	1305	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1306	#define PMSC_RES1_OFFSET 0x08
aungriah	0:a3b83d366423	1307	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1308	#define PMSC_SNOZT_OFFSET 0x0C /* PMSC Snooze Time Register */
aungriah	0:a3b83d366423	1309	#define PMSC_SNOZT_LEN (1)
aungriah	0:a3b83d366423	1310	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1311	#define PMSC_RES2_OFFSET 0x10
aungriah	0:a3b83d366423	1312	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1313	#define PMSC_RES3_OFFSET 0x24
aungriah	0:a3b83d366423	1314	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1315	#define PMSC_TXFINESEQ_OFFSET 0x26
aungriah	0:a3b83d366423	1316	#define PMSC_TXFINESEQ_DISABLE 0x0 /* Writing this disables fine grain sequencing in the transmitter */
aungriah	0:a3b83d366423	1317	#define PMSC_TXFINESEQ_ENABLE 0x0B74 /* Writing this enables fine grain sequencing in the transmitter */
aungriah	0:a3b83d366423	1318	/* offset from PMSC_ID in bytes */
aungriah	0:a3b83d366423	1319	#define PMSC_LEDC_OFFSET 0x28
aungriah	0:a3b83d366423	1320	#define PMSC_LEDC_LEN (4)
aungriah	0:a3b83d366423	1321	#define PMSC_LEDC_MASK 0x000001FFUL /* 32-bit LED control register. */
aungriah	0:a3b83d366423	1322	#define PMSC_LEDC_BLINK_TIM_MASK 0x000000FFUL /* This field determines how long the LEDs remain lit after an event that causes them to be set on. */
aungriah	0:a3b83d366423	1323	#define PMSC_LEDC_BLNKEN 0x00000100UL /* Blink Enable. When this bit is set to 1 the LED blink feature is enabled. */
aungriah	0:a3b83d366423	1324	/* Default blink time. Blink time is expressed in multiples of 14 ms. The value defined here is ~225 ms. */
aungriah	0:a3b83d366423	1325	#define PMSC_LEDC_BLINK_TIME_DEF 0x10
aungriah	0:a3b83d366423	1326	/* Command a blink of all LEDs */
aungriah	0:a3b83d366423	1327	#define PMSC_LEDC_BLINK_NOW_ALL 0x000F0000UL
aungriah	0:a3b83d366423	1328
aungriah	0:a3b83d366423	1329	/**************************************************************************//
aungriah	0:a3b83d366423	1330	* @brief Bit definitions for register 0x37-0x3F
aungriah	0:a3b83d366423	1331	* Please take care not to write to these registers as doing so may cause the DW1000 to malfunction.
aungriah	0:a3b83d366423	1332	**/
aungriah	0:a3b83d366423	1333	#define REG_37_ID_RESERVED 0x37
aungriah	0:a3b83d366423	1334	#define REG_38_ID_RESERVED 0x38
aungriah	0:a3b83d366423	1335	#define REG_39_ID_RESERVED 0x39
aungriah	0:a3b83d366423	1336	#define REG_3A_ID_RESERVED 0x3A
aungriah	0:a3b83d366423	1337	#define REG_3B_ID_RESERVED 0x3B
aungriah	0:a3b83d366423	1338	#define REG_3C_ID_RESERVED 0x3C
aungriah	0:a3b83d366423	1339	#define REG_3D_ID_RESERVED 0x3D
aungriah	0:a3b83d366423	1340	#define REG_3E_ID_RESERVED 0x3E
aungriah	0:a3b83d366423	1341	#define REG_3F_ID_RESERVED 0x3F
aungriah	0:a3b83d366423	1342
aungriah	0:a3b83d366423	1343	/* END DW1000 REGISTER DEFINITION */
aungriah	0:a3b83d366423	1344
aungriah	0:a3b83d366423	1345	#ifdef __cplusplus
aungriah	0:a3b83d366423	1346	}
aungriah	0:a3b83d366423	1347	#endif
aungriah	0:a3b83d366423	1348
aungriah	0:a3b83d366423	1349	#endif
aungriah	0:a3b83d366423	1350

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Created:	06 Dec 2017
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