Alejandro Ungria Hirte / GA-Test

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Dependencies:   mbed-dev

decadriver/deca_device.c@0:3333b6066adf, 2017-12-06 (annotated)

Committer:
aungriah
Date:
Wed Dec 06 21:42:54 2017 +0000
Revision:
0:3333b6066adf
asfaf

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aungriah 0:3333b6066adf 1 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2 * @file deca_device.c
aungriah 0:3333b6066adf 3 * @brief Decawave device configuration and control functions
aungriah 0:3333b6066adf 4 *
aungriah 0:3333b6066adf 5 * @attention
aungriah 0:3333b6066adf 6 *
aungriah 0:3333b6066adf 7 * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
aungriah 0:3333b6066adf 8 *
aungriah 0:3333b6066adf 9 * All rights reserved.
aungriah 0:3333b6066adf 10 *
aungriah 0:3333b6066adf 11 */
aungriah 0:3333b6066adf 12
aungriah 0:3333b6066adf 13 #include <assert.h>
aungriah 0:3333b6066adf 14
aungriah 0:3333b6066adf 15 #include "deca_types.h"
aungriah 0:3333b6066adf 16 #include "deca_param_types.h"
aungriah 0:3333b6066adf 17 #include "deca_regs.h"
aungriah 0:3333b6066adf 18 #include "deca_device_api.h"
aungriah 0:3333b6066adf 19
aungriah 0:3333b6066adf 20 // Defines for enable_clocks function
aungriah 0:3333b6066adf 21 #define FORCE_SYS_XTI 0
aungriah 0:3333b6066adf 22 #define ENABLE_ALL_SEQ 1
aungriah 0:3333b6066adf 23 #define FORCE_SYS_PLL 2
aungriah 0:3333b6066adf 24 #define READ_ACC_ON 7
aungriah 0:3333b6066adf 25 #define READ_ACC_OFF 8
aungriah 0:3333b6066adf 26 #define FORCE_OTP_ON 11
aungriah 0:3333b6066adf 27 #define FORCE_OTP_OFF 12
aungriah 0:3333b6066adf 28 #define FORCE_TX_PLL 13
aungriah 0:3333b6066adf 29 #define FORCE_LDE 14
aungriah 0:3333b6066adf 30
aungriah 0:3333b6066adf 31 // Defines for ACK request bitmask in DATA and MAC COMMAND frame control (first byte) - Used to detect AAT bit wrongly set.
aungriah 0:3333b6066adf 32 #define FCTRL_ACK_REQ_MASK 0x20
aungriah 0:3333b6066adf 33 // Frame control maximum length in bytes.
aungriah 0:3333b6066adf 34 #define FCTRL_LEN_MAX 2
aungriah 0:3333b6066adf 35
aungriah 0:3333b6066adf 36 // #define DWT_API_ERROR_CHECK // define so API checks config input parameters
aungriah 0:3333b6066adf 37
aungriah 0:3333b6066adf 38 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 39 //
aungriah 0:3333b6066adf 40 // Internal functions for controlling and configuring the device
aungriah 0:3333b6066adf 41 //
aungriah 0:3333b6066adf 42 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 43
aungriah 0:3333b6066adf 44 // Enable and Configure specified clocks
aungriah 0:3333b6066adf 45 void _dwt_enableclocks(int clocks) ;
aungriah 0:3333b6066adf 46 // Configure the ucode (FP algorithm) parameters
aungriah 0:3333b6066adf 47 void _dwt_configlde(int prf);
aungriah 0:3333b6066adf 48 // Load ucode from OTP/ROM
aungriah 0:3333b6066adf 49 void _dwt_loaducodefromrom(void);
aungriah 0:3333b6066adf 50 // Read non-volatile memory
aungriah 0:3333b6066adf 51 uint32 _dwt_otpread(uint32 address);
aungriah 0:3333b6066adf 52 // Program the non-volatile memory
aungriah 0:3333b6066adf 53 uint32 _dwt_otpprogword32(uint32 data, uint16 address);
aungriah 0:3333b6066adf 54 // Upload the device configuration into always on memory
aungriah 0:3333b6066adf 55 void _dwt_aonarrayupload(void);
aungriah 0:3333b6066adf 56 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 57
aungriah 0:3333b6066adf 58 /*!
aungriah 0:3333b6066adf 59 * Static data for DW1000 DecaWave Transceiver control
aungriah 0:3333b6066adf 60 */
aungriah 0:3333b6066adf 61
aungriah 0:3333b6066adf 62 // -------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 63 // Structure to hold device data
aungriah 0:3333b6066adf 64 typedef struct
aungriah 0:3333b6066adf 65 {
aungriah 0:3333b6066adf 66 uint32 partID ; // IC Part ID - read during initialisation
aungriah 0:3333b6066adf 67 uint32 lotID ; // IC Lot ID - read during initialisation
aungriah 0:3333b6066adf 68 uint8 longFrames ; // Flag in non-standard long frame mode
aungriah 0:3333b6066adf 69 uint8 otprev ; // OTP revision number (read during initialisation)
aungriah 0:3333b6066adf 70 uint32 txFCTRL ; // Keep TX_FCTRL register config
aungriah 0:3333b6066adf 71 uint8 init_xtrim; // initial XTAL trim value read from OTP (or defaulted to mid-range if OTP not programmed)
aungriah 0:3333b6066adf 72 uint8 dblbuffon; // Double RX buffer mode flag
aungriah 0:3333b6066adf 73 uint32 sysCFGreg ; // Local copy of system config register
aungriah 0:3333b6066adf 74 uint16 sleep_mode; // Used for automatic reloading of LDO tune and microcode at wake-up
aungriah 0:3333b6066adf 75 uint8 wait4resp ; // wait4response was set with last TX start command
aungriah 0:3333b6066adf 76 dwt_cb_data_t cbData; // Callback data structure
aungriah 0:3333b6066adf 77 dwt_cb_t cbTxDone; // Callback for TX confirmation event
aungriah 0:3333b6066adf 78 dwt_cb_t cbRxOk; // Callback for RX good frame event
aungriah 0:3333b6066adf 79 dwt_cb_t cbRxTo; // Callback for RX timeout events
aungriah 0:3333b6066adf 80 dwt_cb_t cbRxErr; // Callback for RX error events
aungriah 0:3333b6066adf 81 } dwt_local_data_t ;
aungriah 0:3333b6066adf 82
aungriah 0:3333b6066adf 83 static dwt_local_data_t dw1000local ; // Static local device data
aungriah 0:3333b6066adf 84
aungriah 0:3333b6066adf 85 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 86 * @fn dwt_initialise()
aungriah 0:3333b6066adf 87 *
aungriah 0:3333b6066adf 88 * @brief This function initiates communications with the DW1000 transceiver
aungriah 0:3333b6066adf 89 * and reads its DEV_ID register (address 0x00) to verify the IC is one supported
aungriah 0:3333b6066adf 90 * by this software (e.g. DW1000 32-bit device ID value is 0xDECA0130). Then it
aungriah 0:3333b6066adf 91 * does any initial once only device configurations needed for use and initialises
aungriah 0:3333b6066adf 92 * as necessary any static data items belonging to this low-level driver.
aungriah 0:3333b6066adf 93 *
aungriah 0:3333b6066adf 94 * NOTES:
aungriah 0:3333b6066adf 95 * 1.this function needs to be run before dwt_configuresleep, also the SPI frequency has to be < 3MHz
aungriah 0:3333b6066adf 96 * 2.it also reads and applies LDO tune and crystal trim values from OTP memory
aungriah 0:3333b6066adf 97 *
aungriah 0:3333b6066adf 98 * input parameters
aungriah 0:3333b6066adf 99 * @param config - specifies what configuration to load
aungriah 0:3333b6066adf 100 * DWT_LOADUCODE 0x1 - load the LDE microcode from ROM - enabled accurate RX timestamp
aungriah 0:3333b6066adf 101 * DWT_LOADNONE 0x0 - do not load any values from OTP memory
aungriah 0:3333b6066adf 102 *
aungriah 0:3333b6066adf 103 * output parameters
aungriah 0:3333b6066adf 104 *
aungriah 0:3333b6066adf 105 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:3333b6066adf 106 */
aungriah 0:3333b6066adf 107 // OTP addresses definitions
aungriah 0:3333b6066adf 108 #define LDOTUNE_ADDRESS (0x04)
aungriah 0:3333b6066adf 109 #define PARTID_ADDRESS (0x06)
aungriah 0:3333b6066adf 110 #define LOTID_ADDRESS (0x07)
aungriah 0:3333b6066adf 111 #define VBAT_ADDRESS (0x08)
aungriah 0:3333b6066adf 112 #define VTEMP_ADDRESS (0x09)
aungriah 0:3333b6066adf 113 #define XTRIM_ADDRESS (0x1E)
aungriah 0:3333b6066adf 114
aungriah 0:3333b6066adf 115 int dwt_initialise(uint16 config)
aungriah 0:3333b6066adf 116 {
aungriah 0:3333b6066adf 117 uint16 otp_addr = 0;
aungriah 0:3333b6066adf 118 uint32 ldo_tune = 0;
aungriah 0:3333b6066adf 119
aungriah 0:3333b6066adf 120 dw1000local.dblbuffon = 0; // Double buffer mode off by default
aungriah 0:3333b6066adf 121 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 122 dw1000local.sleep_mode = 0;
aungriah 0:3333b6066adf 123
aungriah 0:3333b6066adf 124 dw1000local.cbTxDone = NULL;
aungriah 0:3333b6066adf 125 dw1000local.cbRxOk = NULL;
aungriah 0:3333b6066adf 126 dw1000local.cbRxTo = NULL;
aungriah 0:3333b6066adf 127 dw1000local.cbRxErr = NULL;
aungriah 0:3333b6066adf 128
aungriah 0:3333b6066adf 129 // Read and validate device ID return -1 if not recognised
aungriah 0:3333b6066adf 130 if (DWT_DEVICE_ID != dwt_readdevid()) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
aungriah 0:3333b6066adf 131 {
aungriah 0:3333b6066adf 132 return DWT_ERROR ;
aungriah 0:3333b6066adf 133 }
aungriah 0:3333b6066adf 134
aungriah 0:3333b6066adf 135 // Make sure the device is completely reset before starting initialisation
aungriah 0:3333b6066adf 136 dwt_softreset();
aungriah 0:3333b6066adf 137
aungriah 0:3333b6066adf 138 _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
aungriah 0:3333b6066adf 139
aungriah 0:3333b6066adf 140 // Configure the CPLL lock detect
aungriah 0:3333b6066adf 141 dwt_write8bitoffsetreg(EXT_SYNC_ID, EC_CTRL_OFFSET, EC_CTRL_PLLLCK);
aungriah 0:3333b6066adf 142
aungriah 0:3333b6066adf 143 // Read OTP revision number
aungriah 0:3333b6066adf 144 otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
aungriah 0:3333b6066adf 145 dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte
aungriah 0:3333b6066adf 146
aungriah 0:3333b6066adf 147 // Load LDO tune from OTP and kick it if there is a value actually programmed.
aungriah 0:3333b6066adf 148 ldo_tune = _dwt_otpread(LDOTUNE_ADDRESS);
aungriah 0:3333b6066adf 149 if((ldo_tune & 0xFF) != 0)
aungriah 0:3333b6066adf 150 {
aungriah 0:3333b6066adf 151 // Kick LDO tune
aungriah 0:3333b6066adf 152 dwt_write8bitoffsetreg(OTP_IF_ID, OTP_SF, OTP_SF_LDO_KICK); // Set load LDE kick bit
aungriah 0:3333b6066adf 153 dw1000local.sleep_mode |= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
aungriah 0:3333b6066adf 154 }
aungriah 0:3333b6066adf 155
aungriah 0:3333b6066adf 156 // Load Part and Lot ID from OTP
aungriah 0:3333b6066adf 157 dw1000local.partID = _dwt_otpread(PARTID_ADDRESS);
aungriah 0:3333b6066adf 158 dw1000local.lotID = _dwt_otpread(LOTID_ADDRESS);
aungriah 0:3333b6066adf 159
aungriah 0:3333b6066adf 160 // XTAL trim value is set in OTP for DW1000 module and EVK/TREK boards but that might not be the case in a custom design
aungriah 0:3333b6066adf 161 dw1000local.init_xtrim = otp_addr & 0x1F;
aungriah 0:3333b6066adf 162 if (!dw1000local.init_xtrim) // A value of 0 means that the crystal has not been trimmed
aungriah 0:3333b6066adf 163 {
aungriah 0:3333b6066adf 164 dw1000local.init_xtrim = FS_XTALT_MIDRANGE ; // Set to mid-range if no calibration value inside
aungriah 0:3333b6066adf 165 }
aungriah 0:3333b6066adf 166 // Configure XTAL trim
aungriah 0:3333b6066adf 167 dwt_setxtaltrim(dw1000local.init_xtrim);
aungriah 0:3333b6066adf 168
aungriah 0:3333b6066adf 169 // Load leading edge detect code
aungriah 0:3333b6066adf 170 if(config & DWT_LOADUCODE)
aungriah 0:3333b6066adf 171 {
aungriah 0:3333b6066adf 172 _dwt_loaducodefromrom();
aungriah 0:3333b6066adf 173 dw1000local.sleep_mode |= AON_WCFG_ONW_LLDE; // microcode must be loaded at wake-up
aungriah 0:3333b6066adf 174 }
aungriah 0:3333b6066adf 175 else // Should disable the LDERUN enable bit in 0x36, 0x4
aungriah 0:3333b6066adf 176 {
aungriah 0:3333b6066adf 177 uint16 rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1) ;
aungriah 0:3333b6066adf 178 rega &= 0xFDFF ; // Clear LDERUN bit
aungriah 0:3333b6066adf 179 dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1, rega) ;
aungriah 0:3333b6066adf 180 }
aungriah 0:3333b6066adf 181
aungriah 0:3333b6066adf 182 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:3333b6066adf 183
aungriah 0:3333b6066adf 184 // The 3 bits in AON CFG1 register must be cleared to ensure proper operation of the DW1000 in DEEPSLEEP mode.
aungriah 0:3333b6066adf 185 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
aungriah 0:3333b6066adf 186
aungriah 0:3333b6066adf 187 // Read system register / store local copy
aungriah 0:3333b6066adf 188 dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
aungriah 0:3333b6066adf 189
aungriah 0:3333b6066adf 190 return DWT_SUCCESS ;
aungriah 0:3333b6066adf 191
aungriah 0:3333b6066adf 192 } // end dwt_initialise()
aungriah 0:3333b6066adf 193
aungriah 0:3333b6066adf 194 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 195 * @fn dwt_otprevision()
aungriah 0:3333b6066adf 196 *
aungriah 0:3333b6066adf 197 * @brief This is used to return the read OTP revision
aungriah 0:3333b6066adf 198 *
aungriah 0:3333b6066adf 199 * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
aungriah 0:3333b6066adf 200 *
aungriah 0:3333b6066adf 201 * input parameters
aungriah 0:3333b6066adf 202 *
aungriah 0:3333b6066adf 203 * output parameters
aungriah 0:3333b6066adf 204 *
aungriah 0:3333b6066adf 205 * returns the read OTP revision value
aungriah 0:3333b6066adf 206 */
aungriah 0:3333b6066adf 207 uint8 dwt_otprevision(void)
aungriah 0:3333b6066adf 208 {
aungriah 0:3333b6066adf 209 return dw1000local.otprev ;
aungriah 0:3333b6066adf 210 }
aungriah 0:3333b6066adf 211
aungriah 0:3333b6066adf 212 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 213 * @fn dwt_setfinegraintxseq()
aungriah 0:3333b6066adf 214 *
aungriah 0:3333b6066adf 215 * @brief This function enables/disables the fine grain TX sequencing (enabled by default).
aungriah 0:3333b6066adf 216 *
aungriah 0:3333b6066adf 217 * input parameters
aungriah 0:3333b6066adf 218 * @param enable - 1 to enable fine grain TX sequencing, 0 to disable it.
aungriah 0:3333b6066adf 219 *
aungriah 0:3333b6066adf 220 * output parameters none
aungriah 0:3333b6066adf 221 *
aungriah 0:3333b6066adf 222 * no return value
aungriah 0:3333b6066adf 223 */
aungriah 0:3333b6066adf 224 void dwt_setfinegraintxseq(int enable)
aungriah 0:3333b6066adf 225 {
aungriah 0:3333b6066adf 226 if (enable)
aungriah 0:3333b6066adf 227 {
aungriah 0:3333b6066adf 228 dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_ENABLE);
aungriah 0:3333b6066adf 229 }
aungriah 0:3333b6066adf 230 else
aungriah 0:3333b6066adf 231 {
aungriah 0:3333b6066adf 232 dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_DISABLE);
aungriah 0:3333b6066adf 233 }
aungriah 0:3333b6066adf 234 }
aungriah 0:3333b6066adf 235
aungriah 0:3333b6066adf 236 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 237 * @fn dwt_setlnapamode()
aungriah 0:3333b6066adf 238 *
aungriah 0:3333b6066adf 239 * @brief This is used to enable GPIO for external LNA or PA functionality - HW dependent, consult the DW1000 User Manual.
aungriah 0:3333b6066adf 240 * This can also be used for debug as enabling TX and RX GPIOs is quite handy to monitor DW1000's activity.
aungriah 0:3333b6066adf 241 *
aungriah 0:3333b6066adf 242 * NOTE: Enabling PA functionality requires that fine grain TX sequencing is deactivated. This can be done using
aungriah 0:3333b6066adf 243 * dwt_setfinegraintxseq().
aungriah 0:3333b6066adf 244 *
aungriah 0:3333b6066adf 245 * input parameters
aungriah 0:3333b6066adf 246 * @param lna - 1 to enable LNA functionality, 0 to disable it
aungriah 0:3333b6066adf 247 * @param pa - 1 to enable PA functionality, 0 to disable it
aungriah 0:3333b6066adf 248 *
aungriah 0:3333b6066adf 249 * output parameters
aungriah 0:3333b6066adf 250 *
aungriah 0:3333b6066adf 251 * no return value
aungriah 0:3333b6066adf 252 */
aungriah 0:3333b6066adf 253 void dwt_setlnapamode(int lna, int pa)
aungriah 0:3333b6066adf 254 {
aungriah 0:3333b6066adf 255 uint32 gpio_mode = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET);
aungriah 0:3333b6066adf 256 gpio_mode &= ~(GPIO_MSGP4_MASK | GPIO_MSGP5_MASK | GPIO_MSGP6_MASK);
aungriah 0:3333b6066adf 257 if (lna)
aungriah 0:3333b6066adf 258 {
aungriah 0:3333b6066adf 259 gpio_mode |= GPIO_PIN6_EXTRXE;
aungriah 0:3333b6066adf 260 }
aungriah 0:3333b6066adf 261 if (pa)
aungriah 0:3333b6066adf 262 {
aungriah 0:3333b6066adf 263 gpio_mode |= (GPIO_PIN5_EXTTXE | GPIO_PIN4_EXTPA);
aungriah 0:3333b6066adf 264 }
aungriah 0:3333b6066adf 265 dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, gpio_mode);
aungriah 0:3333b6066adf 266 }
aungriah 0:3333b6066adf 267
aungriah 0:3333b6066adf 268 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 269 * @fn dwt_setgpiodirection()
aungriah 0:3333b6066adf 270 *
aungriah 0:3333b6066adf 271 * @brief This is used to set GPIO direction as an input (1) or output (0)
aungriah 0:3333b6066adf 272 *
aungriah 0:3333b6066adf 273 * input parameters
aungriah 0:3333b6066adf 274 * @param gpioNum - this is the GPIO to configure - see GxM0... GxM8 in the deca_regs.h file
aungriah 0:3333b6066adf 275 * @param direction - this sets the GPIO direction - see GxP0... GxP8 in the deca_regs.h file
aungriah 0:3333b6066adf 276 *
aungriah 0:3333b6066adf 277 * output parameters
aungriah 0:3333b6066adf 278 *
aungriah 0:3333b6066adf 279 * no return value
aungriah 0:3333b6066adf 280 */
aungriah 0:3333b6066adf 281 void dwt_setgpiodirection(uint32 gpioNum, uint32 direction)
aungriah 0:3333b6066adf 282 {
aungriah 0:3333b6066adf 283 uint8 buf[GPIO_DIR_LEN];
aungriah 0:3333b6066adf 284 uint32 command = direction | gpioNum;
aungriah 0:3333b6066adf 285
aungriah 0:3333b6066adf 286 buf[0] = command & 0xff;
aungriah 0:3333b6066adf 287 buf[1] = (command >> 8) & 0xff;
aungriah 0:3333b6066adf 288 buf[2] = (command >> 16) & 0xff;
aungriah 0:3333b6066adf 289
aungriah 0:3333b6066adf 290 dwt_writetodevice(GPIO_CTRL_ID, GPIO_DIR_OFFSET, GPIO_DIR_LEN, buf);
aungriah 0:3333b6066adf 291 }
aungriah 0:3333b6066adf 292
aungriah 0:3333b6066adf 293 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 294 * @fn dwt_setgpiovalue()
aungriah 0:3333b6066adf 295 *
aungriah 0:3333b6066adf 296 * @brief This is used to set GPIO value as (1) or (0) only applies if the GPIO is configured as output
aungriah 0:3333b6066adf 297 *
aungriah 0:3333b6066adf 298 * input parameters
aungriah 0:3333b6066adf 299 * @param gpioNum - this is the GPIO to configure - see GxM0... GxM8 in the deca_regs.h file
aungriah 0:3333b6066adf 300 * @param value - this sets the GPIO value - see GDP0... GDP8 in the deca_regs.h file
aungriah 0:3333b6066adf 301 *
aungriah 0:3333b6066adf 302 * output parameters
aungriah 0:3333b6066adf 303 *
aungriah 0:3333b6066adf 304 * no return value
aungriah 0:3333b6066adf 305 */
aungriah 0:3333b6066adf 306 void dwt_setgpiovalue(uint32 gpioNum, uint32 value)
aungriah 0:3333b6066adf 307 {
aungriah 0:3333b6066adf 308 uint8 buf[GPIO_DOUT_LEN];
aungriah 0:3333b6066adf 309 uint32 command = value | gpioNum;
aungriah 0:3333b6066adf 310
aungriah 0:3333b6066adf 311 buf[0] = command & 0xff;
aungriah 0:3333b6066adf 312 buf[1] = (command >> 8) & 0xff;
aungriah 0:3333b6066adf 313 buf[2] = (command >> 16) & 0xff;
aungriah 0:3333b6066adf 314
aungriah 0:3333b6066adf 315 dwt_writetodevice(GPIO_CTRL_ID, GPIO_DOUT_OFFSET, GPIO_DOUT_LEN, buf);
aungriah 0:3333b6066adf 316 }
aungriah 0:3333b6066adf 317
aungriah 0:3333b6066adf 318 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 319 * @fn dwt_getpartid()
aungriah 0:3333b6066adf 320 *
aungriah 0:3333b6066adf 321 * @brief This is used to return the read part ID of the device
aungriah 0:3333b6066adf 322 *
aungriah 0:3333b6066adf 323 * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
aungriah 0:3333b6066adf 324 *
aungriah 0:3333b6066adf 325 * input parameters
aungriah 0:3333b6066adf 326 *
aungriah 0:3333b6066adf 327 * output parameters
aungriah 0:3333b6066adf 328 *
aungriah 0:3333b6066adf 329 * returns the 32 bit part ID value as programmed in the factory
aungriah 0:3333b6066adf 330 */
aungriah 0:3333b6066adf 331 uint32 dwt_getpartid(void)
aungriah 0:3333b6066adf 332 {
aungriah 0:3333b6066adf 333 return dw1000local.partID;
aungriah 0:3333b6066adf 334 }
aungriah 0:3333b6066adf 335
aungriah 0:3333b6066adf 336 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 337 * @fn dwt_getlotid()
aungriah 0:3333b6066adf 338 *
aungriah 0:3333b6066adf 339 * @brief This is used to return the read lot ID of the device
aungriah 0:3333b6066adf 340 *
aungriah 0:3333b6066adf 341 * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
aungriah 0:3333b6066adf 342 *
aungriah 0:3333b6066adf 343 * input parameters
aungriah 0:3333b6066adf 344 *
aungriah 0:3333b6066adf 345 * output parameters
aungriah 0:3333b6066adf 346 *
aungriah 0:3333b6066adf 347 * returns the 32 bit lot ID value as programmed in the factory
aungriah 0:3333b6066adf 348 */
aungriah 0:3333b6066adf 349 uint32 dwt_getlotid(void)
aungriah 0:3333b6066adf 350 {
aungriah 0:3333b6066adf 351 return dw1000local.lotID;
aungriah 0:3333b6066adf 352 }
aungriah 0:3333b6066adf 353
aungriah 0:3333b6066adf 354 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 355 * @fn dwt_readdevid()
aungriah 0:3333b6066adf 356 *
aungriah 0:3333b6066adf 357 * @brief This is used to return the read device type and revision information of the DW1000 device (MP part is 0xDECA0130)
aungriah 0:3333b6066adf 358 *
aungriah 0:3333b6066adf 359 * input parameters
aungriah 0:3333b6066adf 360 *
aungriah 0:3333b6066adf 361 * output parameters
aungriah 0:3333b6066adf 362 *
aungriah 0:3333b6066adf 363 * returns the read value which for DW1000 is 0xDECA0130
aungriah 0:3333b6066adf 364 */
aungriah 0:3333b6066adf 365 uint32 dwt_readdevid(void)
aungriah 0:3333b6066adf 366 {
aungriah 0:3333b6066adf 367 return dwt_read32bitoffsetreg(DEV_ID_ID,0);
aungriah 0:3333b6066adf 368 }
aungriah 0:3333b6066adf 369
aungriah 0:3333b6066adf 370 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 371 * @fn dwt_configuretxrf()
aungriah 0:3333b6066adf 372 *
aungriah 0:3333b6066adf 373 * @brief This function provides the API for the configuration of the TX spectrum
aungriah 0:3333b6066adf 374 * including the power and pulse generator delay. The input is a pointer to the data structure
aungriah 0:3333b6066adf 375 * of type dwt_txconfig_t that holds all the configurable items.
aungriah 0:3333b6066adf 376 *
aungriah 0:3333b6066adf 377 * input parameters
aungriah 0:3333b6066adf 378 * @param config - pointer to the txrf configuration structure, which contains the tx rf config data
aungriah 0:3333b6066adf 379 *
aungriah 0:3333b6066adf 380 * output parameters
aungriah 0:3333b6066adf 381 *
aungriah 0:3333b6066adf 382 * no return value
aungriah 0:3333b6066adf 383 */
aungriah 0:3333b6066adf 384 void dwt_configuretxrf(dwt_txconfig_t *config)
aungriah 0:3333b6066adf 385 {
aungriah 0:3333b6066adf 386
aungriah 0:3333b6066adf 387 // Configure RF TX PG_DELAY
aungriah 0:3333b6066adf 388 dwt_write8bitoffsetreg(TX_CAL_ID, TC_PGDELAY_OFFSET, config->PGdly);
aungriah 0:3333b6066adf 389
aungriah 0:3333b6066adf 390 // Configure TX power
aungriah 0:3333b6066adf 391 dwt_write32bitreg(TX_POWER_ID, config->power);
aungriah 0:3333b6066adf 392
aungriah 0:3333b6066adf 393 }
aungriah 0:3333b6066adf 394
aungriah 0:3333b6066adf 395 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 396 * @fn dwt_configure()
aungriah 0:3333b6066adf 397 *
aungriah 0:3333b6066adf 398 * @brief This function provides the main API for the configuration of the
aungriah 0:3333b6066adf 399 * DW1000 and this low-level driver. The input is a pointer to the data structure
aungriah 0:3333b6066adf 400 * of type dwt_config_t that holds all the configurable items.
aungriah 0:3333b6066adf 401 * The dwt_config_t structure shows which ones are supported
aungriah 0:3333b6066adf 402 *
aungriah 0:3333b6066adf 403 * input parameters
aungriah 0:3333b6066adf 404 * @param config - pointer to the configuration structure, which contains the device configuration data.
aungriah 0:3333b6066adf 405 *
aungriah 0:3333b6066adf 406 * output parameters
aungriah 0:3333b6066adf 407 *
aungriah 0:3333b6066adf 408 * no return value
aungriah 0:3333b6066adf 409 */
aungriah 0:3333b6066adf 410 void dwt_configure(dwt_config_t *config)
aungriah 0:3333b6066adf 411 {
aungriah 0:3333b6066adf 412 uint8 chan = config->chan ;
aungriah 0:3333b6066adf 413 uint32 regval ;
aungriah 0:3333b6066adf 414 uint16 reg16 = lde_replicaCoeff[config->rxCode];
aungriah 0:3333b6066adf 415 uint8 prfIndex = config->prf - DWT_PRF_16M;
aungriah 0:3333b6066adf 416 uint8 bw = ((chan == 4) || (chan == 7)) ? 1 : 0 ; // Select wide or narrow band
aungriah 0:3333b6066adf 417
aungriah 0:3333b6066adf 418 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 419 assert(config->dataRate <= DWT_BR_6M8);
aungriah 0:3333b6066adf 420 assert(config->rxPAC <= DWT_PAC64);
aungriah 0:3333b6066adf 421 assert((chan >= 1) && (chan <= 7) && (chan != 6));
aungriah 0:3333b6066adf 422 assert(((config->prf == DWT_PRF_64M) && (config->txCode >= 9) && (config->txCode <= 24))
aungriah 0:3333b6066adf 423 || ((config->prf == DWT_PRF_16M) && (config->txCode >= 1) && (config->txCode <= 8)));
aungriah 0:3333b6066adf 424 assert(((config->prf == DWT_PRF_64M) && (config->rxCode >= 9) && (config->rxCode <= 24))
aungriah 0:3333b6066adf 425 || ((config->prf == DWT_PRF_16M) && (config->rxCode >= 1) && (config->rxCode <= 8)));
aungriah 0:3333b6066adf 426 assert((config->txPreambLength == DWT_PLEN_64) || (config->txPreambLength == DWT_PLEN_128) || (config->txPreambLength == DWT_PLEN_256)
aungriah 0:3333b6066adf 427 || (config->txPreambLength == DWT_PLEN_512) || (config->txPreambLength == DWT_PLEN_1024) || (config->txPreambLength == DWT_PLEN_1536)
aungriah 0:3333b6066adf 428 || (config->txPreambLength == DWT_PLEN_2048) || (config->txPreambLength == DWT_PLEN_4096));
aungriah 0:3333b6066adf 429 assert((config->phrMode == DWT_PHRMODE_STD) || (config->phrMode == DWT_PHRMODE_EXT));
aungriah 0:3333b6066adf 430 #endif
aungriah 0:3333b6066adf 431
aungriah 0:3333b6066adf 432 // For 110 kbps we need a special setup
aungriah 0:3333b6066adf 433 if(DWT_BR_110K == config->dataRate)
aungriah 0:3333b6066adf 434 {
aungriah 0:3333b6066adf 435 dw1000local.sysCFGreg |= SYS_CFG_RXM110K ;
aungriah 0:3333b6066adf 436 reg16 >>= 3; // lde_replicaCoeff must be divided by 8
aungriah 0:3333b6066adf 437 }
aungriah 0:3333b6066adf 438 else
aungriah 0:3333b6066adf 439 {
aungriah 0:3333b6066adf 440 dw1000local.sysCFGreg &= (~SYS_CFG_RXM110K) ;
aungriah 0:3333b6066adf 441 }
aungriah 0:3333b6066adf 442
aungriah 0:3333b6066adf 443 dw1000local.longFrames = config->phrMode ;
aungriah 0:3333b6066adf 444
aungriah 0:3333b6066adf 445 dw1000local.sysCFGreg &= ~SYS_CFG_PHR_MODE_11;
aungriah 0:3333b6066adf 446 dw1000local.sysCFGreg |= (SYS_CFG_PHR_MODE_11 & (config->phrMode << SYS_CFG_PHR_MODE_SHFT));
aungriah 0:3333b6066adf 447
aungriah 0:3333b6066adf 448 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:3333b6066adf 449 // Set the lde_replicaCoeff
aungriah 0:3333b6066adf 450 dwt_write16bitoffsetreg(LDE_IF_ID, LDE_REPC_OFFSET, reg16) ;
aungriah 0:3333b6066adf 451
aungriah 0:3333b6066adf 452 _dwt_configlde(prfIndex);
aungriah 0:3333b6066adf 453
aungriah 0:3333b6066adf 454 // Configure PLL2/RF PLL block CFG/TUNE (for a given channel)
aungriah 0:3333b6066adf 455 dwt_write32bitoffsetreg(FS_CTRL_ID, FS_PLLCFG_OFFSET, fs_pll_cfg[chan_idx[chan]]);
aungriah 0:3333b6066adf 456 dwt_write8bitoffsetreg(FS_CTRL_ID, FS_PLLTUNE_OFFSET, fs_pll_tune[chan_idx[chan]]);
aungriah 0:3333b6066adf 457
aungriah 0:3333b6066adf 458 // Configure RF RX blocks (for specified channel/bandwidth)
aungriah 0:3333b6066adf 459 dwt_write8bitoffsetreg(RF_CONF_ID, RF_RXCTRLH_OFFSET, rx_config[bw]);
aungriah 0:3333b6066adf 460
aungriah 0:3333b6066adf 461 // Configure RF TX blocks (for specified channel and PRF)
aungriah 0:3333b6066adf 462 // Configure RF TX control
aungriah 0:3333b6066adf 463 dwt_write32bitoffsetreg(RF_CONF_ID, RF_TXCTRL_OFFSET, tx_config[chan_idx[chan]]);
aungriah 0:3333b6066adf 464
aungriah 0:3333b6066adf 465 // Configure the baseband parameters (for specified PRF, bit rate, PAC, and SFD settings)
aungriah 0:3333b6066adf 466 // DTUNE0
aungriah 0:3333b6066adf 467 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE0b_OFFSET, sftsh[config->dataRate][config->nsSFD]);
aungriah 0:3333b6066adf 468
aungriah 0:3333b6066adf 469 // DTUNE1
aungriah 0:3333b6066adf 470 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1a_OFFSET, dtune1[prfIndex]);
aungriah 0:3333b6066adf 471
aungriah 0:3333b6066adf 472 if(config->dataRate == DWT_BR_110K)
aungriah 0:3333b6066adf 473 {
aungriah 0:3333b6066adf 474 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_110K);
aungriah 0:3333b6066adf 475 }
aungriah 0:3333b6066adf 476 else
aungriah 0:3333b6066adf 477 {
aungriah 0:3333b6066adf 478 if(config->txPreambLength == DWT_PLEN_64)
aungriah 0:3333b6066adf 479 {
aungriah 0:3333b6066adf 480 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_6M8_PRE64);
aungriah 0:3333b6066adf 481 dwt_write8bitoffsetreg(DRX_CONF_ID, DRX_TUNE4H_OFFSET, DRX_TUNE4H_PRE64);
aungriah 0:3333b6066adf 482 }
aungriah 0:3333b6066adf 483 else
aungriah 0:3333b6066adf 484 {
aungriah 0:3333b6066adf 485 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_850K_6M8);
aungriah 0:3333b6066adf 486 dwt_write8bitoffsetreg(DRX_CONF_ID, DRX_TUNE4H_OFFSET, DRX_TUNE4H_PRE128PLUS);
aungriah 0:3333b6066adf 487 }
aungriah 0:3333b6066adf 488 }
aungriah 0:3333b6066adf 489
aungriah 0:3333b6066adf 490 // DTUNE2
aungriah 0:3333b6066adf 491 dwt_write32bitoffsetreg(DRX_CONF_ID, DRX_TUNE2_OFFSET, digital_bb_config[prfIndex][config->rxPAC]);
aungriah 0:3333b6066adf 492
aungriah 0:3333b6066adf 493 // DTUNE3 (SFD timeout)
aungriah 0:3333b6066adf 494 // Don't allow 0 - SFD timeout will always be enabled
aungriah 0:3333b6066adf 495 if(config->sfdTO == 0)
aungriah 0:3333b6066adf 496 {
aungriah 0:3333b6066adf 497 config->sfdTO = DWT_SFDTOC_DEF;
aungriah 0:3333b6066adf 498 }
aungriah 0:3333b6066adf 499 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_SFDTOC_OFFSET, config->sfdTO);
aungriah 0:3333b6066adf 500
aungriah 0:3333b6066adf 501 // Configure AGC parameters
aungriah 0:3333b6066adf 502 dwt_write32bitoffsetreg( AGC_CFG_STS_ID, 0xC, agc_config.lo32);
aungriah 0:3333b6066adf 503 dwt_write16bitoffsetreg( AGC_CFG_STS_ID, 0x4, agc_config.target[prfIndex]);
aungriah 0:3333b6066adf 504
aungriah 0:3333b6066adf 505 // Set (non-standard) user SFD for improved performance,
aungriah 0:3333b6066adf 506 if(config->nsSFD)
aungriah 0:3333b6066adf 507 {
aungriah 0:3333b6066adf 508 // Write non standard (DW) SFD length
aungriah 0:3333b6066adf 509 dwt_write8bitoffsetreg(USR_SFD_ID, 0x00, dwnsSFDlen[config->dataRate]);
aungriah 0:3333b6066adf 510 }
aungriah 0:3333b6066adf 511 regval = (CHAN_CTRL_TX_CHAN_MASK & (chan << CHAN_CTRL_TX_CHAN_SHIFT)) | // Transmit Channel
aungriah 0:3333b6066adf 512 (CHAN_CTRL_RX_CHAN_MASK & (chan << CHAN_CTRL_RX_CHAN_SHIFT)) | // Receive Channel
aungriah 0:3333b6066adf 513 (CHAN_CTRL_RXFPRF_MASK & (config->prf << CHAN_CTRL_RXFPRF_SHIFT)) | // RX PRF
aungriah 0:3333b6066adf 514 (CHAN_CTRL_DWSFD & (config->nsSFD << CHAN_CTRL_DWSFD_SHIFT)) | // Use DW nsSFD
aungriah 0:3333b6066adf 515 (CHAN_CTRL_TX_PCOD_MASK & (config->txCode << CHAN_CTRL_TX_PCOD_SHIFT)) | // TX Preamble Code
aungriah 0:3333b6066adf 516 (CHAN_CTRL_RX_PCOD_MASK & (config->rxCode << CHAN_CTRL_RX_PCOD_SHIFT)) ; // RX Preamble Code
aungriah 0:3333b6066adf 517
aungriah 0:3333b6066adf 518 dwt_write32bitreg(CHAN_CTRL_ID,regval) ;
aungriah 0:3333b6066adf 519
aungriah 0:3333b6066adf 520 // Set up TX Preamble Size, PRF and Data Rate
aungriah 0:3333b6066adf 521 dw1000local.txFCTRL = ((config->txPreambLength | config->prf) << TX_FCTRL_TXPRF_SHFT) | (config->dataRate << TX_FCTRL_TXBR_SHFT);
aungriah 0:3333b6066adf 522 dwt_write32bitreg(TX_FCTRL_ID, dw1000local.txFCTRL);
aungriah 0:3333b6066adf 523
aungriah 0:3333b6066adf 524 // The SFD transmit pattern is initialised by the DW1000 upon a user TX request, but (due to an IC issue) it is not done for an auto-ACK TX. The
aungriah 0:3333b6066adf 525 // SYS_CTRL write below works around this issue, by simultaneously initiating and aborting a transmission, which correctly initialises the SFD
aungriah 0:3333b6066adf 526 // after its configuration or reconfiguration.
aungriah 0:3333b6066adf 527 // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
aungriah 0:3333b6066adf 528 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, SYS_CTRL_TXSTRT | SYS_CTRL_TRXOFF); // Request TX start and TRX off at the same time
aungriah 0:3333b6066adf 529 } // end dwt_configure()
aungriah 0:3333b6066adf 530
aungriah 0:3333b6066adf 531 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 532 * @fn dwt_setrxantennadelay()
aungriah 0:3333b6066adf 533 *
aungriah 0:3333b6066adf 534 * @brief This API function writes the antenna delay (in time units) to RX registers
aungriah 0:3333b6066adf 535 *
aungriah 0:3333b6066adf 536 * input parameters:
aungriah 0:3333b6066adf 537 * @param rxDelay - this is the total (RX) antenna delay value, which
aungriah 0:3333b6066adf 538 * will be programmed into the RX register
aungriah 0:3333b6066adf 539 *
aungriah 0:3333b6066adf 540 * output parameters
aungriah 0:3333b6066adf 541 *
aungriah 0:3333b6066adf 542 * no return value
aungriah 0:3333b6066adf 543 */
aungriah 0:3333b6066adf 544 void dwt_setrxantennadelay(uint16 rxDelay)
aungriah 0:3333b6066adf 545 {
aungriah 0:3333b6066adf 546 // Set the RX antenna delay for auto TX timestamp adjustment
aungriah 0:3333b6066adf 547 dwt_write16bitoffsetreg(LDE_IF_ID, LDE_RXANTD_OFFSET, rxDelay);
aungriah 0:3333b6066adf 548 }
aungriah 0:3333b6066adf 549
aungriah 0:3333b6066adf 550 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 551 * @fn dwt_settxantennadelay()
aungriah 0:3333b6066adf 552 *
aungriah 0:3333b6066adf 553 * @brief This API function writes the antenna delay (in time units) to TX registers
aungriah 0:3333b6066adf 554 *
aungriah 0:3333b6066adf 555 * input parameters:
aungriah 0:3333b6066adf 556 * @param txDelay - this is the total (TX) antenna delay value, which
aungriah 0:3333b6066adf 557 * will be programmed into the TX delay register
aungriah 0:3333b6066adf 558 *
aungriah 0:3333b6066adf 559 * output parameters
aungriah 0:3333b6066adf 560 *
aungriah 0:3333b6066adf 561 * no return value
aungriah 0:3333b6066adf 562 */
aungriah 0:3333b6066adf 563 void dwt_settxantennadelay(uint16 txDelay)
aungriah 0:3333b6066adf 564 {
aungriah 0:3333b6066adf 565 // Set the TX antenna delay for auto TX timestamp adjustment
aungriah 0:3333b6066adf 566 dwt_write16bitoffsetreg(TX_ANTD_ID, TX_ANTD_OFFSET, txDelay);
aungriah 0:3333b6066adf 567 }
aungriah 0:3333b6066adf 568
aungriah 0:3333b6066adf 569 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 570 * @fn dwt_writetxdata()
aungriah 0:3333b6066adf 571 *
aungriah 0:3333b6066adf 572 * @brief This API function writes the supplied TX data into the DW1000's
aungriah 0:3333b6066adf 573 * TX buffer. The input parameters are the data length in bytes and a pointer
aungriah 0:3333b6066adf 574 * to those data bytes.
aungriah 0:3333b6066adf 575 *
aungriah 0:3333b6066adf 576 * input parameters
aungriah 0:3333b6066adf 577 * @param txFrameLength - This is the total frame length, including the two byte CRC.
aungriah 0:3333b6066adf 578 * Note: this is the length of TX message (including the 2 byte CRC) - max is 1023
aungriah 0:3333b6066adf 579 * standard PHR mode allows up to 127 bytes
aungriah 0:3333b6066adf 580 * if > 127 is programmed, DWT_PHRMODE_EXT needs to be set in the phrMode configuration
aungriah 0:3333b6066adf 581 * see dwt_configure function
aungriah 0:3333b6066adf 582 * @param txFrameBytes - Pointer to the user’s buffer containing the data to send.
aungriah 0:3333b6066adf 583 * @param txBufferOffset - This specifies an offset in the DW1000’s TX Buffer at which to start writing data.
aungriah 0:3333b6066adf 584 *
aungriah 0:3333b6066adf 585 * output parameters
aungriah 0:3333b6066adf 586 *
aungriah 0:3333b6066adf 587 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:3333b6066adf 588 */
aungriah 0:3333b6066adf 589 int dwt_writetxdata(uint16 txFrameLength, uint8 *txFrameBytes, uint16 txBufferOffset)
aungriah 0:3333b6066adf 590 {
aungriah 0:3333b6066adf 591 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 592 assert(txFrameLength >= 2);
aungriah 0:3333b6066adf 593 assert((dw1000local.longFrames && (txFrameLength <= 1023)) || (txFrameLength <= 127));
aungriah 0:3333b6066adf 594 assert((txBufferOffset + txFrameLength) <= 1024);
aungriah 0:3333b6066adf 595 #endif
aungriah 0:3333b6066adf 596
aungriah 0:3333b6066adf 597 if ((txBufferOffset + txFrameLength) <= 1024)
aungriah 0:3333b6066adf 598 {
aungriah 0:3333b6066adf 599 // Write the data to the IC TX buffer, (-2 bytes for auto generated CRC)
aungriah 0:3333b6066adf 600 dwt_writetodevice( TX_BUFFER_ID, txBufferOffset, txFrameLength-2, txFrameBytes);
aungriah 0:3333b6066adf 601 return DWT_SUCCESS;
aungriah 0:3333b6066adf 602 }
aungriah 0:3333b6066adf 603 else
aungriah 0:3333b6066adf 604 {
aungriah 0:3333b6066adf 605 return DWT_ERROR;
aungriah 0:3333b6066adf 606 }
aungriah 0:3333b6066adf 607 } // end dwt_writetxdata()
aungriah 0:3333b6066adf 608
aungriah 0:3333b6066adf 609 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 610 * @fn dwt_writetxfctrl()
aungriah 0:3333b6066adf 611 *
aungriah 0:3333b6066adf 612 * @brief This API function configures the TX frame control register before the transmission of a frame
aungriah 0:3333b6066adf 613 *
aungriah 0:3333b6066adf 614 * input parameters:
aungriah 0:3333b6066adf 615 * @param txFrameLength - this is the length of TX message (including the 2 byte CRC) - max is 1023
aungriah 0:3333b6066adf 616 * NOTE: standard PHR mode allows up to 127 bytes
aungriah 0:3333b6066adf 617 * if > 127 is programmed, DWT_PHRMODE_EXT needs to be set in the phrMode configuration
aungriah 0:3333b6066adf 618 * see dwt_configure function
aungriah 0:3333b6066adf 619 * @param txBufferOffset - the offset in the tx buffer to start writing the data
aungriah 0:3333b6066adf 620 * @param ranging - 1 if this is a ranging frame, else 0
aungriah 0:3333b6066adf 621 *
aungriah 0:3333b6066adf 622 * output parameters
aungriah 0:3333b6066adf 623 *
aungriah 0:3333b6066adf 624 * no return value
aungriah 0:3333b6066adf 625 */
aungriah 0:3333b6066adf 626 void dwt_writetxfctrl(uint16 txFrameLength, uint16 txBufferOffset, int ranging)
aungriah 0:3333b6066adf 627 {
aungriah 0:3333b6066adf 628
aungriah 0:3333b6066adf 629 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 630 assert((dw1000local.longFrames && (txFrameLength <= 1023)) || (txFrameLength <= 127));
aungriah 0:3333b6066adf 631 #endif
aungriah 0:3333b6066adf 632
aungriah 0:3333b6066adf 633 // Write the frame length to the TX frame control register
aungriah 0:3333b6066adf 634 // dw1000local.txFCTRL has kept configured bit rate information
aungriah 0:3333b6066adf 635 uint32 reg32 = dw1000local.txFCTRL | txFrameLength | (txBufferOffset << TX_FCTRL_TXBOFFS_SHFT) | (ranging << TX_FCTRL_TR_SHFT);
aungriah 0:3333b6066adf 636 dwt_write32bitreg(TX_FCTRL_ID, reg32);
aungriah 0:3333b6066adf 637 } // end dwt_writetxfctrl()
aungriah 0:3333b6066adf 638
aungriah 0:3333b6066adf 639
aungriah 0:3333b6066adf 640 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 641 * @fn dwt_readrxdata()
aungriah 0:3333b6066adf 642 *
aungriah 0:3333b6066adf 643 * @brief This is used to read the data from the RX buffer, from an offset location give by offset parameter
aungriah 0:3333b6066adf 644 *
aungriah 0:3333b6066adf 645 * input parameters
aungriah 0:3333b6066adf 646 * @param buffer - the buffer into which the data will be read
aungriah 0:3333b6066adf 647 * @param length - the length of data to read (in bytes)
aungriah 0:3333b6066adf 648 * @param rxBufferOffset - the offset in the rx buffer from which to read the data
aungriah 0:3333b6066adf 649 *
aungriah 0:3333b6066adf 650 * output parameters
aungriah 0:3333b6066adf 651 *
aungriah 0:3333b6066adf 652 * no return value
aungriah 0:3333b6066adf 653 */
aungriah 0:3333b6066adf 654 void dwt_readrxdata(uint8 *buffer, uint16 length, uint16 rxBufferOffset)
aungriah 0:3333b6066adf 655 {
aungriah 0:3333b6066adf 656 dwt_readfromdevice(RX_BUFFER_ID,rxBufferOffset,length,buffer) ;
aungriah 0:3333b6066adf 657 }
aungriah 0:3333b6066adf 658
aungriah 0:3333b6066adf 659 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 660 * @fn dwt_readaccdata()
aungriah 0:3333b6066adf 661 *
aungriah 0:3333b6066adf 662 * @brief This is used to read the data from the Accumulator buffer, from an offset location give by offset parameter
aungriah 0:3333b6066adf 663 *
aungriah 0:3333b6066adf 664 * NOTE: Because of an internal memory access delay when reading the accumulator the first octet output is a dummy octet
aungriah 0:3333b6066adf 665 * that should be discarded. This is true no matter what sub-index the read begins at.
aungriah 0:3333b6066adf 666 *
aungriah 0:3333b6066adf 667 * input parameters
aungriah 0:3333b6066adf 668 * @param buffer - the buffer into which the data will be read
aungriah 0:3333b6066adf 669 * @param length - the length of data to read (in bytes)
aungriah 0:3333b6066adf 670 * @param accOffset - the offset in the acc buffer from which to read the data
aungriah 0:3333b6066adf 671 *
aungriah 0:3333b6066adf 672 * output parameters
aungriah 0:3333b6066adf 673 *
aungriah 0:3333b6066adf 674 * no return value
aungriah 0:3333b6066adf 675 */
aungriah 0:3333b6066adf 676 void dwt_readaccdata(uint8 *buffer, uint16 len, uint16 accOffset)
aungriah 0:3333b6066adf 677 {
aungriah 0:3333b6066adf 678 // Force on the ACC clocks if we are sequenced
aungriah 0:3333b6066adf 679 _dwt_enableclocks(READ_ACC_ON);
aungriah 0:3333b6066adf 680
aungriah 0:3333b6066adf 681 dwt_readfromdevice(ACC_MEM_ID,accOffset,len,buffer) ;
aungriah 0:3333b6066adf 682
aungriah 0:3333b6066adf 683 _dwt_enableclocks(READ_ACC_OFF); // Revert clocks back
aungriah 0:3333b6066adf 684 }
aungriah 0:3333b6066adf 685
aungriah 0:3333b6066adf 686 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 687 * @fn dwt_readdiagnostics()
aungriah 0:3333b6066adf 688 *
aungriah 0:3333b6066adf 689 * @brief this function reads the RX signal quality diagnostic data
aungriah 0:3333b6066adf 690 *
aungriah 0:3333b6066adf 691 * input parameters
aungriah 0:3333b6066adf 692 * @param diagnostics - diagnostic structure pointer, this will contain the diagnostic data read from the DW1000
aungriah 0:3333b6066adf 693 *
aungriah 0:3333b6066adf 694 * output parameters
aungriah 0:3333b6066adf 695 *
aungriah 0:3333b6066adf 696 * no return value
aungriah 0:3333b6066adf 697 */
aungriah 0:3333b6066adf 698 void dwt_readdiagnostics(dwt_rxdiag_t *diagnostics)
aungriah 0:3333b6066adf 699 {
aungriah 0:3333b6066adf 700 // Read the HW FP index
aungriah 0:3333b6066adf 701 diagnostics->firstPath = dwt_read16bitoffsetreg(RX_TIME_ID, RX_TIME_FP_INDEX_OFFSET);
aungriah 0:3333b6066adf 702
aungriah 0:3333b6066adf 703 // LDE diagnostic data
aungriah 0:3333b6066adf 704 diagnostics->maxNoise = dwt_read16bitoffsetreg(LDE_IF_ID, LDE_THRESH_OFFSET);
aungriah 0:3333b6066adf 705
aungriah 0:3333b6066adf 706 // Read all 8 bytes in one SPI transaction
aungriah 0:3333b6066adf 707 dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8*)&diagnostics->stdNoise);
aungriah 0:3333b6066adf 708
aungriah 0:3333b6066adf 709 diagnostics->firstPathAmp1 = dwt_read16bitoffsetreg(RX_TIME_ID, RX_TIME_FP_AMPL1_OFFSET);
aungriah 0:3333b6066adf 710
aungriah 0:3333b6066adf 711 diagnostics->rxPreamCount = (dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXPACC_MASK) >> RX_FINFO_RXPACC_SHIFT ;
aungriah 0:3333b6066adf 712 }
aungriah 0:3333b6066adf 713
aungriah 0:3333b6066adf 714 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 715 * @fn dwt_readtxtimestamp()
aungriah 0:3333b6066adf 716 *
aungriah 0:3333b6066adf 717 * @brief This is used to read the TX timestamp (adjusted with the programmed antenna delay)
aungriah 0:3333b6066adf 718 *
aungriah 0:3333b6066adf 719 * input parameters
aungriah 0:3333b6066adf 720 * @param timestamp - a pointer to a 5-byte buffer which will store the read TX timestamp time
aungriah 0:3333b6066adf 721 *
aungriah 0:3333b6066adf 722 * output parameters - the timestamp buffer will contain the value after the function call
aungriah 0:3333b6066adf 723 *
aungriah 0:3333b6066adf 724 * no return value
aungriah 0:3333b6066adf 725 */
aungriah 0:3333b6066adf 726 void dwt_readtxtimestamp(uint8 * timestamp)
aungriah 0:3333b6066adf 727 {
aungriah 0:3333b6066adf 728 dwt_readfromdevice(TX_TIME_ID, TX_TIME_TX_STAMP_OFFSET, TX_TIME_TX_STAMP_LEN, timestamp) ; // Read bytes directly into buffer
aungriah 0:3333b6066adf 729 }
aungriah 0:3333b6066adf 730
aungriah 0:3333b6066adf 731 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 732 * @fn dwt_readtxtimestamphi32()
aungriah 0:3333b6066adf 733 *
aungriah 0:3333b6066adf 734 * @brief This is used to read the high 32-bits of the TX timestamp (adjusted with the programmed antenna delay)
aungriah 0:3333b6066adf 735 *
aungriah 0:3333b6066adf 736 * input parameters
aungriah 0:3333b6066adf 737 *
aungriah 0:3333b6066adf 738 * output parameters
aungriah 0:3333b6066adf 739 *
aungriah 0:3333b6066adf 740 * returns high 32-bits of TX timestamp
aungriah 0:3333b6066adf 741 */
aungriah 0:3333b6066adf 742 uint32 dwt_readtxtimestamphi32(void)
aungriah 0:3333b6066adf 743 {
aungriah 0:3333b6066adf 744 return dwt_read32bitoffsetreg(TX_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5
aungriah 0:3333b6066adf 745 }
aungriah 0:3333b6066adf 746
aungriah 0:3333b6066adf 747 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 748 * @fn dwt_readtxtimestamplo32()
aungriah 0:3333b6066adf 749 *
aungriah 0:3333b6066adf 750 * @brief This is used to read the low 32-bits of the TX timestamp (adjusted with the programmed antenna delay)
aungriah 0:3333b6066adf 751 *
aungriah 0:3333b6066adf 752 * input parameters
aungriah 0:3333b6066adf 753 *
aungriah 0:3333b6066adf 754 * output parameters
aungriah 0:3333b6066adf 755 *
aungriah 0:3333b6066adf 756 * returns low 32-bits of TX timestamp
aungriah 0:3333b6066adf 757 */
aungriah 0:3333b6066adf 758 uint32 dwt_readtxtimestamplo32(void)
aungriah 0:3333b6066adf 759 {
aungriah 0:3333b6066adf 760 return dwt_read32bitreg(TX_TIME_ID); // Read TX TIME as a 32-bit register to get the 4 lower bytes out of 5
aungriah 0:3333b6066adf 761 }
aungriah 0:3333b6066adf 762
aungriah 0:3333b6066adf 763 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 764 * @fn dwt_readrxtimestamp()
aungriah 0:3333b6066adf 765 *
aungriah 0:3333b6066adf 766 * @brief This is used to read the RX timestamp (adjusted time of arrival)
aungriah 0:3333b6066adf 767 *
aungriah 0:3333b6066adf 768 * input parameters
aungriah 0:3333b6066adf 769 * @param timestamp - a pointer to a 5-byte buffer which will store the read RX timestamp time
aungriah 0:3333b6066adf 770 *
aungriah 0:3333b6066adf 771 * output parameters - the timestamp buffer will contain the value after the function call
aungriah 0:3333b6066adf 772 *
aungriah 0:3333b6066adf 773 * no return value
aungriah 0:3333b6066adf 774 */
aungriah 0:3333b6066adf 775 void dwt_readrxtimestamp(uint8 * timestamp)
aungriah 0:3333b6066adf 776 {
aungriah 0:3333b6066adf 777 dwt_readfromdevice(RX_TIME_ID, RX_TIME_RX_STAMP_OFFSET, RX_TIME_RX_STAMP_LEN, timestamp) ; // Get the adjusted time of arrival
aungriah 0:3333b6066adf 778 }
aungriah 0:3333b6066adf 779
aungriah 0:3333b6066adf 780 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 781 * @fn dwt_readrxtimestamphi32()
aungriah 0:3333b6066adf 782 *
aungriah 0:3333b6066adf 783 * @brief This is used to read the high 32-bits of the RX timestamp (adjusted with the programmed antenna delay)
aungriah 0:3333b6066adf 784 *
aungriah 0:3333b6066adf 785 * input parameters
aungriah 0:3333b6066adf 786 *
aungriah 0:3333b6066adf 787 * output parameters
aungriah 0:3333b6066adf 788 *
aungriah 0:3333b6066adf 789 * returns high 32-bits of RX timestamp
aungriah 0:3333b6066adf 790 */
aungriah 0:3333b6066adf 791 uint32 dwt_readrxtimestamphi32(void)
aungriah 0:3333b6066adf 792 {
aungriah 0:3333b6066adf 793 return dwt_read32bitoffsetreg(RX_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5
aungriah 0:3333b6066adf 794 }
aungriah 0:3333b6066adf 795
aungriah 0:3333b6066adf 796 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 797 * @fn dwt_readrxtimestamplo32()
aungriah 0:3333b6066adf 798 *
aungriah 0:3333b6066adf 799 * @brief This is used to read the low 32-bits of the RX timestamp (adjusted with the programmed antenna delay)
aungriah 0:3333b6066adf 800 *
aungriah 0:3333b6066adf 801 * input parameters
aungriah 0:3333b6066adf 802 *
aungriah 0:3333b6066adf 803 * output parameters
aungriah 0:3333b6066adf 804 *
aungriah 0:3333b6066adf 805 * returns low 32-bits of RX timestamp
aungriah 0:3333b6066adf 806 */
aungriah 0:3333b6066adf 807 uint32 dwt_readrxtimestamplo32(void)
aungriah 0:3333b6066adf 808 {
aungriah 0:3333b6066adf 809 return dwt_read32bitreg(RX_TIME_ID); // Read RX TIME as a 32-bit register to get the 4 lower bytes out of 5
aungriah 0:3333b6066adf 810 }
aungriah 0:3333b6066adf 811
aungriah 0:3333b6066adf 812 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 813 * @fn dwt_readsystimestamphi32()
aungriah 0:3333b6066adf 814 *
aungriah 0:3333b6066adf 815 * @brief This is used to read the high 32-bits of the system time
aungriah 0:3333b6066adf 816 *
aungriah 0:3333b6066adf 817 * input parameters
aungriah 0:3333b6066adf 818 *
aungriah 0:3333b6066adf 819 * output parameters
aungriah 0:3333b6066adf 820 *
aungriah 0:3333b6066adf 821 * returns high 32-bits of system time timestamp
aungriah 0:3333b6066adf 822 */
aungriah 0:3333b6066adf 823 uint32 dwt_readsystimestamphi32(void)
aungriah 0:3333b6066adf 824 {
aungriah 0:3333b6066adf 825 return dwt_read32bitoffsetreg(SYS_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5
aungriah 0:3333b6066adf 826 }
aungriah 0:3333b6066adf 827
aungriah 0:3333b6066adf 828 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 829 * @fn dwt_readsystime()
aungriah 0:3333b6066adf 830 *
aungriah 0:3333b6066adf 831 * @brief This is used to read the system time
aungriah 0:3333b6066adf 832 *
aungriah 0:3333b6066adf 833 * input parameters
aungriah 0:3333b6066adf 834 * @param timestamp - a pointer to a 5-byte buffer which will store the read system time
aungriah 0:3333b6066adf 835 *
aungriah 0:3333b6066adf 836 * output parameters
aungriah 0:3333b6066adf 837 * @param timestamp - the timestamp buffer will contain the value after the function call
aungriah 0:3333b6066adf 838 *
aungriah 0:3333b6066adf 839 * no return value
aungriah 0:3333b6066adf 840 */
aungriah 0:3333b6066adf 841 void dwt_readsystime(uint8 * timestamp)
aungriah 0:3333b6066adf 842 {
aungriah 0:3333b6066adf 843 dwt_readfromdevice(SYS_TIME_ID, SYS_TIME_OFFSET, SYS_TIME_LEN, timestamp) ;
aungriah 0:3333b6066adf 844 }
aungriah 0:3333b6066adf 845
aungriah 0:3333b6066adf 846 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 847 * @fn dwt_writetodevice()
aungriah 0:3333b6066adf 848 *
aungriah 0:3333b6066adf 849 * @brief this function is used to write to the DW1000 device registers
aungriah 0:3333b6066adf 850 * Notes:
aungriah 0:3333b6066adf 851 * 1. Firstly we create a header (the first byte is a header byte)
aungriah 0:3333b6066adf 852 * a. check if sub index is used, if subindexing is used - set bit-6 to 1 to signify that the sub-index address follows the register index byte
aungriah 0:3333b6066adf 853 * b. set bit-7 (or with 0x80) for write operation
aungriah 0:3333b6066adf 854 * c. if extended sub address index is used (i.e. if index > 127) set bit-7 of the first sub-index byte following the first header byte
aungriah 0:3333b6066adf 855 *
aungriah 0:3333b6066adf 856 * 2. Write the header followed by the data bytes to the DW1000 device
aungriah 0:3333b6066adf 857 *
aungriah 0:3333b6066adf 858 *
aungriah 0:3333b6066adf 859 * input parameters:
aungriah 0:3333b6066adf 860 * @param recordNumber - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 861 * @param index - byte index into register file or buffer being accessed
aungriah 0:3333b6066adf 862 * @param length - number of bytes being written
aungriah 0:3333b6066adf 863 * @param buffer - pointer to buffer containing the 'length' bytes to be written
aungriah 0:3333b6066adf 864 *
aungriah 0:3333b6066adf 865 * output parameters
aungriah 0:3333b6066adf 866 *
aungriah 0:3333b6066adf 867 * no return value
aungriah 0:3333b6066adf 868 */
aungriah 0:3333b6066adf 869 void dwt_writetodevice
aungriah 0:3333b6066adf 870 (
aungriah 0:3333b6066adf 871 uint16 recordNumber,
aungriah 0:3333b6066adf 872 uint16 index,
aungriah 0:3333b6066adf 873 uint32 length,
aungriah 0:3333b6066adf 874 const uint8 *buffer
aungriah 0:3333b6066adf 875 )
aungriah 0:3333b6066adf 876 {
aungriah 0:3333b6066adf 877 uint8 header[3] ; // Buffer to compose header in
aungriah 0:3333b6066adf 878 int cnt = 0; // Counter for length of header
aungriah 0:3333b6066adf 879 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 880 assert(recordNumber <= 0x3F); // Record number is limited to 6-bits.
aungriah 0:3333b6066adf 881 #endif
aungriah 0:3333b6066adf 882
aungriah 0:3333b6066adf 883 // Write message header selecting WRITE operation and addresses as appropriate (this is one to three bytes long)
aungriah 0:3333b6066adf 884 if (index == 0) // For index of 0, no sub-index is required
aungriah 0:3333b6066adf 885 {
aungriah 0:3333b6066adf 886 header[cnt++] = 0x80 | recordNumber ; // Bit-7 is WRITE operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
aungriah 0:3333b6066adf 887 }
aungriah 0:3333b6066adf 888 else
aungriah 0:3333b6066adf 889 {
aungriah 0:3333b6066adf 890 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 891 assert((index <= 0x7FFF) && ((index + length) <= 0x7FFF)); // Index and sub-addressable area are limited to 15-bits.
aungriah 0:3333b6066adf 892 #endif
aungriah 0:3333b6066adf 893 header[cnt++] = 0xC0 | recordNumber ; // Bit-7 is WRITE operation, bit-6 one=sub-address follows, bits 5-0 is reg file id
aungriah 0:3333b6066adf 894
aungriah 0:3333b6066adf 895 if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
aungriah 0:3333b6066adf 896 {
aungriah 0:3333b6066adf 897 header[cnt++] = (uint8)index ; // Bit-7 zero means no extension, bits 6-0 is index.
aungriah 0:3333b6066adf 898 }
aungriah 0:3333b6066adf 899 else
aungriah 0:3333b6066adf 900 {
aungriah 0:3333b6066adf 901 header[cnt++] = 0x80 | (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
aungriah 0:3333b6066adf 902 header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
aungriah 0:3333b6066adf 903 }
aungriah 0:3333b6066adf 904 }
aungriah 0:3333b6066adf 905
aungriah 0:3333b6066adf 906 // Write it to the SPI
aungriah 0:3333b6066adf 907 writetospi(cnt,header,length,buffer);
aungriah 0:3333b6066adf 908 } // end dwt_writetodevice()
aungriah 0:3333b6066adf 909
aungriah 0:3333b6066adf 910 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 911 * @fn dwt_readfromdevice()
aungriah 0:3333b6066adf 912 *
aungriah 0:3333b6066adf 913 * @brief this function is used to read from the DW1000 device registers
aungriah 0:3333b6066adf 914 * Notes:
aungriah 0:3333b6066adf 915 * 1. Firstly we create a header (the first byte is a header byte)
aungriah 0:3333b6066adf 916 * a. check if sub index is used, if subindexing is used - set bit-6 to 1 to signify that the sub-index address follows the register index byte
aungriah 0:3333b6066adf 917 * b. set bit-7 (or with 0x80) for write operation
aungriah 0:3333b6066adf 918 * c. if extended sub address index is used (i.e. if index > 127) set bit-7 of the first sub-index byte following the first header byte
aungriah 0:3333b6066adf 919 *
aungriah 0:3333b6066adf 920 * 2. Write the header followed by the data bytes to the DW1000 device
aungriah 0:3333b6066adf 921 * 3. Store the read data in the input buffer
aungriah 0:3333b6066adf 922 *
aungriah 0:3333b6066adf 923 * input parameters:
aungriah 0:3333b6066adf 924 * @param recordNumber - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 925 * @param index - byte index into register file or buffer being accessed
aungriah 0:3333b6066adf 926 * @param length - number of bytes being read
aungriah 0:3333b6066adf 927 * @param buffer - pointer to buffer in which to return the read data.
aungriah 0:3333b6066adf 928 *
aungriah 0:3333b6066adf 929 * output parameters
aungriah 0:3333b6066adf 930 *
aungriah 0:3333b6066adf 931 * no return value
aungriah 0:3333b6066adf 932 */
aungriah 0:3333b6066adf 933 void dwt_readfromdevice
aungriah 0:3333b6066adf 934 (
aungriah 0:3333b6066adf 935 uint16 recordNumber,
aungriah 0:3333b6066adf 936 uint16 index,
aungriah 0:3333b6066adf 937 uint32 length,
aungriah 0:3333b6066adf 938 uint8 *buffer
aungriah 0:3333b6066adf 939 )
aungriah 0:3333b6066adf 940 {
aungriah 0:3333b6066adf 941 uint8 header[3] ; // Buffer to compose header in
aungriah 0:3333b6066adf 942 int cnt = 0; // Counter for length of header
aungriah 0:3333b6066adf 943 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 944 assert(recordNumber <= 0x3F); // Record number is limited to 6-bits.
aungriah 0:3333b6066adf 945 #endif
aungriah 0:3333b6066adf 946
aungriah 0:3333b6066adf 947 // Write message header selecting READ operation and addresses as appropriate (this is one to three bytes long)
aungriah 0:3333b6066adf 948 if (index == 0) // For index of 0, no sub-index is required
aungriah 0:3333b6066adf 949 {
aungriah 0:3333b6066adf 950 header[cnt++] = (uint8) recordNumber ; // Bit-7 zero is READ operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
aungriah 0:3333b6066adf 951 }
aungriah 0:3333b6066adf 952 else
aungriah 0:3333b6066adf 953 {
aungriah 0:3333b6066adf 954 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 955 assert((index <= 0x7FFF) && ((index + length) <= 0x7FFF)); // Index and sub-addressable area are limited to 15-bits.
aungriah 0:3333b6066adf 956 #endif
aungriah 0:3333b6066adf 957 header[cnt++] = (uint8)(0x40 | recordNumber) ; // Bit-7 zero is READ operation, bit-6 one=sub-address follows, bits 5-0 is reg file id
aungriah 0:3333b6066adf 958
aungriah 0:3333b6066adf 959 if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
aungriah 0:3333b6066adf 960 {
aungriah 0:3333b6066adf 961 header[cnt++] = (uint8) index ; // Bit-7 zero means no extension, bits 6-0 is index.
aungriah 0:3333b6066adf 962 }
aungriah 0:3333b6066adf 963 else
aungriah 0:3333b6066adf 964 {
aungriah 0:3333b6066adf 965 header[cnt++] = 0x80 | (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
aungriah 0:3333b6066adf 966 header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
aungriah 0:3333b6066adf 967 }
aungriah 0:3333b6066adf 968 }
aungriah 0:3333b6066adf 969
aungriah 0:3333b6066adf 970 // Do the read from the SPI
aungriah 0:3333b6066adf 971 readfromspi(cnt, header, length, buffer); // result is stored in the buffer
aungriah 0:3333b6066adf 972 } // end dwt_readfromdevice()
aungriah 0:3333b6066adf 973
aungriah 0:3333b6066adf 974
aungriah 0:3333b6066adf 975
aungriah 0:3333b6066adf 976 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 977 * @fn dwt_read32bitoffsetreg()
aungriah 0:3333b6066adf 978 *
aungriah 0:3333b6066adf 979 * @brief this function is used to read 32-bit value from the DW1000 device registers
aungriah 0:3333b6066adf 980 *
aungriah 0:3333b6066adf 981 * input parameters:
aungriah 0:3333b6066adf 982 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 983 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:3333b6066adf 984 *
aungriah 0:3333b6066adf 985 * output parameters
aungriah 0:3333b6066adf 986 *
aungriah 0:3333b6066adf 987 * returns 32 bit register value
aungriah 0:3333b6066adf 988 */
aungriah 0:3333b6066adf 989 uint32 dwt_read32bitoffsetreg(int regFileID,int regOffset)
aungriah 0:3333b6066adf 990 {
aungriah 0:3333b6066adf 991 uint32 regval = 0 ;
aungriah 0:3333b6066adf 992 int j ;
aungriah 0:3333b6066adf 993 uint8 buffer[4] ;
aungriah 0:3333b6066adf 994
aungriah 0:3333b6066adf 995 dwt_readfromdevice(regFileID,regOffset,4,buffer); // Read 4 bytes (32-bits) register into buffer
aungriah 0:3333b6066adf 996
aungriah 0:3333b6066adf 997 for (j = 3 ; j >= 0 ; j --)
aungriah 0:3333b6066adf 998 {
aungriah 0:3333b6066adf 999 regval = (regval << 8) + buffer[j] ;
aungriah 0:3333b6066adf 1000 }
aungriah 0:3333b6066adf 1001 return regval ;
aungriah 0:3333b6066adf 1002
aungriah 0:3333b6066adf 1003 } // end dwt_read32bitoffsetreg()
aungriah 0:3333b6066adf 1004
aungriah 0:3333b6066adf 1005 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1006 * @fn dwt_read16bitoffsetreg()
aungriah 0:3333b6066adf 1007 *
aungriah 0:3333b6066adf 1008 * @brief this function is used to read 16-bit value from the DW1000 device registers
aungriah 0:3333b6066adf 1009 *
aungriah 0:3333b6066adf 1010 * input parameters:
aungriah 0:3333b6066adf 1011 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 1012 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:3333b6066adf 1013 *
aungriah 0:3333b6066adf 1014 * output parameters
aungriah 0:3333b6066adf 1015 *
aungriah 0:3333b6066adf 1016 * returns 16 bit register value
aungriah 0:3333b6066adf 1017 */
aungriah 0:3333b6066adf 1018 uint16 dwt_read16bitoffsetreg(int regFileID,int regOffset)
aungriah 0:3333b6066adf 1019 {
aungriah 0:3333b6066adf 1020 uint16 regval = 0 ;
aungriah 0:3333b6066adf 1021 uint8 buffer[2] ;
aungriah 0:3333b6066adf 1022
aungriah 0:3333b6066adf 1023 dwt_readfromdevice(regFileID,regOffset,2,buffer); // Read 2 bytes (16-bits) register into buffer
aungriah 0:3333b6066adf 1024
aungriah 0:3333b6066adf 1025 regval = (buffer[1] << 8) + buffer[0] ;
aungriah 0:3333b6066adf 1026 return regval ;
aungriah 0:3333b6066adf 1027
aungriah 0:3333b6066adf 1028 } // end dwt_read16bitoffsetreg()
aungriah 0:3333b6066adf 1029
aungriah 0:3333b6066adf 1030 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1031 * @fn dwt_read8bitoffsetreg()
aungriah 0:3333b6066adf 1032 *
aungriah 0:3333b6066adf 1033 * @brief this function is used to read an 8-bit value from the DW1000 device registers
aungriah 0:3333b6066adf 1034 *
aungriah 0:3333b6066adf 1035 * input parameters:
aungriah 0:3333b6066adf 1036 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 1037 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:3333b6066adf 1038 *
aungriah 0:3333b6066adf 1039 * output parameters
aungriah 0:3333b6066adf 1040 *
aungriah 0:3333b6066adf 1041 * returns 8-bit register value
aungriah 0:3333b6066adf 1042 */
aungriah 0:3333b6066adf 1043 uint8 dwt_read8bitoffsetreg(int regFileID, int regOffset)
aungriah 0:3333b6066adf 1044 {
aungriah 0:3333b6066adf 1045 uint8 regval;
aungriah 0:3333b6066adf 1046
aungriah 0:3333b6066adf 1047 dwt_readfromdevice(regFileID, regOffset, 1, &regval);
aungriah 0:3333b6066adf 1048
aungriah 0:3333b6066adf 1049 return regval ;
aungriah 0:3333b6066adf 1050 }
aungriah 0:3333b6066adf 1051
aungriah 0:3333b6066adf 1052 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1053 * @fn dwt_write8bitoffsetreg()
aungriah 0:3333b6066adf 1054 *
aungriah 0:3333b6066adf 1055 * @brief this function is used to write an 8-bit value to the DW1000 device registers
aungriah 0:3333b6066adf 1056 *
aungriah 0:3333b6066adf 1057 * input parameters:
aungriah 0:3333b6066adf 1058 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 1059 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:3333b6066adf 1060 * @param regval - the value to write
aungriah 0:3333b6066adf 1061 *
aungriah 0:3333b6066adf 1062 * output parameters
aungriah 0:3333b6066adf 1063 *
aungriah 0:3333b6066adf 1064 * no return value
aungriah 0:3333b6066adf 1065 */
aungriah 0:3333b6066adf 1066 void dwt_write8bitoffsetreg(int regFileID, int regOffset, uint8 regval)
aungriah 0:3333b6066adf 1067 {
aungriah 0:3333b6066adf 1068 dwt_writetodevice(regFileID, regOffset, 1, &regval);
aungriah 0:3333b6066adf 1069 }
aungriah 0:3333b6066adf 1070
aungriah 0:3333b6066adf 1071 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1072 * @fn dwt_write16bitoffsetreg()
aungriah 0:3333b6066adf 1073 *
aungriah 0:3333b6066adf 1074 * @brief this function is used to write 16-bit value to the DW1000 device registers
aungriah 0:3333b6066adf 1075 *
aungriah 0:3333b6066adf 1076 * input parameters:
aungriah 0:3333b6066adf 1077 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 1078 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:3333b6066adf 1079 * @param regval - the value to write
aungriah 0:3333b6066adf 1080 *
aungriah 0:3333b6066adf 1081 * output parameters
aungriah 0:3333b6066adf 1082 *
aungriah 0:3333b6066adf 1083 * no return value
aungriah 0:3333b6066adf 1084 */
aungriah 0:3333b6066adf 1085 void dwt_write16bitoffsetreg(int regFileID,int regOffset,uint16 regval)
aungriah 0:3333b6066adf 1086 {
aungriah 0:3333b6066adf 1087 uint8 buffer[2] ;
aungriah 0:3333b6066adf 1088
aungriah 0:3333b6066adf 1089 buffer[0] = regval & 0xFF;
aungriah 0:3333b6066adf 1090 buffer[1] = regval >> 8 ;
aungriah 0:3333b6066adf 1091
aungriah 0:3333b6066adf 1092 dwt_writetodevice(regFileID,regOffset,2,buffer);
aungriah 0:3333b6066adf 1093 } // end dwt_write16bitoffsetreg()
aungriah 0:3333b6066adf 1094
aungriah 0:3333b6066adf 1095 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1096 * @fn dwt_write32bitoffsetreg()
aungriah 0:3333b6066adf 1097 *
aungriah 0:3333b6066adf 1098 * @brief this function is used to write 32-bit value to the DW1000 device registers
aungriah 0:3333b6066adf 1099 *
aungriah 0:3333b6066adf 1100 * input parameters:
aungriah 0:3333b6066adf 1101 * @param regFileID - ID of register file or buffer being accessed
aungriah 0:3333b6066adf 1102 * @param regOffset - the index into register file or buffer being accessed
aungriah 0:3333b6066adf 1103 * @param regval - the value to write
aungriah 0:3333b6066adf 1104 *
aungriah 0:3333b6066adf 1105 * output parameters
aungriah 0:3333b6066adf 1106 *
aungriah 0:3333b6066adf 1107 * no return value
aungriah 0:3333b6066adf 1108 */
aungriah 0:3333b6066adf 1109 void dwt_write32bitoffsetreg(int regFileID,int regOffset,uint32 regval)
aungriah 0:3333b6066adf 1110 {
aungriah 0:3333b6066adf 1111 int j ;
aungriah 0:3333b6066adf 1112 uint8 buffer[4] ;
aungriah 0:3333b6066adf 1113
aungriah 0:3333b6066adf 1114 for ( j = 0 ; j < 4 ; j++ )
aungriah 0:3333b6066adf 1115 {
aungriah 0:3333b6066adf 1116 buffer[j] = regval & 0xff ;
aungriah 0:3333b6066adf 1117 regval >>= 8 ;
aungriah 0:3333b6066adf 1118 }
aungriah 0:3333b6066adf 1119
aungriah 0:3333b6066adf 1120 dwt_writetodevice(regFileID,regOffset,4,buffer);
aungriah 0:3333b6066adf 1121 } // end dwt_write32bitoffsetreg()
aungriah 0:3333b6066adf 1122
aungriah 0:3333b6066adf 1123 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1124 * @fn dwt_enableframefilter()
aungriah 0:3333b6066adf 1125 *
aungriah 0:3333b6066adf 1126 * @brief This is used to enable the frame filtering - (the default option is to
aungriah 0:3333b6066adf 1127 * accept any data and ACK frames with correct destination address
aungriah 0:3333b6066adf 1128 *
aungriah 0:3333b6066adf 1129 * input parameters
aungriah 0:3333b6066adf 1130 * @param - bitmask - enables/disables the frame filtering options according to
aungriah 0:3333b6066adf 1131 * DWT_FF_NOTYPE_EN 0x000 no frame types allowed
aungriah 0:3333b6066adf 1132 * DWT_FF_COORD_EN 0x002 behave as coordinator (can receive frames with no destination address (PAN ID has to match))
aungriah 0:3333b6066adf 1133 * DWT_FF_BEACON_EN 0x004 beacon frames allowed
aungriah 0:3333b6066adf 1134 * DWT_FF_DATA_EN 0x008 data frames allowed
aungriah 0:3333b6066adf 1135 * DWT_FF_ACK_EN 0x010 ack frames allowed
aungriah 0:3333b6066adf 1136 * DWT_FF_MAC_EN 0x020 mac control frames allowed
aungriah 0:3333b6066adf 1137 * DWT_FF_RSVD_EN 0x040 reserved frame types allowed
aungriah 0:3333b6066adf 1138 *
aungriah 0:3333b6066adf 1139 * output parameters
aungriah 0:3333b6066adf 1140 *
aungriah 0:3333b6066adf 1141 * no return value
aungriah 0:3333b6066adf 1142 */
aungriah 0:3333b6066adf 1143 void dwt_enableframefilter(uint16 enable)
aungriah 0:3333b6066adf 1144 {
aungriah 0:3333b6066adf 1145 uint32 sysconfig = SYS_CFG_MASK & dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
aungriah 0:3333b6066adf 1146
aungriah 0:3333b6066adf 1147 if(enable)
aungriah 0:3333b6066adf 1148 {
aungriah 0:3333b6066adf 1149 // Enable frame filtering and configure frame types
aungriah 0:3333b6066adf 1150 sysconfig &= ~(SYS_CFG_FF_ALL_EN); // Clear all
aungriah 0:3333b6066adf 1151 sysconfig |= (enable & SYS_CFG_FF_ALL_EN) | SYS_CFG_FFE;
aungriah 0:3333b6066adf 1152 }
aungriah 0:3333b6066adf 1153 else
aungriah 0:3333b6066adf 1154 {
aungriah 0:3333b6066adf 1155 sysconfig &= ~(SYS_CFG_FFE);
aungriah 0:3333b6066adf 1156 }
aungriah 0:3333b6066adf 1157
aungriah 0:3333b6066adf 1158 dw1000local.sysCFGreg = sysconfig ;
aungriah 0:3333b6066adf 1159 dwt_write32bitreg(SYS_CFG_ID,sysconfig) ;
aungriah 0:3333b6066adf 1160 }
aungriah 0:3333b6066adf 1161
aungriah 0:3333b6066adf 1162 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1163 * @fn dwt_setpanid()
aungriah 0:3333b6066adf 1164 *
aungriah 0:3333b6066adf 1165 * @brief This is used to set the PAN ID
aungriah 0:3333b6066adf 1166 *
aungriah 0:3333b6066adf 1167 * input parameters
aungriah 0:3333b6066adf 1168 * @param panID - this is the PAN ID
aungriah 0:3333b6066adf 1169 *
aungriah 0:3333b6066adf 1170 * output parameters
aungriah 0:3333b6066adf 1171 *
aungriah 0:3333b6066adf 1172 * no return value
aungriah 0:3333b6066adf 1173 */
aungriah 0:3333b6066adf 1174 void dwt_setpanid(uint16 panID)
aungriah 0:3333b6066adf 1175 {
aungriah 0:3333b6066adf 1176 // PAN ID is high 16 bits of register
aungriah 0:3333b6066adf 1177 dwt_write16bitoffsetreg(PANADR_ID, PANADR_PAN_ID_OFFSET, panID);
aungriah 0:3333b6066adf 1178 }
aungriah 0:3333b6066adf 1179
aungriah 0:3333b6066adf 1180 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1181 * @fn dwt_setaddress16()
aungriah 0:3333b6066adf 1182 *
aungriah 0:3333b6066adf 1183 * @brief This is used to set 16-bit (short) address
aungriah 0:3333b6066adf 1184 *
aungriah 0:3333b6066adf 1185 * input parameters
aungriah 0:3333b6066adf 1186 * @param shortAddress - this sets the 16 bit short address
aungriah 0:3333b6066adf 1187 *
aungriah 0:3333b6066adf 1188 * output parameters
aungriah 0:3333b6066adf 1189 *
aungriah 0:3333b6066adf 1190 * no return value
aungriah 0:3333b6066adf 1191 */
aungriah 0:3333b6066adf 1192 void dwt_setaddress16(uint16 shortAddress)
aungriah 0:3333b6066adf 1193 {
aungriah 0:3333b6066adf 1194 // Short address into low 16 bits
aungriah 0:3333b6066adf 1195 dwt_write16bitoffsetreg(PANADR_ID, PANADR_SHORT_ADDR_OFFSET, shortAddress);
aungriah 0:3333b6066adf 1196 }
aungriah 0:3333b6066adf 1197
aungriah 0:3333b6066adf 1198 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1199 * @fn dwt_seteui()
aungriah 0:3333b6066adf 1200 *
aungriah 0:3333b6066adf 1201 * @brief This is used to set the EUI 64-bit (long) address
aungriah 0:3333b6066adf 1202 *
aungriah 0:3333b6066adf 1203 * input parameters
aungriah 0:3333b6066adf 1204 * @param eui64 - this is the pointer to a buffer that contains the 64bit address
aungriah 0:3333b6066adf 1205 *
aungriah 0:3333b6066adf 1206 * output parameters
aungriah 0:3333b6066adf 1207 *
aungriah 0:3333b6066adf 1208 * no return value
aungriah 0:3333b6066adf 1209 */
aungriah 0:3333b6066adf 1210 void dwt_seteui(uint8 *eui64)
aungriah 0:3333b6066adf 1211 {
aungriah 0:3333b6066adf 1212 dwt_writetodevice(EUI_64_ID, EUI_64_OFFSET, EUI_64_LEN, eui64);
aungriah 0:3333b6066adf 1213 }
aungriah 0:3333b6066adf 1214
aungriah 0:3333b6066adf 1215 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1216 * @fn dwt_geteui()
aungriah 0:3333b6066adf 1217 *
aungriah 0:3333b6066adf 1218 * @brief This is used to get the EUI 64-bit from the DW1000
aungriah 0:3333b6066adf 1219 *
aungriah 0:3333b6066adf 1220 * input parameters
aungriah 0:3333b6066adf 1221 * @param eui64 - this is the pointer to a buffer that will contain the read 64-bit EUI value
aungriah 0:3333b6066adf 1222 *
aungriah 0:3333b6066adf 1223 * output parameters
aungriah 0:3333b6066adf 1224 *
aungriah 0:3333b6066adf 1225 * no return value
aungriah 0:3333b6066adf 1226 */
aungriah 0:3333b6066adf 1227 void dwt_geteui(uint8 *eui64)
aungriah 0:3333b6066adf 1228 {
aungriah 0:3333b6066adf 1229 dwt_readfromdevice(EUI_64_ID, EUI_64_OFFSET, EUI_64_LEN, eui64);
aungriah 0:3333b6066adf 1230 }
aungriah 0:3333b6066adf 1231
aungriah 0:3333b6066adf 1232 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1233 * @fn dwt_otpread()
aungriah 0:3333b6066adf 1234 *
aungriah 0:3333b6066adf 1235 * @brief This is used to read the OTP data from given address into provided array
aungriah 0:3333b6066adf 1236 *
aungriah 0:3333b6066adf 1237 * input parameters
aungriah 0:3333b6066adf 1238 * @param address - this is the OTP address to read from
aungriah 0:3333b6066adf 1239 * @param array - this is the pointer to the array into which to read the data
aungriah 0:3333b6066adf 1240 * @param length - this is the number of 32 bit words to read (array needs to be at least this length)
aungriah 0:3333b6066adf 1241 *
aungriah 0:3333b6066adf 1242 * output parameters
aungriah 0:3333b6066adf 1243 *
aungriah 0:3333b6066adf 1244 * no return value
aungriah 0:3333b6066adf 1245 */
aungriah 0:3333b6066adf 1246 void dwt_otpread(uint32 address, uint32 *array, uint8 length)
aungriah 0:3333b6066adf 1247 {
aungriah 0:3333b6066adf 1248 int i;
aungriah 0:3333b6066adf 1249
aungriah 0:3333b6066adf 1250 _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: Set system clock to XTAL - this is necessary to make sure the values read by _dwt_otpread are reliable
aungriah 0:3333b6066adf 1251
aungriah 0:3333b6066adf 1252 for(i=0; i<length; i++)
aungriah 0:3333b6066adf 1253 {
aungriah 0:3333b6066adf 1254 array[i] = _dwt_otpread(address + i) ;
aungriah 0:3333b6066adf 1255 }
aungriah 0:3333b6066adf 1256
aungriah 0:3333b6066adf 1257 _dwt_enableclocks(ENABLE_ALL_SEQ); // Restore system clock to PLL
aungriah 0:3333b6066adf 1258
aungriah 0:3333b6066adf 1259 return ;
aungriah 0:3333b6066adf 1260 }
aungriah 0:3333b6066adf 1261
aungriah 0:3333b6066adf 1262 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1263 * @fn _dwt_otpread()
aungriah 0:3333b6066adf 1264 *
aungriah 0:3333b6066adf 1265 * @brief function to read the OTP memory. Ensure that MR,MRa,MRb are reset to 0.
aungriah 0:3333b6066adf 1266 *
aungriah 0:3333b6066adf 1267 * input parameters
aungriah 0:3333b6066adf 1268 * @param address - address to read at
aungriah 0:3333b6066adf 1269 *
aungriah 0:3333b6066adf 1270 * output parameters
aungriah 0:3333b6066adf 1271 *
aungriah 0:3333b6066adf 1272 * returns the 32bit of read data
aungriah 0:3333b6066adf 1273 */
aungriah 0:3333b6066adf 1274 uint32 _dwt_otpread(uint32 address)
aungriah 0:3333b6066adf 1275 {
aungriah 0:3333b6066adf 1276 uint32 ret_data;
aungriah 0:3333b6066adf 1277
aungriah 0:3333b6066adf 1278 // Write the address
aungriah 0:3333b6066adf 1279 dwt_write16bitoffsetreg(OTP_IF_ID, OTP_ADDR, address);
aungriah 0:3333b6066adf 1280
aungriah 0:3333b6066adf 1281 // Perform OTP Read - Manual read mode has to be set
aungriah 0:3333b6066adf 1282 dwt_write8bitoffsetreg(OTP_IF_ID, OTP_CTRL, OTP_CTRL_OTPREAD | OTP_CTRL_OTPRDEN);
aungriah 0:3333b6066adf 1283 dwt_write8bitoffsetreg(OTP_IF_ID, OTP_CTRL, 0x00); // OTPREAD is self clearing but OTPRDEN is not
aungriah 0:3333b6066adf 1284
aungriah 0:3333b6066adf 1285 // Read read data, available 40ns after rising edge of OTP_READ
aungriah 0:3333b6066adf 1286 ret_data = dwt_read32bitoffsetreg(OTP_IF_ID, OTP_RDAT);
aungriah 0:3333b6066adf 1287
aungriah 0:3333b6066adf 1288 // Return the 32bit of read data
aungriah 0:3333b6066adf 1289 return ret_data;
aungriah 0:3333b6066adf 1290 }
aungriah 0:3333b6066adf 1291
aungriah 0:3333b6066adf 1292 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1293 * @fn _dwt_otpsetmrregs()
aungriah 0:3333b6066adf 1294 *
aungriah 0:3333b6066adf 1295 * @brief Configure the MR registers for initial programming (enable charge pump).
aungriah 0:3333b6066adf 1296 * Read margin is used to stress the read back from the
aungriah 0:3333b6066adf 1297 * programmed bit. In normal operation this is relaxed.
aungriah 0:3333b6066adf 1298 *
aungriah 0:3333b6066adf 1299 * input parameters
aungriah 0:3333b6066adf 1300 * @param mode - "0" : Reset all to 0x0: MRA=0x0000, MRB=0x0000, MR=0x0000
aungriah 0:3333b6066adf 1301 * "1" : Set for inital programming: MRA=0x9220, MRB=0x000E, MR=0x1024
aungriah 0:3333b6066adf 1302 * "2" : Set for soak programming: MRA=0x9220, MRB=0x0003, MR=0x1824
aungriah 0:3333b6066adf 1303 * "3" : High Vpp: MRA=0x9220, MRB=0x004E, MR=0x1824
aungriah 0:3333b6066adf 1304 * "4" : Low Read Margin: MRA=0x0000, MRB=0x0003, MR=0x0000
aungriah 0:3333b6066adf 1305 * "5" : Array Clean: MRA=0x0049, MRB=0x0003, MR=0x0024
aungriah 0:3333b6066adf 1306 * "4" : Very Low Read Margin: MRA=0x0000, MRB=0x0003, MR=0x0000
aungriah 0:3333b6066adf 1307 *
aungriah 0:3333b6066adf 1308 * output parameters
aungriah 0:3333b6066adf 1309 *
aungriah 0:3333b6066adf 1310 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:3333b6066adf 1311 */
aungriah 0:3333b6066adf 1312 uint32 _dwt_otpsetmrregs(int mode)
aungriah 0:3333b6066adf 1313 {
aungriah 0:3333b6066adf 1314 uint8 rd_buf[4];
aungriah 0:3333b6066adf 1315 uint8 wr_buf[4];
aungriah 0:3333b6066adf 1316 uint32 mra=0,mrb=0,mr=0;
aungriah 0:3333b6066adf 1317
aungriah 0:3333b6066adf 1318 // PROGRAMME MRA
aungriah 0:3333b6066adf 1319 // Set MRA, MODE_SEL
aungriah 0:3333b6066adf 1320 wr_buf[0] = 0x03;
aungriah 0:3333b6066adf 1321 dwt_writetodevice(OTP_IF_ID, OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1322
aungriah 0:3333b6066adf 1323 // Load data
aungriah 0:3333b6066adf 1324 switch(mode&0x0f) {
aungriah 0:3333b6066adf 1325 case 0x0 :
aungriah 0:3333b6066adf 1326 mr =0x0000;
aungriah 0:3333b6066adf 1327 mra=0x0000;
aungriah 0:3333b6066adf 1328 mrb=0x0000;
aungriah 0:3333b6066adf 1329 break;
aungriah 0:3333b6066adf 1330 case 0x1 :
aungriah 0:3333b6066adf 1331 mr =0x1024;
aungriah 0:3333b6066adf 1332 mra=0x9220; // Enable CPP mon
aungriah 0:3333b6066adf 1333 mrb=0x000e;
aungriah 0:3333b6066adf 1334 break;
aungriah 0:3333b6066adf 1335 case 0x2 :
aungriah 0:3333b6066adf 1336 mr =0x1824;
aungriah 0:3333b6066adf 1337 mra=0x9220;
aungriah 0:3333b6066adf 1338 mrb=0x0003;
aungriah 0:3333b6066adf 1339 break;
aungriah 0:3333b6066adf 1340 case 0x3 :
aungriah 0:3333b6066adf 1341 mr =0x1824;
aungriah 0:3333b6066adf 1342 mra=0x9220;
aungriah 0:3333b6066adf 1343 mrb=0x004e;
aungriah 0:3333b6066adf 1344 break;
aungriah 0:3333b6066adf 1345 case 0x4 :
aungriah 0:3333b6066adf 1346 mr =0x0000;
aungriah 0:3333b6066adf 1347 mra=0x0000;
aungriah 0:3333b6066adf 1348 mrb=0x0003;
aungriah 0:3333b6066adf 1349 break;
aungriah 0:3333b6066adf 1350 case 0x5 :
aungriah 0:3333b6066adf 1351 mr =0x0024;
aungriah 0:3333b6066adf 1352 mra=0x0000;
aungriah 0:3333b6066adf 1353 mrb=0x0003;
aungriah 0:3333b6066adf 1354 break;
aungriah 0:3333b6066adf 1355 default :
aungriah 0:3333b6066adf 1356 return DWT_ERROR;
aungriah 0:3333b6066adf 1357 }
aungriah 0:3333b6066adf 1358
aungriah 0:3333b6066adf 1359 wr_buf[0] = mra & 0x00ff;
aungriah 0:3333b6066adf 1360 wr_buf[1] = (mra & 0xff00)>>8;
aungriah 0:3333b6066adf 1361 dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
aungriah 0:3333b6066adf 1362
aungriah 0:3333b6066adf 1363
aungriah 0:3333b6066adf 1364 // Set WRITE_MR
aungriah 0:3333b6066adf 1365 wr_buf[0] = 0x08;
aungriah 0:3333b6066adf 1366 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1367
aungriah 0:3333b6066adf 1368 // Wait?
aungriah 0:3333b6066adf 1369
aungriah 0:3333b6066adf 1370 // Set Clear Mode sel
aungriah 0:3333b6066adf 1371 wr_buf[0] = 0x02;
aungriah 0:3333b6066adf 1372 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1373
aungriah 0:3333b6066adf 1374 // Set AUX update, write MR
aungriah 0:3333b6066adf 1375 wr_buf[0] = 0x88;
aungriah 0:3333b6066adf 1376 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1377 // Clear write MR
aungriah 0:3333b6066adf 1378 wr_buf[0] = 0x80;
aungriah 0:3333b6066adf 1379 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1380 // Clear AUX update
aungriah 0:3333b6066adf 1381 wr_buf[0] = 0x00;
aungriah 0:3333b6066adf 1382 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1383
aungriah 0:3333b6066adf 1384 ///////////////////////////////////////////
aungriah 0:3333b6066adf 1385 // PROGRAM MRB
aungriah 0:3333b6066adf 1386 // Set SLOW, MRB, MODE_SEL
aungriah 0:3333b6066adf 1387 wr_buf[0] = 0x05;
aungriah 0:3333b6066adf 1388 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1389
aungriah 0:3333b6066adf 1390 wr_buf[0] = mrb & 0x00ff;
aungriah 0:3333b6066adf 1391 wr_buf[1] = (mrb & 0xff00)>>8;
aungriah 0:3333b6066adf 1392 dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
aungriah 0:3333b6066adf 1393
aungriah 0:3333b6066adf 1394 // Set WRITE_MR
aungriah 0:3333b6066adf 1395 wr_buf[0] = 0x08;
aungriah 0:3333b6066adf 1396 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1397
aungriah 0:3333b6066adf 1398 // Wait?
aungriah 0:3333b6066adf 1399
aungriah 0:3333b6066adf 1400 // Set Clear Mode sel
aungriah 0:3333b6066adf 1401 wr_buf[0] = 0x04;
aungriah 0:3333b6066adf 1402 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1403
aungriah 0:3333b6066adf 1404 // Set AUX update, write MR
aungriah 0:3333b6066adf 1405 wr_buf[0] = 0x88;
aungriah 0:3333b6066adf 1406 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1407 // Clear write MR
aungriah 0:3333b6066adf 1408 wr_buf[0] = 0x80;
aungriah 0:3333b6066adf 1409 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1410 // Clear AUX update
aungriah 0:3333b6066adf 1411 wr_buf[0] = 0x00;
aungriah 0:3333b6066adf 1412 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1413
aungriah 0:3333b6066adf 1414 ///////////////////////////////////////////
aungriah 0:3333b6066adf 1415 // PROGRAM MR
aungriah 0:3333b6066adf 1416 // Set SLOW, MODE_SEL
aungriah 0:3333b6066adf 1417 wr_buf[0] = 0x01;
aungriah 0:3333b6066adf 1418 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1419 // Load data
aungriah 0:3333b6066adf 1420
aungriah 0:3333b6066adf 1421 wr_buf[0] = mr & 0x00ff;
aungriah 0:3333b6066adf 1422 wr_buf[1] = (mr & 0xff00)>>8;
aungriah 0:3333b6066adf 1423 dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
aungriah 0:3333b6066adf 1424
aungriah 0:3333b6066adf 1425 // Set WRITE_MR
aungriah 0:3333b6066adf 1426 wr_buf[0] = 0x08;
aungriah 0:3333b6066adf 1427 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1428
aungriah 0:3333b6066adf 1429 // Wait?
aungriah 0:3333b6066adf 1430 deca_sleep(10);
aungriah 0:3333b6066adf 1431 // Set Clear Mode sel
aungriah 0:3333b6066adf 1432 wr_buf[0] = 0x00;
aungriah 0:3333b6066adf 1433 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1434
aungriah 0:3333b6066adf 1435 // Read confirm mode writes.
aungriah 0:3333b6066adf 1436 // Set man override, MRA_SEL
aungriah 0:3333b6066adf 1437 wr_buf[0] = OTP_CTRL_OTPRDEN;
aungriah 0:3333b6066adf 1438 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1439 wr_buf[0] = 0x02;
aungriah 0:3333b6066adf 1440 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1441 // MRB_SEL
aungriah 0:3333b6066adf 1442 wr_buf[0] = 0x04;
aungriah 0:3333b6066adf 1443 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1444 deca_sleep(100);
aungriah 0:3333b6066adf 1445
aungriah 0:3333b6066adf 1446 // Clear mode sel
aungriah 0:3333b6066adf 1447 wr_buf[0] = 0x00;
aungriah 0:3333b6066adf 1448 dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
aungriah 0:3333b6066adf 1449 // Clear MAN_OVERRIDE
aungriah 0:3333b6066adf 1450 wr_buf[0] = 0x00;
aungriah 0:3333b6066adf 1451 dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
aungriah 0:3333b6066adf 1452
aungriah 0:3333b6066adf 1453 deca_sleep(10);
aungriah 0:3333b6066adf 1454
aungriah 0:3333b6066adf 1455 if (((mode&0x0f) == 0x1)||((mode&0x0f) == 0x2))
aungriah 0:3333b6066adf 1456 {
aungriah 0:3333b6066adf 1457 // Read status register
aungriah 0:3333b6066adf 1458 dwt_readfromdevice(OTP_IF_ID, OTP_STAT,1,rd_buf);
aungriah 0:3333b6066adf 1459 }
aungriah 0:3333b6066adf 1460
aungriah 0:3333b6066adf 1461 return DWT_SUCCESS;
aungriah 0:3333b6066adf 1462 }
aungriah 0:3333b6066adf 1463
aungriah 0:3333b6066adf 1464 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1465 * @fn _dwt_otpprogword32()
aungriah 0:3333b6066adf 1466 *
aungriah 0:3333b6066adf 1467 * @brief function to program the OTP memory. Ensure that MR,MRa,MRb are reset to 0.
aungriah 0:3333b6066adf 1468 * VNM Charge pump needs to be enabled (see _dwt_otpsetmrregs)
aungriah 0:3333b6066adf 1469 * Note the address is only 11 bits long.
aungriah 0:3333b6066adf 1470 *
aungriah 0:3333b6066adf 1471 * input parameters
aungriah 0:3333b6066adf 1472 * @param address - address to read at
aungriah 0:3333b6066adf 1473 *
aungriah 0:3333b6066adf 1474 * output parameters
aungriah 0:3333b6066adf 1475 *
aungriah 0:3333b6066adf 1476 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:3333b6066adf 1477 */
aungriah 0:3333b6066adf 1478 uint32 _dwt_otpprogword32(uint32 data, uint16 address)
aungriah 0:3333b6066adf 1479 {
aungriah 0:3333b6066adf 1480 uint8 rd_buf[1];
aungriah 0:3333b6066adf 1481 uint8 wr_buf[4];
aungriah 0:3333b6066adf 1482 uint8 otp_done;
aungriah 0:3333b6066adf 1483
aungriah 0:3333b6066adf 1484 // Read status register
aungriah 0:3333b6066adf 1485 dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
aungriah 0:3333b6066adf 1486
aungriah 0:3333b6066adf 1487 if((rd_buf[0] & 0x02) != 0x02)
aungriah 0:3333b6066adf 1488 {
aungriah 0:3333b6066adf 1489 return DWT_ERROR;
aungriah 0:3333b6066adf 1490 }
aungriah 0:3333b6066adf 1491
aungriah 0:3333b6066adf 1492 // Write the data
aungriah 0:3333b6066adf 1493 wr_buf[3] = (data>>24) & 0xff;
aungriah 0:3333b6066adf 1494 wr_buf[2] = (data>>16) & 0xff;
aungriah 0:3333b6066adf 1495 wr_buf[1] = (data>>8) & 0xff;
aungriah 0:3333b6066adf 1496 wr_buf[0] = data & 0xff;
aungriah 0:3333b6066adf 1497 dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 4, wr_buf);
aungriah 0:3333b6066adf 1498
aungriah 0:3333b6066adf 1499 // Write the address [10:0]
aungriah 0:3333b6066adf 1500 wr_buf[1] = (address>>8) & 0x07;
aungriah 0:3333b6066adf 1501 wr_buf[0] = address & 0xff;
aungriah 0:3333b6066adf 1502 dwt_writetodevice(OTP_IF_ID, OTP_ADDR, 2, wr_buf);
aungriah 0:3333b6066adf 1503
aungriah 0:3333b6066adf 1504 // Enable Sequenced programming
aungriah 0:3333b6066adf 1505 wr_buf[0] = OTP_CTRL_OTPPROG;
aungriah 0:3333b6066adf 1506 dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
aungriah 0:3333b6066adf 1507 wr_buf[0] = 0x00; // And clear
aungriah 0:3333b6066adf 1508 dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
aungriah 0:3333b6066adf 1509
aungriah 0:3333b6066adf 1510 // WAIT for status to flag PRGM OK..
aungriah 0:3333b6066adf 1511 otp_done = 0;
aungriah 0:3333b6066adf 1512 while(otp_done == 0)
aungriah 0:3333b6066adf 1513 {
aungriah 0:3333b6066adf 1514 deca_sleep(1);
aungriah 0:3333b6066adf 1515 dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
aungriah 0:3333b6066adf 1516
aungriah 0:3333b6066adf 1517 if((rd_buf[0] & 0x01) == 0x01)
aungriah 0:3333b6066adf 1518 {
aungriah 0:3333b6066adf 1519 otp_done = 1;
aungriah 0:3333b6066adf 1520 }
aungriah 0:3333b6066adf 1521 }
aungriah 0:3333b6066adf 1522
aungriah 0:3333b6066adf 1523 return DWT_SUCCESS;
aungriah 0:3333b6066adf 1524 }
aungriah 0:3333b6066adf 1525
aungriah 0:3333b6066adf 1526 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1527 * @fn dwt_otpwriteandverify()
aungriah 0:3333b6066adf 1528 *
aungriah 0:3333b6066adf 1529 * @brief This is used to program 32-bit value into the DW1000 OTP memory.
aungriah 0:3333b6066adf 1530 *
aungriah 0:3333b6066adf 1531 * input parameters
aungriah 0:3333b6066adf 1532 * @param value - this is the 32-bit value to be programmed into OTP
aungriah 0:3333b6066adf 1533 * @param address - this is the 16-bit OTP address into which the 32-bit value is programmed
aungriah 0:3333b6066adf 1534 *
aungriah 0:3333b6066adf 1535 * output parameters
aungriah 0:3333b6066adf 1536 *
aungriah 0:3333b6066adf 1537 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:3333b6066adf 1538 */
aungriah 0:3333b6066adf 1539 uint32 dwt_otpwriteandverify(uint32 value, uint16 address)
aungriah 0:3333b6066adf 1540 {
aungriah 0:3333b6066adf 1541 int prog_ok = DWT_SUCCESS;
aungriah 0:3333b6066adf 1542 int retry = 0;
aungriah 0:3333b6066adf 1543 // Firstly set the system clock to crystal
aungriah 0:3333b6066adf 1544 _dwt_enableclocks(FORCE_SYS_XTI); //set system clock to XTI
aungriah 0:3333b6066adf 1545
aungriah 0:3333b6066adf 1546 //
aungriah 0:3333b6066adf 1547 //!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!
aungriah 0:3333b6066adf 1548 //Set the supply to 3.7V
aungriah 0:3333b6066adf 1549 //
aungriah 0:3333b6066adf 1550
aungriah 0:3333b6066adf 1551 _dwt_otpsetmrregs(1); // Set mode for programming
aungriah 0:3333b6066adf 1552
aungriah 0:3333b6066adf 1553 // For each value to program - the readback/check is done couple of times to verify it has programmed successfully
aungriah 0:3333b6066adf 1554 while(1)
aungriah 0:3333b6066adf 1555 {
aungriah 0:3333b6066adf 1556 _dwt_otpprogword32(value, address);
aungriah 0:3333b6066adf 1557
aungriah 0:3333b6066adf 1558 if(_dwt_otpread(address) == value)
aungriah 0:3333b6066adf 1559 {
aungriah 0:3333b6066adf 1560 break;
aungriah 0:3333b6066adf 1561 }
aungriah 0:3333b6066adf 1562 retry++;
aungriah 0:3333b6066adf 1563 if(retry==5)
aungriah 0:3333b6066adf 1564 {
aungriah 0:3333b6066adf 1565 break;
aungriah 0:3333b6066adf 1566 }
aungriah 0:3333b6066adf 1567 }
aungriah 0:3333b6066adf 1568
aungriah 0:3333b6066adf 1569 // Even if the above does not exit before retry reaches 5, the programming has probably been successful
aungriah 0:3333b6066adf 1570
aungriah 0:3333b6066adf 1571 _dwt_otpsetmrregs(4); // Set mode for reading
aungriah 0:3333b6066adf 1572
aungriah 0:3333b6066adf 1573 if(_dwt_otpread(address) != value) // If this does not pass please check voltage supply on VDDIO
aungriah 0:3333b6066adf 1574 {
aungriah 0:3333b6066adf 1575 prog_ok = DWT_ERROR;
aungriah 0:3333b6066adf 1576 }
aungriah 0:3333b6066adf 1577
aungriah 0:3333b6066adf 1578 _dwt_otpsetmrregs(0); // Setting OTP mode register for low RM read - resetting the device would be alternative
aungriah 0:3333b6066adf 1579
aungriah 0:3333b6066adf 1580 return prog_ok;
aungriah 0:3333b6066adf 1581 }
aungriah 0:3333b6066adf 1582
aungriah 0:3333b6066adf 1583 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1584 * @fn _dwt_aonconfigupload()
aungriah 0:3333b6066adf 1585 *
aungriah 0:3333b6066adf 1586 * @brief This function uploads always on (AON) configuration, as set in the AON_CFG0_OFFSET register.
aungriah 0:3333b6066adf 1587 *
aungriah 0:3333b6066adf 1588 * input parameters
aungriah 0:3333b6066adf 1589 *
aungriah 0:3333b6066adf 1590 * output parameters
aungriah 0:3333b6066adf 1591 *
aungriah 0:3333b6066adf 1592 * no return value
aungriah 0:3333b6066adf 1593 */
aungriah 0:3333b6066adf 1594 void _dwt_aonconfigupload(void)
aungriah 0:3333b6066adf 1595 {
aungriah 0:3333b6066adf 1596 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_UPL_CFG);
aungriah 0:3333b6066adf 1597 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00); // Clear the register
aungriah 0:3333b6066adf 1598 }
aungriah 0:3333b6066adf 1599
aungriah 0:3333b6066adf 1600 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1601 * @fn _dwt_aonarrayupload()
aungriah 0:3333b6066adf 1602 *
aungriah 0:3333b6066adf 1603 * @brief This function uploads always on (AON) data array and configuration. Thus if this function is used, then _dwt_aonconfigupload
aungriah 0:3333b6066adf 1604 * is not necessary. The DW1000 will go so SLEEP straight after this if the DWT_SLP_EN has been set.
aungriah 0:3333b6066adf 1605 *
aungriah 0:3333b6066adf 1606 * input parameters
aungriah 0:3333b6066adf 1607 *
aungriah 0:3333b6066adf 1608 * output parameters
aungriah 0:3333b6066adf 1609 *
aungriah 0:3333b6066adf 1610 * no return value
aungriah 0:3333b6066adf 1611 */
aungriah 0:3333b6066adf 1612 void _dwt_aonarrayupload(void)
aungriah 0:3333b6066adf 1613 {
aungriah 0:3333b6066adf 1614 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00); // Clear the register
aungriah 0:3333b6066adf 1615 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_SAVE);
aungriah 0:3333b6066adf 1616 }
aungriah 0:3333b6066adf 1617
aungriah 0:3333b6066adf 1618 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1619 * @fn dwt_entersleep()
aungriah 0:3333b6066adf 1620 *
aungriah 0:3333b6066adf 1621 * @brief This function puts the device into deep sleep or sleep. dwt_configuresleep() should be called first
aungriah 0:3333b6066adf 1622 * to configure the sleep and on-wake/wake-up parameters
aungriah 0:3333b6066adf 1623 *
aungriah 0:3333b6066adf 1624 * input parameters
aungriah 0:3333b6066adf 1625 *
aungriah 0:3333b6066adf 1626 * output parameters
aungriah 0:3333b6066adf 1627 *
aungriah 0:3333b6066adf 1628 * no return value
aungriah 0:3333b6066adf 1629 */
aungriah 0:3333b6066adf 1630 void dwt_entersleep(void)
aungriah 0:3333b6066adf 1631 {
aungriah 0:3333b6066adf 1632 // Copy config to AON - upload the new configuration
aungriah 0:3333b6066adf 1633 _dwt_aonarrayupload();
aungriah 0:3333b6066adf 1634 }
aungriah 0:3333b6066adf 1635
aungriah 0:3333b6066adf 1636 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1637 * @fn dwt_configuresleepcnt()
aungriah 0:3333b6066adf 1638 *
aungriah 0:3333b6066adf 1639 * @brief sets the sleep counter to new value, this function programs the high 16-bits of the 28-bit counter
aungriah 0:3333b6066adf 1640 *
aungriah 0:3333b6066adf 1641 * NOTE: this function needs to be run before dwt_configuresleep, also the SPI frequency has to be < 3MHz
aungriah 0:3333b6066adf 1642 *
aungriah 0:3333b6066adf 1643 * input parameters
aungriah 0:3333b6066adf 1644 * @param sleepcnt - this it value of the sleep counter to program
aungriah 0:3333b6066adf 1645 *
aungriah 0:3333b6066adf 1646 * output parameters
aungriah 0:3333b6066adf 1647 *
aungriah 0:3333b6066adf 1648 * no return value
aungriah 0:3333b6066adf 1649 */
aungriah 0:3333b6066adf 1650 void dwt_configuresleepcnt(uint16 sleepcnt)
aungriah 0:3333b6066adf 1651 {
aungriah 0:3333b6066adf 1652 // Force system clock to crystal
aungriah 0:3333b6066adf 1653 _dwt_enableclocks(FORCE_SYS_XTI);
aungriah 0:3333b6066adf 1654
aungriah 0:3333b6066adf 1655 // Reset sleep configuration to make sure we don't accidentally go to sleep
aungriah 0:3333b6066adf 1656 dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, 0x00); // NB: this write change the default LPCLKDIVA value which is not used anyway.
aungriah 0:3333b6066adf 1657 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
aungriah 0:3333b6066adf 1658
aungriah 0:3333b6066adf 1659 // Disable the sleep counter
aungriah 0:3333b6066adf 1660 _dwt_aonconfigupload();
aungriah 0:3333b6066adf 1661
aungriah 0:3333b6066adf 1662 // Set new value
aungriah 0:3333b6066adf 1663 dwt_write16bitoffsetreg(AON_ID, AON_CFG0_OFFSET + AON_CFG0_SLEEP_TIM_OFFSET, sleepcnt);
aungriah 0:3333b6066adf 1664 _dwt_aonconfigupload();
aungriah 0:3333b6066adf 1665
aungriah 0:3333b6066adf 1666 // Enable the sleep counter
aungriah 0:3333b6066adf 1667 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, AON_CFG1_SLEEP_CEN);
aungriah 0:3333b6066adf 1668 _dwt_aonconfigupload();
aungriah 0:3333b6066adf 1669
aungriah 0:3333b6066adf 1670 // Put system PLL back on
aungriah 0:3333b6066adf 1671 _dwt_enableclocks(ENABLE_ALL_SEQ);
aungriah 0:3333b6066adf 1672 }
aungriah 0:3333b6066adf 1673
aungriah 0:3333b6066adf 1674
aungriah 0:3333b6066adf 1675 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1676 * @fn dwt_calibratesleepcnt()
aungriah 0:3333b6066adf 1677 *
aungriah 0:3333b6066adf 1678 * @brief calibrates the local oscillator as its frequency can vary between 7 and 13kHz depending on temp and voltage
aungriah 0:3333b6066adf 1679 *
aungriah 0:3333b6066adf 1680 * NOTE: this function needs to be run before dwt_configuresleepcnt, so that we know what the counter units are
aungriah 0:3333b6066adf 1681 *
aungriah 0:3333b6066adf 1682 * input parameters
aungriah 0:3333b6066adf 1683 *
aungriah 0:3333b6066adf 1684 * output parameters
aungriah 0:3333b6066adf 1685 *
aungriah 0:3333b6066adf 1686 * returns the number of XTAL/2 cycles per low-power oscillator cycle. LP OSC frequency = 19.2 MHz/return value
aungriah 0:3333b6066adf 1687 */
aungriah 0:3333b6066adf 1688 uint16 dwt_calibratesleepcnt(void)
aungriah 0:3333b6066adf 1689 {
aungriah 0:3333b6066adf 1690 uint16 result;
aungriah 0:3333b6066adf 1691
aungriah 0:3333b6066adf 1692 // Enable calibration of the sleep counter
aungriah 0:3333b6066adf 1693 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, AON_CFG1_LPOSC_CAL);
aungriah 0:3333b6066adf 1694 _dwt_aonconfigupload();
aungriah 0:3333b6066adf 1695
aungriah 0:3333b6066adf 1696 // Disable calibration of the sleep counter
aungriah 0:3333b6066adf 1697 dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
aungriah 0:3333b6066adf 1698 _dwt_aonconfigupload();
aungriah 0:3333b6066adf 1699
aungriah 0:3333b6066adf 1700 // Force system clock to crystal
aungriah 0:3333b6066adf 1701 _dwt_enableclocks(FORCE_SYS_XTI);
aungriah 0:3333b6066adf 1702
aungriah 0:3333b6066adf 1703 deca_sleep(1);
aungriah 0:3333b6066adf 1704
aungriah 0:3333b6066adf 1705 // Read the number of XTAL/2 cycles one LP oscillator cycle took.
aungriah 0:3333b6066adf 1706 // Set up address - Read upper byte first
aungriah 0:3333b6066adf 1707 dwt_write8bitoffsetreg(AON_ID, AON_ADDR_OFFSET, AON_ADDR_LPOSC_CAL_1);
aungriah 0:3333b6066adf 1708
aungriah 0:3333b6066adf 1709 // Enable manual override
aungriah 0:3333b6066adf 1710 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB);
aungriah 0:3333b6066adf 1711
aungriah 0:3333b6066adf 1712 // Read confirm data that was written
aungriah 0:3333b6066adf 1713 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB | AON_CTRL_DCA_READ);
aungriah 0:3333b6066adf 1714
aungriah 0:3333b6066adf 1715 // Read back byte from AON
aungriah 0:3333b6066adf 1716 result = dwt_read8bitoffsetreg(AON_ID, AON_RDAT_OFFSET);
aungriah 0:3333b6066adf 1717 result <<= 8;
aungriah 0:3333b6066adf 1718
aungriah 0:3333b6066adf 1719 // Set up address - Read lower byte
aungriah 0:3333b6066adf 1720 dwt_write8bitoffsetreg(AON_ID, AON_ADDR_OFFSET, AON_ADDR_LPOSC_CAL_0);
aungriah 0:3333b6066adf 1721
aungriah 0:3333b6066adf 1722 // Enable manual override
aungriah 0:3333b6066adf 1723 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB);
aungriah 0:3333b6066adf 1724
aungriah 0:3333b6066adf 1725 // Read confirm data that was written
aungriah 0:3333b6066adf 1726 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB | AON_CTRL_DCA_READ);
aungriah 0:3333b6066adf 1727
aungriah 0:3333b6066adf 1728 // Read back byte from AON
aungriah 0:3333b6066adf 1729 result |= dwt_read8bitoffsetreg(AON_ID, AON_RDAT_OFFSET);
aungriah 0:3333b6066adf 1730
aungriah 0:3333b6066adf 1731 // Disable manual override
aungriah 0:3333b6066adf 1732 dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00);
aungriah 0:3333b6066adf 1733
aungriah 0:3333b6066adf 1734 // Put system PLL back on
aungriah 0:3333b6066adf 1735 _dwt_enableclocks(ENABLE_ALL_SEQ);
aungriah 0:3333b6066adf 1736
aungriah 0:3333b6066adf 1737 // Returns the number of XTAL/2 cycles per one LP OSC cycle
aungriah 0:3333b6066adf 1738 // This can be converted into LP OSC frequency by 19.2 MHz/result
aungriah 0:3333b6066adf 1739 return result;
aungriah 0:3333b6066adf 1740 }
aungriah 0:3333b6066adf 1741
aungriah 0:3333b6066adf 1742 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1743 * @fn dwt_configuresleep()
aungriah 0:3333b6066adf 1744 *
aungriah 0:3333b6066adf 1745 * @brief configures the device for both DEEP_SLEEP and SLEEP modes, and on-wake mode
aungriah 0:3333b6066adf 1746 * i.e. before entering the sleep, the device should be programmed for TX or RX, then upon "waking up" the TX/RX settings
aungriah 0:3333b6066adf 1747 * will be preserved and the device can immediately perform the desired action TX/RX
aungriah 0:3333b6066adf 1748 *
aungriah 0:3333b6066adf 1749 * NOTE: e.g. Tag operation - after deep sleep, the device needs to just load the TX buffer and send the frame
aungriah 0:3333b6066adf 1750 *
aungriah 0:3333b6066adf 1751 *
aungriah 0:3333b6066adf 1752 * mode: the array and LDE code (OTP/ROM) and LDO tune, and set sleep persist
aungriah 0:3333b6066adf 1753 * DWT_PRESRV_SLEEP 0x0100 - preserve sleep
aungriah 0:3333b6066adf 1754 * DWT_LOADOPSET 0x0080 - load operating parameter set on wakeup
aungriah 0:3333b6066adf 1755 * DWT_CONFIG 0x0040 - download the AON array into the HIF (configuration download)
aungriah 0:3333b6066adf 1756 * DWT_LOADEUI 0x0008
aungriah 0:3333b6066adf 1757 * DWT_GOTORX 0x0002
aungriah 0:3333b6066adf 1758 * DWT_TANDV 0x0001
aungriah 0:3333b6066adf 1759 *
aungriah 0:3333b6066adf 1760 * wake: wake up parameters
aungriah 0:3333b6066adf 1761 * DWT_XTAL_EN 0x10 - keep XTAL running during sleep
aungriah 0:3333b6066adf 1762 * DWT_WAKE_SLPCNT 0x8 - wake up after sleep count
aungriah 0:3333b6066adf 1763 * DWT_WAKE_CS 0x4 - wake up on chip select
aungriah 0:3333b6066adf 1764 * DWT_WAKE_WK 0x2 - wake up on WAKEUP PIN
aungriah 0:3333b6066adf 1765 * DWT_SLP_EN 0x1 - enable sleep/deep sleep functionality
aungriah 0:3333b6066adf 1766 *
aungriah 0:3333b6066adf 1767 * input parameters
aungriah 0:3333b6066adf 1768 * @param mode - config on-wake parameters
aungriah 0:3333b6066adf 1769 * @param wake - config wake up parameters
aungriah 0:3333b6066adf 1770 *
aungriah 0:3333b6066adf 1771 * output parameters
aungriah 0:3333b6066adf 1772 *
aungriah 0:3333b6066adf 1773 * no return value
aungriah 0:3333b6066adf 1774 */
aungriah 0:3333b6066adf 1775 void dwt_configuresleep(uint16 mode, uint8 wake)
aungriah 0:3333b6066adf 1776 {
aungriah 0:3333b6066adf 1777 // Add predefined sleep settings before writing the mode
aungriah 0:3333b6066adf 1778 mode |= dw1000local.sleep_mode;
aungriah 0:3333b6066adf 1779 dwt_write16bitoffsetreg(AON_ID, AON_WCFG_OFFSET, mode);
aungriah 0:3333b6066adf 1780
aungriah 0:3333b6066adf 1781 dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, wake);
aungriah 0:3333b6066adf 1782 }
aungriah 0:3333b6066adf 1783
aungriah 0:3333b6066adf 1784 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1785 * @fn dwt_entersleepaftertx(int enable)
aungriah 0:3333b6066adf 1786 *
aungriah 0:3333b6066adf 1787 * @brief sets the auto TX to sleep bit. This means that after a frame
aungriah 0:3333b6066adf 1788 * transmission the device will enter deep sleep mode. The dwt_configuresleep() function
aungriah 0:3333b6066adf 1789 * needs to be called before this to configure the on-wake settings
aungriah 0:3333b6066adf 1790 *
aungriah 0:3333b6066adf 1791 * NOTE: the IRQ line has to be low/inactive (i.e. no pending events)
aungriah 0:3333b6066adf 1792 *
aungriah 0:3333b6066adf 1793 * input parameters
aungriah 0:3333b6066adf 1794 * @param enable - 1 to configure the device to enter deep sleep after TX, 0 - disables the configuration
aungriah 0:3333b6066adf 1795 *
aungriah 0:3333b6066adf 1796 * output parameters
aungriah 0:3333b6066adf 1797 *
aungriah 0:3333b6066adf 1798 * no return value
aungriah 0:3333b6066adf 1799 */
aungriah 0:3333b6066adf 1800 void dwt_entersleepaftertx(int enable)
aungriah 0:3333b6066adf 1801 {
aungriah 0:3333b6066adf 1802 uint32 reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
aungriah 0:3333b6066adf 1803 // Set the auto TX -> sleep bit
aungriah 0:3333b6066adf 1804 if(enable)
aungriah 0:3333b6066adf 1805 {
aungriah 0:3333b6066adf 1806 reg |= PMSC_CTRL1_ATXSLP;
aungriah 0:3333b6066adf 1807 }
aungriah 0:3333b6066adf 1808 else
aungriah 0:3333b6066adf 1809 {
aungriah 0:3333b6066adf 1810 reg &= ~(PMSC_CTRL1_ATXSLP);
aungriah 0:3333b6066adf 1811 }
aungriah 0:3333b6066adf 1812 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, reg);
aungriah 0:3333b6066adf 1813 }
aungriah 0:3333b6066adf 1814
aungriah 0:3333b6066adf 1815
aungriah 0:3333b6066adf 1816 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1817 * @fn dwt_spicswakeup()
aungriah 0:3333b6066adf 1818 *
aungriah 0:3333b6066adf 1819 * @brief wake up the device from sleep mode using the SPI read,
aungriah 0:3333b6066adf 1820 * the device will wake up on chip select line going low if the line is held low for at least 500us.
aungriah 0:3333b6066adf 1821 * To define the length depending on the time one wants to hold
aungriah 0:3333b6066adf 1822 * the chip select line low, use the following formula:
aungriah 0:3333b6066adf 1823 *
aungriah 0:3333b6066adf 1824 * length (bytes) = time (s) * byte_rate (Hz)
aungriah 0:3333b6066adf 1825 *
aungriah 0:3333b6066adf 1826 * where fastest byte_rate is spi_rate (Hz) / 8 if the SPI is sending the bytes back-to-back.
aungriah 0:3333b6066adf 1827 * To save time and power, a system designer could determine byte_rate value more precisely.
aungriah 0:3333b6066adf 1828 *
aungriah 0:3333b6066adf 1829 * NOTE: Alternatively the device can be waken up with WAKE_UP pin if configured for that operation
aungriah 0:3333b6066adf 1830 *
aungriah 0:3333b6066adf 1831 * input parameters
aungriah 0:3333b6066adf 1832 * @param buff - this is a pointer to the dummy buffer which will be used in the SPI read transaction used for the WAKE UP of the device
aungriah 0:3333b6066adf 1833 * @param length - this is the length of the dummy buffer
aungriah 0:3333b6066adf 1834 *
aungriah 0:3333b6066adf 1835 * output parameters
aungriah 0:3333b6066adf 1836 *
aungriah 0:3333b6066adf 1837 * returns DWT_SUCCESS for success, or DWT_ERROR for error
aungriah 0:3333b6066adf 1838 */
aungriah 0:3333b6066adf 1839 int dwt_spicswakeup(uint8 *buff, uint16 length)
aungriah 0:3333b6066adf 1840 {
aungriah 0:3333b6066adf 1841 if(dwt_readdevid() != DWT_DEVICE_ID) // Device was in deep sleep (the first read fails)
aungriah 0:3333b6066adf 1842 {
aungriah 0:3333b6066adf 1843 // Need to keep chip select line low for at least 500us
aungriah 0:3333b6066adf 1844 dwt_readfromdevice(0x0, 0x0, length, buff); // Do a long read to wake up the chip (hold the chip select low)
aungriah 0:3333b6066adf 1845
aungriah 0:3333b6066adf 1846 // Need 5ms for XTAL to start and stabilise (could wait for PLL lock IRQ status bit !!!)
aungriah 0:3333b6066adf 1847 // NOTE: Polling of the STATUS register is not possible unless frequency is < 3MHz
aungriah 0:3333b6066adf 1848 deca_sleep(5);
aungriah 0:3333b6066adf 1849 }
aungriah 0:3333b6066adf 1850 else
aungriah 0:3333b6066adf 1851 {
aungriah 0:3333b6066adf 1852 return DWT_SUCCESS;
aungriah 0:3333b6066adf 1853 }
aungriah 0:3333b6066adf 1854 // DEBUG - check if still in sleep mode
aungriah 0:3333b6066adf 1855 if(dwt_readdevid() != DWT_DEVICE_ID)
aungriah 0:3333b6066adf 1856 {
aungriah 0:3333b6066adf 1857 return DWT_ERROR;
aungriah 0:3333b6066adf 1858 }
aungriah 0:3333b6066adf 1859
aungriah 0:3333b6066adf 1860 return DWT_SUCCESS;
aungriah 0:3333b6066adf 1861 }
aungriah 0:3333b6066adf 1862
aungriah 0:3333b6066adf 1863 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1864 * @fn _dwt_configlde()
aungriah 0:3333b6066adf 1865 *
aungriah 0:3333b6066adf 1866 * @brief configure LDE algorithm parameters
aungriah 0:3333b6066adf 1867 *
aungriah 0:3333b6066adf 1868 * input parameters
aungriah 0:3333b6066adf 1869 * @param prf - this is the PRF index (0 or 1) 0 corresponds to 16 and 1 to 64 PRF
aungriah 0:3333b6066adf 1870 *
aungriah 0:3333b6066adf 1871 * output parameters
aungriah 0:3333b6066adf 1872 *
aungriah 0:3333b6066adf 1873 * no return value
aungriah 0:3333b6066adf 1874 */
aungriah 0:3333b6066adf 1875 void _dwt_configlde(int prfIndex)
aungriah 0:3333b6066adf 1876 {
aungriah 0:3333b6066adf 1877 dwt_write8bitoffsetreg(LDE_IF_ID, LDE_CFG1_OFFSET, LDE_PARAM1); // 8-bit configuration register
aungriah 0:3333b6066adf 1878
aungriah 0:3333b6066adf 1879 if(prfIndex)
aungriah 0:3333b6066adf 1880 {
aungriah 0:3333b6066adf 1881 dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_64); // 16-bit LDE configuration tuning register
aungriah 0:3333b6066adf 1882 }
aungriah 0:3333b6066adf 1883 else
aungriah 0:3333b6066adf 1884 {
aungriah 0:3333b6066adf 1885 dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_16);
aungriah 0:3333b6066adf 1886 }
aungriah 0:3333b6066adf 1887 }
aungriah 0:3333b6066adf 1888
aungriah 0:3333b6066adf 1889
aungriah 0:3333b6066adf 1890 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1891 * @fn _dwt_loaducodefromrom()
aungriah 0:3333b6066adf 1892 *
aungriah 0:3333b6066adf 1893 * @brief load ucode from OTP MEMORY or ROM
aungriah 0:3333b6066adf 1894 *
aungriah 0:3333b6066adf 1895 * input parameters
aungriah 0:3333b6066adf 1896 *
aungriah 0:3333b6066adf 1897 * output parameters
aungriah 0:3333b6066adf 1898 *
aungriah 0:3333b6066adf 1899 * no return value
aungriah 0:3333b6066adf 1900 */
aungriah 0:3333b6066adf 1901 void _dwt_loaducodefromrom(void)
aungriah 0:3333b6066adf 1902 {
aungriah 0:3333b6066adf 1903 // Set up clocks
aungriah 0:3333b6066adf 1904 _dwt_enableclocks(FORCE_LDE);
aungriah 0:3333b6066adf 1905
aungriah 0:3333b6066adf 1906 // Kick off the LDE load
aungriah 0:3333b6066adf 1907 dwt_write16bitoffsetreg(OTP_IF_ID, OTP_CTRL, OTP_CTRL_LDELOAD); // Set load LDE kick bit
aungriah 0:3333b6066adf 1908
aungriah 0:3333b6066adf 1909 deca_sleep(1); // Allow time for code to upload (should take up to 120 us)
aungriah 0:3333b6066adf 1910
aungriah 0:3333b6066adf 1911 // Default clocks (ENABLE_ALL_SEQ)
aungriah 0:3333b6066adf 1912 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:3333b6066adf 1913 }
aungriah 0:3333b6066adf 1914
aungriah 0:3333b6066adf 1915 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1916 * @fn dwt_loadopsettabfromotp()
aungriah 0:3333b6066adf 1917 *
aungriah 0:3333b6066adf 1918 * @brief This is used to select which Operational Parameter Set table to load from OTP memory
aungriah 0:3333b6066adf 1919 *
aungriah 0:3333b6066adf 1920 * input parameters
aungriah 0:3333b6066adf 1921 * @param ops_sel - Operational Parameter Set table to load:
aungriah 0:3333b6066adf 1922 * DWT_OPSET_64LEN = 0x0 - load the operational parameter set table for 64 length preamble configuration
aungriah 0:3333b6066adf 1923 * DWT_OPSET_TIGHT = 0x1 - load the operational parameter set table for tight xtal offsets (<1ppm)
aungriah 0:3333b6066adf 1924 * DWT_OPSET_DEFLT = 0x2 - load the default operational parameter set table (this is loaded from reset)
aungriah 0:3333b6066adf 1925 *
aungriah 0:3333b6066adf 1926 * output parameters
aungriah 0:3333b6066adf 1927 *
aungriah 0:3333b6066adf 1928 * no return value
aungriah 0:3333b6066adf 1929 */
aungriah 0:3333b6066adf 1930 void dwt_loadopsettabfromotp(uint8 ops_sel)
aungriah 0:3333b6066adf 1931 {
aungriah 0:3333b6066adf 1932 uint16 reg = ((ops_sel << OTP_SF_OPS_SEL_SHFT) & OTP_SF_OPS_SEL_MASK) | OTP_SF_OPS_KICK; // Select defined OPS table and trigger its loading
aungriah 0:3333b6066adf 1933
aungriah 0:3333b6066adf 1934 // Set up clocks
aungriah 0:3333b6066adf 1935 _dwt_enableclocks(FORCE_LDE);
aungriah 0:3333b6066adf 1936
aungriah 0:3333b6066adf 1937 dwt_write16bitoffsetreg(OTP_IF_ID, OTP_SF, reg);
aungriah 0:3333b6066adf 1938
aungriah 0:3333b6066adf 1939 // Default clocks (ENABLE_ALL_SEQ)
aungriah 0:3333b6066adf 1940 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:3333b6066adf 1941
aungriah 0:3333b6066adf 1942 }
aungriah 0:3333b6066adf 1943
aungriah 0:3333b6066adf 1944 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1945 * @fn dwt_setsmarttxpower()
aungriah 0:3333b6066adf 1946 *
aungriah 0:3333b6066adf 1947 * @brief This call enables or disables the smart TX power feature.
aungriah 0:3333b6066adf 1948 *
aungriah 0:3333b6066adf 1949 * input parameters
aungriah 0:3333b6066adf 1950 * @param enable - this enables or disables the TX smart power (1 = enable, 0 = disable)
aungriah 0:3333b6066adf 1951 *
aungriah 0:3333b6066adf 1952 * output parameters
aungriah 0:3333b6066adf 1953 *
aungriah 0:3333b6066adf 1954 * no return value
aungriah 0:3333b6066adf 1955 */
aungriah 0:3333b6066adf 1956 void dwt_setsmarttxpower(int enable)
aungriah 0:3333b6066adf 1957 {
aungriah 0:3333b6066adf 1958 // Config system register
aungriah 0:3333b6066adf 1959 dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
aungriah 0:3333b6066adf 1960
aungriah 0:3333b6066adf 1961 // Disable smart power configuration
aungriah 0:3333b6066adf 1962 if(enable)
aungriah 0:3333b6066adf 1963 {
aungriah 0:3333b6066adf 1964 dw1000local.sysCFGreg &= ~(SYS_CFG_DIS_STXP) ;
aungriah 0:3333b6066adf 1965 }
aungriah 0:3333b6066adf 1966 else
aungriah 0:3333b6066adf 1967 {
aungriah 0:3333b6066adf 1968 dw1000local.sysCFGreg |= SYS_CFG_DIS_STXP ;
aungriah 0:3333b6066adf 1969 }
aungriah 0:3333b6066adf 1970
aungriah 0:3333b6066adf 1971 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:3333b6066adf 1972 }
aungriah 0:3333b6066adf 1973
aungriah 0:3333b6066adf 1974
aungriah 0:3333b6066adf 1975 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1976 * @fn dwt_enableautoack()
aungriah 0:3333b6066adf 1977 *
aungriah 0:3333b6066adf 1978 * @brief This call enables the auto-ACK feature. If the responseDelayTime (parameter) is 0, the ACK will be sent a.s.a.p.
aungriah 0:3333b6066adf 1979 * otherwise it will be sent with a programmed delay (in symbols), max is 255.
aungriah 0:3333b6066adf 1980 * NOTE: needs to have frame filtering enabled as well
aungriah 0:3333b6066adf 1981 *
aungriah 0:3333b6066adf 1982 * input parameters
aungriah 0:3333b6066adf 1983 * @param responseDelayTime - if non-zero the ACK is sent after this delay, max is 255.
aungriah 0:3333b6066adf 1984 *
aungriah 0:3333b6066adf 1985 * output parameters
aungriah 0:3333b6066adf 1986 *
aungriah 0:3333b6066adf 1987 * no return value
aungriah 0:3333b6066adf 1988 */
aungriah 0:3333b6066adf 1989 void dwt_enableautoack(uint8 responseDelayTime)
aungriah 0:3333b6066adf 1990 {
aungriah 0:3333b6066adf 1991 // Set auto ACK reply delay
aungriah 0:3333b6066adf 1992 dwt_write8bitoffsetreg(ACK_RESP_T_ID, ACK_RESP_T_ACK_TIM_OFFSET, responseDelayTime); // In symbols
aungriah 0:3333b6066adf 1993 // Enable auto ACK
aungriah 0:3333b6066adf 1994 dw1000local.sysCFGreg |= SYS_CFG_AUTOACK;
aungriah 0:3333b6066adf 1995 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:3333b6066adf 1996 }
aungriah 0:3333b6066adf 1997
aungriah 0:3333b6066adf 1998 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 1999 * @fn dwt_setdblrxbuffmode()
aungriah 0:3333b6066adf 2000 *
aungriah 0:3333b6066adf 2001 * @brief This call enables the double receive buffer mode
aungriah 0:3333b6066adf 2002 *
aungriah 0:3333b6066adf 2003 * input parameters
aungriah 0:3333b6066adf 2004 * @param enable - 1 to enable, 0 to disable the double buffer mode
aungriah 0:3333b6066adf 2005 *
aungriah 0:3333b6066adf 2006 * output parameters
aungriah 0:3333b6066adf 2007 *
aungriah 0:3333b6066adf 2008 * no return value
aungriah 0:3333b6066adf 2009 */
aungriah 0:3333b6066adf 2010 void dwt_setdblrxbuffmode(int enable)
aungriah 0:3333b6066adf 2011 {
aungriah 0:3333b6066adf 2012 if(enable)
aungriah 0:3333b6066adf 2013 {
aungriah 0:3333b6066adf 2014 // Enable double RX buffer mode
aungriah 0:3333b6066adf 2015 dw1000local.sysCFGreg &= ~SYS_CFG_DIS_DRXB;
aungriah 0:3333b6066adf 2016 dw1000local.dblbuffon = 1;
aungriah 0:3333b6066adf 2017 }
aungriah 0:3333b6066adf 2018 else
aungriah 0:3333b6066adf 2019 {
aungriah 0:3333b6066adf 2020 // Disable double RX buffer mode
aungriah 0:3333b6066adf 2021 dw1000local.sysCFGreg |= SYS_CFG_DIS_DRXB;
aungriah 0:3333b6066adf 2022 dw1000local.dblbuffon = 0;
aungriah 0:3333b6066adf 2023 }
aungriah 0:3333b6066adf 2024
aungriah 0:3333b6066adf 2025 dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
aungriah 0:3333b6066adf 2026 }
aungriah 0:3333b6066adf 2027
aungriah 0:3333b6066adf 2028 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2029 * @fn dwt_setrxaftertxdelay()
aungriah 0:3333b6066adf 2030 *
aungriah 0:3333b6066adf 2031 * @brief This sets the receiver turn on delay time after a transmission of a frame
aungriah 0:3333b6066adf 2032 *
aungriah 0:3333b6066adf 2033 * input parameters
aungriah 0:3333b6066adf 2034 * @param rxDelayTime - (20 bits) - the delay is in UWB microseconds
aungriah 0:3333b6066adf 2035 *
aungriah 0:3333b6066adf 2036 * output parameters
aungriah 0:3333b6066adf 2037 *
aungriah 0:3333b6066adf 2038 * no return value
aungriah 0:3333b6066adf 2039 */
aungriah 0:3333b6066adf 2040 void dwt_setrxaftertxdelay(uint32 rxDelayTime)
aungriah 0:3333b6066adf 2041 {
aungriah 0:3333b6066adf 2042 uint32 val = dwt_read32bitreg(ACK_RESP_T_ID) ; // Read ACK_RESP_T_ID register
aungriah 0:3333b6066adf 2043
aungriah 0:3333b6066adf 2044 val &= ~(ACK_RESP_T_W4R_TIM_MASK) ; // Clear the timer (19:0)
aungriah 0:3333b6066adf 2045
aungriah 0:3333b6066adf 2046 val |= (rxDelayTime & ACK_RESP_T_W4R_TIM_MASK) ; // In UWB microseconds (e.g. turn the receiver on 20uus after TX)
aungriah 0:3333b6066adf 2047
aungriah 0:3333b6066adf 2048 dwt_write32bitreg(ACK_RESP_T_ID, val) ;
aungriah 0:3333b6066adf 2049 }
aungriah 0:3333b6066adf 2050
aungriah 0:3333b6066adf 2051 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2052 * @fn dwt_setcallbacks()
aungriah 0:3333b6066adf 2053 *
aungriah 0:3333b6066adf 2054 * @brief This function is used to register the different callbacks called when one of the corresponding event occurs.
aungriah 0:3333b6066adf 2055 *
aungriah 0:3333b6066adf 2056 * NOTE: Callbacks can be undefined (set to NULL). In this case, dwt_isr() will process the event as usual but the 'null'
aungriah 0:3333b6066adf 2057 * callback will not be called.
aungriah 0:3333b6066adf 2058 *
aungriah 0:3333b6066adf 2059 * input parameters
aungriah 0:3333b6066adf 2060 * @param cbTxDone - the pointer to the TX confirmation event callback function
aungriah 0:3333b6066adf 2061 * @param cbRxOk - the pointer to the RX good frame event callback function
aungriah 0:3333b6066adf 2062 * @param cbRxTo - the pointer to the RX timeout events callback function
aungriah 0:3333b6066adf 2063 * @param cbRxErr - the pointer to the RX error events callback function
aungriah 0:3333b6066adf 2064 *
aungriah 0:3333b6066adf 2065 * output parameters
aungriah 0:3333b6066adf 2066 *
aungriah 0:3333b6066adf 2067 * no return value
aungriah 0:3333b6066adf 2068 */
aungriah 0:3333b6066adf 2069 void dwt_setcallbacks(dwt_cb_t cbTxDone, dwt_cb_t cbRxOk, dwt_cb_t cbRxTo, dwt_cb_t cbRxErr)
aungriah 0:3333b6066adf 2070 {
aungriah 0:3333b6066adf 2071 dw1000local.cbTxDone = cbTxDone;
aungriah 0:3333b6066adf 2072 dw1000local.cbRxOk = cbRxOk;
aungriah 0:3333b6066adf 2073 dw1000local.cbRxTo = cbRxTo;
aungriah 0:3333b6066adf 2074 dw1000local.cbRxErr = cbRxErr;
aungriah 0:3333b6066adf 2075 }
aungriah 0:3333b6066adf 2076
aungriah 0:3333b6066adf 2077 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2078 * @fn dwt_checkirq()
aungriah 0:3333b6066adf 2079 *
aungriah 0:3333b6066adf 2080 * @brief This function checks if the IRQ line is active - this is used instead of interrupt handler
aungriah 0:3333b6066adf 2081 *
aungriah 0:3333b6066adf 2082 * input parameters
aungriah 0:3333b6066adf 2083 *
aungriah 0:3333b6066adf 2084 * output parameters
aungriah 0:3333b6066adf 2085 *
aungriah 0:3333b6066adf 2086 * return value is 1 if the IRQS bit is set and 0 otherwise
aungriah 0:3333b6066adf 2087 */
aungriah 0:3333b6066adf 2088 uint8 dwt_checkirq(void)
aungriah 0:3333b6066adf 2089 {
aungriah 0:3333b6066adf 2090 return (dwt_read8bitoffsetreg(SYS_STATUS_ID, SYS_STATUS_OFFSET) & SYS_STATUS_IRQS); // Reading the lower byte only is enough for this operation
aungriah 0:3333b6066adf 2091 }
aungriah 0:3333b6066adf 2092
aungriah 0:3333b6066adf 2093 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2094 * @fn dwt_isr()
aungriah 0:3333b6066adf 2095 *
aungriah 0:3333b6066adf 2096 * @brief This is the DW1000's general Interrupt Service Routine. It will process/report the following events:
aungriah 0:3333b6066adf 2097 * - RXFCG (through cbRxOk callback)
aungriah 0:3333b6066adf 2098 * - TXFRS (through cbTxDone callback)
aungriah 0:3333b6066adf 2099 * - RXRFTO/RXPTO (through cbRxTo callback)
aungriah 0:3333b6066adf 2100 * - RXPHE/RXFCE/RXRFSL/RXSFDTO/AFFREJ/LDEERR (through cbRxTo cbRxErr)
aungriah 0:3333b6066adf 2101 * For all events, corresponding interrupts are cleared and necessary resets are performed. In addition, in the RXFCG case,
aungriah 0:3333b6066adf 2102 * received frame information and frame control are read before calling the callback. If double buffering is activated, it
aungriah 0:3333b6066adf 2103 * will also toggle between reception buffers once the reception callback processing has ended.
aungriah 0:3333b6066adf 2104 *
aungriah 0:3333b6066adf 2105 * /!\ This version of the ISR supports double buffering but does not support automatic RX re-enabling!
aungriah 0:3333b6066adf 2106 *
aungriah 0:3333b6066adf 2107 * NOTE: In PC based system using (Cheetah or ARM) USB to SPI converter there can be no interrupts, however we still need something
aungriah 0:3333b6066adf 2108 * to take the place of it and operate in a polled way. In an embedded system this function should be configured to be triggered
aungriah 0:3333b6066adf 2109 * on any of the interrupts described above.
aungriah 0:3333b6066adf 2110
aungriah 0:3333b6066adf 2111 * input parameters
aungriah 0:3333b6066adf 2112 *
aungriah 0:3333b6066adf 2113 * output parameters
aungriah 0:3333b6066adf 2114 *
aungriah 0:3333b6066adf 2115 * no return value
aungriah 0:3333b6066adf 2116 */
aungriah 0:3333b6066adf 2117 void dwt_isr(void)
aungriah 0:3333b6066adf 2118 {
aungriah 0:3333b6066adf 2119 uint32 status = dw1000local.cbData.status = dwt_read32bitreg(SYS_STATUS_ID); // Read status register low 32bits
aungriah 0:3333b6066adf 2120
aungriah 0:3333b6066adf 2121 // Handle RX good frame event
aungriah 0:3333b6066adf 2122 if(status & SYS_STATUS_RXFCG)
aungriah 0:3333b6066adf 2123 {
aungriah 0:3333b6066adf 2124 uint16 finfo16;
aungriah 0:3333b6066adf 2125 uint16 len;
aungriah 0:3333b6066adf 2126
aungriah 0:3333b6066adf 2127 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_GOOD); // Clear all receive status bits
aungriah 0:3333b6066adf 2128
aungriah 0:3333b6066adf 2129 dw1000local.cbData.rx_flags = 0;
aungriah 0:3333b6066adf 2130
aungriah 0:3333b6066adf 2131 // Read frame info - Only the first two bytes of the register are used here.
aungriah 0:3333b6066adf 2132 finfo16 = dwt_read16bitoffsetreg(RX_FINFO_ID, RX_FINFO_OFFSET);
aungriah 0:3333b6066adf 2133
aungriah 0:3333b6066adf 2134 // Report frame length - Standard frame length up to 127, extended frame length up to 1023 bytes
aungriah 0:3333b6066adf 2135 len = finfo16 & RX_FINFO_RXFL_MASK_1023;
aungriah 0:3333b6066adf 2136 if(dw1000local.longFrames == 0)
aungriah 0:3333b6066adf 2137 {
aungriah 0:3333b6066adf 2138 len &= RX_FINFO_RXFLEN_MASK;
aungriah 0:3333b6066adf 2139 }
aungriah 0:3333b6066adf 2140 dw1000local.cbData.datalength = len;
aungriah 0:3333b6066adf 2141
aungriah 0:3333b6066adf 2142 // Report ranging bit
aungriah 0:3333b6066adf 2143 if(finfo16 & RX_FINFO_RNG)
aungriah 0:3333b6066adf 2144 {
aungriah 0:3333b6066adf 2145 dw1000local.cbData.rx_flags |= DWT_CB_DATA_RX_FLAG_RNG;
aungriah 0:3333b6066adf 2146 }
aungriah 0:3333b6066adf 2147
aungriah 0:3333b6066adf 2148 // Report frame control - First bytes of the received frame.
aungriah 0:3333b6066adf 2149 dwt_readfromdevice(RX_BUFFER_ID, 0, FCTRL_LEN_MAX, dw1000local.cbData.fctrl);
aungriah 0:3333b6066adf 2150
aungriah 0:3333b6066adf 2151 // Because of a previous frame not being received properly, AAT bit can be set upon the proper reception of a frame not requesting for
aungriah 0:3333b6066adf 2152 // acknowledgement (ACK frame is not actually sent though). If the AAT bit is set, check ACK request bit in frame control to confirm (this
aungriah 0:3333b6066adf 2153 // implementation works only for IEEE802.15.4-2011 compliant frames).
aungriah 0:3333b6066adf 2154 // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
aungriah 0:3333b6066adf 2155 if((status & SYS_STATUS_AAT) && ((dw1000local.cbData.fctrl[0] & FCTRL_ACK_REQ_MASK) == 0))
aungriah 0:3333b6066adf 2156 {
aungriah 0:3333b6066adf 2157 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_AAT); // Clear AAT status bit in register
aungriah 0:3333b6066adf 2158 dw1000local.cbData.status &= ~SYS_STATUS_AAT; // Clear AAT status bit in callback data register copy
aungriah 0:3333b6066adf 2159 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 2160 }
aungriah 0:3333b6066adf 2161
aungriah 0:3333b6066adf 2162 // Call the corresponding callback if present
aungriah 0:3333b6066adf 2163 if(dw1000local.cbRxOk != NULL)
aungriah 0:3333b6066adf 2164 {
aungriah 0:3333b6066adf 2165 dw1000local.cbRxOk(&dw1000local.cbData);
aungriah 0:3333b6066adf 2166 }
aungriah 0:3333b6066adf 2167
aungriah 0:3333b6066adf 2168 if (dw1000local.dblbuffon)
aungriah 0:3333b6066adf 2169 {
aungriah 0:3333b6066adf 2170 // Toggle the Host side Receive Buffer Pointer
aungriah 0:3333b6066adf 2171 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET, 1);
aungriah 0:3333b6066adf 2172 }
aungriah 0:3333b6066adf 2173 }
aungriah 0:3333b6066adf 2174
aungriah 0:3333b6066adf 2175 // Handle TX confirmation event
aungriah 0:3333b6066adf 2176 if(status & SYS_STATUS_TXFRS)
aungriah 0:3333b6066adf 2177 {
aungriah 0:3333b6066adf 2178 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_TX); // Clear TX event bits
aungriah 0:3333b6066adf 2179
aungriah 0:3333b6066adf 2180 // In the case where this TXFRS interrupt is due to the automatic transmission of an ACK solicited by a response (with ACK request bit set)
aungriah 0:3333b6066adf 2181 // that we receive through using wait4resp to a previous TX (and assuming that the IRQ processing of that TX has already been handled), then
aungriah 0:3333b6066adf 2182 // we need to handle the IC issue which turns on the RX again in this situation (i.e. because it is wrongly applying the wait4resp after the
aungriah 0:3333b6066adf 2183 // ACK TX).
aungriah 0:3333b6066adf 2184 // See section "Transmit and automatically wait for response" in DW1000 User Manual
aungriah 0:3333b6066adf 2185 if((status & SYS_STATUS_AAT) && dw1000local.wait4resp)
aungriah 0:3333b6066adf 2186 {
aungriah 0:3333b6066adf 2187 dwt_forcetrxoff(); // Turn the RX off
aungriah 0:3333b6066adf 2188 dwt_rxreset(); // Reset in case we were late and a frame was already being received
aungriah 0:3333b6066adf 2189 }
aungriah 0:3333b6066adf 2190
aungriah 0:3333b6066adf 2191 // Call the corresponding callback if present
aungriah 0:3333b6066adf 2192 if(dw1000local.cbTxDone != NULL)
aungriah 0:3333b6066adf 2193 {
aungriah 0:3333b6066adf 2194 dw1000local.cbTxDone(&dw1000local.cbData);
aungriah 0:3333b6066adf 2195 }
aungriah 0:3333b6066adf 2196 }
aungriah 0:3333b6066adf 2197
aungriah 0:3333b6066adf 2198 // Handle frame reception/preamble detect timeout events
aungriah 0:3333b6066adf 2199 if(status & SYS_STATUS_ALL_RX_TO)
aungriah 0:3333b6066adf 2200 {
aungriah 0:3333b6066adf 2201 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXRFTO); // Clear RX timeout event bits
aungriah 0:3333b6066adf 2202
aungriah 0:3333b6066adf 2203 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 2204
aungriah 0:3333b6066adf 2205 // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure
aungriah 0:3333b6066adf 2206 // the next good frame's timestamp is computed correctly.
aungriah 0:3333b6066adf 2207 // See section "RX Message timestamp" in DW1000 User Manual.
aungriah 0:3333b6066adf 2208 dwt_forcetrxoff();
aungriah 0:3333b6066adf 2209 dwt_rxreset();
aungriah 0:3333b6066adf 2210
aungriah 0:3333b6066adf 2211 // Call the corresponding callback if present
aungriah 0:3333b6066adf 2212 if(dw1000local.cbRxTo != NULL)
aungriah 0:3333b6066adf 2213 {
aungriah 0:3333b6066adf 2214 dw1000local.cbRxTo(&dw1000local.cbData);
aungriah 0:3333b6066adf 2215 }
aungriah 0:3333b6066adf 2216 }
aungriah 0:3333b6066adf 2217
aungriah 0:3333b6066adf 2218 // Handle RX errors events
aungriah 0:3333b6066adf 2219 if(status & SYS_STATUS_ALL_RX_ERR)
aungriah 0:3333b6066adf 2220 {
aungriah 0:3333b6066adf 2221 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR); // Clear RX error event bits
aungriah 0:3333b6066adf 2222
aungriah 0:3333b6066adf 2223 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 2224
aungriah 0:3333b6066adf 2225 // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure
aungriah 0:3333b6066adf 2226 // the next good frame's timestamp is computed correctly.
aungriah 0:3333b6066adf 2227 // See section "RX Message timestamp" in DW1000 User Manual.
aungriah 0:3333b6066adf 2228 dwt_forcetrxoff();
aungriah 0:3333b6066adf 2229 dwt_rxreset();
aungriah 0:3333b6066adf 2230
aungriah 0:3333b6066adf 2231 // Call the corresponding callback if present
aungriah 0:3333b6066adf 2232 if(dw1000local.cbRxErr != NULL)
aungriah 0:3333b6066adf 2233 {
aungriah 0:3333b6066adf 2234 dw1000local.cbRxErr(&dw1000local.cbData);
aungriah 0:3333b6066adf 2235 }
aungriah 0:3333b6066adf 2236 }
aungriah 0:3333b6066adf 2237 }
aungriah 0:3333b6066adf 2238
aungriah 0:3333b6066adf 2239 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2240 * @fn dwt_isr_lplisten()
aungriah 0:3333b6066adf 2241 *
aungriah 0:3333b6066adf 2242 * @brief This is the DW1000's Interrupt Service Routine to use when low-power listening scheme is implemented. It will
aungriah 0:3333b6066adf 2243 * only process/report the RXFCG event (through cbRxOk callback).
aungriah 0:3333b6066adf 2244 * It clears RXFCG interrupt and reads received frame information and frame control before calling the callback.
aungriah 0:3333b6066adf 2245 *
aungriah 0:3333b6066adf 2246 * /!\ This version of the ISR is designed for single buffering case only!
aungriah 0:3333b6066adf 2247 *
aungriah 0:3333b6066adf 2248 * input parameters
aungriah 0:3333b6066adf 2249 *
aungriah 0:3333b6066adf 2250 * output parameters
aungriah 0:3333b6066adf 2251 *
aungriah 0:3333b6066adf 2252 * no return value
aungriah 0:3333b6066adf 2253 */
aungriah 0:3333b6066adf 2254 void dwt_lowpowerlistenisr(void)
aungriah 0:3333b6066adf 2255 {
aungriah 0:3333b6066adf 2256 uint32 status = dw1000local.cbData.status = dwt_read32bitreg(SYS_STATUS_ID); // Read status register low 32bits
aungriah 0:3333b6066adf 2257 uint16 finfo16;
aungriah 0:3333b6066adf 2258 uint16 len;
aungriah 0:3333b6066adf 2259
aungriah 0:3333b6066adf 2260 // The only interrupt handled when in low-power listening mode is RX good frame so proceed directly to the handling of the received frame.
aungriah 0:3333b6066adf 2261
aungriah 0:3333b6066adf 2262 // Deactivate low-power listening before clearing the interrupt. If not, the DW1000 will go back to sleep as soon as the interrupt is cleared.
aungriah 0:3333b6066adf 2263 dwt_setlowpowerlistening(0);
aungriah 0:3333b6066adf 2264
aungriah 0:3333b6066adf 2265 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_GOOD); // Clear all receive status bits
aungriah 0:3333b6066adf 2266
aungriah 0:3333b6066adf 2267 dw1000local.cbData.rx_flags = 0;
aungriah 0:3333b6066adf 2268
aungriah 0:3333b6066adf 2269 // Read frame info - Only the first two bytes of the register are used here.
aungriah 0:3333b6066adf 2270 finfo16 = dwt_read16bitoffsetreg(RX_FINFO_ID, 0);
aungriah 0:3333b6066adf 2271
aungriah 0:3333b6066adf 2272 // Report frame length - Standard frame length up to 127, extended frame length up to 1023 bytes
aungriah 0:3333b6066adf 2273 len = finfo16 & RX_FINFO_RXFL_MASK_1023;
aungriah 0:3333b6066adf 2274 if(dw1000local.longFrames == 0)
aungriah 0:3333b6066adf 2275 {
aungriah 0:3333b6066adf 2276 len &= RX_FINFO_RXFLEN_MASK;
aungriah 0:3333b6066adf 2277 }
aungriah 0:3333b6066adf 2278 dw1000local.cbData.datalength = len;
aungriah 0:3333b6066adf 2279
aungriah 0:3333b6066adf 2280 // Report ranging bit
aungriah 0:3333b6066adf 2281 if(finfo16 & RX_FINFO_RNG)
aungriah 0:3333b6066adf 2282 {
aungriah 0:3333b6066adf 2283 dw1000local.cbData.rx_flags |= DWT_CB_DATA_RX_FLAG_RNG;
aungriah 0:3333b6066adf 2284 }
aungriah 0:3333b6066adf 2285
aungriah 0:3333b6066adf 2286 // Report frame control - First bytes of the received frame.
aungriah 0:3333b6066adf 2287 dwt_readfromdevice(RX_BUFFER_ID, 0, FCTRL_LEN_MAX, dw1000local.cbData.fctrl);
aungriah 0:3333b6066adf 2288
aungriah 0:3333b6066adf 2289 // Because of a previous frame not being received properly, AAT bit can be set upon the proper reception of a frame not requesting for
aungriah 0:3333b6066adf 2290 // acknowledgement (ACK frame is not actually sent though). If the AAT bit is set, check ACK request bit in frame control to confirm (this
aungriah 0:3333b6066adf 2291 // implementation works only for IEEE802.15.4-2011 compliant frames).
aungriah 0:3333b6066adf 2292 // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
aungriah 0:3333b6066adf 2293 if((status & SYS_STATUS_AAT) && ((dw1000local.cbData.fctrl[0] & FCTRL_ACK_REQ_MASK) == 0))
aungriah 0:3333b6066adf 2294 {
aungriah 0:3333b6066adf 2295 dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_AAT); // Clear AAT status bit in register
aungriah 0:3333b6066adf 2296 dw1000local.cbData.status &= ~SYS_STATUS_AAT; // Clear AAT status bit in callback data register copy
aungriah 0:3333b6066adf 2297 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 2298 }
aungriah 0:3333b6066adf 2299
aungriah 0:3333b6066adf 2300 // Call the corresponding callback if present
aungriah 0:3333b6066adf 2301 if(dw1000local.cbRxOk != NULL)
aungriah 0:3333b6066adf 2302 {
aungriah 0:3333b6066adf 2303 dw1000local.cbRxOk(&dw1000local.cbData);
aungriah 0:3333b6066adf 2304 }
aungriah 0:3333b6066adf 2305 }
aungriah 0:3333b6066adf 2306
aungriah 0:3333b6066adf 2307 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2308 * @fn dwt_setleds()
aungriah 0:3333b6066adf 2309 *
aungriah 0:3333b6066adf 2310 * @brief This is used to set up Tx/Rx GPIOs which could be used to control LEDs
aungriah 0:3333b6066adf 2311 * Note: not completely IC dependent, also needs board with LEDS fitted on right I/O lines
aungriah 0:3333b6066adf 2312 * this function enables GPIOs 2 and 3 which are connected to LED3 and LED4 on EVB1000
aungriah 0:3333b6066adf 2313 *
aungriah 0:3333b6066adf 2314 * input parameters
aungriah 0:3333b6066adf 2315 * @param mode - this is a bit field interpreted as follows:
aungriah 0:3333b6066adf 2316 * - bit 0: 1 to enable LEDs, 0 to disable them
aungriah 0:3333b6066adf 2317 * - bit 1: 1 to make LEDs blink once on init. Only valid if bit 0 is set (enable LEDs)
aungriah 0:3333b6066adf 2318 * - bit 2 to 7: reserved
aungriah 0:3333b6066adf 2319 *
aungriah 0:3333b6066adf 2320 * output parameters none
aungriah 0:3333b6066adf 2321 *
aungriah 0:3333b6066adf 2322 * no return value
aungriah 0:3333b6066adf 2323 */
aungriah 0:3333b6066adf 2324 void dwt_setleds(uint8 mode)
aungriah 0:3333b6066adf 2325 {
aungriah 0:3333b6066adf 2326 uint32 reg;
aungriah 0:3333b6066adf 2327
aungriah 0:3333b6066adf 2328 if (mode & DWT_LEDS_ENABLE)
aungriah 0:3333b6066adf 2329 {
aungriah 0:3333b6066adf 2330 // Set up MFIO for LED output.
aungriah 0:3333b6066adf 2331 reg = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET);
aungriah 0:3333b6066adf 2332 reg &= ~(GPIO_MSGP2_MASK | GPIO_MSGP3_MASK);
aungriah 0:3333b6066adf 2333 reg |= (GPIO_PIN2_RXLED | GPIO_PIN3_TXLED);
aungriah 0:3333b6066adf 2334 dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, reg);
aungriah 0:3333b6066adf 2335
aungriah 0:3333b6066adf 2336 // Enable LP Oscillator to run from counter and turn on de-bounce clock.
aungriah 0:3333b6066adf 2337 reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET);
aungriah 0:3333b6066adf 2338 reg |= (PMSC_CTRL0_GPDCE | PMSC_CTRL0_KHZCLEN);
aungriah 0:3333b6066adf 2339 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, reg);
aungriah 0:3333b6066adf 2340
aungriah 0:3333b6066adf 2341 // Enable LEDs to blink and set default blink time.
aungriah 0:3333b6066adf 2342 reg = PMSC_LEDC_BLNKEN | PMSC_LEDC_BLINK_TIME_DEF;
aungriah 0:3333b6066adf 2343 // Make LEDs blink once if requested.
aungriah 0:3333b6066adf 2344 if (mode & DWT_LEDS_INIT_BLINK)
aungriah 0:3333b6066adf 2345 {
aungriah 0:3333b6066adf 2346 reg |= PMSC_LEDC_BLINK_NOW_ALL;
aungriah 0:3333b6066adf 2347 }
aungriah 0:3333b6066adf 2348 dwt_write32bitoffsetreg(PMSC_ID, PMSC_LEDC_OFFSET, reg);
aungriah 0:3333b6066adf 2349 // Clear force blink bits if needed.
aungriah 0:3333b6066adf 2350 if(mode & DWT_LEDS_INIT_BLINK)
aungriah 0:3333b6066adf 2351 {
aungriah 0:3333b6066adf 2352 reg &= ~PMSC_LEDC_BLINK_NOW_ALL;
aungriah 0:3333b6066adf 2353 dwt_write32bitoffsetreg(PMSC_ID, PMSC_LEDC_OFFSET, reg);
aungriah 0:3333b6066adf 2354 }
aungriah 0:3333b6066adf 2355 }
aungriah 0:3333b6066adf 2356 else
aungriah 0:3333b6066adf 2357 {
aungriah 0:3333b6066adf 2358 // Clear the GPIO bits that are used for LED control.
aungriah 0:3333b6066adf 2359 reg = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET);
aungriah 0:3333b6066adf 2360 reg &= ~(GPIO_MSGP2_MASK | GPIO_MSGP3_MASK);
aungriah 0:3333b6066adf 2361 dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, reg);
aungriah 0:3333b6066adf 2362 }
aungriah 0:3333b6066adf 2363 }
aungriah 0:3333b6066adf 2364
aungriah 0:3333b6066adf 2365 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2366 * @fn _dwt_enableclocks()
aungriah 0:3333b6066adf 2367 *
aungriah 0:3333b6066adf 2368 * @brief function to enable/disable clocks to particular digital blocks/system
aungriah 0:3333b6066adf 2369 *
aungriah 0:3333b6066adf 2370 * input parameters
aungriah 0:3333b6066adf 2371 * @param clocks - set of clocks to enable/disable
aungriah 0:3333b6066adf 2372 *
aungriah 0:3333b6066adf 2373 * output parameters none
aungriah 0:3333b6066adf 2374 *
aungriah 0:3333b6066adf 2375 * no return value
aungriah 0:3333b6066adf 2376 */
aungriah 0:3333b6066adf 2377 void _dwt_enableclocks(int clocks)
aungriah 0:3333b6066adf 2378 {
aungriah 0:3333b6066adf 2379 uint8 reg[2];
aungriah 0:3333b6066adf 2380
aungriah 0:3333b6066adf 2381 dwt_readfromdevice(PMSC_ID, PMSC_CTRL0_OFFSET, 2, reg);
aungriah 0:3333b6066adf 2382 switch(clocks)
aungriah 0:3333b6066adf 2383 {
aungriah 0:3333b6066adf 2384 case ENABLE_ALL_SEQ:
aungriah 0:3333b6066adf 2385 {
aungriah 0:3333b6066adf 2386 reg[0] = 0x00 ;
aungriah 0:3333b6066adf 2387 reg[1] = reg[1] & 0xfe;
aungriah 0:3333b6066adf 2388 }
aungriah 0:3333b6066adf 2389 break;
aungriah 0:3333b6066adf 2390 case FORCE_SYS_XTI:
aungriah 0:3333b6066adf 2391 {
aungriah 0:3333b6066adf 2392 // System and RX
aungriah 0:3333b6066adf 2393 reg[0] = 0x01 | (reg[0] & 0xfc);
aungriah 0:3333b6066adf 2394 }
aungriah 0:3333b6066adf 2395 break;
aungriah 0:3333b6066adf 2396 case FORCE_SYS_PLL:
aungriah 0:3333b6066adf 2397 {
aungriah 0:3333b6066adf 2398 // System
aungriah 0:3333b6066adf 2399 reg[0] = 0x02 | (reg[0] & 0xfc);
aungriah 0:3333b6066adf 2400 }
aungriah 0:3333b6066adf 2401 break;
aungriah 0:3333b6066adf 2402 case READ_ACC_ON:
aungriah 0:3333b6066adf 2403 {
aungriah 0:3333b6066adf 2404 reg[0] = 0x48 | (reg[0] & 0xb3);
aungriah 0:3333b6066adf 2405 reg[1] = 0x80 | reg[1];
aungriah 0:3333b6066adf 2406 }
aungriah 0:3333b6066adf 2407 break;
aungriah 0:3333b6066adf 2408 case READ_ACC_OFF:
aungriah 0:3333b6066adf 2409 {
aungriah 0:3333b6066adf 2410 reg[0] = reg[0] & 0xb3;
aungriah 0:3333b6066adf 2411 reg[1] = 0x7f & reg[1];
aungriah 0:3333b6066adf 2412 }
aungriah 0:3333b6066adf 2413 break;
aungriah 0:3333b6066adf 2414 case FORCE_OTP_ON:
aungriah 0:3333b6066adf 2415 {
aungriah 0:3333b6066adf 2416 reg[1] = 0x02 | reg[1];
aungriah 0:3333b6066adf 2417 }
aungriah 0:3333b6066adf 2418 break;
aungriah 0:3333b6066adf 2419 case FORCE_OTP_OFF:
aungriah 0:3333b6066adf 2420 {
aungriah 0:3333b6066adf 2421 reg[1] = reg[1] & 0xfd;
aungriah 0:3333b6066adf 2422 }
aungriah 0:3333b6066adf 2423 break;
aungriah 0:3333b6066adf 2424 case FORCE_TX_PLL:
aungriah 0:3333b6066adf 2425 {
aungriah 0:3333b6066adf 2426 reg[0] = 0x20 | (reg[0] & 0xcf);
aungriah 0:3333b6066adf 2427 }
aungriah 0:3333b6066adf 2428 break;
aungriah 0:3333b6066adf 2429 case FORCE_LDE:
aungriah 0:3333b6066adf 2430 {
aungriah 0:3333b6066adf 2431 reg[0] = 0x01;
aungriah 0:3333b6066adf 2432 reg[1] = 0x03;
aungriah 0:3333b6066adf 2433 }
aungriah 0:3333b6066adf 2434 break;
aungriah 0:3333b6066adf 2435 default:
aungriah 0:3333b6066adf 2436 break;
aungriah 0:3333b6066adf 2437 }
aungriah 0:3333b6066adf 2438
aungriah 0:3333b6066adf 2439
aungriah 0:3333b6066adf 2440 // Need to write lower byte separately before setting the higher byte(s)
aungriah 0:3333b6066adf 2441 dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, &reg[0]);
aungriah 0:3333b6066adf 2442 dwt_writetodevice(PMSC_ID, 0x1, 1, &reg[1]);
aungriah 0:3333b6066adf 2443
aungriah 0:3333b6066adf 2444 } // end _dwt_enableclocks()
aungriah 0:3333b6066adf 2445
aungriah 0:3333b6066adf 2446 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2447 * @fn _dwt_disablesequencing()
aungriah 0:3333b6066adf 2448 *
aungriah 0:3333b6066adf 2449 * @brief This function disables the TX blocks sequencing, it disables PMSC control of RF blocks, system clock is also set to XTAL
aungriah 0:3333b6066adf 2450 *
aungriah 0:3333b6066adf 2451 * input parameters none
aungriah 0:3333b6066adf 2452 *
aungriah 0:3333b6066adf 2453 * output parameters none
aungriah 0:3333b6066adf 2454 *
aungriah 0:3333b6066adf 2455 * no return value
aungriah 0:3333b6066adf 2456 */
aungriah 0:3333b6066adf 2457 void _dwt_disablesequencing(void) // Disable sequencing and go to state "INIT"
aungriah 0:3333b6066adf 2458 {
aungriah 0:3333b6066adf 2459 _dwt_enableclocks(FORCE_SYS_XTI); // Set system clock to XTI
aungriah 0:3333b6066adf 2460
aungriah 0:3333b6066adf 2461 dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, PMSC_CTRL1_PKTSEQ_DISABLE); // Disable PMSC ctrl of RF and RX clk blocks
aungriah 0:3333b6066adf 2462 }
aungriah 0:3333b6066adf 2463
aungriah 0:3333b6066adf 2464 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2465 * @fn dwt_setdelayedtrxtime()
aungriah 0:3333b6066adf 2466 *
aungriah 0:3333b6066adf 2467 * @brief This API function configures the delayed transmit time or the delayed RX on time
aungriah 0:3333b6066adf 2468 *
aungriah 0:3333b6066adf 2469 * input parameters
aungriah 0:3333b6066adf 2470 * @param starttime - the TX/RX start time (the 32 bits should be the high 32 bits of the system time at which to send the message,
aungriah 0:3333b6066adf 2471 * or at which to turn on the receiver)
aungriah 0:3333b6066adf 2472 *
aungriah 0:3333b6066adf 2473 * output parameters none
aungriah 0:3333b6066adf 2474 *
aungriah 0:3333b6066adf 2475 * no return value
aungriah 0:3333b6066adf 2476 */
aungriah 0:3333b6066adf 2477 void dwt_setdelayedtrxtime(uint32 starttime)
aungriah 0:3333b6066adf 2478 {
aungriah 0:3333b6066adf 2479 dwt_write32bitoffsetreg(DX_TIME_ID, 1, starttime); // Write at offset 1 as the lower 9 bits of this register are ignored
aungriah 0:3333b6066adf 2480
aungriah 0:3333b6066adf 2481 } // end dwt_setdelayedtrxtime()
aungriah 0:3333b6066adf 2482
aungriah 0:3333b6066adf 2483 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2484 * @fn dwt_starttx()
aungriah 0:3333b6066adf 2485 *
aungriah 0:3333b6066adf 2486 * @brief This call initiates the transmission, input parameter indicates which TX mode is used see below
aungriah 0:3333b6066adf 2487 *
aungriah 0:3333b6066adf 2488 * input parameters:
aungriah 0:3333b6066adf 2489 * @param mode - if 0 immediate TX (no response expected)
aungriah 0:3333b6066adf 2490 * if 1 delayed TX (no response expected)
aungriah 0:3333b6066adf 2491 * if 2 immediate TX (response expected - so the receiver will be automatically turned on after TX is done)
aungriah 0:3333b6066adf 2492 * if 3 delayed TX (response expected - so the receiver will be automatically turned on after TX is done)
aungriah 0:3333b6066adf 2493 *
aungriah 0:3333b6066adf 2494 * output parameters
aungriah 0:3333b6066adf 2495 *
aungriah 0:3333b6066adf 2496 * returns DWT_SUCCESS for success, or DWT_ERROR for error (e.g. a delayed transmission will fail if the delayed time has passed)
aungriah 0:3333b6066adf 2497 */
aungriah 0:3333b6066adf 2498 int dwt_starttx(uint8 mode)
aungriah 0:3333b6066adf 2499 {
aungriah 0:3333b6066adf 2500 int retval = DWT_SUCCESS ;
aungriah 0:3333b6066adf 2501 uint8 temp = 0x00;
aungriah 0:3333b6066adf 2502 uint16 checkTxOK = 0 ;
aungriah 0:3333b6066adf 2503
aungriah 0:3333b6066adf 2504 if(mode & DWT_RESPONSE_EXPECTED)
aungriah 0:3333b6066adf 2505 {
aungriah 0:3333b6066adf 2506 temp = (uint8)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
aungriah 0:3333b6066adf 2507 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:3333b6066adf 2508 dw1000local.wait4resp = 1;
aungriah 0:3333b6066adf 2509 }
aungriah 0:3333b6066adf 2510
aungriah 0:3333b6066adf 2511 if (mode & DWT_START_TX_DELAYED)
aungriah 0:3333b6066adf 2512 {
aungriah 0:3333b6066adf 2513 // Both SYS_CTRL_TXSTRT and SYS_CTRL_TXDLYS to correctly enable TX
aungriah 0:3333b6066adf 2514 temp |= (uint8)(SYS_CTRL_TXDLYS | SYS_CTRL_TXSTRT) ;
aungriah 0:3333b6066adf 2515 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:3333b6066adf 2516 checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID, 3); // Read at offset 3 to get the upper 2 bytes out of 5
aungriah 0:3333b6066adf 2517 if ((checkTxOK & SYS_STATUS_TXERR) == 0) // Transmit Delayed Send set over Half a Period away or Power Up error (there is enough time to send but not to power up individual blocks).
aungriah 0:3333b6066adf 2518 {
aungriah 0:3333b6066adf 2519 retval = DWT_SUCCESS ; // All okay
aungriah 0:3333b6066adf 2520 }
aungriah 0:3333b6066adf 2521 else
aungriah 0:3333b6066adf 2522 {
aungriah 0:3333b6066adf 2523 // I am taking DSHP set to Indicate that the TXDLYS was set too late for the specified DX_TIME.
aungriah 0:3333b6066adf 2524 // Remedial Action - (a) cancel delayed send
aungriah 0:3333b6066adf 2525 temp = (uint8)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
aungriah 0:3333b6066adf 2526 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:3333b6066adf 2527 // Note event Delayed TX Time too Late
aungriah 0:3333b6066adf 2528 // Could fall through to start a normal send (below) just sending late.....
aungriah 0:3333b6066adf 2529 // ... instead return and assume return value of 1 will be used to detect and recover from the issue.
aungriah 0:3333b6066adf 2530 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 2531 retval = DWT_ERROR ; // Failed !
aungriah 0:3333b6066adf 2532 }
aungriah 0:3333b6066adf 2533 }
aungriah 0:3333b6066adf 2534 else
aungriah 0:3333b6066adf 2535 {
aungriah 0:3333b6066adf 2536 temp |= (uint8)SYS_CTRL_TXSTRT ;
aungriah 0:3333b6066adf 2537 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:3333b6066adf 2538 }
aungriah 0:3333b6066adf 2539
aungriah 0:3333b6066adf 2540 return retval;
aungriah 0:3333b6066adf 2541
aungriah 0:3333b6066adf 2542 } // end dwt_starttx()
aungriah 0:3333b6066adf 2543
aungriah 0:3333b6066adf 2544 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2545 * @fn dwt_forcetrxoff()
aungriah 0:3333b6066adf 2546 *
aungriah 0:3333b6066adf 2547 * @brief This is used to turn off the transceiver
aungriah 0:3333b6066adf 2548 *
aungriah 0:3333b6066adf 2549 * input parameters
aungriah 0:3333b6066adf 2550 *
aungriah 0:3333b6066adf 2551 * output parameters
aungriah 0:3333b6066adf 2552 *
aungriah 0:3333b6066adf 2553 * no return value
aungriah 0:3333b6066adf 2554 */
aungriah 0:3333b6066adf 2555 void dwt_forcetrxoff(void)
aungriah 0:3333b6066adf 2556 {
aungriah 0:3333b6066adf 2557 decaIrqStatus_t stat ;
aungriah 0:3333b6066adf 2558 uint32 mask;
aungriah 0:3333b6066adf 2559
aungriah 0:3333b6066adf 2560 mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask
aungriah 0:3333b6066adf 2561
aungriah 0:3333b6066adf 2562 // Need to beware of interrupts occurring in the middle of following read modify write cycle
aungriah 0:3333b6066adf 2563 // We can disable the radio, but before the status is cleared an interrupt can be set (e.g. the
aungriah 0:3333b6066adf 2564 // event has just happened before the radio was disabled)
aungriah 0:3333b6066adf 2565 // thus we need to disable interrupt during this operation
aungriah 0:3333b6066adf 2566 stat = decamutexon() ;
aungriah 0:3333b6066adf 2567
aungriah 0:3333b6066adf 2568 dwt_write32bitreg(SYS_MASK_ID, 0) ; // Clear interrupt mask - so we don't get any unwanted events
aungriah 0:3333b6066adf 2569
aungriah 0:3333b6066adf 2570 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, (uint8)SYS_CTRL_TRXOFF) ; // Disable the radio
aungriah 0:3333b6066adf 2571
aungriah 0:3333b6066adf 2572 // Forcing Transceiver off - so we do not want to see any new events that may have happened
aungriah 0:3333b6066adf 2573 dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD));
aungriah 0:3333b6066adf 2574
aungriah 0:3333b6066adf 2575 dwt_syncrxbufptrs();
aungriah 0:3333b6066adf 2576
aungriah 0:3333b6066adf 2577 dwt_write32bitreg(SYS_MASK_ID, mask) ; // Set interrupt mask to what it was
aungriah 0:3333b6066adf 2578
aungriah 0:3333b6066adf 2579 // Enable/restore interrupts again...
aungriah 0:3333b6066adf 2580 decamutexoff(stat) ;
aungriah 0:3333b6066adf 2581 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 2582
aungriah 0:3333b6066adf 2583 } // end deviceforcetrxoff()
aungriah 0:3333b6066adf 2584
aungriah 0:3333b6066adf 2585 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2586 * @fn dwt_syncrxbufptrs()
aungriah 0:3333b6066adf 2587 *
aungriah 0:3333b6066adf 2588 * @brief this function synchronizes rx buffer pointers
aungriah 0:3333b6066adf 2589 * need to make sure that the host/IC buffer pointers are aligned before starting RX
aungriah 0:3333b6066adf 2590 *
aungriah 0:3333b6066adf 2591 * input parameters:
aungriah 0:3333b6066adf 2592 *
aungriah 0:3333b6066adf 2593 * output parameters
aungriah 0:3333b6066adf 2594 *
aungriah 0:3333b6066adf 2595 * no return value
aungriah 0:3333b6066adf 2596 */
aungriah 0:3333b6066adf 2597 void dwt_syncrxbufptrs(void)
aungriah 0:3333b6066adf 2598 {
aungriah 0:3333b6066adf 2599 uint8 buff ;
aungriah 0:3333b6066adf 2600 // Need to make sure that the host/IC buffer pointers are aligned before starting RX
aungriah 0:3333b6066adf 2601 buff = dwt_read8bitoffsetreg(SYS_STATUS_ID, 3); // Read 1 byte at offset 3 to get the 4th byte out of 5
aungriah 0:3333b6066adf 2602
aungriah 0:3333b6066adf 2603 if((buff & (SYS_STATUS_ICRBP >> 24)) != // IC side Receive Buffer Pointer
aungriah 0:3333b6066adf 2604 ((buff & (SYS_STATUS_HSRBP>>24)) << 1) ) // Host Side Receive Buffer Pointer
aungriah 0:3333b6066adf 2605 {
aungriah 0:3333b6066adf 2606 dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET , 0x01) ; // We need to swap RX buffer status reg (write one to toggle internally)
aungriah 0:3333b6066adf 2607 }
aungriah 0:3333b6066adf 2608 }
aungriah 0:3333b6066adf 2609
aungriah 0:3333b6066adf 2610 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2611 * @fn dwt_setsniffmode()
aungriah 0:3333b6066adf 2612 *
aungriah 0:3333b6066adf 2613 * @brief enable/disable and configure SNIFF mode.
aungriah 0:3333b6066adf 2614 *
aungriah 0:3333b6066adf 2615 * SNIFF mode is a low-power reception mode where the receiver is sequenced on and off instead of being on all the time.
aungriah 0:3333b6066adf 2616 * The time spent in each state (on/off) is specified through the parameters below.
aungriah 0:3333b6066adf 2617 * See DW1000 User Manual section 4.5 "Low-Power SNIFF mode" for more details.
aungriah 0:3333b6066adf 2618 *
aungriah 0:3333b6066adf 2619 * input parameters:
aungriah 0:3333b6066adf 2620 * @param enable - 1 to enable SNIFF mode, 0 to disable. When 0, all other parameters are not taken into account.
aungriah 0:3333b6066adf 2621 * @param timeOn - duration of receiver ON phase, expressed in multiples of PAC size. The counter automatically adds 1 PAC
aungriah 0:3333b6066adf 2622 * size to the value set. Min value that can be set is 1 (i.e. an ON time of 2 PAC size), max value is 15.
aungriah 0:3333b6066adf 2623 * @param timeOff - duration of receiver OFF phase, expressed in multiples of 128/125 µs (~1 µs). Max value is 255.
aungriah 0:3333b6066adf 2624 *
aungriah 0:3333b6066adf 2625 * output parameters
aungriah 0:3333b6066adf 2626 *
aungriah 0:3333b6066adf 2627 * no return value
aungriah 0:3333b6066adf 2628 */
aungriah 0:3333b6066adf 2629 void dwt_setsniffmode(int enable, uint8 timeOn, uint8 timeOff)
aungriah 0:3333b6066adf 2630 {
aungriah 0:3333b6066adf 2631 uint32 pmsc_reg;
aungriah 0:3333b6066adf 2632 if (enable)
aungriah 0:3333b6066adf 2633 {
aungriah 0:3333b6066adf 2634 /* Configure ON/OFF times and enable PLL2 on/off sequencing by SNIFF mode. */
aungriah 0:3333b6066adf 2635 uint16 sniff_reg = ((timeOff << 8) | timeOn) & RX_SNIFF_MASK;
aungriah 0:3333b6066adf 2636 dwt_write16bitoffsetreg(RX_SNIFF_ID, RX_SNIFF_OFFSET, sniff_reg);
aungriah 0:3333b6066adf 2637 pmsc_reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET);
aungriah 0:3333b6066adf 2638 pmsc_reg |= PMSC_CTRL0_PLL2_SEQ_EN;
aungriah 0:3333b6066adf 2639 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, pmsc_reg);
aungriah 0:3333b6066adf 2640 }
aungriah 0:3333b6066adf 2641 else
aungriah 0:3333b6066adf 2642 {
aungriah 0:3333b6066adf 2643 /* Clear ON/OFF times and disable PLL2 on/off sequencing by SNIFF mode. */
aungriah 0:3333b6066adf 2644 dwt_write16bitoffsetreg(RX_SNIFF_ID, RX_SNIFF_OFFSET, 0x0000);
aungriah 0:3333b6066adf 2645 pmsc_reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET);
aungriah 0:3333b6066adf 2646 pmsc_reg &= ~PMSC_CTRL0_PLL2_SEQ_EN;
aungriah 0:3333b6066adf 2647 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, pmsc_reg);
aungriah 0:3333b6066adf 2648 }
aungriah 0:3333b6066adf 2649 }
aungriah 0:3333b6066adf 2650
aungriah 0:3333b6066adf 2651 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2652 * @fn dwt_setlowpowerlistening()
aungriah 0:3333b6066adf 2653 *
aungriah 0:3333b6066adf 2654 * @brief enable/disable low-power listening mode.
aungriah 0:3333b6066adf 2655 *
aungriah 0:3333b6066adf 2656 * Low-power listening is a feature whereby the DW1000 is predominantly in the SLEEP state but wakes periodically, (after
aungriah 0:3333b6066adf 2657 * this "long sleep"), for a very short time to sample the air for a preamble sequence. This preamble sampling "listening"
aungriah 0:3333b6066adf 2658 * phase is actually two reception phases separated by a "short sleep" time. See DW1000 User Manual section "Low-Power
aungriah 0:3333b6066adf 2659 * Listening" for more details.
aungriah 0:3333b6066adf 2660 *
aungriah 0:3333b6066adf 2661 * NOTE: Before enabling low-power listening, the following functions have to be called to fully configure it:
aungriah 0:3333b6066adf 2662 * - dwt_configuresleep() to configure long sleep phase. "mode" parameter should at least have DWT_PRESRV_SLEEP,
aungriah 0:3333b6066adf 2663 * DWT_CONFIG and DWT_RX_EN set and "wake" parameter should at least have both DWT_WAKE_SLPCNT and DWT_SLP_EN set.
aungriah 0:3333b6066adf 2664 * - dwt_calibratesleepcnt() and dwt_configuresleepcnt() to define the "long sleep" phase duration.
aungriah 0:3333b6066adf 2665 * - dwt_setsnoozetime() to define the "short sleep" phase duration.
aungriah 0:3333b6066adf 2666 * - dwt_setpreambledetecttimeout() to define the reception phases duration.
aungriah 0:3333b6066adf 2667 * - dwt_setinterrupt() to activate RX good frame interrupt (DWT_INT_RFCG) only.
aungriah 0:3333b6066adf 2668 * When configured, low-power listening mode can be triggered either by putting the DW1000 to sleep (using
aungriah 0:3333b6066adf 2669 * dwt_entersleep()) or by activating reception (using dwt_rxenable()).
aungriah 0:3333b6066adf 2670 *
aungriah 0:3333b6066adf 2671 * Please refer to the low-power listening examples (examples 8a/8b accompanying the API distribution on Decawave's
aungriah 0:3333b6066adf 2672 * website). They form a working example code that shows how to use low-power listening correctly.
aungriah 0:3333b6066adf 2673 *
aungriah 0:3333b6066adf 2674 * input parameters:
aungriah 0:3333b6066adf 2675 * @param enable - 1 to enable low-power listening, 0 to disable.
aungriah 0:3333b6066adf 2676 *
aungriah 0:3333b6066adf 2677 * output parameters
aungriah 0:3333b6066adf 2678 *
aungriah 0:3333b6066adf 2679 * no return value
aungriah 0:3333b6066adf 2680 */
aungriah 0:3333b6066adf 2681 void dwt_setlowpowerlistening(int enable)
aungriah 0:3333b6066adf 2682 {
aungriah 0:3333b6066adf 2683 uint32 pmsc_reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
aungriah 0:3333b6066adf 2684 if (enable)
aungriah 0:3333b6066adf 2685 {
aungriah 0:3333b6066adf 2686 /* Configure RX to sleep and snooze features. */
aungriah 0:3333b6066adf 2687 pmsc_reg |= (PMSC_CTRL1_ARXSLP | PMSC_CTRL1_SNOZE);
aungriah 0:3333b6066adf 2688 }
aungriah 0:3333b6066adf 2689 else
aungriah 0:3333b6066adf 2690 {
aungriah 0:3333b6066adf 2691 /* Reset RX to sleep and snooze features. */
aungriah 0:3333b6066adf 2692 pmsc_reg &= ~(PMSC_CTRL1_ARXSLP | PMSC_CTRL1_SNOZE);
aungriah 0:3333b6066adf 2693 }
aungriah 0:3333b6066adf 2694 dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, pmsc_reg);
aungriah 0:3333b6066adf 2695 }
aungriah 0:3333b6066adf 2696
aungriah 0:3333b6066adf 2697 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2698 * @fn dwt_setsnoozetime()
aungriah 0:3333b6066adf 2699 *
aungriah 0:3333b6066adf 2700 * @brief Set duration of "short sleep" phase when in low-power listening mode.
aungriah 0:3333b6066adf 2701 *
aungriah 0:3333b6066adf 2702 * input parameters:
aungriah 0:3333b6066adf 2703 * @param snooze_time - "short sleep" phase duration, expressed in multiples of 512/19.2 µs (~26.7 µs). The counter
aungriah 0:3333b6066adf 2704 * automatically adds 1 to the value set. The smallest working value that should be set is 1,
aungriah 0:3333b6066adf 2705 * i.e. giving a snooze time of 2 units (or ~53 µs).
aungriah 0:3333b6066adf 2706 *
aungriah 0:3333b6066adf 2707 * output parameters
aungriah 0:3333b6066adf 2708 *
aungriah 0:3333b6066adf 2709 * no return value
aungriah 0:3333b6066adf 2710 */
aungriah 0:3333b6066adf 2711 void dwt_setsnoozetime(uint8 snooze_time)
aungriah 0:3333b6066adf 2712 {
aungriah 0:3333b6066adf 2713 dwt_write8bitoffsetreg(PMSC_ID, PMSC_SNOZT_OFFSET, snooze_time);
aungriah 0:3333b6066adf 2714 }
aungriah 0:3333b6066adf 2715
aungriah 0:3333b6066adf 2716 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2717 * @fn dwt_rxenable()
aungriah 0:3333b6066adf 2718 *
aungriah 0:3333b6066adf 2719 * @brief This call turns on the receiver, can be immediate or delayed (depending on the mode parameter). In the case of a
aungriah 0:3333b6066adf 2720 * "late" error the receiver will only be turned on if the DWT_IDLE_ON_DLY_ERR is not set.
aungriah 0:3333b6066adf 2721 * The receiver will stay turned on, listening to any messages until
aungriah 0:3333b6066adf 2722 * it either receives a good frame, an error (CRC, PHY header, Reed Solomon) or it times out (SFD, Preamble or Frame).
aungriah 0:3333b6066adf 2723 *
aungriah 0:3333b6066adf 2724 * input parameters
aungriah 0:3333b6066adf 2725 * @param mode - this can be one of the following allowed values:
aungriah 0:3333b6066adf 2726 *
aungriah 0:3333b6066adf 2727 * DWT_START_RX_IMMEDIATE 0 used to enbale receiver immediately
aungriah 0:3333b6066adf 2728 * DWT_START_RX_DELAYED 1 used to set up delayed RX, if "late" error triggers, then the RX will be enabled immediately
aungriah 0:3333b6066adf 2729 * (DWT_START_RX_DELAYED | DWT_IDLE_ON_DLY_ERR) 3 used to disable re-enabling of receiver if delayed RX failed due to "late" error
aungriah 0:3333b6066adf 2730 * (DWT_START_RX_IMMEDIATE | DWT_NO_SYNC_PTRS) 4 used to re-enable RX without trying to sync IC and host side buffer pointers, typically when
aungriah 0:3333b6066adf 2731 * performing manual RX re-enabling in double buffering mode
aungriah 0:3333b6066adf 2732 *
aungriah 0:3333b6066adf 2733 * returns DWT_SUCCESS for success, or DWT_ERROR for error (e.g. a delayed receive enable will be too far in the future if delayed time has passed)
aungriah 0:3333b6066adf 2734 */
aungriah 0:3333b6066adf 2735 int dwt_rxenable(int mode)
aungriah 0:3333b6066adf 2736 {
aungriah 0:3333b6066adf 2737 uint16 temp ;
aungriah 0:3333b6066adf 2738 uint8 temp1 ;
aungriah 0:3333b6066adf 2739
aungriah 0:3333b6066adf 2740 if ((mode & DWT_NO_SYNC_PTRS) == 0)
aungriah 0:3333b6066adf 2741 {
aungriah 0:3333b6066adf 2742 dwt_syncrxbufptrs();
aungriah 0:3333b6066adf 2743 }
aungriah 0:3333b6066adf 2744
aungriah 0:3333b6066adf 2745 temp = (uint16)SYS_CTRL_RXENAB ;
aungriah 0:3333b6066adf 2746
aungriah 0:3333b6066adf 2747 if (mode & DWT_START_RX_DELAYED)
aungriah 0:3333b6066adf 2748 {
aungriah 0:3333b6066adf 2749 temp |= (uint16)SYS_CTRL_RXDLYE ;
aungriah 0:3333b6066adf 2750 }
aungriah 0:3333b6066adf 2751
aungriah 0:3333b6066adf 2752 dwt_write16bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp);
aungriah 0:3333b6066adf 2753
aungriah 0:3333b6066adf 2754 if (mode & DWT_START_RX_DELAYED) // check for errors
aungriah 0:3333b6066adf 2755 {
aungriah 0:3333b6066adf 2756 temp1 = dwt_read8bitoffsetreg(SYS_STATUS_ID, 3); // Read 1 byte at offset 3 to get the 4th byte out of 5
aungriah 0:3333b6066adf 2757 if ((temp1 & (SYS_STATUS_HPDWARN >> 24)) != 0) // if delay has passed do immediate RX on unless DWT_IDLE_ON_DLY_ERR is true
aungriah 0:3333b6066adf 2758 {
aungriah 0:3333b6066adf 2759 dwt_forcetrxoff(); // turn the delayed receive off
aungriah 0:3333b6066adf 2760
aungriah 0:3333b6066adf 2761 if((mode & DWT_IDLE_ON_DLY_ERR) == 0) // if DWT_IDLE_ON_DLY_ERR not set then re-enable receiver
aungriah 0:3333b6066adf 2762 {
aungriah 0:3333b6066adf 2763 dwt_write16bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, SYS_CTRL_RXENAB);
aungriah 0:3333b6066adf 2764 }
aungriah 0:3333b6066adf 2765 return DWT_ERROR; // return warning indication
aungriah 0:3333b6066adf 2766 }
aungriah 0:3333b6066adf 2767 }
aungriah 0:3333b6066adf 2768
aungriah 0:3333b6066adf 2769 return DWT_SUCCESS;
aungriah 0:3333b6066adf 2770 } // end dwt_rxenable()
aungriah 0:3333b6066adf 2771
aungriah 0:3333b6066adf 2772 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2773 * @fn dwt_setrxtimeout()
aungriah 0:3333b6066adf 2774 *
aungriah 0:3333b6066adf 2775 * @brief This call enables RX timeout (SY_STAT_RFTO event)
aungriah 0:3333b6066adf 2776 *
aungriah 0:3333b6066adf 2777 * input parameters
aungriah 0:3333b6066adf 2778 * @param time - how long the receiver remains on from the RX enable command
aungriah 0:3333b6066adf 2779 * The time parameter used here is in 1.0256 us (512/499.2MHz) units
aungriah 0:3333b6066adf 2780 * If set to 0 the timeout is disabled.
aungriah 0:3333b6066adf 2781 *
aungriah 0:3333b6066adf 2782 * output parameters
aungriah 0:3333b6066adf 2783 *
aungriah 0:3333b6066adf 2784 * no return value
aungriah 0:3333b6066adf 2785 */
aungriah 0:3333b6066adf 2786 void dwt_setrxtimeout(uint16 time)
aungriah 0:3333b6066adf 2787 {
aungriah 0:3333b6066adf 2788 uint8 temp ;
aungriah 0:3333b6066adf 2789
aungriah 0:3333b6066adf 2790 temp = dwt_read8bitoffsetreg(SYS_CFG_ID, 3); // Read at offset 3 to get the upper byte only
aungriah 0:3333b6066adf 2791
aungriah 0:3333b6066adf 2792 if(time > 0)
aungriah 0:3333b6066adf 2793 {
aungriah 0:3333b6066adf 2794 dwt_write16bitoffsetreg(RX_FWTO_ID, RX_FWTO_OFFSET, time) ;
aungriah 0:3333b6066adf 2795
aungriah 0:3333b6066adf 2796 temp |= (uint8)(SYS_CFG_RXWTOE>>24); // Shift RXWTOE mask as we read the upper byte only
aungriah 0:3333b6066adf 2797 // OR in 32bit value (1 bit set), I know this is in high byte.
aungriah 0:3333b6066adf 2798 dw1000local.sysCFGreg |= SYS_CFG_RXWTOE;
aungriah 0:3333b6066adf 2799
aungriah 0:3333b6066adf 2800 dwt_write8bitoffsetreg(SYS_CFG_ID, 3, temp); // Write at offset 3 to write the upper byte only
aungriah 0:3333b6066adf 2801 }
aungriah 0:3333b6066adf 2802 else
aungriah 0:3333b6066adf 2803 {
aungriah 0:3333b6066adf 2804 temp &= ~((uint8)(SYS_CFG_RXWTOE>>24)); // Shift RXWTOE mask as we read the upper byte only
aungriah 0:3333b6066adf 2805 // AND in inverted 32bit value (1 bit clear), I know this is in high byte.
aungriah 0:3333b6066adf 2806 dw1000local.sysCFGreg &= ~(SYS_CFG_RXWTOE);
aungriah 0:3333b6066adf 2807
aungriah 0:3333b6066adf 2808 dwt_write8bitoffsetreg(SYS_CFG_ID, 3, temp); // Write at offset 3 to write the upper byte only
aungriah 0:3333b6066adf 2809 }
aungriah 0:3333b6066adf 2810
aungriah 0:3333b6066adf 2811 } // end dwt_setrxtimeout()
aungriah 0:3333b6066adf 2812
aungriah 0:3333b6066adf 2813
aungriah 0:3333b6066adf 2814 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2815 * @fn dwt_setpreambledetecttimeout()
aungriah 0:3333b6066adf 2816 *
aungriah 0:3333b6066adf 2817 * @brief This call enables preamble timeout (SY_STAT_RXPTO event)
aungriah 0:3333b6066adf 2818 *
aungriah 0:3333b6066adf 2819 * input parameters
aungriah 0:3333b6066adf 2820 * @param timeout - Preamble detection timeout, expressed in multiples of PAC size. The counter automatically adds 1 PAC
aungriah 0:3333b6066adf 2821 * size to the value set. Min value that can be set is 1 (i.e. a timeout of 2 PAC size).
aungriah 0:3333b6066adf 2822 *
aungriah 0:3333b6066adf 2823 * output parameters
aungriah 0:3333b6066adf 2824 *
aungriah 0:3333b6066adf 2825 * no return value
aungriah 0:3333b6066adf 2826 */
aungriah 0:3333b6066adf 2827 void dwt_setpreambledetecttimeout(uint16 timeout)
aungriah 0:3333b6066adf 2828 {
aungriah 0:3333b6066adf 2829 dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_PRETOC_OFFSET, timeout);
aungriah 0:3333b6066adf 2830 }
aungriah 0:3333b6066adf 2831
aungriah 0:3333b6066adf 2832 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2833 * @fn void dwt_setinterrupt()
aungriah 0:3333b6066adf 2834 *
aungriah 0:3333b6066adf 2835 * @brief This function enables the specified events to trigger an interrupt.
aungriah 0:3333b6066adf 2836 * The following events can be enabled:
aungriah 0:3333b6066adf 2837 * DWT_INT_TFRS 0x00000080 // frame sent
aungriah 0:3333b6066adf 2838 * DWT_INT_RFCG 0x00004000 // frame received with good CRC
aungriah 0:3333b6066adf 2839 * DWT_INT_RPHE 0x00001000 // receiver PHY header error
aungriah 0:3333b6066adf 2840 * DWT_INT_RFCE 0x00008000 // receiver CRC error
aungriah 0:3333b6066adf 2841 * DWT_INT_RFSL 0x00010000 // receiver sync loss error
aungriah 0:3333b6066adf 2842 * DWT_INT_RFTO 0x00020000 // frame wait timeout
aungriah 0:3333b6066adf 2843 * DWT_INT_RXPTO 0x00200000 // preamble detect timeout
aungriah 0:3333b6066adf 2844 * DWT_INT_SFDT 0x04000000 // SFD timeout
aungriah 0:3333b6066adf 2845 * DWT_INT_ARFE 0x20000000 // frame rejected (due to frame filtering configuration)
aungriah 0:3333b6066adf 2846 *
aungriah 0:3333b6066adf 2847 *
aungriah 0:3333b6066adf 2848 * input parameters:
aungriah 0:3333b6066adf 2849 * @param bitmask - sets the events which will generate interrupt
aungriah 0:3333b6066adf 2850 * @param enable - if set the interrupts are enabled else they are cleared
aungriah 0:3333b6066adf 2851 *
aungriah 0:3333b6066adf 2852 * output parameters
aungriah 0:3333b6066adf 2853 *
aungriah 0:3333b6066adf 2854 * no return value
aungriah 0:3333b6066adf 2855 */
aungriah 0:3333b6066adf 2856 void dwt_setinterrupt(uint32 bitmask, uint8 enable)
aungriah 0:3333b6066adf 2857 {
aungriah 0:3333b6066adf 2858 decaIrqStatus_t stat ;
aungriah 0:3333b6066adf 2859 uint32 mask ;
aungriah 0:3333b6066adf 2860
aungriah 0:3333b6066adf 2861 // Need to beware of interrupts occurring in the middle of following read modify write cycle
aungriah 0:3333b6066adf 2862 stat = decamutexon() ;
aungriah 0:3333b6066adf 2863
aungriah 0:3333b6066adf 2864 mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read register
aungriah 0:3333b6066adf 2865
aungriah 0:3333b6066adf 2866 if(enable)
aungriah 0:3333b6066adf 2867 {
aungriah 0:3333b6066adf 2868 mask |= bitmask ;
aungriah 0:3333b6066adf 2869 }
aungriah 0:3333b6066adf 2870 else
aungriah 0:3333b6066adf 2871 {
aungriah 0:3333b6066adf 2872 mask &= ~bitmask ; // Clear the bit
aungriah 0:3333b6066adf 2873 }
aungriah 0:3333b6066adf 2874 dwt_write32bitreg(SYS_MASK_ID,mask) ; // New value
aungriah 0:3333b6066adf 2875
aungriah 0:3333b6066adf 2876 decamutexoff(stat) ;
aungriah 0:3333b6066adf 2877 }
aungriah 0:3333b6066adf 2878
aungriah 0:3333b6066adf 2879 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2880 * @fn dwt_configeventcounters()
aungriah 0:3333b6066adf 2881 *
aungriah 0:3333b6066adf 2882 * @brief This is used to enable/disable the event counter in the IC
aungriah 0:3333b6066adf 2883 *
aungriah 0:3333b6066adf 2884 * input parameters
aungriah 0:3333b6066adf 2885 * @param - enable - 1 enables (and reset), 0 disables the event counters
aungriah 0:3333b6066adf 2886 * output parameters
aungriah 0:3333b6066adf 2887 *
aungriah 0:3333b6066adf 2888 * no return value
aungriah 0:3333b6066adf 2889 */
aungriah 0:3333b6066adf 2890 void dwt_configeventcounters(int enable)
aungriah 0:3333b6066adf 2891 {
aungriah 0:3333b6066adf 2892 // Need to clear and disable, can't just clear
aungriah 0:3333b6066adf 2893 dwt_write8bitoffsetreg(DIG_DIAG_ID, EVC_CTRL_OFFSET, (uint8)(EVC_CLR));
aungriah 0:3333b6066adf 2894
aungriah 0:3333b6066adf 2895 if(enable)
aungriah 0:3333b6066adf 2896 {
aungriah 0:3333b6066adf 2897 dwt_write8bitoffsetreg(DIG_DIAG_ID, EVC_CTRL_OFFSET, (uint8)(EVC_EN)); // Enable
aungriah 0:3333b6066adf 2898 }
aungriah 0:3333b6066adf 2899 }
aungriah 0:3333b6066adf 2900
aungriah 0:3333b6066adf 2901 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2902 * @fn dwt_readeventcounters()
aungriah 0:3333b6066adf 2903 *
aungriah 0:3333b6066adf 2904 * @brief This is used to read the event counters in the IC
aungriah 0:3333b6066adf 2905 *
aungriah 0:3333b6066adf 2906 * input parameters
aungriah 0:3333b6066adf 2907 * @param counters - pointer to the dwt_deviceentcnts_t structure which will hold the read data
aungriah 0:3333b6066adf 2908 *
aungriah 0:3333b6066adf 2909 * output parameters
aungriah 0:3333b6066adf 2910 *
aungriah 0:3333b6066adf 2911 * no return value
aungriah 0:3333b6066adf 2912 */
aungriah 0:3333b6066adf 2913 void dwt_readeventcounters(dwt_deviceentcnts_t *counters)
aungriah 0:3333b6066adf 2914 {
aungriah 0:3333b6066adf 2915 uint32 temp;
aungriah 0:3333b6066adf 2916
aungriah 0:3333b6066adf 2917 temp= dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_PHE_OFFSET); // Read sync loss (31-16), PHE (15-0)
aungriah 0:3333b6066adf 2918 counters->PHE = temp & 0xFFF;
aungriah 0:3333b6066adf 2919 counters->RSL = (temp >> 16) & 0xFFF;
aungriah 0:3333b6066adf 2920
aungriah 0:3333b6066adf 2921 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_FCG_OFFSET); // Read CRC bad (31-16), CRC good (15-0)
aungriah 0:3333b6066adf 2922 counters->CRCG = temp & 0xFFF;
aungriah 0:3333b6066adf 2923 counters->CRCB = (temp >> 16) & 0xFFF;
aungriah 0:3333b6066adf 2924
aungriah 0:3333b6066adf 2925 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_FFR_OFFSET); // Overruns (31-16), address errors (15-0)
aungriah 0:3333b6066adf 2926 counters->ARFE = temp & 0xFFF;
aungriah 0:3333b6066adf 2927 counters->OVER = (temp >> 16) & 0xFFF;
aungriah 0:3333b6066adf 2928
aungriah 0:3333b6066adf 2929 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_STO_OFFSET); // Read PTO (31-16), SFDTO (15-0)
aungriah 0:3333b6066adf 2930 counters->PTO = (temp >> 16) & 0xFFF;
aungriah 0:3333b6066adf 2931 counters->SFDTO = temp & 0xFFF;
aungriah 0:3333b6066adf 2932
aungriah 0:3333b6066adf 2933 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_FWTO_OFFSET); // Read RX TO (31-16), TXFRAME (15-0)
aungriah 0:3333b6066adf 2934 counters->TXF = (temp >> 16) & 0xFFF;
aungriah 0:3333b6066adf 2935 counters->RTO = temp & 0xFFF;
aungriah 0:3333b6066adf 2936
aungriah 0:3333b6066adf 2937 temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_HPW_OFFSET); // Read half period warning events
aungriah 0:3333b6066adf 2938 counters->HPW = temp & 0xFFF;
aungriah 0:3333b6066adf 2939 counters->TXW = (temp >> 16) & 0xFFF; // Power-up warning events
aungriah 0:3333b6066adf 2940
aungriah 0:3333b6066adf 2941 }
aungriah 0:3333b6066adf 2942
aungriah 0:3333b6066adf 2943 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2944 * @fn dwt_rxreset()
aungriah 0:3333b6066adf 2945 *
aungriah 0:3333b6066adf 2946 * @brief this function resets the receiver of the DW1000
aungriah 0:3333b6066adf 2947 *
aungriah 0:3333b6066adf 2948 * input parameters:
aungriah 0:3333b6066adf 2949 *
aungriah 0:3333b6066adf 2950 * output parameters
aungriah 0:3333b6066adf 2951 *
aungriah 0:3333b6066adf 2952 * no return value
aungriah 0:3333b6066adf 2953 */
aungriah 0:3333b6066adf 2954 void dwt_rxreset(void)
aungriah 0:3333b6066adf 2955 {
aungriah 0:3333b6066adf 2956 // Set RX reset
aungriah 0:3333b6066adf 2957 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_RX);
aungriah 0:3333b6066adf 2958
aungriah 0:3333b6066adf 2959 // Clear RX reset
aungriah 0:3333b6066adf 2960 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_CLEAR);
aungriah 0:3333b6066adf 2961 }
aungriah 0:3333b6066adf 2962
aungriah 0:3333b6066adf 2963 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2964 * @fn dwt_softreset()
aungriah 0:3333b6066adf 2965 *
aungriah 0:3333b6066adf 2966 * @brief this function resets the DW1000
aungriah 0:3333b6066adf 2967 *
aungriah 0:3333b6066adf 2968 * input parameters:
aungriah 0:3333b6066adf 2969 *
aungriah 0:3333b6066adf 2970 * output parameters
aungriah 0:3333b6066adf 2971 *
aungriah 0:3333b6066adf 2972 * no return value
aungriah 0:3333b6066adf 2973 */
aungriah 0:3333b6066adf 2974 void dwt_softreset(void)
aungriah 0:3333b6066adf 2975 {
aungriah 0:3333b6066adf 2976 _dwt_disablesequencing();
aungriah 0:3333b6066adf 2977
aungriah 0:3333b6066adf 2978 // Clear any AON auto download bits (as reset will trigger AON download)
aungriah 0:3333b6066adf 2979 dwt_write16bitoffsetreg(AON_ID, AON_WCFG_OFFSET, 0x00);
aungriah 0:3333b6066adf 2980 // Clear the wake-up configuration
aungriah 0:3333b6066adf 2981 dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, 0x00);
aungriah 0:3333b6066adf 2982 // Upload the new configuration
aungriah 0:3333b6066adf 2983 _dwt_aonarrayupload();
aungriah 0:3333b6066adf 2984
aungriah 0:3333b6066adf 2985 // Reset HIF, TX, RX and PMSC
aungriah 0:3333b6066adf 2986 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_ALL);
aungriah 0:3333b6066adf 2987
aungriah 0:3333b6066adf 2988 // DW1000 needs a 10us sleep to let clk PLL lock after reset - the PLL will automatically lock after the reset
aungriah 0:3333b6066adf 2989 // Could also have polled the PLL lock flag, but then the SPI needs to be < 3MHz !! So a simple delay is easier
aungriah 0:3333b6066adf 2990 deca_sleep(1);
aungriah 0:3333b6066adf 2991
aungriah 0:3333b6066adf 2992 // Clear reset
aungriah 0:3333b6066adf 2993 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_SOFTRESET_OFFSET, PMSC_CTRL0_RESET_CLEAR);
aungriah 0:3333b6066adf 2994
aungriah 0:3333b6066adf 2995 dw1000local.wait4resp = 0;
aungriah 0:3333b6066adf 2996 }
aungriah 0:3333b6066adf 2997
aungriah 0:3333b6066adf 2998 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 2999 * @fn dwt_setxtaltrim()
aungriah 0:3333b6066adf 3000 *
aungriah 0:3333b6066adf 3001 * @brief This is used to adjust the crystal frequency
aungriah 0:3333b6066adf 3002 *
aungriah 0:3333b6066adf 3003 * input parameters:
aungriah 0:3333b6066adf 3004 * @param value - crystal trim value (in range 0x0 to 0x1F) 31 steps (~1.5ppm per step)
aungriah 0:3333b6066adf 3005 *
aungriah 0:3333b6066adf 3006 * output parameters
aungriah 0:3333b6066adf 3007 *
aungriah 0:3333b6066adf 3008 * no return value
aungriah 0:3333b6066adf 3009 */
aungriah 0:3333b6066adf 3010 void dwt_setxtaltrim(uint8 value)
aungriah 0:3333b6066adf 3011 {
aungriah 0:3333b6066adf 3012 // The 3 MSb in this 8-bit register must be kept to 0b011 to avoid any malfunction.
aungriah 0:3333b6066adf 3013 uint8 reg_val = (3 << 5) | (value & FS_XTALT_MASK);
aungriah 0:3333b6066adf 3014 dwt_write8bitoffsetreg(FS_CTRL_ID, FS_XTALT_OFFSET, reg_val);
aungriah 0:3333b6066adf 3015 }
aungriah 0:3333b6066adf 3016
aungriah 0:3333b6066adf 3017 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 3018 * @fn dwt_getinitxtaltrim()
aungriah 0:3333b6066adf 3019 *
aungriah 0:3333b6066adf 3020 * @brief This function returns the value of XTAL trim that has been applied during initialisation (dwt_init). This can
aungriah 0:3333b6066adf 3021 * be either the value read in OTP memory or a default value.
aungriah 0:3333b6066adf 3022 *
aungriah 0:3333b6066adf 3023 * NOTE: The value returned by this function is the initial value only! It is not updated on dwt_setxtaltrim calls.
aungriah 0:3333b6066adf 3024 *
aungriah 0:3333b6066adf 3025 * input parameters
aungriah 0:3333b6066adf 3026 *
aungriah 0:3333b6066adf 3027 * output parameters
aungriah 0:3333b6066adf 3028 *
aungriah 0:3333b6066adf 3029 * returns the XTAL trim value set upon initialisation
aungriah 0:3333b6066adf 3030 */
aungriah 0:3333b6066adf 3031 uint8 dwt_getinitxtaltrim(void)
aungriah 0:3333b6066adf 3032 {
aungriah 0:3333b6066adf 3033 return dw1000local.init_xtrim;
aungriah 0:3333b6066adf 3034 }
aungriah 0:3333b6066adf 3035
aungriah 0:3333b6066adf 3036 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 3037 * @fn dwt_configcwmode()
aungriah 0:3333b6066adf 3038 *
aungriah 0:3333b6066adf 3039 * @brief this function sets the DW1000 to transmit cw signal at specific channel frequency
aungriah 0:3333b6066adf 3040 *
aungriah 0:3333b6066adf 3041 * input parameters:
aungriah 0:3333b6066adf 3042 * @param chan - specifies the operating channel (e.g. 1, 2, 3, 4, 5, 6 or 7)
aungriah 0:3333b6066adf 3043 *
aungriah 0:3333b6066adf 3044 * output parameters
aungriah 0:3333b6066adf 3045 *
aungriah 0:3333b6066adf 3046 * no return value
aungriah 0:3333b6066adf 3047 */
aungriah 0:3333b6066adf 3048 void dwt_configcwmode(uint8 chan)
aungriah 0:3333b6066adf 3049 {
aungriah 0:3333b6066adf 3050 #ifdef DWT_API_ERROR_CHECK
aungriah 0:3333b6066adf 3051 assert((chan >= 1) && (chan <= 7) && (chan != 6));
aungriah 0:3333b6066adf 3052 #endif
aungriah 0:3333b6066adf 3053
aungriah 0:3333b6066adf 3054 //
aungriah 0:3333b6066adf 3055 // Disable TX/RX RF block sequencing (needed for cw frame mode)
aungriah 0:3333b6066adf 3056 //
aungriah 0:3333b6066adf 3057 _dwt_disablesequencing();
aungriah 0:3333b6066adf 3058
aungriah 0:3333b6066adf 3059 // Config RF pll (for a given channel)
aungriah 0:3333b6066adf 3060 // Configure PLL2/RF PLL block CFG/TUNE
aungriah 0:3333b6066adf 3061 dwt_write32bitoffsetreg(FS_CTRL_ID, FS_PLLCFG_OFFSET, fs_pll_cfg[chan_idx[chan]]);
aungriah 0:3333b6066adf 3062 dwt_write8bitoffsetreg(FS_CTRL_ID, FS_PLLTUNE_OFFSET, fs_pll_tune[chan_idx[chan]]);
aungriah 0:3333b6066adf 3063 // PLL wont be enabled until a TX/RX enable is issued later on
aungriah 0:3333b6066adf 3064 // Configure RF TX blocks (for specified channel and prf)
aungriah 0:3333b6066adf 3065 // Config RF TX control
aungriah 0:3333b6066adf 3066 dwt_write32bitoffsetreg(RF_CONF_ID, RF_TXCTRL_OFFSET, tx_config[chan_idx[chan]]);
aungriah 0:3333b6066adf 3067
aungriah 0:3333b6066adf 3068 //
aungriah 0:3333b6066adf 3069 // Enable RF PLL
aungriah 0:3333b6066adf 3070 //
aungriah 0:3333b6066adf 3071 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXPLLPOWEN_MASK); // Enable LDO and RF PLL blocks
aungriah 0:3333b6066adf 3072 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXALLEN_MASK); // Enable the rest of TX blocks
aungriah 0:3333b6066adf 3073
aungriah 0:3333b6066adf 3074 //
aungriah 0:3333b6066adf 3075 // Configure TX clocks
aungriah 0:3333b6066adf 3076 //
aungriah 0:3333b6066adf 3077 dwt_write8bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, 0x22);
aungriah 0:3333b6066adf 3078 dwt_write8bitoffsetreg(PMSC_ID, 0x1, 0x07);
aungriah 0:3333b6066adf 3079
aungriah 0:3333b6066adf 3080 // Disable fine grain TX sequencing
aungriah 0:3333b6066adf 3081 dwt_setfinegraintxseq(0);
aungriah 0:3333b6066adf 3082
aungriah 0:3333b6066adf 3083 // Configure CW mode
aungriah 0:3333b6066adf 3084 dwt_write8bitoffsetreg(TX_CAL_ID, TC_PGTEST_OFFSET, TC_PGTEST_CW);
aungriah 0:3333b6066adf 3085 }
aungriah 0:3333b6066adf 3086
aungriah 0:3333b6066adf 3087 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 3088 * @fn dwt_configcontinuousframemode()
aungriah 0:3333b6066adf 3089 *
aungriah 0:3333b6066adf 3090 * @brief this function sets the DW1000 to continuous tx frame mode for regulatory approvals testing.
aungriah 0:3333b6066adf 3091 *
aungriah 0:3333b6066adf 3092 * input parameters:
aungriah 0:3333b6066adf 3093 * @param framerepetitionrate - This is a 32-bit value that is used to set the interval between transmissions.
aungriah 0:3333b6066adf 3094 * The minimum value is 4. The units are approximately 8 ns. (or more precisely 512/(499.2e6*128) seconds)).
aungriah 0:3333b6066adf 3095 *
aungriah 0:3333b6066adf 3096 * output parameters
aungriah 0:3333b6066adf 3097 *
aungriah 0:3333b6066adf 3098 * no return value
aungriah 0:3333b6066adf 3099 */
aungriah 0:3333b6066adf 3100 void dwt_configcontinuousframemode(uint32 framerepetitionrate)
aungriah 0:3333b6066adf 3101 {
aungriah 0:3333b6066adf 3102 //
aungriah 0:3333b6066adf 3103 // Disable TX/RX RF block sequencing (needed for continuous frame mode)
aungriah 0:3333b6066adf 3104 //
aungriah 0:3333b6066adf 3105 _dwt_disablesequencing();
aungriah 0:3333b6066adf 3106
aungriah 0:3333b6066adf 3107 //
aungriah 0:3333b6066adf 3108 // Enable RF PLL and TX blocks
aungriah 0:3333b6066adf 3109 //
aungriah 0:3333b6066adf 3110 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXPLLPOWEN_MASK); // Enable LDO and RF PLL blocks
aungriah 0:3333b6066adf 3111 dwt_write32bitreg(RF_CONF_ID, RF_CONF_TXALLEN_MASK); // Enable the rest of TX blocks
aungriah 0:3333b6066adf 3112
aungriah 0:3333b6066adf 3113 //
aungriah 0:3333b6066adf 3114 // Configure TX clocks
aungriah 0:3333b6066adf 3115 //
aungriah 0:3333b6066adf 3116 _dwt_enableclocks(FORCE_SYS_PLL);
aungriah 0:3333b6066adf 3117 _dwt_enableclocks(FORCE_TX_PLL);
aungriah 0:3333b6066adf 3118
aungriah 0:3333b6066adf 3119 // Set the frame repetition rate
aungriah 0:3333b6066adf 3120 if(framerepetitionrate < 4)
aungriah 0:3333b6066adf 3121 {
aungriah 0:3333b6066adf 3122 framerepetitionrate = 4;
aungriah 0:3333b6066adf 3123 }
aungriah 0:3333b6066adf 3124 dwt_write32bitreg(DX_TIME_ID, framerepetitionrate);
aungriah 0:3333b6066adf 3125
aungriah 0:3333b6066adf 3126 //
aungriah 0:3333b6066adf 3127 // Configure continuous frame TX
aungriah 0:3333b6066adf 3128 //
aungriah 0:3333b6066adf 3129 dwt_write8bitoffsetreg(DIG_DIAG_ID, DIAG_TMC_OFFSET, (uint8)(DIAG_TMC_TX_PSTM)); // Turn the tx power spectrum test mode - continuous sending of frames
aungriah 0:3333b6066adf 3130 }
aungriah 0:3333b6066adf 3131
aungriah 0:3333b6066adf 3132 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 3133 * @fn dwt_readtempvbat()
aungriah 0:3333b6066adf 3134 *
aungriah 0:3333b6066adf 3135 * @brief this function reads the battery voltage and temperature of the MP
aungriah 0:3333b6066adf 3136 * The values read here will be the current values sampled by DW1000 AtoD converters.
aungriah 0:3333b6066adf 3137 * Note on Temperature: the temperature value needs to be converted to give the real temperature
aungriah 0:3333b6066adf 3138 * the formula is: 1.13 * reading - 113.0
aungriah 0:3333b6066adf 3139 * Note on Voltage: the voltage value needs to be converted to give the real voltage
aungriah 0:3333b6066adf 3140 * the formula is: 0.0057 * reading + 2.3
aungriah 0:3333b6066adf 3141 *
aungriah 0:3333b6066adf 3142 * NB: To correctly read the temperature this read should be done with xtal clock
aungriah 0:3333b6066adf 3143 * however that means that the receiver will be switched off, if receiver needs to be on then
aungriah 0:3333b6066adf 3144 * the timer is used to make sure the value is stable before reading
aungriah 0:3333b6066adf 3145 *
aungriah 0:3333b6066adf 3146 * input parameters:
aungriah 0:3333b6066adf 3147 * @param fastSPI - set to 1 if SPI rate > than 3MHz is used
aungriah 0:3333b6066adf 3148 *
aungriah 0:3333b6066adf 3149 * output parameters
aungriah 0:3333b6066adf 3150 *
aungriah 0:3333b6066adf 3151 * returns (temp_raw<<8)|(vbat_raw)
aungriah 0:3333b6066adf 3152 */
aungriah 0:3333b6066adf 3153 uint16 dwt_readtempvbat(uint8 fastSPI)
aungriah 0:3333b6066adf 3154 {
aungriah 0:3333b6066adf 3155 uint8 wr_buf[2];
aungriah 0:3333b6066adf 3156 uint8 vbat_raw;
aungriah 0:3333b6066adf 3157 uint8 temp_raw;
aungriah 0:3333b6066adf 3158
aungriah 0:3333b6066adf 3159 // These writes should be single writes and in sequence
aungriah 0:3333b6066adf 3160 wr_buf[0] = 0x80; // Enable TLD Bias
aungriah 0:3333b6066adf 3161 dwt_writetodevice(RF_CONF_ID,0x11,1,wr_buf);
aungriah 0:3333b6066adf 3162
aungriah 0:3333b6066adf 3163 wr_buf[0] = 0x0A; // Enable TLD Bias and ADC Bias
aungriah 0:3333b6066adf 3164 dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf);
aungriah 0:3333b6066adf 3165
aungriah 0:3333b6066adf 3166 wr_buf[0] = 0x0f; // Enable Outputs (only after Biases are up and running)
aungriah 0:3333b6066adf 3167 dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf); //
aungriah 0:3333b6066adf 3168
aungriah 0:3333b6066adf 3169 // Reading All SAR inputs
aungriah 0:3333b6066adf 3170 wr_buf[0] = 0x00;
aungriah 0:3333b6066adf 3171 dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
aungriah 0:3333b6066adf 3172 wr_buf[0] = 0x01; // Set SAR enable
aungriah 0:3333b6066adf 3173 dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
aungriah 0:3333b6066adf 3174
aungriah 0:3333b6066adf 3175 if(fastSPI == 1)
aungriah 0:3333b6066adf 3176 {
aungriah 0:3333b6066adf 3177 deca_sleep(1); // If using PLL clocks(and fast SPI rate) then this sleep is needed
aungriah 0:3333b6066adf 3178 // Read voltage and temperature.
aungriah 0:3333b6066adf 3179 dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
aungriah 0:3333b6066adf 3180 }
aungriah 0:3333b6066adf 3181 else //change to a slow clock
aungriah 0:3333b6066adf 3182 {
aungriah 0:3333b6066adf 3183 _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read are reliable
aungriah 0:3333b6066adf 3184 // Read voltage and temperature.
aungriah 0:3333b6066adf 3185 dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
aungriah 0:3333b6066adf 3186 // Default clocks (ENABLE_ALL_SEQ)
aungriah 0:3333b6066adf 3187 _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
aungriah 0:3333b6066adf 3188 }
aungriah 0:3333b6066adf 3189
aungriah 0:3333b6066adf 3190 vbat_raw = wr_buf[0];
aungriah 0:3333b6066adf 3191 temp_raw = wr_buf[1];
aungriah 0:3333b6066adf 3192
aungriah 0:3333b6066adf 3193 wr_buf[0] = 0x00; // Clear SAR enable
aungriah 0:3333b6066adf 3194 dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
aungriah 0:3333b6066adf 3195
aungriah 0:3333b6066adf 3196 return ((temp_raw<<8)|(vbat_raw));
aungriah 0:3333b6066adf 3197 }
aungriah 0:3333b6066adf 3198
aungriah 0:3333b6066adf 3199 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 3200 * @fn dwt_readwakeuptemp()
aungriah 0:3333b6066adf 3201 *
aungriah 0:3333b6066adf 3202 * @brief this function reads the temperature of the DW1000 that was sampled
aungriah 0:3333b6066adf 3203 * on waking from Sleep/Deepsleep. They are not current values, but read on last
aungriah 0:3333b6066adf 3204 * wakeup if DWT_TANDV bit is set in mode parameter of dwt_configuresleep
aungriah 0:3333b6066adf 3205 *
aungriah 0:3333b6066adf 3206 * input parameters:
aungriah 0:3333b6066adf 3207 *
aungriah 0:3333b6066adf 3208 * output parameters:
aungriah 0:3333b6066adf 3209 *
aungriah 0:3333b6066adf 3210 * returns: 8-bit raw temperature sensor value
aungriah 0:3333b6066adf 3211 */
aungriah 0:3333b6066adf 3212 uint8 dwt_readwakeuptemp(void)
aungriah 0:3333b6066adf 3213 {
aungriah 0:3333b6066adf 3214 return dwt_read8bitoffsetreg(TX_CAL_ID, TC_SARL_SAR_LTEMP_OFFSET);
aungriah 0:3333b6066adf 3215 }
aungriah 0:3333b6066adf 3216
aungriah 0:3333b6066adf 3217 /*! ------------------------------------------------------------------------------------------------------------------
aungriah 0:3333b6066adf 3218 * @fn dwt_readwakeupvbat()
aungriah 0:3333b6066adf 3219 *
aungriah 0:3333b6066adf 3220 * @brief this function reads the battery voltage of the DW1000 that was sampled
aungriah 0:3333b6066adf 3221 * on waking from Sleep/Deepsleep. They are not current values, but read on last
aungriah 0:3333b6066adf 3222 * wakeup if DWT_TANDV bit is set in mode parameter of dwt_configuresleep
aungriah 0:3333b6066adf 3223 *
aungriah 0:3333b6066adf 3224 * input parameters:
aungriah 0:3333b6066adf 3225 *
aungriah 0:3333b6066adf 3226 * output parameters:
aungriah 0:3333b6066adf 3227 *
aungriah 0:3333b6066adf 3228 * returns: 8-bit raw battery voltage sensor value
aungriah 0:3333b6066adf 3229 */
aungriah 0:3333b6066adf 3230 uint8 dwt_readwakeupvbat(void)
aungriah 0:3333b6066adf 3231 {
aungriah 0:3333b6066adf 3232 return dwt_read8bitoffsetreg(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET);
aungriah 0:3333b6066adf 3233 }
aungriah 0:3333b6066adf 3234
aungriah 0:3333b6066adf 3235
aungriah 0:3333b6066adf 3236 /* ===============================================================================================
aungriah 0:3333b6066adf 3237 List of expected (known) device ID handled by this software
aungriah 0:3333b6066adf 3238 ===============================================================================================
aungriah 0:3333b6066adf 3239
aungriah 0:3333b6066adf 3240 0xDECA0130 // DW1000 - MP
aungriah 0:3333b6066adf 3241
aungriah 0:3333b6066adf 3242 ===============================================================================================
aungriah 0:3333b6066adf 3243 */
aungriah 0:3333b6066adf 3244
aungriah 0:3333b6066adf 3245