Alejandro Ungria Hirte / GA-Test

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Dependencies:   mbed-dev

DecaWave/SMConfig.h@0:3333b6066adf, 2017-12-06 (annotated)

Committer:
aungriah
Date:
Wed Dec 06 21:42:54 2017 +0000
Revision:
0:3333b6066adf
asfaf

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aungriah 0:3333b6066adf 1 #ifndef _SMCONFIG_H_
aungriah 0:3333b6066adf 2 #define _SMCONFIG_H_
aungriah 0:3333b6066adf 3
aungriah 0:3333b6066adf 4 #include "mbed.h"
aungriah 0:3333b6066adf 5 #include "deca_device_api.h"
aungriah 0:3333b6066adf 6 #include "deca_param_types.h"
aungriah 0:3333b6066adf 7 //#include "frames.h"
aungriah 0:3333b6066adf 8
aungriah 0:3333b6066adf 9 #define DWT_PRF_64M_RFDLY (515.2f)
aungriah 0:3333b6066adf 10 #define DWT_PRF_16M_RFDLY (514.7f)
aungriah 0:3333b6066adf 11
aungriah 0:3333b6066adf 12
aungriah 0:3333b6066adf 13 struct ppsConfig_s {
aungriah 0:3333b6066adf 14 /*PPS_Role*/ int Role;
aungriah 0:3333b6066adf 15
aungriah 0:3333b6066adf 16 PinName SpiMosi;
aungriah 0:3333b6066adf 17 PinName SpiMiso;
aungriah 0:3333b6066adf 18 PinName SpiClk;
aungriah 0:3333b6066adf 19
aungriah 0:3333b6066adf 20 PinName DwCs;
aungriah 0:3333b6066adf 21 PinName DwIrq;
aungriah 0:3333b6066adf 22 PinName DwRst;
aungriah 0:3333b6066adf 23
aungriah 0:3333b6066adf 24 PinName LedGreen;
aungriah 0:3333b6066adf 25 PinName LedRed;
aungriah 0:3333b6066adf 26
aungriah 0:3333b6066adf 27 PinName BatIn;
aungriah 0:3333b6066adf 28 PinName Buzzer;
aungriah 0:3333b6066adf 29 PinName Vibra;
aungriah 0:3333b6066adf 30
aungriah 0:3333b6066adf 31 PinName CanRx;
aungriah 0:3333b6066adf 32 PinName CanTx;
aungriah 0:3333b6066adf 33 PinName CanStandby;
aungriah 0:3333b6066adf 34
aungriah 0:3333b6066adf 35 PinName I2cSda;
aungriah 0:3333b6066adf 36 PinName I2cScl;
aungriah 0:3333b6066adf 37
aungriah 0:3333b6066adf 38 PinName DipSwitch0;
aungriah 0:3333b6066adf 39 PinName DipSwitch1;
aungriah 0:3333b6066adf 40 PinName DipSwitch2;
aungriah 0:3333b6066adf 41 PinName DipSwitch3;
aungriah 0:3333b6066adf 42 PinName DipSwitch4;
aungriah 0:3333b6066adf 43 PinName DipSwitch5;
aungriah 0:3333b6066adf 44 PinName DipSwitch6;
aungriah 0:3333b6066adf 45 PinName DipSwitch7;
aungriah 0:3333b6066adf 46 };
aungriah 0:3333b6066adf 47
aungriah 0:3333b6066adf 48 typedef ppsConfig_s ppsConfig_t;
aungriah 0:3333b6066adf 49
aungriah 0:3333b6066adf 50 struct chConfig_t {
aungriah 0:3333b6066adf 51 uint8_t channel ;
aungriah 0:3333b6066adf 52 uint8_t prf ;
aungriah 0:3333b6066adf 53 uint8_t datarate ;
aungriah 0:3333b6066adf 54 uint8_t preambleCode ;
aungriah 0:3333b6066adf 55 uint8_t preambleLength ;
aungriah 0:3333b6066adf 56 uint8_t pacSize ;
aungriah 0:3333b6066adf 57 uint8_t nsSFD ;
aungriah 0:3333b6066adf 58 uint16_t sfdTO ;
aungriah 0:3333b6066adf 59 };
aungriah 0:3333b6066adf 60
aungriah 0:3333b6066adf 61 struct tx_struct {
aungriah 0:3333b6066adf 62 uint8_t PGdelay;
aungriah 0:3333b6066adf 63
aungriah 0:3333b6066adf 64 //TX POWER
aungriah 0:3333b6066adf 65 //31:24 BOOST_0.125ms_PWR
aungriah 0:3333b6066adf 66 //23:16 BOOST_0.25ms_PWR-TX_SHR_PWR
aungriah 0:3333b6066adf 67 //15:8 BOOST_0.5ms_PWR-TX_PHR_PWR
aungriah 0:3333b6066adf 68 //7:0 DEFAULT_PWR-TX_DATA_PWR
aungriah 0:3333b6066adf 69 uint32_t txPwr[2]; //
aungriah 0:3333b6066adf 70 };
aungriah 0:3333b6066adf 71
aungriah 0:3333b6066adf 72 void SMsetconfig(uint8_t dr_mode, dwt_config_t *dw_config, dwt_txconfig_t *dw_configtx);
aungriah 0:3333b6066adf 73 uint8_t SMpower(float gain);
aungriah 0:3333b6066adf 74 float SMgain(uint8_t power);
aungriah 0:3333b6066adf 75
aungriah 0:3333b6066adf 76 extern const agc_cfg_struct agc_config ;
aungriah 0:3333b6066adf 77
aungriah 0:3333b6066adf 78 //SFD threshold settings for 110k, 850k, 6.8Mb standard and non-standard
aungriah 0:3333b6066adf 79 extern const uint16_t sftsh[NUM_BR][NUM_SFD];
aungriah 0:3333b6066adf 80
aungriah 0:3333b6066adf 81 extern const uint16_t dtune1[NUM_PRF];
aungriah 0:3333b6066adf 82
aungriah 0:3333b6066adf 83 #define XMLPARAMS_VERSION (1.17f)
aungriah 0:3333b6066adf 84
aungriah 0:3333b6066adf 85 extern const uint8_t pll2_config[NUM_CH][5];
aungriah 0:3333b6066adf 86 extern const uint8_t pll2calcfg;
aungriah 0:3333b6066adf 87 extern const uint8_t rx_config[NUM_BW];
aungriah 0:3333b6066adf 88 //extern const uint32_t tx_config[NUM_CH];
aungriah 0:3333b6066adf 89 extern const uint8_t dwnsSFDlen[NUM_BR]; //length of SFD for each of the bitrates
aungriah 0:3333b6066adf 90 //extern const uint32_t digital_bb_config[NUM_PRF][NUM_PACS];
aungriah 0:3333b6066adf 91 extern const uint8_t chan_idx[NUM_CH_SUPPORTED];
aungriah 0:3333b6066adf 92
aungriah 0:3333b6066adf 93 extern const uint16_t lde_replicaCoeff[PCODES];
aungriah 0:3333b6066adf 94 extern const tx_struct txSpectrumConfig[NUM_CH_SUPPORTED];
aungriah 0:3333b6066adf 95 extern const uint16_t rfDelays[NUM_PRF];
aungriah 0:3333b6066adf 96
aungriah 0:3333b6066adf 97 extern const chConfig_t chConfig[NUM_CH_SUPPORTED];
aungriah 0:3333b6066adf 98 extern const float ChannelFrequency[NUM_CH_SUPPORTED];
aungriah 0:3333b6066adf 99 extern const float ChannelBandwidth[NUM_CH_SUPPORTED];
aungriah 0:3333b6066adf 100 extern const char* ChannelBitrate[3];
aungriah 0:3333b6066adf 101 extern const char* ChannelPRF[3];
aungriah 0:3333b6066adf 102 extern const uint8_t ChannelPAC[4];
aungriah 0:3333b6066adf 103 extern uint16_t ChannelPLEN(uint8_t PLEN);
aungriah 0:3333b6066adf 104
aungriah 0:3333b6066adf 105 extern const tx_struct txSpectrumConfig[NUM_CH_SUPPORTED];
aungriah 0:3333b6066adf 106 #endif
aungriah 0:3333b6066adf 107