Atar Babgei / SX1276Lib

Fork of SX1276 Lib

Fork of SX1276Lib by Semtech

sx1276/sx1276-hal.cpp@29:d0d219851731, 2017-01-23 (annotated)

Committer:
atarbey
Date:
Mon Jan 23 12:18:01 2017 +0000
Revision:
29:d0d219851731
Parent:
28:8fb2ff77baef 
Modified for Drifter v1.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 22 PinName antSwitch )
mluis 21:2e496deb7858 23 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
GregCr 0:e6ceb13d2d05 24 antSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 25 #if( defined ( TARGET_NUCLEO_L152RE ) )
GregCr 12:aa5b3bf7fdf4 26 fake( D8 )
atarbey 28:8fb2ff77baef 27 #elif ( defined( TARGET_MOTE_L152RC ) || defined( TARGET_XDOT_L151CC) )
atarbey 27:2aed13d8cd19 28 fake( PB_2 )
GregCr 12:aa5b3bf7fdf4 29 #else
GregCr 0:e6ceb13d2d05 30 fake( A3 )
GregCr 0:e6ceb13d2d05 31 #endif
GregCr 0:e6ceb13d2d05 32 {
mluis 21:2e496deb7858 33 this->RadioEvents = events;
mluis 21:2e496deb7858 34
GregCr 0:e6ceb13d2d05 35 Reset( );
GregCr 0:e6ceb13d2d05 36
GregCr 0:e6ceb13d2d05 37 RxChainCalibration( );
GregCr 0:e6ceb13d2d05 38
GregCr 0:e6ceb13d2d05 39 IoInit( );
GregCr 0:e6ceb13d2d05 40
GregCr 0:e6ceb13d2d05 41 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43 IoIrqInit( dioIrq );
GregCr 0:e6ceb13d2d05 44
GregCr 0:e6ceb13d2d05 45 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 46
GregCr 0:e6ceb13d2d05 47 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 48
mluis 21:2e496deb7858 49 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 50 }
GregCr 0:e6ceb13d2d05 51
mluis 21:2e496deb7858 52 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 53 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 54 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
GregCr 0:e6ceb13d2d05 55 antSwitch( A4 ),
GregCr 0:e6ceb13d2d05 56 fake( D8 )
mluis 20:e05596ba4166 57 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 58 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 20:e05596ba4166 59 antSwitch( P0_23 ),
mluis 20:e05596ba4166 60 fake( A3 )
atarbey 27:2aed13d8cd19 61 #elif defined( TARGET_XDOT_L151CC)
atarbey 28:8fb2ff77baef 62 : SX1276( events, PA_15, PA_14, PB_3, PB_4, PC_13, PB_6, PB_8, PB_2, PB_9, PB_15, PB_5 ),
atarbey 28:8fb2ff77baef 63 antSwitch( PB_0 ),
atarbey 28:8fb2ff77baef 64 fake( PB_1 )
atarbey 28:8fb2ff77baef 65 #elif defined( TARGET_MOTE_L152RC )
atarbey 29:d0d219851731 66 // This is Pinout Setting for Drifter v1.1 (To Do: move to commisioning / main file)
atarbey 29:d0d219851731 67 : SX1276( events, PB_5, PB_4, PB_3, PA_15, PA_1, PA_6, PA_7, PA_8, PB_15, PA_0, PB_14 ),
atarbey 27:2aed13d8cd19 68 antSwitch( PB_0 ),
atarbey 29:d0d219851731 69 fake( PB_2 )
GregCr 0:e6ceb13d2d05 70 #else
mluis 21:2e496deb7858 71 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
GregCr 12:aa5b3bf7fdf4 72 antSwitch( A4 ),
GregCr 12:aa5b3bf7fdf4 73 fake( A3 )
GregCr 0:e6ceb13d2d05 74 #endif
GregCr 0:e6ceb13d2d05 75 {
mluis 21:2e496deb7858 76 this->RadioEvents = events;
mluis 21:2e496deb7858 77
GregCr 0:e6ceb13d2d05 78 Reset( );
GregCr 0:e6ceb13d2d05 79
atarbey 29:d0d219851731 80 //Determine the board type
atarbey 29:d0d219851731 81 // board known: Hope RFM95 / RFM98: SX1276MB1LAS (PA_Boost Pin),
atarbey 29:d0d219851731 82 // Semtech Board : SX1276MB1MAS (RFO Pin)
atarbey 29:d0d219851731 83 boardConnected = SX1276MB1LAS;
GregCr 1:f979673946c0 84
GregCr 0:e6ceb13d2d05 85 RxChainCalibration( );
GregCr 0:e6ceb13d2d05 86
GregCr 0:e6ceb13d2d05 87 IoInit( );
GregCr 0:e6ceb13d2d05 88
GregCr 0:e6ceb13d2d05 89 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 90 IoIrqInit( dioIrq );
GregCr 0:e6ceb13d2d05 91
GregCr 0:e6ceb13d2d05 92 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 93
GregCr 0:e6ceb13d2d05 94 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 95
mluis 21:2e496deb7858 96 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 97 }
GregCr 0:e6ceb13d2d05 98
GregCr 0:e6ceb13d2d05 99 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 100 // Board relative functions
GregCr 0:e6ceb13d2d05 101 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 102 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 103 {
GregCr 5:11ec8a6ba4f0 104 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 105 {
GregCr 5:11ec8a6ba4f0 106 antSwitch.input( );
GregCr 5:11ec8a6ba4f0 107 wait_ms( 1 );
GregCr 5:11ec8a6ba4f0 108 if( antSwitch == 1 )
GregCr 5:11ec8a6ba4f0 109 {
GregCr 5:11ec8a6ba4f0 110 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 111 }
GregCr 5:11ec8a6ba4f0 112 else
GregCr 5:11ec8a6ba4f0 113 {
GregCr 5:11ec8a6ba4f0 114 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 115 }
GregCr 5:11ec8a6ba4f0 116 antSwitch.output( );
GregCr 5:11ec8a6ba4f0 117 wait_ms( 1 );
GregCr 1:f979673946c0 118 }
GregCr 2:5eb3066446dd 119 return ( boardConnected );
GregCr 1:f979673946c0 120 }
GregCr 0:e6ceb13d2d05 121
GregCr 0:e6ceb13d2d05 122 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 123 {
GregCr 0:e6ceb13d2d05 124 AntSwInit( );
GregCr 0:e6ceb13d2d05 125 SpiInit( );
GregCr 0:e6ceb13d2d05 126 }
GregCr 0:e6ceb13d2d05 127
mluis 22:7f3aab69cca9 128 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 129 {
GregCr 0:e6ceb13d2d05 130 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 131 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 132 {
GregCr 0:e6ceb13d2d05 133 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 134 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 135 }
GregCr 0:e6ceb13d2d05 136 }
GregCr 0:e6ceb13d2d05 137
GregCr 0:e6ceb13d2d05 138 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 139 {
GregCr 0:e6ceb13d2d05 140 nss = 1;
GregCr 0:e6ceb13d2d05 141 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 142 uint32_t frequencyToSet = 8000000;
atarbey 28:8fb2ff77baef 143 #if( defined( TARGET_MOTE_L152RC ) || defined( TARGET_XDOT_L151CC) || defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 144 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 145 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 146 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 147 #else
GregCr 0:e6ceb13d2d05 148 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 149 #endif
GregCr 0:e6ceb13d2d05 150 wait(0.1);
GregCr 0:e6ceb13d2d05 151 }
GregCr 0:e6ceb13d2d05 152
GregCr 0:e6ceb13d2d05 153 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 154 {
atarbey 28:8fb2ff77baef 155 #if( defined( TARGET_MOTE_L152RC ) || defined( TARGET_XDOT_L151CC) || defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
mluis 22:7f3aab69cca9 156 dio0.mode(PullDown);
mluis 22:7f3aab69cca9 157 dio1.mode(PullDown);
mluis 22:7f3aab69cca9 158 dio2.mode(PullDown);
mluis 22:7f3aab69cca9 159 dio3.mode(PullDown);
mluis 22:7f3aab69cca9 160 dio4.mode(PullDown);
mluis 22:7f3aab69cca9 161 #endif
GregCr 0:e6ceb13d2d05 162 dio0.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) );
GregCr 0:e6ceb13d2d05 163 dio1.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) );
GregCr 0:e6ceb13d2d05 164 dio2.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) );
GregCr 0:e6ceb13d2d05 165 dio3.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) );
GregCr 0:e6ceb13d2d05 166 dio4.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) );
atarbey 28:8fb2ff77baef 167
GregCr 0:e6ceb13d2d05 168 }
GregCr 0:e6ceb13d2d05 169
GregCr 0:e6ceb13d2d05 170 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 171 {
GregCr 0:e6ceb13d2d05 172 //nothing
GregCr 0:e6ceb13d2d05 173 }
GregCr 0:e6ceb13d2d05 174
GregCr 0:e6ceb13d2d05 175 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 176 {
GregCr 0:e6ceb13d2d05 177 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 178 {
GregCr 3:ca84be1f3fac 179 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 180 {
GregCr 1:f979673946c0 181 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 182 }
GregCr 1:f979673946c0 183 else
GregCr 1:f979673946c0 184 {
GregCr 1:f979673946c0 185 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 186 }
GregCr 0:e6ceb13d2d05 187 }
GregCr 0:e6ceb13d2d05 188 else
GregCr 0:e6ceb13d2d05 189 {
GregCr 0:e6ceb13d2d05 190 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 191 }
GregCr 0:e6ceb13d2d05 192 }
GregCr 0:e6ceb13d2d05 193
GregCr 0:e6ceb13d2d05 194 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 195 {
GregCr 0:e6ceb13d2d05 196 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 197 {
GregCr 0:e6ceb13d2d05 198 isRadioActive = status;
GregCr 0:e6ceb13d2d05 199
GregCr 0:e6ceb13d2d05 200 if( status == false )
GregCr 0:e6ceb13d2d05 201 {
GregCr 0:e6ceb13d2d05 202 AntSwInit( );
GregCr 0:e6ceb13d2d05 203 }
GregCr 0:e6ceb13d2d05 204 else
GregCr 0:e6ceb13d2d05 205 {
GregCr 0:e6ceb13d2d05 206 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 207 }
GregCr 0:e6ceb13d2d05 208 }
GregCr 0:e6ceb13d2d05 209 }
GregCr 0:e6ceb13d2d05 210
GregCr 0:e6ceb13d2d05 211 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 212 {
GregCr 0:e6ceb13d2d05 213 antSwitch = 0;
GregCr 0:e6ceb13d2d05 214 }
GregCr 0:e6ceb13d2d05 215
GregCr 0:e6ceb13d2d05 216 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 217 {
GregCr 0:e6ceb13d2d05 218 antSwitch = 0;
GregCr 0:e6ceb13d2d05 219 }
GregCr 0:e6ceb13d2d05 220
GregCr 0:e6ceb13d2d05 221 void SX1276MB1xAS::SetAntSw( uint8_t rxTx )
GregCr 0:e6ceb13d2d05 222 {
GregCr 0:e6ceb13d2d05 223 if( this->rxTx == rxTx )
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 //no need to go further
GregCr 0:e6ceb13d2d05 226 return;
GregCr 0:e6ceb13d2d05 227 }
GregCr 0:e6ceb13d2d05 228
GregCr 0:e6ceb13d2d05 229 this->rxTx = rxTx;
GregCr 0:e6ceb13d2d05 230
GregCr 0:e6ceb13d2d05 231 if( rxTx != 0 )
GregCr 0:e6ceb13d2d05 232 {
GregCr 0:e6ceb13d2d05 233 antSwitch = 1;
GregCr 0:e6ceb13d2d05 234 }
GregCr 0:e6ceb13d2d05 235 else
GregCr 0:e6ceb13d2d05 236 {
GregCr 0:e6ceb13d2d05 237 antSwitch = 0;
GregCr 0:e6ceb13d2d05 238 }
GregCr 0:e6ceb13d2d05 239 }
GregCr 0:e6ceb13d2d05 240
GregCr 0:e6ceb13d2d05 241 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 242 {
GregCr 0:e6ceb13d2d05 243 //TODO: Implement check, currently all frequencies are supported
GregCr 0:e6ceb13d2d05 244 return true;
GregCr 0:e6ceb13d2d05 245 }
GregCr 0:e6ceb13d2d05 246
GregCr 0:e6ceb13d2d05 247
GregCr 0:e6ceb13d2d05 248 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 249 {
GregCr 4:f0ce52e94d3f 250 reset.output();
GregCr 0:e6ceb13d2d05 251 reset = 0;
GregCr 0:e6ceb13d2d05 252 wait_ms( 1 );
GregCr 4:f0ce52e94d3f 253 reset.input();
GregCr 0:e6ceb13d2d05 254 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 255 }
GregCr 0:e6ceb13d2d05 256
GregCr 0:e6ceb13d2d05 257 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 258 {
GregCr 0:e6ceb13d2d05 259 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 260 }
GregCr 0:e6ceb13d2d05 261
GregCr 0:e6ceb13d2d05 262 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 263 {
GregCr 0:e6ceb13d2d05 264 uint8_t data;
GregCr 0:e6ceb13d2d05 265 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 266 return data;
GregCr 0:e6ceb13d2d05 267 }
GregCr 0:e6ceb13d2d05 268
GregCr 0:e6ceb13d2d05 269 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 270 {
GregCr 0:e6ceb13d2d05 271 uint8_t i;
GregCr 0:e6ceb13d2d05 272
GregCr 0:e6ceb13d2d05 273 nss = 0;
GregCr 0:e6ceb13d2d05 274 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 275 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 276 {
GregCr 0:e6ceb13d2d05 277 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 278 }
GregCr 0:e6ceb13d2d05 279 nss = 1;
GregCr 0:e6ceb13d2d05 280 }
GregCr 0:e6ceb13d2d05 281
GregCr 0:e6ceb13d2d05 282 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 283 {
GregCr 0:e6ceb13d2d05 284 uint8_t i;
GregCr 0:e6ceb13d2d05 285
GregCr 0:e6ceb13d2d05 286 nss = 0;
GregCr 0:e6ceb13d2d05 287 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 288 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 289 {
GregCr 0:e6ceb13d2d05 290 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 291 }
GregCr 0:e6ceb13d2d05 292 nss = 1;
GregCr 0:e6ceb13d2d05 293 }
GregCr 0:e6ceb13d2d05 294
GregCr 0:e6ceb13d2d05 295 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 296 {
GregCr 0:e6ceb13d2d05 297 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 298 }
GregCr 0:e6ceb13d2d05 299
GregCr 0:e6ceb13d2d05 300 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 301 {
GregCr 0:e6ceb13d2d05 302 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 303 }