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SDFileSystem.cpp@0:6c621d41bf07, 2010-12-08 (annotated)

Committer:: ashwin_athani
Date:: Wed Dec 08 06:21:06 2010 +0000
Revision:: 0:6c621d41bf07

Who changed what in which revision?

User	Revision	Line number	New contents of line
ashwin_athani	0:6c621d41bf07	1	/* mbed Microcontroller Library - SDFileSystem
ashwin_athani	0:6c621d41bf07	2	* Copyright (c) 2008-2009, sford
ashwin_athani	0:6c621d41bf07	3	*
ashwin_athani	0:6c621d41bf07	4	* Introduction
ashwin_athani	0:6c621d41bf07	5	* ------------
ashwin_athani	0:6c621d41bf07	6	* SD and MMC cards support a number of interfaces, but common to them all
ashwin_athani	0:6c621d41bf07	7	* is one based on SPI. This is the one I'm implmenting because it means
ashwin_athani	0:6c621d41bf07	8	* it is much more portable even though not so performant, and we already
ashwin_athani	0:6c621d41bf07	9	* have the mbed SPI Interface!
ashwin_athani	0:6c621d41bf07	10	*
ashwin_athani	0:6c621d41bf07	11	* The main reference I'm using is Chapter 7, "SPI Mode" of:
ashwin_athani	0:6c621d41bf07	12	* http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
ashwin_athani	0:6c621d41bf07	13	*
ashwin_athani	0:6c621d41bf07	14	* SPI Startup
ashwin_athani	0:6c621d41bf07	15	* -----------
ashwin_athani	0:6c621d41bf07	16	* The SD card powers up in SD mode. The SPI interface mode is selected by
ashwin_athani	0:6c621d41bf07	17	* asserting CS low and sending the reset command (CMD0). The card will
ashwin_athani	0:6c621d41bf07	18	* respond with a (R1) response.
ashwin_athani	0:6c621d41bf07	19	*
ashwin_athani	0:6c621d41bf07	20	* CMD8 is optionally sent to determine the voltage range supported, and
ashwin_athani	0:6c621d41bf07	21	* indirectly determine whether it is a version 1.x SD/non-SD card or
ashwin_athani	0:6c621d41bf07	22	* version 2.x. I'll just ignore this for now.
ashwin_athani	0:6c621d41bf07	23	*
ashwin_athani	0:6c621d41bf07	24	* ACMD41 is repeatedly issued to initialise the card, until "in idle"
ashwin_athani	0:6c621d41bf07	25	* (bit 0) of the R1 response goes to '0', indicating it is initialised.
ashwin_athani	0:6c621d41bf07	26	*
ashwin_athani	0:6c621d41bf07	27	* You should also indicate whether the host supports High Capicity cards,
ashwin_athani	0:6c621d41bf07	28	* and check whether the card is high capacity - i'll also ignore this
ashwin_athani	0:6c621d41bf07	29	*
ashwin_athani	0:6c621d41bf07	30	* SPI Protocol
ashwin_athani	0:6c621d41bf07	31	* ------------
ashwin_athani	0:6c621d41bf07	32	* The SD SPI protocol is based on transactions made up of 8-bit words, with
ashwin_athani	0:6c621d41bf07	33	* the host starting every bus transaction by asserting the CS signal low. The
ashwin_athani	0:6c621d41bf07	34	* card always responds to commands, data blocks and errors.
ashwin_athani	0:6c621d41bf07	35	*
ashwin_athani	0:6c621d41bf07	36	* The protocol supports a CRC, but by default it is off (except for the
ashwin_athani	0:6c621d41bf07	37	* first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
ashwin_athani	0:6c621d41bf07	38	* I'll leave the CRC off I think!
ashwin_athani	0:6c621d41bf07	39	*
ashwin_athani	0:6c621d41bf07	40	* Standard capacity cards have variable data block sizes, whereas High
ashwin_athani	0:6c621d41bf07	41	* Capacity cards fix the size of data block to 512 bytes. I'll therefore
ashwin_athani	0:6c621d41bf07	42	* just always use the Standard Capacity cards with a block size of 512 bytes.
ashwin_athani	0:6c621d41bf07	43	* This is set with CMD16.
ashwin_athani	0:6c621d41bf07	44	*
ashwin_athani	0:6c621d41bf07	45	* You can read and write single blocks (CMD17, CMD25) or multiple blocks
ashwin_athani	0:6c621d41bf07	46	* (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
ashwin_athani	0:6c621d41bf07	47	* the card gets a read command, it responds with a response token, and then
ashwin_athani	0:6c621d41bf07	48	* a data token or an error.
ashwin_athani	0:6c621d41bf07	49	*
ashwin_athani	0:6c621d41bf07	50	* SPI Command Format
ashwin_athani	0:6c621d41bf07	51	* ------------------
ashwin_athani	0:6c621d41bf07	52	* Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
ashwin_athani	0:6c621d41bf07	53	*
ashwin_athani	0:6c621d41bf07	54	* +---------------+------------+------------+-----------+----------+--------------+
ashwin_athani	0:6c621d41bf07	55	* \| 01 \| cmd[5:0] \| arg[31:24] \| arg[23:16] \| arg[15:8] \| arg[7:0] \| crc[6:0] \| 1 \|
ashwin_athani	0:6c621d41bf07	56	* +---------------+------------+------------+-----------+----------+--------------+
ashwin_athani	0:6c621d41bf07	57	*
ashwin_athani	0:6c621d41bf07	58	* As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
ashwin_athani	0:6c621d41bf07	59	*
ashwin_athani	0:6c621d41bf07	60	* All Application Specific commands shall be preceded with APP_CMD (CMD55).
ashwin_athani	0:6c621d41bf07	61	*
ashwin_athani	0:6c621d41bf07	62	* SPI Response Format
ashwin_athani	0:6c621d41bf07	63	* -------------------
ashwin_athani	0:6c621d41bf07	64	* The main response format (R1) is a status byte (normally zero). Key flags:
ashwin_athani	0:6c621d41bf07	65	* idle - 1 if the card is in an idle state/initialising
ashwin_athani	0:6c621d41bf07	66	* cmd - 1 if an illegal command code was detected
ashwin_athani	0:6c621d41bf07	67	*
ashwin_athani	0:6c621d41bf07	68	* +-------------------------------------------------+
ashwin_athani	0:6c621d41bf07	69	* R1 \| 0 \| arg \| addr \| seq \| crc \| cmd \| erase \| idle \|
ashwin_athani	0:6c621d41bf07	70	* +-------------------------------------------------+
ashwin_athani	0:6c621d41bf07	71	*
ashwin_athani	0:6c621d41bf07	72	* R1b is the same, except it is followed by a busy signal (zeros) until
ashwin_athani	0:6c621d41bf07	73	* the first non-zero byte when it is ready again.
ashwin_athani	0:6c621d41bf07	74	*
ashwin_athani	0:6c621d41bf07	75	* Data Response Token
ashwin_athani	0:6c621d41bf07	76	* -------------------
ashwin_athani	0:6c621d41bf07	77	* Every data block written to the card is acknowledged by a byte
ashwin_athani	0:6c621d41bf07	78	* response token
ashwin_athani	0:6c621d41bf07	79	*
ashwin_athani	0:6c621d41bf07	80	* +----------------------+
ashwin_athani	0:6c621d41bf07	81	* \| xxx \| 0 \| status \| 1 \|
ashwin_athani	0:6c621d41bf07	82	* +----------------------+
ashwin_athani	0:6c621d41bf07	83	* 010 - OK!
ashwin_athani	0:6c621d41bf07	84	* 101 - CRC Error
ashwin_athani	0:6c621d41bf07	85	* 110 - Write Error
ashwin_athani	0:6c621d41bf07	86	*
ashwin_athani	0:6c621d41bf07	87	* Single Block Read and Write
ashwin_athani	0:6c621d41bf07	88	* ---------------------------
ashwin_athani	0:6c621d41bf07	89	*
ashwin_athani	0:6c621d41bf07	90	* Block transfers have a byte header, followed by the data, followed
ashwin_athani	0:6c621d41bf07	91	* by a 16-bit CRC. In our case, the data will always be 512 bytes.
ashwin_athani	0:6c621d41bf07	92	*
ashwin_athani	0:6c621d41bf07	93	* +------+---------+---------+- - - -+---------+-----------+----------+
ashwin_athani	0:6c621d41bf07	94	* \| 0xFE \| data[0] \| data[1] \| \| data[n] \| crc[15:8] \| crc[7:0] \|
ashwin_athani	0:6c621d41bf07	95	* +------+---------+---------+- - - -+---------+-----------+----------+
ashwin_athani	0:6c621d41bf07	96	*/
ashwin_athani	0:6c621d41bf07	97
ashwin_athani	0:6c621d41bf07	98	#include "SDFileSystem.h"
ashwin_athani	0:6c621d41bf07	99
ashwin_athani	0:6c621d41bf07	100	#define SD_COMMAND_TIMEOUT 5000
ashwin_athani	0:6c621d41bf07	101
ashwin_athani	0:6c621d41bf07	102	SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
ashwin_athani	0:6c621d41bf07	103	FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs) {
ashwin_athani	0:6c621d41bf07	104	_cs = 1;
ashwin_athani	0:6c621d41bf07	105	}
ashwin_athani	0:6c621d41bf07	106
ashwin_athani	0:6c621d41bf07	107	int SDFileSystem::disk_initialize() {
ashwin_athani	0:6c621d41bf07	108
ashwin_athani	0:6c621d41bf07	109	_spi.frequency(100000); // Set to 100kHz for initialisation
ashwin_athani	0:6c621d41bf07	110
ashwin_athani	0:6c621d41bf07	111	// Initialise the card by clocking it with cs = 1
ashwin_athani	0:6c621d41bf07	112	_cs = 1;
ashwin_athani	0:6c621d41bf07	113	for(int i=0; i<16; i++) {
ashwin_athani	0:6c621d41bf07	114	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	115	}
ashwin_athani	0:6c621d41bf07	116
ashwin_athani	0:6c621d41bf07	117	// send CMD0, should return with all zeros except IDLE STATE set (bit 0)
ashwin_athani	0:6c621d41bf07	118	if(_cmd(0, 0) != 0x01) {
ashwin_athani	0:6c621d41bf07	119	fprintf(stderr, "Not in idle state\n");
ashwin_athani	0:6c621d41bf07	120	return 1;
ashwin_athani	0:6c621d41bf07	121	}
ashwin_athani	0:6c621d41bf07	122
ashwin_athani	0:6c621d41bf07	123	// ACMD41 to give host capacity support (repeat until not busy)
ashwin_athani	0:6c621d41bf07	124	// ACMD41 is application specific command, so we send APP_CMD (CMD55) beforehand
ashwin_athani	0:6c621d41bf07	125	for(int i=0;; i++) {
ashwin_athani	0:6c621d41bf07	126	_cmd(55, 0);
ashwin_athani	0:6c621d41bf07	127	int response = _cmd(41, 0);
ashwin_athani	0:6c621d41bf07	128	if(response == 0) {
ashwin_athani	0:6c621d41bf07	129	break;
ashwin_athani	0:6c621d41bf07	130	} else if(i > SD_COMMAND_TIMEOUT) {
ashwin_athani	0:6c621d41bf07	131	fprintf(stderr, "Timeout waiting for card\n");
ashwin_athani	0:6c621d41bf07	132	return 1;
ashwin_athani	0:6c621d41bf07	133	}
ashwin_athani	0:6c621d41bf07	134	}
ashwin_athani	0:6c621d41bf07	135
ashwin_athani	0:6c621d41bf07	136	_sectors = _sd_sectors();
ashwin_athani	0:6c621d41bf07	137
ashwin_athani	0:6c621d41bf07	138	// Set block length to 512 (CMD16)
ashwin_athani	0:6c621d41bf07	139	if(_cmd(16, 512) != 0) {
ashwin_athani	0:6c621d41bf07	140	fprintf(stderr, "Set block timeout\n");
ashwin_athani	0:6c621d41bf07	141	return 1;
ashwin_athani	0:6c621d41bf07	142	}
ashwin_athani	0:6c621d41bf07	143
ashwin_athani	0:6c621d41bf07	144	_spi.frequency(1000000); // Set to 1MHz for data transfer
ashwin_athani	0:6c621d41bf07	145	return 0;
ashwin_athani	0:6c621d41bf07	146	}
ashwin_athani	0:6c621d41bf07	147
ashwin_athani	0:6c621d41bf07	148	int SDFileSystem::disk_write(const char *buffer, int block_number) {
ashwin_athani	0:6c621d41bf07	149	// set write address for single block (CMD24)
ashwin_athani	0:6c621d41bf07	150	if(_cmd(24, block_number * 512) != 0) {
ashwin_athani	0:6c621d41bf07	151	return 1;
ashwin_athani	0:6c621d41bf07	152	}
ashwin_athani	0:6c621d41bf07	153
ashwin_athani	0:6c621d41bf07	154	// send the data block
ashwin_athani	0:6c621d41bf07	155	_write(buffer, 512);
ashwin_athani	0:6c621d41bf07	156	return 0;
ashwin_athani	0:6c621d41bf07	157	}
ashwin_athani	0:6c621d41bf07	158
ashwin_athani	0:6c621d41bf07	159	int SDFileSystem::disk_read(char *buffer, int block_number) {
ashwin_athani	0:6c621d41bf07	160	// set read address for single block (CMD17)
ashwin_athani	0:6c621d41bf07	161	if(_cmd(17, block_number * 512) != 0) {
ashwin_athani	0:6c621d41bf07	162	return 1;
ashwin_athani	0:6c621d41bf07	163	}
ashwin_athani	0:6c621d41bf07	164
ashwin_athani	0:6c621d41bf07	165	// receive the data
ashwin_athani	0:6c621d41bf07	166	_read(buffer, 512);
ashwin_athani	0:6c621d41bf07	167	return 0;
ashwin_athani	0:6c621d41bf07	168	}
ashwin_athani	0:6c621d41bf07	169
ashwin_athani	0:6c621d41bf07	170	int SDFileSystem::disk_status() { return 0; }
ashwin_athani	0:6c621d41bf07	171	int SDFileSystem::disk_sync() { return 0; }
ashwin_athani	0:6c621d41bf07	172	int SDFileSystem::disk_sectors() { return _sectors; }
ashwin_athani	0:6c621d41bf07	173
ashwin_athani	0:6c621d41bf07	174	// PRIVATE FUNCTIONS
ashwin_athani	0:6c621d41bf07	175
ashwin_athani	0:6c621d41bf07	176	int SDFileSystem::_cmd(int cmd, int arg) {
ashwin_athani	0:6c621d41bf07	177	_cs = 0;
ashwin_athani	0:6c621d41bf07	178
ashwin_athani	0:6c621d41bf07	179	// send a command
ashwin_athani	0:6c621d41bf07	180	_spi.write(0x40 \| cmd);
ashwin_athani	0:6c621d41bf07	181	_spi.write(arg >> 24);
ashwin_athani	0:6c621d41bf07	182	_spi.write(arg >> 16);
ashwin_athani	0:6c621d41bf07	183	_spi.write(arg >> 8);
ashwin_athani	0:6c621d41bf07	184	_spi.write(arg >> 0);
ashwin_athani	0:6c621d41bf07	185	_spi.write(0x95);
ashwin_athani	0:6c621d41bf07	186
ashwin_athani	0:6c621d41bf07	187	// wait for the repsonse (response[7] == 0)
ashwin_athani	0:6c621d41bf07	188	for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
ashwin_athani	0:6c621d41bf07	189	int response = _spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	190	if(!(response & 0x80)) {
ashwin_athani	0:6c621d41bf07	191	_cs = 1;
ashwin_athani	0:6c621d41bf07	192	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	193	return response;
ashwin_athani	0:6c621d41bf07	194	}
ashwin_athani	0:6c621d41bf07	195	}
ashwin_athani	0:6c621d41bf07	196	_cs = 1;
ashwin_athani	0:6c621d41bf07	197	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	198	return -1; // timeout
ashwin_athani	0:6c621d41bf07	199	}
ashwin_athani	0:6c621d41bf07	200
ashwin_athani	0:6c621d41bf07	201	int SDFileSystem::_read(char *buffer, int length) {
ashwin_athani	0:6c621d41bf07	202	_cs = 0;
ashwin_athani	0:6c621d41bf07	203
ashwin_athani	0:6c621d41bf07	204	// read until start byte (0xFF)
ashwin_athani	0:6c621d41bf07	205	while(_spi.write(0xFF) != 0xFE);
ashwin_athani	0:6c621d41bf07	206
ashwin_athani	0:6c621d41bf07	207	// read data
ashwin_athani	0:6c621d41bf07	208	for(int i=0; i<length; i++) {
ashwin_athani	0:6c621d41bf07	209	buffer[i] = _spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	210	}
ashwin_athani	0:6c621d41bf07	211	_spi.write(0xFF); // checksum
ashwin_athani	0:6c621d41bf07	212	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	213
ashwin_athani	0:6c621d41bf07	214	_cs = 1;
ashwin_athani	0:6c621d41bf07	215	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	216	return 0;
ashwin_athani	0:6c621d41bf07	217	}
ashwin_athani	0:6c621d41bf07	218
ashwin_athani	0:6c621d41bf07	219	int SDFileSystem::_write(const char *buffer, int length) {
ashwin_athani	0:6c621d41bf07	220	_cs = 0;
ashwin_athani	0:6c621d41bf07	221
ashwin_athani	0:6c621d41bf07	222	// indicate start of block
ashwin_athani	0:6c621d41bf07	223	_spi.write(0xFE);
ashwin_athani	0:6c621d41bf07	224
ashwin_athani	0:6c621d41bf07	225	// write the data
ashwin_athani	0:6c621d41bf07	226	for(int i=0; i<length; i++) {
ashwin_athani	0:6c621d41bf07	227	_spi.write(buffer[i]);
ashwin_athani	0:6c621d41bf07	228	}
ashwin_athani	0:6c621d41bf07	229
ashwin_athani	0:6c621d41bf07	230	// write the checksum
ashwin_athani	0:6c621d41bf07	231	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	232	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	233
ashwin_athani	0:6c621d41bf07	234	// check the repsonse token
ashwin_athani	0:6c621d41bf07	235	if((_spi.write(0xFF) & 0x1F) != 0x05) {
ashwin_athani	0:6c621d41bf07	236	_cs = 1;
ashwin_athani	0:6c621d41bf07	237	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	238	return 1;
ashwin_athani	0:6c621d41bf07	239	}
ashwin_athani	0:6c621d41bf07	240
ashwin_athani	0:6c621d41bf07	241	// wait for write to finish
ashwin_athani	0:6c621d41bf07	242	while(_spi.write(0xFF) == 0);
ashwin_athani	0:6c621d41bf07	243
ashwin_athani	0:6c621d41bf07	244	_cs = 1;
ashwin_athani	0:6c621d41bf07	245	_spi.write(0xFF);
ashwin_athani	0:6c621d41bf07	246	return 0;
ashwin_athani	0:6c621d41bf07	247	}
ashwin_athani	0:6c621d41bf07	248
ashwin_athani	0:6c621d41bf07	249	static int ext_bits(char *data, int msb, int lsb) {
ashwin_athani	0:6c621d41bf07	250	int bits = 0;
ashwin_athani	0:6c621d41bf07	251	int size = 1 + msb - lsb;
ashwin_athani	0:6c621d41bf07	252	for(int i=0; i<size; i++) {
ashwin_athani	0:6c621d41bf07	253	int position = lsb + i;
ashwin_athani	0:6c621d41bf07	254	int byte = 15 - (position >> 3);
ashwin_athani	0:6c621d41bf07	255	int bit = position & 0x7;
ashwin_athani	0:6c621d41bf07	256	int value = (data[byte] >> bit) & 1;
ashwin_athani	0:6c621d41bf07	257	bits \|= value << i;
ashwin_athani	0:6c621d41bf07	258	}
ashwin_athani	0:6c621d41bf07	259	return bits;
ashwin_athani	0:6c621d41bf07	260	}
ashwin_athani	0:6c621d41bf07	261
ashwin_athani	0:6c621d41bf07	262	int SDFileSystem::_sd_sectors() {
ashwin_athani	0:6c621d41bf07	263
ashwin_athani	0:6c621d41bf07	264	// CMD9, Response R2 (R1 byte + 16-byte block read)
ashwin_athani	0:6c621d41bf07	265	if(_cmd(9, 0) != 0) {
ashwin_athani	0:6c621d41bf07	266	fprintf(stderr, "Didn't get a response from the disk\n");
ashwin_athani	0:6c621d41bf07	267	return 0;
ashwin_athani	0:6c621d41bf07	268	}
ashwin_athani	0:6c621d41bf07	269
ashwin_athani	0:6c621d41bf07	270	char csd[16];
ashwin_athani	0:6c621d41bf07	271	if(_read(csd, 16) != 0) {
ashwin_athani	0:6c621d41bf07	272	fprintf(stderr, "Couldn't read csd response from disk\n");
ashwin_athani	0:6c621d41bf07	273	return 0;
ashwin_athani	0:6c621d41bf07	274	}
ashwin_athani	0:6c621d41bf07	275
ashwin_athani	0:6c621d41bf07	276	// csd_structure : csd[127:126]
ashwin_athani	0:6c621d41bf07	277	// c_size : csd[73:62]
ashwin_athani	0:6c621d41bf07	278	// c_size_mult : csd[49:47]
ashwin_athani	0:6c621d41bf07	279	// read_bl_len : csd[83:80]
ashwin_athani	0:6c621d41bf07	280
ashwin_athani	0:6c621d41bf07	281	int csd_structure = ext_bits(csd, 127, 126);
ashwin_athani	0:6c621d41bf07	282	int c_size = ext_bits(csd, 73, 62);
ashwin_athani	0:6c621d41bf07	283	int c_size_mult = ext_bits(csd, 49, 47);
ashwin_athani	0:6c621d41bf07	284	int read_bl_len = ext_bits(csd, 83, 80);
ashwin_athani	0:6c621d41bf07	285
ashwin_athani	0:6c621d41bf07	286	if(csd_structure != 0) {
ashwin_athani	0:6c621d41bf07	287	fprintf(stderr, "This disk tastes funny! I only know about type 0 CSD structures");
ashwin_athani	0:6c621d41bf07	288	return 0;
ashwin_athani	0:6c621d41bf07	289	}
ashwin_athani	0:6c621d41bf07	290
ashwin_athani	0:6c621d41bf07	291	int blocks = (c_size + 1) * (1 << (c_size_mult + 2));
ashwin_athani	0:6c621d41bf07	292	int block_size = 1 << read_bl_len;
ashwin_athani	0:6c621d41bf07	293
ashwin_athani	0:6c621d41bf07	294	if(block_size != 512) {
ashwin_athani	0:6c621d41bf07	295	fprintf(stderr, "This disk tastes funny! I only like 512-byte blocks");
ashwin_athani	0:6c621d41bf07	296	return 0;
ashwin_athani	0:6c621d41bf07	297	}
ashwin_athani	0:6c621d41bf07	298
ashwin_athani	0:6c621d41bf07	299	return blocks;
ashwin_athani	0:6c621d41bf07	300	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	08 Dec 2010
Imports:	30
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	4

SDFileSystem.cpp@0:6c621d41bf07, 2010-12-08 (annotated)

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