mX_SD_card - mX mbed BaseBoard SD card

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Ashwin Athani / Mbed 2 deprecated mX_SD_card

mX mbed BaseBoard SD card

SDFileSystem.cpp@0:c44f7e0926c7, 2010-12-08 (annotated)

Committer:: ashwin_athani
Date:: Wed Dec 08 06:27:28 2010 +0000
Revision:: 0:c44f7e0926c7

Who changed what in which revision?

User	Revision	Line number	New contents of line
ashwin_athani	0:c44f7e0926c7	1	/* mbed Microcontroller Library - SDFileSystem
ashwin_athani	0:c44f7e0926c7	2	* Copyright (c) 2008-2009, sford
ashwin_athani	0:c44f7e0926c7	3	*/
ashwin_athani	0:c44f7e0926c7	4
ashwin_athani	0:c44f7e0926c7	5	// VERY DRAFT CODE! Needs serious rework/refactoring
ashwin_athani	0:c44f7e0926c7	6
ashwin_athani	0:c44f7e0926c7	7	/* Introduction
ashwin_athani	0:c44f7e0926c7	8	* ------------
ashwin_athani	0:c44f7e0926c7	9	* SD and MMC cards support a number of interfaces, but common to them all
ashwin_athani	0:c44f7e0926c7	10	* is one based on SPI. This is the one I'm implmenting because it means
ashwin_athani	0:c44f7e0926c7	11	* it is much more portable even though not so performant, and we already
ashwin_athani	0:c44f7e0926c7	12	* have the mbed SPI Interface!
ashwin_athani	0:c44f7e0926c7	13	*
ashwin_athani	0:c44f7e0926c7	14	* The main reference I'm using is Chapter 7, "SPI Mode" of:
ashwin_athani	0:c44f7e0926c7	15	* http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
ashwin_athani	0:c44f7e0926c7	16	*
ashwin_athani	0:c44f7e0926c7	17	* SPI Startup
ashwin_athani	0:c44f7e0926c7	18	* -----------
ashwin_athani	0:c44f7e0926c7	19	* The SD card powers up in SD mode. The SPI interface mode is selected by
ashwin_athani	0:c44f7e0926c7	20	* asserting CS low and sending the reset command (CMD0). The card will
ashwin_athani	0:c44f7e0926c7	21	* respond with a (R1) response.
ashwin_athani	0:c44f7e0926c7	22	*
ashwin_athani	0:c44f7e0926c7	23	* CMD8 is optionally sent to determine the voltage range supported, and
ashwin_athani	0:c44f7e0926c7	24	* indirectly determine whether it is a version 1.x SD/non-SD card or
ashwin_athani	0:c44f7e0926c7	25	* version 2.x. I'll just ignore this for now.
ashwin_athani	0:c44f7e0926c7	26	*
ashwin_athani	0:c44f7e0926c7	27	* ACMD41 is repeatedly issued to initialise the card, until "in idle"
ashwin_athani	0:c44f7e0926c7	28	* (bit 0) of the R1 response goes to '0', indicating it is initialised.
ashwin_athani	0:c44f7e0926c7	29	*
ashwin_athani	0:c44f7e0926c7	30	* You should also indicate whether the host supports High Capicity cards,
ashwin_athani	0:c44f7e0926c7	31	* and check whether the card is high capacity - i'll also ignore this
ashwin_athani	0:c44f7e0926c7	32	*
ashwin_athani	0:c44f7e0926c7	33	* SPI Protocol
ashwin_athani	0:c44f7e0926c7	34	* ------------
ashwin_athani	0:c44f7e0926c7	35	* The SD SPI protocol is based on transactions made up of 8-bit words, with
ashwin_athani	0:c44f7e0926c7	36	* the host starting every bus transaction by asserting the CS signal low. The
ashwin_athani	0:c44f7e0926c7	37	* card always responds to commands, data blocks and errors.
ashwin_athani	0:c44f7e0926c7	38	*
ashwin_athani	0:c44f7e0926c7	39	* The protocol supports a CRC, but by default it is off (except for the
ashwin_athani	0:c44f7e0926c7	40	* first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
ashwin_athani	0:c44f7e0926c7	41	* I'll leave the CRC off I think!
ashwin_athani	0:c44f7e0926c7	42	*
ashwin_athani	0:c44f7e0926c7	43	* Standard capacity cards have variable data block sizes, whereas High
ashwin_athani	0:c44f7e0926c7	44	* Capacity cards fix the size of data block to 512 bytes. I'll therefore
ashwin_athani	0:c44f7e0926c7	45	* just always use the Standard Capacity cards with a block size of 512 bytes.
ashwin_athani	0:c44f7e0926c7	46	* This is set with CMD16.
ashwin_athani	0:c44f7e0926c7	47	*
ashwin_athani	0:c44f7e0926c7	48	* You can read and write single blocks (CMD17, CMD25) or multiple blocks
ashwin_athani	0:c44f7e0926c7	49	* (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
ashwin_athani	0:c44f7e0926c7	50	* the card gets a read command, it responds with a response token, and then
ashwin_athani	0:c44f7e0926c7	51	* a data token or an error.
ashwin_athani	0:c44f7e0926c7	52	*
ashwin_athani	0:c44f7e0926c7	53	* SPI Command Format
ashwin_athani	0:c44f7e0926c7	54	* ------------------
ashwin_athani	0:c44f7e0926c7	55	* Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
ashwin_athani	0:c44f7e0926c7	56	*
ashwin_athani	0:c44f7e0926c7	57	* +---------------+------------+------------+-----------+----------+--------------+
ashwin_athani	0:c44f7e0926c7	58	* \| 01 \| cmd[5:0] \| arg[31:24] \| arg[23:16] \| arg[15:8] \| arg[7:0] \| crc[6:0] \| 1 \|
ashwin_athani	0:c44f7e0926c7	59	* +---------------+------------+------------+-----------+----------+--------------+
ashwin_athani	0:c44f7e0926c7	60	*
ashwin_athani	0:c44f7e0926c7	61	* As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
ashwin_athani	0:c44f7e0926c7	62	*
ashwin_athani	0:c44f7e0926c7	63	* All Application Specific commands shall be preceded with APP_CMD (CMD55).
ashwin_athani	0:c44f7e0926c7	64	*
ashwin_athani	0:c44f7e0926c7	65	* SPI Response Format
ashwin_athani	0:c44f7e0926c7	66	* -------------------
ashwin_athani	0:c44f7e0926c7	67	* The main response format (R1) is a status byte (normally zero). Key flags:
ashwin_athani	0:c44f7e0926c7	68	* idle - 1 if the card is in an idle state/initialising
ashwin_athani	0:c44f7e0926c7	69	* cmd - 1 if an illegal command code was detected
ashwin_athani	0:c44f7e0926c7	70	*
ashwin_athani	0:c44f7e0926c7	71	* +-------------------------------------------------+
ashwin_athani	0:c44f7e0926c7	72	* R1 \| 0 \| arg \| addr \| seq \| crc \| cmd \| erase \| idle \|
ashwin_athani	0:c44f7e0926c7	73	* +-------------------------------------------------+
ashwin_athani	0:c44f7e0926c7	74	*
ashwin_athani	0:c44f7e0926c7	75	* R1b is the same, except it is followed by a busy signal (zeros) until
ashwin_athani	0:c44f7e0926c7	76	* the first non-zero byte when it is ready again.
ashwin_athani	0:c44f7e0926c7	77	*
ashwin_athani	0:c44f7e0926c7	78	* Data Response Token
ashwin_athani	0:c44f7e0926c7	79	* -------------------
ashwin_athani	0:c44f7e0926c7	80	* Every data block written to the card is acknowledged by a byte
ashwin_athani	0:c44f7e0926c7	81	* response token
ashwin_athani	0:c44f7e0926c7	82	*
ashwin_athani	0:c44f7e0926c7	83	* +----------------------+
ashwin_athani	0:c44f7e0926c7	84	* \| xxx \| 0 \| status \| 1 \|
ashwin_athani	0:c44f7e0926c7	85	* +----------------------+
ashwin_athani	0:c44f7e0926c7	86	* 010 - OK!
ashwin_athani	0:c44f7e0926c7	87	* 101 - CRC Error
ashwin_athani	0:c44f7e0926c7	88	* 110 - Write Error
ashwin_athani	0:c44f7e0926c7	89	*
ashwin_athani	0:c44f7e0926c7	90	* Single Block Read and Write
ashwin_athani	0:c44f7e0926c7	91	* ---------------------------
ashwin_athani	0:c44f7e0926c7	92	*
ashwin_athani	0:c44f7e0926c7	93	* Block transfers have a byte header, followed by the data, followed
ashwin_athani	0:c44f7e0926c7	94	* by a 16-bit CRC. In our case, the data will always be 512 bytes.
ashwin_athani	0:c44f7e0926c7	95	*
ashwin_athani	0:c44f7e0926c7	96	* +------+---------+---------+- - - -+---------+-----------+----------+
ashwin_athani	0:c44f7e0926c7	97	* \| 0xFE \| data[0] \| data[1] \| \| data[n] \| crc[15:8] \| crc[7:0] \|
ashwin_athani	0:c44f7e0926c7	98	* +------+---------+---------+- - - -+---------+-----------+----------+
ashwin_athani	0:c44f7e0926c7	99	*/
ashwin_athani	0:c44f7e0926c7	100
ashwin_athani	0:c44f7e0926c7	101	#include "SDFileSystem.h"
ashwin_athani	0:c44f7e0926c7	102
ashwin_athani	0:c44f7e0926c7	103	#define SD_COMMAND_TIMEOUT 5000
ashwin_athani	0:c44f7e0926c7	104
ashwin_athani	0:c44f7e0926c7	105	SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
ashwin_athani	0:c44f7e0926c7	106	FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs) {
ashwin_athani	0:c44f7e0926c7	107	_cs = 1;
ashwin_athani	0:c44f7e0926c7	108	}
ashwin_athani	0:c44f7e0926c7	109
ashwin_athani	0:c44f7e0926c7	110	#define R1_IDLE_STATE (1 << 0)
ashwin_athani	0:c44f7e0926c7	111	#define R1_ERASE_RESET (1 << 1)
ashwin_athani	0:c44f7e0926c7	112	#define R1_ILLEGAL_COMMAND (1 << 2)
ashwin_athani	0:c44f7e0926c7	113	#define R1_COM_CRC_ERROR (1 << 3)
ashwin_athani	0:c44f7e0926c7	114	#define R1_ERASE_SEQUENCE_ERROR (1 << 4)
ashwin_athani	0:c44f7e0926c7	115	#define R1_ADDRESS_ERROR (1 << 5)
ashwin_athani	0:c44f7e0926c7	116	#define R1_PARAMETER_ERROR (1 << 6)
ashwin_athani	0:c44f7e0926c7	117
ashwin_athani	0:c44f7e0926c7	118	// Types
ashwin_athani	0:c44f7e0926c7	119	// - v1.x Standard Capacity
ashwin_athani	0:c44f7e0926c7	120	// - v2.x Standard Capacity
ashwin_athani	0:c44f7e0926c7	121	// - v2.x High Capacity
ashwin_athani	0:c44f7e0926c7	122	// - Not recognised as an SD Card
ashwin_athani	0:c44f7e0926c7	123
ashwin_athani	0:c44f7e0926c7	124	#define SDCARD_FAIL 0
ashwin_athani	0:c44f7e0926c7	125	#define SDCARD_V1 1
ashwin_athani	0:c44f7e0926c7	126	#define SDCARD_V2 2
ashwin_athani	0:c44f7e0926c7	127	#define SDCARD_V2HC 3
ashwin_athani	0:c44f7e0926c7	128
ashwin_athani	0:c44f7e0926c7	129	int SDFileSystem::initialise_card() {
ashwin_athani	0:c44f7e0926c7	130	// Set to 100kHz for initialisation, and clock card with cs = 1
ashwin_athani	0:c44f7e0926c7	131	_spi.frequency(100000);
ashwin_athani	0:c44f7e0926c7	132	_cs = 1;
ashwin_athani	0:c44f7e0926c7	133	for(int i=0; i<16; i++) {
ashwin_athani	0:c44f7e0926c7	134	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	135	}
ashwin_athani	0:c44f7e0926c7	136
ashwin_athani	0:c44f7e0926c7	137	// send CMD0, should return with all zeros except IDLE STATE set (bit 0)
ashwin_athani	0:c44f7e0926c7	138	if(_cmd(0, 0) != R1_IDLE_STATE) {
ashwin_athani	0:c44f7e0926c7	139	fprintf(stderr, "No disk, or could not put SD card in to SPI idle state\n");
ashwin_athani	0:c44f7e0926c7	140	return SDCARD_FAIL;
ashwin_athani	0:c44f7e0926c7	141	}
ashwin_athani	0:c44f7e0926c7	142
ashwin_athani	0:c44f7e0926c7	143	// send CMD8 to determine whther it is ver 2.x
ashwin_athani	0:c44f7e0926c7	144	int r = _cmd8();
ashwin_athani	0:c44f7e0926c7	145	if(r == R1_IDLE_STATE) {
ashwin_athani	0:c44f7e0926c7	146	return initialise_card_v2();
ashwin_athani	0:c44f7e0926c7	147	} else if(r == (R1_IDLE_STATE \| R1_ILLEGAL_COMMAND)) {
ashwin_athani	0:c44f7e0926c7	148	return initialise_card_v1();
ashwin_athani	0:c44f7e0926c7	149	} else {
ashwin_athani	0:c44f7e0926c7	150	fprintf(stderr, "Not in idle state after sending CMD8 (not an SD card?)\n");
ashwin_athani	0:c44f7e0926c7	151	return SDCARD_FAIL;
ashwin_athani	0:c44f7e0926c7	152	}
ashwin_athani	0:c44f7e0926c7	153	}
ashwin_athani	0:c44f7e0926c7	154
ashwin_athani	0:c44f7e0926c7	155	int SDFileSystem::initialise_card_v1() {
ashwin_athani	0:c44f7e0926c7	156	for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
ashwin_athani	0:c44f7e0926c7	157	_cmd(55, 0);
ashwin_athani	0:c44f7e0926c7	158	if(_cmd(41, 0) == 0) {
ashwin_athani	0:c44f7e0926c7	159	return SDCARD_V1;
ashwin_athani	0:c44f7e0926c7	160	}
ashwin_athani	0:c44f7e0926c7	161	}
ashwin_athani	0:c44f7e0926c7	162
ashwin_athani	0:c44f7e0926c7	163	fprintf(stderr, "Timeout waiting for v1.x card\n");
ashwin_athani	0:c44f7e0926c7	164	return SDCARD_FAIL;
ashwin_athani	0:c44f7e0926c7	165	}
ashwin_athani	0:c44f7e0926c7	166
ashwin_athani	0:c44f7e0926c7	167	int SDFileSystem::initialise_card_v2() {
ashwin_athani	0:c44f7e0926c7	168
ashwin_athani	0:c44f7e0926c7	169	for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
ashwin_athani	0:c44f7e0926c7	170	_cmd(55, 0);
ashwin_athani	0:c44f7e0926c7	171	if(_cmd(41, 0) == 0) {
ashwin_athani	0:c44f7e0926c7	172	_cmd58();
ashwin_athani	0:c44f7e0926c7	173	return SDCARD_V2;
ashwin_athani	0:c44f7e0926c7	174	}
ashwin_athani	0:c44f7e0926c7	175	}
ashwin_athani	0:c44f7e0926c7	176
ashwin_athani	0:c44f7e0926c7	177	fprintf(stderr, "Timeout waiting for v2.x card\n");
ashwin_athani	0:c44f7e0926c7	178	return SDCARD_FAIL;
ashwin_athani	0:c44f7e0926c7	179	}
ashwin_athani	0:c44f7e0926c7	180
ashwin_athani	0:c44f7e0926c7	181	int SDFileSystem::disk_initialize() {
ashwin_athani	0:c44f7e0926c7	182
ashwin_athani	0:c44f7e0926c7	183	int i = initialise_card();
ashwin_athani	0:c44f7e0926c7	184	// printf("init card = %d\n", i);
ashwin_athani	0:c44f7e0926c7	185	// printf("OK\n");
ashwin_athani	0:c44f7e0926c7	186
ashwin_athani	0:c44f7e0926c7	187	_sectors = _sd_sectors();
ashwin_athani	0:c44f7e0926c7	188
ashwin_athani	0:c44f7e0926c7	189	// Set block length to 512 (CMD16)
ashwin_athani	0:c44f7e0926c7	190	if(_cmd(16, 512) != 0) {
ashwin_athani	0:c44f7e0926c7	191	fprintf(stderr, "Set 512-byte block timed out\n");
ashwin_athani	0:c44f7e0926c7	192	return 1;
ashwin_athani	0:c44f7e0926c7	193	}
ashwin_athani	0:c44f7e0926c7	194
ashwin_athani	0:c44f7e0926c7	195	_spi.frequency(1000000); // Set to 1MHz for data transfer
ashwin_athani	0:c44f7e0926c7	196	return 0;
ashwin_athani	0:c44f7e0926c7	197	}
ashwin_athani	0:c44f7e0926c7	198
ashwin_athani	0:c44f7e0926c7	199	int SDFileSystem::disk_write(const char *buffer, int block_number) {
ashwin_athani	0:c44f7e0926c7	200	// set write address for single block (CMD24)
ashwin_athani	0:c44f7e0926c7	201	if(_cmd(24, block_number * 512) != 0) {
ashwin_athani	0:c44f7e0926c7	202	return 1;
ashwin_athani	0:c44f7e0926c7	203	}
ashwin_athani	0:c44f7e0926c7	204
ashwin_athani	0:c44f7e0926c7	205	// send the data block
ashwin_athani	0:c44f7e0926c7	206	_write(buffer, 512);
ashwin_athani	0:c44f7e0926c7	207	return 0;
ashwin_athani	0:c44f7e0926c7	208	}
ashwin_athani	0:c44f7e0926c7	209
ashwin_athani	0:c44f7e0926c7	210	int SDFileSystem::disk_read(char *buffer, int block_number) {
ashwin_athani	0:c44f7e0926c7	211	// set read address for single block (CMD17)
ashwin_athani	0:c44f7e0926c7	212	if(_cmd(17, block_number * 512) != 0) {
ashwin_athani	0:c44f7e0926c7	213	return 1;
ashwin_athani	0:c44f7e0926c7	214	}
ashwin_athani	0:c44f7e0926c7	215
ashwin_athani	0:c44f7e0926c7	216	// receive the data
ashwin_athani	0:c44f7e0926c7	217	_read(buffer, 512);
ashwin_athani	0:c44f7e0926c7	218	return 0;
ashwin_athani	0:c44f7e0926c7	219	}
ashwin_athani	0:c44f7e0926c7	220
ashwin_athani	0:c44f7e0926c7	221	int SDFileSystem::disk_status() { return 0; }
ashwin_athani	0:c44f7e0926c7	222	int SDFileSystem::disk_sync() { return 0; }
ashwin_athani	0:c44f7e0926c7	223	int SDFileSystem::disk_sectors() { return _sectors; }
ashwin_athani	0:c44f7e0926c7	224
ashwin_athani	0:c44f7e0926c7	225	// PRIVATE FUNCTIONS
ashwin_athani	0:c44f7e0926c7	226
ashwin_athani	0:c44f7e0926c7	227	int SDFileSystem::_cmd(int cmd, int arg) {
ashwin_athani	0:c44f7e0926c7	228	_cs = 0;
ashwin_athani	0:c44f7e0926c7	229
ashwin_athani	0:c44f7e0926c7	230	// send a command
ashwin_athani	0:c44f7e0926c7	231	_spi.write(0x40 \| cmd);
ashwin_athani	0:c44f7e0926c7	232	_spi.write(arg >> 24);
ashwin_athani	0:c44f7e0926c7	233	_spi.write(arg >> 16);
ashwin_athani	0:c44f7e0926c7	234	_spi.write(arg >> 8);
ashwin_athani	0:c44f7e0926c7	235	_spi.write(arg >> 0);
ashwin_athani	0:c44f7e0926c7	236	_spi.write(0x95);
ashwin_athani	0:c44f7e0926c7	237
ashwin_athani	0:c44f7e0926c7	238	// wait for the repsonse (response[7] == 0)
ashwin_athani	0:c44f7e0926c7	239	for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
ashwin_athani	0:c44f7e0926c7	240	int response = _spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	241	if(!(response & 0x80)) {
ashwin_athani	0:c44f7e0926c7	242	_cs = 1;
ashwin_athani	0:c44f7e0926c7	243	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	244	return response;
ashwin_athani	0:c44f7e0926c7	245	}
ashwin_athani	0:c44f7e0926c7	246	}
ashwin_athani	0:c44f7e0926c7	247	_cs = 1;
ashwin_athani	0:c44f7e0926c7	248	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	249	return -1; // timeout
ashwin_athani	0:c44f7e0926c7	250	}
ashwin_athani	0:c44f7e0926c7	251	int SDFileSystem::_cmdx(int cmd, int arg) {
ashwin_athani	0:c44f7e0926c7	252	_cs = 0;
ashwin_athani	0:c44f7e0926c7	253
ashwin_athani	0:c44f7e0926c7	254	// send a command
ashwin_athani	0:c44f7e0926c7	255	_spi.write(0x40 \| cmd);
ashwin_athani	0:c44f7e0926c7	256	_spi.write(arg >> 24);
ashwin_athani	0:c44f7e0926c7	257	_spi.write(arg >> 16);
ashwin_athani	0:c44f7e0926c7	258	_spi.write(arg >> 8);
ashwin_athani	0:c44f7e0926c7	259	_spi.write(arg >> 0);
ashwin_athani	0:c44f7e0926c7	260	_spi.write(0x95);
ashwin_athani	0:c44f7e0926c7	261
ashwin_athani	0:c44f7e0926c7	262	// wait for the repsonse (response[7] == 0)
ashwin_athani	0:c44f7e0926c7	263	for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
ashwin_athani	0:c44f7e0926c7	264	int response = _spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	265	if(!(response & 0x80)) {
ashwin_athani	0:c44f7e0926c7	266	return response;
ashwin_athani	0:c44f7e0926c7	267	}
ashwin_athani	0:c44f7e0926c7	268	}
ashwin_athani	0:c44f7e0926c7	269	_cs = 1;
ashwin_athani	0:c44f7e0926c7	270	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	271	return -1; // timeout
ashwin_athani	0:c44f7e0926c7	272	}
ashwin_athani	0:c44f7e0926c7	273
ashwin_athani	0:c44f7e0926c7	274
ashwin_athani	0:c44f7e0926c7	275	int SDFileSystem::_cmd58() {
ashwin_athani	0:c44f7e0926c7	276	_cs = 0;
ashwin_athani	0:c44f7e0926c7	277	int arg = 0;
ashwin_athani	0:c44f7e0926c7	278
ashwin_athani	0:c44f7e0926c7	279	// send a command
ashwin_athani	0:c44f7e0926c7	280	_spi.write(0x40 \| 58);
ashwin_athani	0:c44f7e0926c7	281	_spi.write(arg >> 24);
ashwin_athani	0:c44f7e0926c7	282	_spi.write(arg >> 16);
ashwin_athani	0:c44f7e0926c7	283	_spi.write(arg >> 8);
ashwin_athani	0:c44f7e0926c7	284	_spi.write(arg >> 0);
ashwin_athani	0:c44f7e0926c7	285	_spi.write(0x95);
ashwin_athani	0:c44f7e0926c7	286
ashwin_athani	0:c44f7e0926c7	287	// wait for the repsonse (response[7] == 0)
ashwin_athani	0:c44f7e0926c7	288	for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
ashwin_athani	0:c44f7e0926c7	289	int response = _spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	290	if(!(response & 0x80)) {
ashwin_athani	0:c44f7e0926c7	291	int ocr = _spi.write(0xFF) << 24;
ashwin_athani	0:c44f7e0926c7	292	ocr \|= _spi.write(0xFF) << 16;
ashwin_athani	0:c44f7e0926c7	293	ocr \|= _spi.write(0xFF) << 8;
ashwin_athani	0:c44f7e0926c7	294	ocr \|= _spi.write(0xFF) << 0;
ashwin_athani	0:c44f7e0926c7	295	// printf("OCR = 0x%08X\n", ocr);
ashwin_athani	0:c44f7e0926c7	296	_cs = 1;
ashwin_athani	0:c44f7e0926c7	297	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	298	return response;
ashwin_athani	0:c44f7e0926c7	299	}
ashwin_athani	0:c44f7e0926c7	300	}
ashwin_athani	0:c44f7e0926c7	301	_cs = 1;
ashwin_athani	0:c44f7e0926c7	302	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	303	return -1; // timeout
ashwin_athani	0:c44f7e0926c7	304	}
ashwin_athani	0:c44f7e0926c7	305
ashwin_athani	0:c44f7e0926c7	306	int SDFileSystem::_cmd8() {
ashwin_athani	0:c44f7e0926c7	307	_cs = 0;
ashwin_athani	0:c44f7e0926c7	308
ashwin_athani	0:c44f7e0926c7	309	// send a command
ashwin_athani	0:c44f7e0926c7	310	_spi.write(0x40 \| 8); // CMD8
ashwin_athani	0:c44f7e0926c7	311	_spi.write(0x00); // reserved
ashwin_athani	0:c44f7e0926c7	312	_spi.write(0x00); // reserved
ashwin_athani	0:c44f7e0926c7	313	_spi.write(0x01); // 3.3v
ashwin_athani	0:c44f7e0926c7	314	_spi.write(0xAA); // check pattern
ashwin_athani	0:c44f7e0926c7	315	_spi.write(0x87); // crc
ashwin_athani	0:c44f7e0926c7	316
ashwin_athani	0:c44f7e0926c7	317	// wait for the repsonse (response[7] == 0)
ashwin_athani	0:c44f7e0926c7	318	for(int i=0; i<SD_COMMAND_TIMEOUT * 1000; i++) {
ashwin_athani	0:c44f7e0926c7	319	char response[5];
ashwin_athani	0:c44f7e0926c7	320	response[0] = _spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	321	if(!(response[0] & 0x80)) {
ashwin_athani	0:c44f7e0926c7	322	for(int j=1; j<5; j++) {
ashwin_athani	0:c44f7e0926c7	323	response[i] = _spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	324	}
ashwin_athani	0:c44f7e0926c7	325	_cs = 1;
ashwin_athani	0:c44f7e0926c7	326	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	327	return response[0];
ashwin_athani	0:c44f7e0926c7	328	}
ashwin_athani	0:c44f7e0926c7	329	}
ashwin_athani	0:c44f7e0926c7	330	_cs = 1;
ashwin_athani	0:c44f7e0926c7	331	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	332	return -1; // timeout
ashwin_athani	0:c44f7e0926c7	333	}
ashwin_athani	0:c44f7e0926c7	334
ashwin_athani	0:c44f7e0926c7	335	int SDFileSystem::_read(char *buffer, int length) {
ashwin_athani	0:c44f7e0926c7	336	_cs = 0;
ashwin_athani	0:c44f7e0926c7	337
ashwin_athani	0:c44f7e0926c7	338	// read until start byte (0xFF)
ashwin_athani	0:c44f7e0926c7	339	while(_spi.write(0xFF) != 0xFE);
ashwin_athani	0:c44f7e0926c7	340
ashwin_athani	0:c44f7e0926c7	341	// read data
ashwin_athani	0:c44f7e0926c7	342	for(int i=0; i<length; i++) {
ashwin_athani	0:c44f7e0926c7	343	buffer[i] = _spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	344	}
ashwin_athani	0:c44f7e0926c7	345	_spi.write(0xFF); // checksum
ashwin_athani	0:c44f7e0926c7	346	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	347
ashwin_athani	0:c44f7e0926c7	348	_cs = 1;
ashwin_athani	0:c44f7e0926c7	349	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	350	return 0;
ashwin_athani	0:c44f7e0926c7	351	}
ashwin_athani	0:c44f7e0926c7	352
ashwin_athani	0:c44f7e0926c7	353	int SDFileSystem::_write(const char *buffer, int length) {
ashwin_athani	0:c44f7e0926c7	354	_cs = 0;
ashwin_athani	0:c44f7e0926c7	355
ashwin_athani	0:c44f7e0926c7	356	// indicate start of block
ashwin_athani	0:c44f7e0926c7	357	_spi.write(0xFE);
ashwin_athani	0:c44f7e0926c7	358
ashwin_athani	0:c44f7e0926c7	359	// write the data
ashwin_athani	0:c44f7e0926c7	360	for(int i=0; i<length; i++) {
ashwin_athani	0:c44f7e0926c7	361	_spi.write(buffer[i]);
ashwin_athani	0:c44f7e0926c7	362	}
ashwin_athani	0:c44f7e0926c7	363
ashwin_athani	0:c44f7e0926c7	364	// write the checksum
ashwin_athani	0:c44f7e0926c7	365	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	366	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	367
ashwin_athani	0:c44f7e0926c7	368	// check the repsonse token
ashwin_athani	0:c44f7e0926c7	369	if((_spi.write(0xFF) & 0x1F) != 0x05) {
ashwin_athani	0:c44f7e0926c7	370	_cs = 1;
ashwin_athani	0:c44f7e0926c7	371	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	372	return 1;
ashwin_athani	0:c44f7e0926c7	373	}
ashwin_athani	0:c44f7e0926c7	374
ashwin_athani	0:c44f7e0926c7	375	// wait for write to finish
ashwin_athani	0:c44f7e0926c7	376	while(_spi.write(0xFF) == 0);
ashwin_athani	0:c44f7e0926c7	377
ashwin_athani	0:c44f7e0926c7	378	_cs = 1;
ashwin_athani	0:c44f7e0926c7	379	_spi.write(0xFF);
ashwin_athani	0:c44f7e0926c7	380	return 0;
ashwin_athani	0:c44f7e0926c7	381	}
ashwin_athani	0:c44f7e0926c7	382
ashwin_athani	0:c44f7e0926c7	383	static int ext_bits(char *data, int msb, int lsb) {
ashwin_athani	0:c44f7e0926c7	384	int bits = 0;
ashwin_athani	0:c44f7e0926c7	385	int size = 1 + msb - lsb;
ashwin_athani	0:c44f7e0926c7	386	for(int i=0; i<size; i++) {
ashwin_athani	0:c44f7e0926c7	387	int position = lsb + i;
ashwin_athani	0:c44f7e0926c7	388	int byte = 15 - (position >> 3);
ashwin_athani	0:c44f7e0926c7	389	int bit = position & 0x7;
ashwin_athani	0:c44f7e0926c7	390	int value = (data[byte] >> bit) & 1;
ashwin_athani	0:c44f7e0926c7	391	bits \|= value << i;
ashwin_athani	0:c44f7e0926c7	392	}
ashwin_athani	0:c44f7e0926c7	393	return bits;
ashwin_athani	0:c44f7e0926c7	394	}
ashwin_athani	0:c44f7e0926c7	395
ashwin_athani	0:c44f7e0926c7	396	int SDFileSystem::_sd_sectors() {
ashwin_athani	0:c44f7e0926c7	397
ashwin_athani	0:c44f7e0926c7	398	// CMD9, Response R2 (R1 byte + 16-byte block read)
ashwin_athani	0:c44f7e0926c7	399	if(_cmdx(9, 0) != 0) {
ashwin_athani	0:c44f7e0926c7	400	fprintf(stderr, "Didn't get a response from the disk\n");
ashwin_athani	0:c44f7e0926c7	401	return 0;
ashwin_athani	0:c44f7e0926c7	402	}
ashwin_athani	0:c44f7e0926c7	403
ashwin_athani	0:c44f7e0926c7	404	char csd[16];
ashwin_athani	0:c44f7e0926c7	405	if(_read(csd, 16) != 0) {
ashwin_athani	0:c44f7e0926c7	406	fprintf(stderr, "Couldn't read csd response from disk\n");
ashwin_athani	0:c44f7e0926c7	407	return 0;
ashwin_athani	0:c44f7e0926c7	408	}
ashwin_athani	0:c44f7e0926c7	409
ashwin_athani	0:c44f7e0926c7	410	// csd_structure : csd[127:126]
ashwin_athani	0:c44f7e0926c7	411	// c_size : csd[73:62]
ashwin_athani	0:c44f7e0926c7	412	// c_size_mult : csd[49:47]
ashwin_athani	0:c44f7e0926c7	413	// read_bl_len : csd[83:80] - the maximum read block length
ashwin_athani	0:c44f7e0926c7	414
ashwin_athani	0:c44f7e0926c7	415	int csd_structure = ext_bits(csd, 127, 126);
ashwin_athani	0:c44f7e0926c7	416	int c_size = ext_bits(csd, 73, 62);
ashwin_athani	0:c44f7e0926c7	417	int c_size_mult = ext_bits(csd, 49, 47);
ashwin_athani	0:c44f7e0926c7	418	int read_bl_len = ext_bits(csd, 83, 80);
ashwin_athani	0:c44f7e0926c7	419
ashwin_athani	0:c44f7e0926c7	420	// printf("CSD_STRUCT = %d\n", csd_structure);
ashwin_athani	0:c44f7e0926c7	421
ashwin_athani	0:c44f7e0926c7	422	if(csd_structure != 0) {
ashwin_athani	0:c44f7e0926c7	423	fprintf(stderr, "This disk tastes funny! I only know about type 0 CSD structures\n");
ashwin_athani	0:c44f7e0926c7	424	return 0;
ashwin_athani	0:c44f7e0926c7	425	}
ashwin_athani	0:c44f7e0926c7	426
ashwin_athani	0:c44f7e0926c7	427	// memory capacity = BLOCKNR * BLOCK_LEN
ashwin_athani	0:c44f7e0926c7	428	// where
ashwin_athani	0:c44f7e0926c7	429	// BLOCKNR = (C_SIZE+1) * MULT
ashwin_athani	0:c44f7e0926c7	430	// MULT = 2^(C_SIZE_MULT+2) (C_SIZE_MULT < 8)
ashwin_athani	0:c44f7e0926c7	431	// BLOCK_LEN = 2^READ_BL_LEN, (READ_BL_LEN < 12)
ashwin_athani	0:c44f7e0926c7	432
ashwin_athani	0:c44f7e0926c7	433	int block_len = 1 << read_bl_len;
ashwin_athani	0:c44f7e0926c7	434	int mult = 1 << (c_size_mult + 2);
ashwin_athani	0:c44f7e0926c7	435	int blocknr = (c_size + 1) * mult;
ashwin_athani	0:c44f7e0926c7	436	int capacity = blocknr * block_len;
ashwin_athani	0:c44f7e0926c7	437
ashwin_athani	0:c44f7e0926c7	438	int blocks = capacity / 512;
ashwin_athani	0:c44f7e0926c7	439
ashwin_athani	0:c44f7e0926c7	440	return blocks;
ashwin_athani	0:c44f7e0926c7	441	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	08 Dec 2010
Imports:	41
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	3

SDFileSystem.cpp@0:c44f7e0926c7, 2010-12-08 (annotated)

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