Diff: SimpleDMA/SimpleDMA_KL25_46.cpp

Revision:

100:1ff35c07217c

Parent:

76:7f5912b6340e

--- a/SimpleDMA/SimpleDMA_KL25_46.cpp	Sat Mar 02 21:05:43 2019 +0000
+++ b/SimpleDMA/SimpleDMA_KL25_46.cpp	Thu Nov 28 23:18:23 2019 +0000
@@ -66,16 +66,33 @@
 
 int SimpleDMA::start(uint32_t length, bool wait)
 {
+    // prepare the transfer
+    volatile uint8_t *chcfg = prepare(length, wait);
+    
+    // check for errors
+    if (chcfg == NULL)
+        return -1;
+        
+    // ready to go - set the ENBL bit in the DMAMUX channel config register
+    // to start the trnasfer
+    *chcfg |= DMAMUX_CHCFG_ENBL_MASK;
+    
+    // return success
+    return 0;
+}
+
+volatile uint8_t *SimpleDMA::prepare(uint32_t length, bool wait)
+{
     if (auto_channel)
         _channel = getFreeChannel();
     else if (!wait && isBusy())
-        return -1;
+        return NULL;
     else {
         while (isBusy());
     }
     
     if (length > DMA_DSR_BCR_BCR_MASK)
-        return -1;
+        return NULL;
 
     irq_owner[_channel] = this;
     
@@ -127,10 +144,8 @@
     dmareg->DCR = config;      
     dmareg->DSR_BCR = length;
     
-    // Start - set the ENBL bit in the DMAMUX channel config register
-    *chcfg |= DMAMUX_CHCFG_ENBL_MASK;
-
-    return 0;
+    // success - return the channel config register
+    return chcfg;
 }
 
 void SimpleDMA::link(SimpleDMA &dest, bool all)